1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
4 *
5 * Written by Jacob Shin - AMD, Inc.
6 * Maintained by: Borislav Petkov <bp@alien8.de>
7 */
8 #include <linux/interrupt.h>
9 #include <linux/notifier.h>
10 #include <linux/kobject.h>
11 #include <linux/percpu.h>
12 #include <linux/errno.h>
13 #include <linux/sched.h>
14 #include <linux/sysfs.h>
15 #include <linux/slab.h>
16 #include <linux/init.h>
17 #include <linux/cpu.h>
18 #include <linux/smp.h>
19 #include <linux/string.h>
20
21 #include <asm/traps.h>
22 #include <asm/apic.h>
23 #include <asm/mce.h>
24 #include <asm/msr.h>
25 #include <asm/trace/irq_vectors.h>
26
27 #include "internal.h"
28
29 #define NR_BLOCKS 5
30 #define THRESHOLD_MAX 0xFFF
31 #define INT_TYPE_APIC 0x00020000
32 #define MASK_VALID_HI 0x80000000
33 #define MASK_CNTP_HI 0x40000000
34 #define MASK_LOCKED_HI 0x20000000
35 #define MASK_LVTOFF_HI 0x00F00000
36 #define MASK_COUNT_EN_HI 0x00080000
37 #define MASK_INT_TYPE_HI 0x00060000
38 #define MASK_OVERFLOW_HI 0x00010000
39 #define MASK_ERR_COUNT_HI 0x00000FFF
40 #define MASK_BLKPTR_LO 0xFF000000
41 #define MCG_XBLK_ADDR 0xC0000400
42
43 /* Deferred error settings */
44 #define MSR_CU_DEF_ERR 0xC0000410
45 #define MASK_DEF_LVTOFF 0x000000F0
46
47 /* Scalable MCA: */
48
49 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
50 #define SMCA_THR_LVT_OFF 0xF000
51
52 static bool thresholding_irq_en;
53
54 struct mce_amd_cpu_data {
55 mce_banks_t thr_intr_banks;
56 mce_banks_t dfr_intr_banks;
57
58 u32 thr_intr_en: 1,
59 dfr_intr_en: 1,
60 __resv: 30;
61 };
62
63 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data);
64
65 static const char * const th_names[] = {
66 "load_store",
67 "insn_fetch",
68 "combined_unit",
69 "decode_unit",
70 "northbridge",
71 "execution_unit",
72 };
73
74 static const char * const smca_umc_block_names[] = {
75 "dram_ecc",
76 "misc_umc"
77 };
78
79 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
80
81 struct smca_hwid {
82 unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
83 u32 hwid_mcatype; /* (hwid,mcatype) tuple */
84 };
85
86 struct smca_bank {
87 const struct smca_hwid *hwid;
88 u32 id; /* Value of MCA_IPID[InstanceId]. */
89 u8 sysfs_id; /* Value used for sysfs name. */
90 u64 paddrv :1, /* Physical Address Valid bit in MCA_CONFIG */
91 __reserved :63;
92 };
93
94 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
95 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
96
97 static const char * const smca_names[] = {
98 [SMCA_CS ... SMCA_CS_V2] = "coherent_station",
99 [SMCA_DACC_BE] = "dacc_be",
100 [SMCA_DACC_FE] = "dacc_fe",
101 [SMCA_DE] = "decode_unit",
102 [SMCA_EDDR5CMN] = "eddr5_cmn",
103 [SMCA_EX] = "execution_unit",
104 [SMCA_FP] = "floating_point",
105 [SMCA_GMI_PCS] = "gmi_pcs",
106 [SMCA_GMI_PHY] = "gmi_phy",
107 [SMCA_IF] = "insn_fetch",
108 [SMCA_L2_CACHE] = "l2_cache",
109 [SMCA_L3_CACHE] = "l3_cache",
110 [SMCA_LS ... SMCA_LS_V2] = "load_store",
111 [SMCA_MA_LLC] = "ma_llc",
112 [SMCA_MP5] = "mp5",
113 [SMCA_MPART] = "mpart",
114 [SMCA_MPASP ... SMCA_MPASP_V2] = "mpasp",
115 [SMCA_MPDACC] = "mpdacc",
116 [SMCA_MPDMA] = "mpdma",
117 [SMCA_MPM] = "mpm",
118 [SMCA_MPRAS] = "mpras",
119 [SMCA_NBIF] = "nbif",
120 [SMCA_NBIO] = "nbio",
121 [SMCA_PB] = "param_block",
122 [SMCA_PCIE ... SMCA_PCIE_V2] = "pcie",
123 [SMCA_PCIE_PL] = "pcie_pl",
124 [SMCA_PIE] = "pie",
125 [SMCA_PSP ... SMCA_PSP_V2] = "psp",
126 [SMCA_RESERVED] = "reserved",
127 [SMCA_SATA] = "sata",
128 [SMCA_SHUB] = "shub",
129 [SMCA_SMU ... SMCA_SMU_V2] = "smu",
130 [SMCA_SSBDCI] = "ssbdci",
131
132 /* UMC v2 is separate because both of them can exist in a single system. */
133 [SMCA_UMC] = "umc",
134 [SMCA_UMC_V2] = "umc_v2",
135 [SMCA_USB] = "usb",
136 [SMCA_USR_CP] = "usr_cp",
137 [SMCA_USR_DP] = "usr_dp",
138 [SMCA_WAFL_PHY] = "wafl_phy",
139 [SMCA_XGMI_PCS] = "xgmi_pcs",
140 [SMCA_XGMI_PHY] = "xgmi_phy",
141 };
142
smca_get_name(enum smca_bank_types t)143 static const char *smca_get_name(enum smca_bank_types t)
144 {
145 if (t >= N_SMCA_BANK_TYPES)
146 return NULL;
147
148 return smca_names[t];
149 }
150
smca_get_bank_type(unsigned int cpu,unsigned int bank)151 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
152 {
153 struct smca_bank *b;
154
155 if (bank >= MAX_NR_BANKS)
156 return N_SMCA_BANK_TYPES;
157
158 b = &per_cpu(smca_banks, cpu)[bank];
159 if (!b->hwid)
160 return N_SMCA_BANK_TYPES;
161
162 return b->hwid->bank_type;
163 }
164 EXPORT_SYMBOL_GPL(smca_get_bank_type);
165
166 /*
167 * Format:
168 * { bank_type, hwid_mcatype }
169 *
170 * alphanumerically sorted by bank type.
171 */
172 static const struct smca_hwid smca_hwid_mcatypes[] = {
173 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
174 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
175 { SMCA_DACC_BE, HWID_MCATYPE(0x164, 0x0) },
176 { SMCA_DACC_FE, HWID_MCATYPE(0x157, 0x0) },
177 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) },
178 { SMCA_EDDR5CMN, HWID_MCATYPE(0x1E0, 0x0) },
179 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) },
180 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) },
181 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) },
182 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) },
183 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
184 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
185 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) },
186 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
187 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
188 { SMCA_MA_LLC, HWID_MCATYPE(0x2E, 0x4) },
189 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) },
190 { SMCA_MPART, HWID_MCATYPE(0xFF, 0x2) },
191 { SMCA_MPASP, HWID_MCATYPE(0xFD, 0x0) },
192 { SMCA_MPASP_V2, HWID_MCATYPE(0xFD, 0x1) },
193 { SMCA_MPDACC, HWID_MCATYPE(0xBE, 0x0) },
194 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) },
195 { SMCA_MPM, HWID_MCATYPE(0xF9, 0x0) },
196 { SMCA_MPRAS, HWID_MCATYPE(0x12, 0x0) },
197 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) },
198 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) },
199 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
200 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) },
201 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) },
202 { SMCA_PCIE_PL, HWID_MCATYPE(0x1E1, 0x0) },
203 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
204 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
205 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
206 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
207 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) },
208 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) },
209 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
210 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
211 { SMCA_SSBDCI, HWID_MCATYPE(0x5C, 0x0) },
212 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
213 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) },
214 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) },
215 { SMCA_USR_CP, HWID_MCATYPE(0x180, 0x0) },
216 { SMCA_USR_DP, HWID_MCATYPE(0x170, 0x0) },
217 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) },
218 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) },
219 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) },
220 };
221
222 /*
223 * In SMCA enabled processors, we can have multiple banks for a given IP type.
224 * So to define a unique name for each bank, we use a temp c-string to append
225 * the MCA_IPID[InstanceId] to type's name in get_name().
226 *
227 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
228 * is greater than 8 plus 1 (for underscore) plus length of longest type name.
229 */
230 #define MAX_MCATYPE_NAME_LEN 30
231 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
232
233 struct threshold_block {
234 /* This block's number within its bank. */
235 unsigned int block;
236 /* MCA bank number that contains this block. */
237 unsigned int bank;
238 /* CPU which controls this block's MCA bank. */
239 unsigned int cpu;
240 /* MCA_MISC MSR address for this block. */
241 u32 address;
242 /* Enable/Disable APIC interrupt. */
243 bool interrupt_enable;
244 /* Bank can generate an interrupt. */
245 bool interrupt_capable;
246 /* Value upon which threshold interrupt is generated. */
247 u16 threshold_limit;
248 /* sysfs object */
249 struct kobject kobj;
250 /* List of threshold blocks within this block's MCA bank. */
251 struct list_head miscj;
252 };
253
254 struct threshold_bank {
255 struct kobject *kobj;
256 /* List of threshold blocks within this MCA bank. */
257 struct list_head miscj;
258 };
259
260 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
261
262 /*
263 * A list of the banks enabled on each logical CPU. Controls which respective
264 * descriptors to initialize later in mce_threshold_create_device().
265 */
266 static DEFINE_PER_CPU(u64, bank_map);
267
268 static void amd_threshold_interrupt(void);
269 static void amd_deferred_error_interrupt(void);
270
default_deferred_error_interrupt(void)271 static void default_deferred_error_interrupt(void)
272 {
273 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
274 }
275 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
276
smca_configure(unsigned int bank,unsigned int cpu)277 static void smca_configure(unsigned int bank, unsigned int cpu)
278 {
279 struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data);
280 u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
281 const struct smca_hwid *s_hwid;
282 unsigned int i, hwid_mcatype;
283 u32 high, low;
284 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
285
286 /* Set appropriate bits in MCA_CONFIG */
287 if (!rdmsr_safe(smca_config, &low, &high)) {
288 /*
289 * OS is required to set the MCAX bit to acknowledge that it is
290 * now using the new MSR ranges and new registers under each
291 * bank. It also means that the OS will configure deferred
292 * errors in the new MCx_CONFIG register. If the bit is not set,
293 * uncorrectable errors will cause a system panic.
294 *
295 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
296 */
297 high |= BIT(0);
298
299 /*
300 * SMCA sets the Deferred Error Interrupt type per bank.
301 *
302 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
303 * if the DeferredIntType bit field is available.
304 *
305 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
306 * high portion of the MSR). OS should set this to 0x1 to enable
307 * APIC based interrupt. First, check that no interrupt has been
308 * set.
309 */
310 if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) {
311 __set_bit(bank, data->dfr_intr_banks);
312 high |= BIT(5);
313 }
314
315 /*
316 * SMCA Corrected Error Interrupt
317 *
318 * MCA_CONFIG[IntPresent] is bit 10, and tells us if the bank can
319 * send an MCA Thresholding interrupt without the OS initializing
320 * this feature. This can be used if the threshold limit is managed
321 * by the platform.
322 *
323 * MCA_CONFIG[IntEn] is bit 40 (8 in the high portion of the MSR).
324 * The OS should set this to inform the platform that the OS is ready
325 * to handle the MCA Thresholding interrupt.
326 */
327 if ((low & BIT(10)) && data->thr_intr_en) {
328 __set_bit(bank, data->thr_intr_banks);
329 high |= BIT(8);
330 }
331
332 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
333
334 if (low & MCI_CONFIG_PADDRV)
335 this_cpu_ptr(smca_banks)[bank].paddrv = 1;
336
337 wrmsr(smca_config, low, high);
338 }
339
340 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
341 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
342 return;
343 }
344
345 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
346 (high & MCI_IPID_MCATYPE) >> 16);
347
348 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
349 s_hwid = &smca_hwid_mcatypes[i];
350
351 if (hwid_mcatype == s_hwid->hwid_mcatype) {
352 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
353 this_cpu_ptr(smca_banks)[bank].id = low;
354 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
355 break;
356 }
357 }
358 }
359
360 struct thresh_restart {
361 struct threshold_block *b;
362 int set_lvt_off;
363 int lvt_off;
364 u16 old_limit;
365 };
366
bank4_names(const struct threshold_block * b)367 static const char *bank4_names(const struct threshold_block *b)
368 {
369 switch (b->address) {
370 /* MSR4_MISC0 */
371 case 0x00000413:
372 return "dram";
373
374 case 0xc0000408:
375 return "ht_links";
376
377 case 0xc0000409:
378 return "l3_cache";
379
380 default:
381 WARN(1, "Funny MSR: 0x%08x\n", b->address);
382 return "";
383 }
384 };
385
386
lvt_interrupt_supported(unsigned int bank,u32 msr_high_bits)387 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
388 {
389 /*
390 * bank 4 supports APIC LVT interrupts implicitly since forever.
391 */
392 if (bank == 4)
393 return true;
394
395 /*
396 * IntP: interrupt present; if this bit is set, the thresholding
397 * bank can generate APIC LVT interrupts
398 */
399 return msr_high_bits & BIT(28);
400 }
401
lvt_off_valid(struct threshold_block * b,int apic,u32 lo,u32 hi)402 static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
403 {
404 int msr = (hi & MASK_LVTOFF_HI) >> 20;
405
406 /*
407 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
408 * the BIOS provides the value. The original field where LVT offset
409 * was set is reserved. Return early here:
410 */
411 if (mce_flags.smca)
412 return false;
413
414 if (apic < 0) {
415 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
416 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
417 b->bank, b->block, b->address, hi, lo);
418 return false;
419 }
420
421 if (apic != msr) {
422 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
423 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
424 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
425 return false;
426 }
427
428 return true;
429 };
430
431 /* Reprogram MCx_MISC MSR behind this threshold block. */
threshold_restart_block(void * _tr)432 static void threshold_restart_block(void *_tr)
433 {
434 struct thresh_restart *tr = _tr;
435 u32 hi, lo;
436
437 /* sysfs write might race against an offline operation */
438 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
439 return;
440
441 rdmsr(tr->b->address, lo, hi);
442
443 /*
444 * Reset error count and overflow bit.
445 * This is done during init or after handling an interrupt.
446 */
447 if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) {
448 hi &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
449 hi |= THRESHOLD_MAX - tr->b->threshold_limit;
450 } else if (tr->old_limit) { /* change limit w/o reset */
451 int new_count = (hi & THRESHOLD_MAX) +
452 (tr->old_limit - tr->b->threshold_limit);
453
454 hi = (hi & ~MASK_ERR_COUNT_HI) |
455 (new_count & THRESHOLD_MAX);
456 }
457
458 /* clear IntType */
459 hi &= ~MASK_INT_TYPE_HI;
460
461 if (!tr->b->interrupt_capable)
462 goto done;
463
464 if (tr->set_lvt_off) {
465 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
466 /* set new lvt offset */
467 hi &= ~MASK_LVTOFF_HI;
468 hi |= tr->lvt_off << 20;
469 }
470 }
471
472 if (tr->b->interrupt_enable)
473 hi |= INT_TYPE_APIC;
474
475 done:
476
477 hi |= MASK_COUNT_EN_HI;
478 wrmsr(tr->b->address, lo, hi);
479 }
480
threshold_restart_bank(unsigned int bank,bool intr_en)481 static void threshold_restart_bank(unsigned int bank, bool intr_en)
482 {
483 struct threshold_bank **thr_banks = this_cpu_read(threshold_banks);
484 struct threshold_block *block, *tmp;
485 struct thresh_restart tr;
486
487 if (!thr_banks || !thr_banks[bank])
488 return;
489
490 memset(&tr, 0, sizeof(tr));
491
492 list_for_each_entry_safe(block, tmp, &thr_banks[bank]->miscj, miscj) {
493 tr.b = block;
494 tr.b->interrupt_enable = intr_en;
495 threshold_restart_block(&tr);
496 }
497 }
498
499 /* Try to use the threshold limit reported through APEI. */
get_thr_limit(void)500 static u16 get_thr_limit(void)
501 {
502 u32 thr_limit = mce_get_apei_thr_limit();
503
504 /* Fallback to old default if APEI limit is not available. */
505 if (!thr_limit)
506 return THRESHOLD_MAX;
507
508 return min(thr_limit, THRESHOLD_MAX);
509 }
510
mce_threshold_block_init(struct threshold_block * b,int offset)511 static void mce_threshold_block_init(struct threshold_block *b, int offset)
512 {
513 struct thresh_restart tr = {
514 .b = b,
515 .set_lvt_off = 1,
516 .lvt_off = offset,
517 };
518
519 b->threshold_limit = get_thr_limit();
520 threshold_restart_block(&tr);
521 };
522
setup_APIC_mce_threshold(int reserved,int new)523 static int setup_APIC_mce_threshold(int reserved, int new)
524 {
525 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
526 APIC_DELIVERY_MODE_FIXED, 0))
527 return new;
528
529 return reserved;
530 }
531
get_block_address(u32 current_addr,u32 low,u32 high,unsigned int bank,unsigned int block,unsigned int cpu)532 static u32 get_block_address(u32 current_addr, u32 low, u32 high,
533 unsigned int bank, unsigned int block,
534 unsigned int cpu)
535 {
536 u32 addr = 0, offset = 0;
537
538 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
539 return addr;
540
541 if (mce_flags.smca) {
542 if (!block)
543 return MSR_AMD64_SMCA_MCx_MISC(bank);
544
545 if (!(low & MASK_BLKPTR_LO))
546 return 0;
547
548 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
549 }
550
551 /* Fall back to method we used for older processors: */
552 switch (block) {
553 case 0:
554 addr = mca_msr_reg(bank, MCA_MISC);
555 break;
556 case 1:
557 offset = ((low & MASK_BLKPTR_LO) >> 21);
558 if (offset)
559 addr = MCG_XBLK_ADDR + offset;
560 break;
561 default:
562 addr = ++current_addr;
563 }
564 return addr;
565 }
566
prepare_threshold_block(unsigned int bank,unsigned int block,u32 addr,int offset,u32 misc_high)567 static int prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
568 int offset, u32 misc_high)
569 {
570 unsigned int cpu = smp_processor_id();
571 struct threshold_block b;
572 int new;
573
574 if (!block)
575 per_cpu(bank_map, cpu) |= BIT_ULL(bank);
576
577 memset(&b, 0, sizeof(b));
578 b.cpu = cpu;
579 b.bank = bank;
580 b.block = block;
581 b.address = addr;
582 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high);
583
584 if (!b.interrupt_capable)
585 goto done;
586
587 __set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks);
588 b.interrupt_enable = 1;
589
590 if (mce_flags.smca)
591 goto done;
592
593 new = (misc_high & MASK_LVTOFF_HI) >> 20;
594 offset = setup_APIC_mce_threshold(offset, new);
595 if (offset == new)
596 thresholding_irq_en = true;
597
598 done:
599 mce_threshold_block_init(&b, offset);
600
601 return offset;
602 }
603
amd_filter_mce(struct mce * m)604 bool amd_filter_mce(struct mce *m)
605 {
606 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);
607 struct cpuinfo_x86 *c = &boot_cpu_data;
608
609 /* Bogus hw errors on Cezanne A0. */
610 if (c->x86 == 0x19 &&
611 c->x86_model == 0x50 &&
612 c->x86_stepping == 0x0) {
613 if (!(m->status & MCI_STATUS_EN))
614 return true;
615 }
616
617 /* See Family 17h Models 10h-2Fh Erratum #1114. */
618 if (c->x86 == 0x17 &&
619 c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
620 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)
621 return true;
622
623 /* NB GART TLB error reporting is disabled by default. */
624 if (c->x86 < 0x17) {
625 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)
626 return true;
627 }
628
629 return false;
630 }
631
632 /*
633 * Turn off thresholding banks for the following conditions:
634 * - MC4_MISC thresholding is not supported on Family 0x15.
635 * - Prevent possible spurious interrupts from the IF bank on Family 0x17
636 * Models 0x10-0x2F due to Erratum #1114.
637 */
disable_err_thresholding(struct cpuinfo_x86 * c,unsigned int bank)638 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
639 {
640 int i, num_msrs;
641 u64 hwcr;
642 bool need_toggle;
643 u32 msrs[NR_BLOCKS];
644
645 if (c->x86 == 0x15 && bank == 4) {
646 msrs[0] = 0x00000413; /* MC4_MISC0 */
647 msrs[1] = 0xc0000408; /* MC4_MISC1 */
648 num_msrs = 2;
649 } else if (c->x86 == 0x17 &&
650 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
651
652 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF)
653 return;
654
655 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
656 num_msrs = 1;
657 } else {
658 return;
659 }
660
661 rdmsrq(MSR_K7_HWCR, hwcr);
662
663 /* McStatusWrEn has to be set */
664 need_toggle = !(hwcr & BIT(18));
665 if (need_toggle)
666 wrmsrq(MSR_K7_HWCR, hwcr | BIT(18));
667
668 /* Clear CntP bit safely */
669 for (i = 0; i < num_msrs; i++)
670 msr_clear_bit(msrs[i], 62);
671
672 /* restore old settings */
673 if (need_toggle)
674 wrmsrq(MSR_K7_HWCR, hwcr);
675 }
676
amd_apply_cpu_quirks(struct cpuinfo_x86 * c)677 static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c)
678 {
679 struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
680
681 /* This should be disabled by the BIOS, but isn't always */
682 if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
683 /*
684 * disable GART TBL walk error reporting, which
685 * trips off incorrectly with the IOMMU & 3ware
686 * & Cerberus:
687 */
688 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
689 }
690
691 /*
692 * Various K7s with broken bank 0 around. Always disable
693 * by default.
694 */
695 if (c->x86 == 6 && this_cpu_read(mce_num_banks))
696 mce_banks[0].ctl = 0;
697 }
698
699 /*
700 * Enable the APIC LVT interrupt vectors once per-CPU. This should be done before hardware is
701 * ready to send interrupts.
702 *
703 * Individual error sources are enabled later during per-bank init.
704 */
smca_enable_interrupt_vectors(void)705 static void smca_enable_interrupt_vectors(void)
706 {
707 struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data);
708 u64 mca_intr_cfg, offset;
709
710 if (!mce_flags.smca || !mce_flags.succor)
711 return;
712
713 if (rdmsrq_safe(MSR_CU_DEF_ERR, &mca_intr_cfg))
714 return;
715
716 offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12;
717 if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
718 data->thr_intr_en = 1;
719
720 offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4;
721 if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
722 data->dfr_intr_en = 1;
723 }
724
725 /* cpu init entry point, called from mce.c with preempt off */
mce_amd_feature_init(struct cpuinfo_x86 * c)726 void mce_amd_feature_init(struct cpuinfo_x86 *c)
727 {
728 unsigned int bank, block, cpu = smp_processor_id();
729 u32 low = 0, high = 0, address = 0;
730 int offset = -1;
731
732 amd_apply_cpu_quirks(c);
733
734 mce_flags.amd_threshold = 1;
735
736 smca_enable_interrupt_vectors();
737
738 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
739 if (mce_flags.smca) {
740 smca_configure(bank, cpu);
741
742 if (!this_cpu_ptr(&mce_amd_data)->thr_intr_en)
743 continue;
744 }
745
746 disable_err_thresholding(c, bank);
747
748 for (block = 0; block < NR_BLOCKS; ++block) {
749 address = get_block_address(address, low, high, bank, block, cpu);
750 if (!address)
751 break;
752
753 if (rdmsr_safe(address, &low, &high))
754 break;
755
756 if (!(high & MASK_VALID_HI))
757 continue;
758
759 if (!(high & MASK_CNTP_HI) ||
760 (high & MASK_LOCKED_HI))
761 continue;
762
763 offset = prepare_threshold_block(bank, block, address, offset, high);
764 }
765 }
766 }
767
smca_bsp_init(void)768 void smca_bsp_init(void)
769 {
770 mce_threshold_vector = amd_threshold_interrupt;
771 deferred_error_int_vector = amd_deferred_error_interrupt;
772 }
773
774 /*
775 * DRAM ECC errors are reported in the Northbridge (bank 4) with
776 * Extended Error Code 8.
777 */
legacy_mce_is_memory_error(struct mce * m)778 static bool legacy_mce_is_memory_error(struct mce *m)
779 {
780 return m->bank == 4 && XEC(m->status, 0x1f) == 8;
781 }
782
783 /*
784 * DRAM ECC errors are reported in Unified Memory Controllers with
785 * Extended Error Code 0.
786 */
smca_mce_is_memory_error(struct mce * m)787 static bool smca_mce_is_memory_error(struct mce *m)
788 {
789 enum smca_bank_types bank_type;
790
791 if (XEC(m->status, 0x3f))
792 return false;
793
794 bank_type = smca_get_bank_type(m->extcpu, m->bank);
795
796 return bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2;
797 }
798
amd_mce_is_memory_error(struct mce * m)799 bool amd_mce_is_memory_error(struct mce *m)
800 {
801 if (mce_flags.smca)
802 return smca_mce_is_memory_error(m);
803 else
804 return legacy_mce_is_memory_error(m);
805 }
806
807 /*
808 * Some AMD systems have an explicit indicator that the value in MCA_ADDR is a
809 * system physical address. Individual cases though, need to be detected for
810 * other systems. Future cases will be added as needed.
811 *
812 * 1) General case
813 * a) Assume address is not usable.
814 * 2) Poison errors
815 * a) Indicated by MCA_STATUS[43]: poison. Defined for all banks except legacy
816 * northbridge (bank 4).
817 * b) Refers to poison consumption in the core. Does not include "no action",
818 * "action optional", or "deferred" error severities.
819 * c) Will include a usable address so that immediate action can be taken.
820 * 3) Northbridge DRAM ECC errors
821 * a) Reported in legacy bank 4 with extended error code (XEC) 8.
822 * b) MCA_STATUS[43] is *not* defined as poison in legacy bank 4. Therefore,
823 * this bit should not be checked.
824 * 4) MCI_STATUS_PADDRVAL is set
825 * a) Will provide a valid system physical address.
826 *
827 * NOTE: SMCA UMC memory errors fall into case #1.
828 */
amd_mce_usable_address(struct mce * m)829 bool amd_mce_usable_address(struct mce *m)
830 {
831 /* Check special northbridge case 3) first. */
832 if (!mce_flags.smca) {
833 if (legacy_mce_is_memory_error(m))
834 return true;
835 else if (m->bank == 4)
836 return false;
837 }
838
839 if (this_cpu_ptr(smca_banks)[m->bank].paddrv)
840 return m->status & MCI_STATUS_PADDRV;
841
842 /* Check poison bit for all other bank types. */
843 if (m->status & MCI_STATUS_POISON)
844 return true;
845
846 /* Assume address is not usable for all others. */
847 return false;
848 }
849
DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)850 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)
851 {
852 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
853 inc_irq_stat(irq_deferred_error_count);
854 deferred_error_int_vector();
855 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
856 apic_eoi();
857 }
858
859 /* APIC interrupt handler for deferred errors */
amd_deferred_error_interrupt(void)860 static void amd_deferred_error_interrupt(void)
861 {
862 machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_banks);
863 }
864
mce_amd_handle_storm(unsigned int bank,bool on)865 void mce_amd_handle_storm(unsigned int bank, bool on)
866 {
867 threshold_restart_bank(bank, on);
868 }
869
amd_reset_thr_limit(unsigned int bank)870 static void amd_reset_thr_limit(unsigned int bank)
871 {
872 threshold_restart_bank(bank, true);
873 }
874
875 /*
876 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
877 * goes off when error_count reaches threshold_limit.
878 */
amd_threshold_interrupt(void)879 static void amd_threshold_interrupt(void)
880 {
881 machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->thr_intr_banks);
882 }
883
amd_clear_bank(struct mce * m)884 void amd_clear_bank(struct mce *m)
885 {
886 amd_reset_thr_limit(m->bank);
887
888 if (mce_flags.smca) {
889 /*
890 * Clear MCA_DESTAT for all deferred errors even those
891 * logged in MCA_STATUS.
892 */
893 if (m->status & MCI_STATUS_DEFERRED)
894 mce_wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(m->bank), 0);
895
896 /* Don't clear MCA_STATUS if MCA_DESTAT was used exclusively. */
897 if (m->kflags & MCE_CHECK_DFR_REGS)
898 return;
899 }
900
901 mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);
902 }
903
904 /*
905 * Sysfs Interface
906 */
907
908 struct threshold_attr {
909 struct attribute attr;
910 ssize_t (*show) (struct threshold_block *, char *);
911 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
912 };
913
914 #define SHOW_FIELDS(name) \
915 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
916 { \
917 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
918 }
919 SHOW_FIELDS(interrupt_enable)
SHOW_FIELDS(threshold_limit)920 SHOW_FIELDS(threshold_limit)
921
922 static ssize_t
923 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
924 {
925 struct thresh_restart tr;
926 unsigned long new;
927
928 if (!b->interrupt_capable)
929 return -EINVAL;
930
931 if (kstrtoul(buf, 0, &new) < 0)
932 return -EINVAL;
933
934 b->interrupt_enable = !!new;
935
936 memset(&tr, 0, sizeof(tr));
937 tr.b = b;
938
939 if (smp_call_function_single(b->cpu, threshold_restart_block, &tr, 1))
940 return -ENODEV;
941
942 return size;
943 }
944
945 static ssize_t
store_threshold_limit(struct threshold_block * b,const char * buf,size_t size)946 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
947 {
948 struct thresh_restart tr;
949 unsigned long new;
950
951 if (kstrtoul(buf, 0, &new) < 0)
952 return -EINVAL;
953
954 if (new > THRESHOLD_MAX)
955 new = THRESHOLD_MAX;
956 if (new < 1)
957 new = 1;
958
959 memset(&tr, 0, sizeof(tr));
960 tr.old_limit = b->threshold_limit;
961 b->threshold_limit = new;
962 tr.b = b;
963
964 if (smp_call_function_single(b->cpu, threshold_restart_block, &tr, 1))
965 return -ENODEV;
966
967 return size;
968 }
969
show_error_count(struct threshold_block * b,char * buf)970 static ssize_t show_error_count(struct threshold_block *b, char *buf)
971 {
972 u32 lo, hi;
973
974 /* CPU might be offline by now */
975 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi))
976 return -ENODEV;
977
978 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
979 (THRESHOLD_MAX - b->threshold_limit)));
980 }
981
982 static struct threshold_attr error_count = {
983 .attr = {.name = __stringify(error_count), .mode = 0444 },
984 .show = show_error_count,
985 };
986
987 #define RW_ATTR(val) \
988 static struct threshold_attr val = { \
989 .attr = {.name = __stringify(val), .mode = 0644 }, \
990 .show = show_## val, \
991 .store = store_## val, \
992 };
993
994 RW_ATTR(interrupt_enable);
995 RW_ATTR(threshold_limit);
996
997 static struct attribute *default_attrs[] = {
998 &threshold_limit.attr,
999 &error_count.attr,
1000 NULL, /* possibly interrupt_enable if supported, see below */
1001 NULL,
1002 };
1003 ATTRIBUTE_GROUPS(default);
1004
1005 #define to_block(k) container_of(k, struct threshold_block, kobj)
1006 #define to_attr(a) container_of(a, struct threshold_attr, attr)
1007
show(struct kobject * kobj,struct attribute * attr,char * buf)1008 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1009 {
1010 struct threshold_block *b = to_block(kobj);
1011 struct threshold_attr *a = to_attr(attr);
1012 ssize_t ret;
1013
1014 ret = a->show ? a->show(b, buf) : -EIO;
1015
1016 return ret;
1017 }
1018
store(struct kobject * kobj,struct attribute * attr,const char * buf,size_t count)1019 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1020 const char *buf, size_t count)
1021 {
1022 struct threshold_block *b = to_block(kobj);
1023 struct threshold_attr *a = to_attr(attr);
1024 ssize_t ret;
1025
1026 ret = a->store ? a->store(b, buf, count) : -EIO;
1027
1028 return ret;
1029 }
1030
1031 static const struct sysfs_ops threshold_ops = {
1032 .show = show,
1033 .store = store,
1034 };
1035
1036 static void threshold_block_release(struct kobject *kobj);
1037
1038 static const struct kobj_type threshold_ktype = {
1039 .sysfs_ops = &threshold_ops,
1040 .default_groups = default_groups,
1041 .release = threshold_block_release,
1042 };
1043
get_name(unsigned int cpu,unsigned int bank,struct threshold_block * b)1044 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b)
1045 {
1046 enum smca_bank_types bank_type;
1047
1048 if (!mce_flags.smca) {
1049 if (b && bank == 4)
1050 return bank4_names(b);
1051
1052 return th_names[bank];
1053 }
1054
1055 bank_type = smca_get_bank_type(cpu, bank);
1056
1057 if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) {
1058 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1059 return smca_umc_block_names[b->block];
1060 }
1061
1062 if (b && b->block) {
1063 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_block_%u", b->block);
1064 return buf_mcatype;
1065 }
1066
1067 if (bank_type >= N_SMCA_BANK_TYPES) {
1068 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_bank_%u", bank);
1069 return buf_mcatype;
1070 }
1071
1072 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1)
1073 return smca_get_name(bank_type);
1074
1075 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1076 "%s_%u", smca_get_name(bank_type),
1077 per_cpu(smca_banks, cpu)[bank].sysfs_id);
1078 return buf_mcatype;
1079 }
1080
allocate_threshold_blocks(unsigned int cpu,struct threshold_bank * tb,unsigned int bank,unsigned int block,u32 address)1081 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb,
1082 unsigned int bank, unsigned int block,
1083 u32 address)
1084 {
1085 struct threshold_block *b = NULL;
1086 u32 low, high;
1087 int err;
1088
1089 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
1090 return 0;
1091
1092 if (rdmsr_safe(address, &low, &high))
1093 return 0;
1094
1095 if (!(high & MASK_VALID_HI)) {
1096 if (block)
1097 goto recurse;
1098 else
1099 return 0;
1100 }
1101
1102 if (!(high & MASK_CNTP_HI) ||
1103 (high & MASK_LOCKED_HI))
1104 goto recurse;
1105
1106 b = kzalloc_obj(struct threshold_block);
1107 if (!b)
1108 return -ENOMEM;
1109
1110 b->block = block;
1111 b->bank = bank;
1112 b->cpu = cpu;
1113 b->address = address;
1114 b->interrupt_enable = 0;
1115 b->interrupt_capable = lvt_interrupt_supported(bank, high);
1116 b->threshold_limit = get_thr_limit();
1117
1118 if (b->interrupt_capable) {
1119 default_attrs[2] = &interrupt_enable.attr;
1120 b->interrupt_enable = 1;
1121 } else {
1122 default_attrs[2] = NULL;
1123 }
1124
1125 list_add(&b->miscj, &tb->miscj);
1126
1127 mce_threshold_block_init(b, (high & MASK_LVTOFF_HI) >> 20);
1128
1129 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
1130 if (err)
1131 goto out_free;
1132 recurse:
1133 address = get_block_address(address, low, high, bank, ++block, cpu);
1134 if (!address)
1135 return 0;
1136
1137 err = allocate_threshold_blocks(cpu, tb, bank, block, address);
1138 if (err)
1139 goto out_free;
1140
1141 if (b)
1142 kobject_uevent(&b->kobj, KOBJ_ADD);
1143
1144 return 0;
1145
1146 out_free:
1147 if (b) {
1148 list_del(&b->miscj);
1149 kobject_put(&b->kobj);
1150 }
1151 return err;
1152 }
1153
threshold_create_bank(struct threshold_bank ** bp,unsigned int cpu,unsigned int bank)1154 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
1155 unsigned int bank)
1156 {
1157 struct device *dev = this_cpu_read(mce_device);
1158 struct threshold_bank *b = NULL;
1159 const char *name = get_name(cpu, bank, NULL);
1160 int err = 0;
1161
1162 if (!dev)
1163 return -ENODEV;
1164
1165 b = kzalloc_obj(struct threshold_bank);
1166 if (!b) {
1167 err = -ENOMEM;
1168 goto out;
1169 }
1170
1171 /* Associate the bank with the per-CPU MCE device */
1172 b->kobj = kobject_create_and_add(name, &dev->kobj);
1173 if (!b->kobj) {
1174 err = -EINVAL;
1175 goto out_free;
1176 }
1177
1178 INIT_LIST_HEAD(&b->miscj);
1179
1180 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));
1181 if (err)
1182 goto out_kobj;
1183
1184 bp[bank] = b;
1185 return 0;
1186
1187 out_kobj:
1188 kobject_put(b->kobj);
1189 out_free:
1190 kfree(b);
1191 out:
1192 return err;
1193 }
1194
threshold_block_release(struct kobject * kobj)1195 static void threshold_block_release(struct kobject *kobj)
1196 {
1197 kfree(to_block(kobj));
1198 }
1199
threshold_remove_bank(struct threshold_bank * bank)1200 static void threshold_remove_bank(struct threshold_bank *bank)
1201 {
1202 struct threshold_block *pos, *tmp;
1203
1204 list_for_each_entry_safe(pos, tmp, &bank->miscj, miscj) {
1205 list_del(&pos->miscj);
1206 kobject_put(&pos->kobj);
1207 }
1208
1209 kobject_put(bank->kobj);
1210 kfree(bank);
1211 }
1212
__threshold_remove_device(struct threshold_bank ** bp)1213 static void __threshold_remove_device(struct threshold_bank **bp)
1214 {
1215 unsigned int bank, numbanks = this_cpu_read(mce_num_banks);
1216
1217 for (bank = 0; bank < numbanks; bank++) {
1218 if (!bp[bank])
1219 continue;
1220
1221 threshold_remove_bank(bp[bank]);
1222 bp[bank] = NULL;
1223 }
1224 kfree(bp);
1225 }
1226
mce_threshold_remove_device(unsigned int cpu)1227 void mce_threshold_remove_device(unsigned int cpu)
1228 {
1229 struct threshold_bank **bp = this_cpu_read(threshold_banks);
1230
1231 if (!bp)
1232 return;
1233
1234 /*
1235 * Clear the pointer before cleaning up, so that the interrupt won't
1236 * touch anything of this.
1237 */
1238 this_cpu_write(threshold_banks, NULL);
1239
1240 __threshold_remove_device(bp);
1241 return;
1242 }
1243
1244 /**
1245 * mce_threshold_create_device - Create the per-CPU MCE threshold device
1246 * @cpu: The plugged in CPU
1247 *
1248 * Create directories and files for all valid threshold banks.
1249 *
1250 * This is invoked from the CPU hotplug callback which was installed in
1251 * mcheck_init_device(). The invocation happens in context of the hotplug
1252 * thread running on @cpu. The callback is invoked on all CPUs which are
1253 * online when the callback is installed or during a real hotplug event.
1254 */
mce_threshold_create_device(unsigned int cpu)1255 void mce_threshold_create_device(unsigned int cpu)
1256 {
1257 unsigned int numbanks, bank;
1258 struct threshold_bank **bp;
1259
1260 if (!mce_flags.amd_threshold)
1261 return;
1262
1263 bp = this_cpu_read(threshold_banks);
1264 if (bp)
1265 return;
1266
1267 numbanks = this_cpu_read(mce_num_banks);
1268 bp = kzalloc_objs(*bp, numbanks);
1269 if (!bp)
1270 return;
1271
1272 for (bank = 0; bank < numbanks; ++bank) {
1273 if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))
1274 continue;
1275 if (threshold_create_bank(bp, cpu, bank)) {
1276 __threshold_remove_device(bp);
1277 return;
1278 }
1279 }
1280 this_cpu_write(threshold_banks, bp);
1281
1282 if (thresholding_irq_en)
1283 mce_threshold_vector = amd_threshold_interrupt;
1284 return;
1285 }
1286