1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J721E SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy.h> 8#include <dt-bindings/phy/phy-ti.h> 9#include <dt-bindings/mux/mux.h> 10 11#include "k3-serdes.h" 12 13/ { 14 cmn_refclk: clock-cmnrefclk { 15 #clock-cells = <0>; 16 compatible = "fixed-clock"; 17 clock-frequency = <0>; 18 }; 19 20 cmn_refclk1: clock-cmnrefclk1 { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <0>; 24 }; 25}; 26 27&cbass_main { 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x0 0x70000000 0x0 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x0 0x0 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x0 0x20000>; 37 }; 38 }; 39 40 scm_conf: scm-conf@100000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */ 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x00100000 0x1c000>; 46 47 pcie0_ctrl: pcie-ctrl@4070 { 48 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 49 reg = <0x4070 0x4>; 50 }; 51 52 pcie1_ctrl: pcie-ctrl@4074 { 53 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 54 reg = <0x4074 0x4>; 55 }; 56 57 pcie2_ctrl: pcie-ctrl@4078 { 58 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 59 reg = <0x4078 0x4>; 60 }; 61 62 pcie3_ctrl: pcie-ctrl@407c { 63 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 64 reg = <0x407c 0x4>; 65 }; 66 67 serdes_ln_ctrl: mux-controller@4080 { 68 compatible = "reg-mux"; 69 reg = <0x4080 0x50>; 70 #mux-control-cells = <1>; 71 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 72 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 73 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 74 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */ 75 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ 76 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ 77 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>, 78 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 79 <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 80 <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>, 81 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 82 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 83 }; 84 85 cpsw0_phy_gmii_sel: phy@4044 { 86 compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 87 ti,qsgmii-main-ports = <2>, <2>; 88 reg = <0x4044 0x20>; 89 #phy-cells = <1>; 90 }; 91 92 usb_serdes_mux: mux-controller@4000 { 93 compatible = "reg-mux"; 94 reg = <0x4000 0x20>; 95 #mux-control-cells = <1>; 96 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */ 97 <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */ 98 }; 99 100 ehrpwm_tbclk: clock-controller@4140 { 101 compatible = "ti,am654-ehrpwm-tbclk"; 102 reg = <0x4140 0x18>; 103 #clock-cells = <1>; 104 }; 105 }; 106 107 main_ehrpwm0: pwm@3000000 { 108 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 109 #pwm-cells = <3>; 110 reg = <0x00 0x3000000 0x00 0x100>; 111 power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; 112 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; 113 clock-names = "tbclk", "fck"; 114 status = "disabled"; 115 }; 116 117 main_ehrpwm1: pwm@3010000 { 118 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 119 #pwm-cells = <3>; 120 reg = <0x00 0x3010000 0x00 0x100>; 121 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; 123 clock-names = "tbclk", "fck"; 124 status = "disabled"; 125 }; 126 127 main_ehrpwm2: pwm@3020000 { 128 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 129 #pwm-cells = <3>; 130 reg = <0x00 0x3020000 0x00 0x100>; 131 power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; 132 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; 133 clock-names = "tbclk", "fck"; 134 status = "disabled"; 135 }; 136 137 main_ehrpwm3: pwm@3030000 { 138 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 139 #pwm-cells = <3>; 140 reg = <0x00 0x3030000 0x00 0x100>; 141 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 142 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; 143 clock-names = "tbclk", "fck"; 144 status = "disabled"; 145 }; 146 147 main_ehrpwm4: pwm@3040000 { 148 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 149 #pwm-cells = <3>; 150 reg = <0x00 0x3040000 0x00 0x100>; 151 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 152 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; 153 clock-names = "tbclk", "fck"; 154 status = "disabled"; 155 }; 156 157 main_ehrpwm5: pwm@3050000 { 158 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 159 #pwm-cells = <3>; 160 reg = <0x00 0x3050000 0x00 0x100>; 161 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 162 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; 163 clock-names = "tbclk", "fck"; 164 status = "disabled"; 165 }; 166 167 gic500: interrupt-controller@1800000 { 168 compatible = "arm,gic-v3"; 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 #interrupt-cells = <3>; 173 interrupt-controller; 174 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 175 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 176 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 177 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 178 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 179 180 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 181 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 182 183 gic_its: msi-controller@1820000 { 184 compatible = "arm,gic-v3-its"; 185 reg = <0x00 0x01820000 0x00 0x10000>; 186 socionext,synquacer-pre-its = <0x1000000 0x400000>; 187 msi-controller; 188 #msi-cells = <1>; 189 }; 190 }; 191 192 main_gpio_intr: interrupt-controller@a00000 { 193 compatible = "ti,sci-intr"; 194 reg = <0x00 0x00a00000 0x00 0x800>; 195 ti,intr-trigger-type = <1>; 196 interrupt-controller; 197 interrupt-parent = <&gic500>; 198 #interrupt-cells = <1>; 199 ti,sci = <&dmsc>; 200 ti,sci-dev-id = <131>; 201 ti,interrupt-ranges = <8 392 56>; 202 }; 203 204 main_navss: bus@30000000 { 205 compatible = "simple-bus"; 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 209 dma-coherent; 210 dma-ranges; 211 212 ti,sci-dev-id = <199>; 213 214 main_navss_intr: interrupt-controller@310e0000 { 215 compatible = "ti,sci-intr"; 216 reg = <0x0 0x310e0000 0x0 0x4000>; 217 ti,intr-trigger-type = <4>; 218 interrupt-controller; 219 interrupt-parent = <&gic500>; 220 #interrupt-cells = <1>; 221 ti,sci = <&dmsc>; 222 ti,sci-dev-id = <213>; 223 ti,interrupt-ranges = <0 64 64>, 224 <64 448 64>, 225 <128 672 64>; 226 }; 227 228 main_udmass_inta: interrupt-controller@33d00000 { 229 compatible = "ti,sci-inta"; 230 reg = <0x0 0x33d00000 0x0 0x100000>; 231 interrupt-controller; 232 interrupt-parent = <&main_navss_intr>; 233 msi-controller; 234 #interrupt-cells = <0>; 235 ti,sci = <&dmsc>; 236 ti,sci-dev-id = <209>; 237 ti,interrupt-ranges = <0 0 256>; 238 }; 239 240 secure_proxy_main: mailbox@32c00000 { 241 compatible = "ti,am654-secure-proxy"; 242 #mbox-cells = <1>; 243 reg-names = "target_data", "rt", "scfg"; 244 reg = <0x00 0x32c00000 0x00 0x100000>, 245 <0x00 0x32400000 0x00 0x100000>, 246 <0x00 0x32800000 0x00 0x100000>; 247 interrupt-names = "rx_011"; 248 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 249 bootph-all; 250 }; 251 252 smmu0: iommu@36600000 { 253 compatible = "arm,smmu-v3"; 254 reg = <0x0 0x36600000 0x0 0x100000>; 255 interrupt-parent = <&gic500>; 256 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>; 258 interrupt-names = "eventq", "gerror"; 259 #iommu-cells = <1>; 260 }; 261 262 hwspinlock: spinlock@30e00000 { 263 compatible = "ti,am654-hwspinlock"; 264 reg = <0x00 0x30e00000 0x00 0x1000>; 265 #hwlock-cells = <1>; 266 }; 267 268 mailbox0_cluster0: mailbox@31f80000 { 269 compatible = "ti,am654-mailbox"; 270 reg = <0x00 0x31f80000 0x00 0x200>; 271 #mbox-cells = <1>; 272 ti,mbox-num-users = <4>; 273 ti,mbox-num-fifos = <16>; 274 interrupt-parent = <&main_navss_intr>; 275 status = "disabled"; 276 }; 277 278 mailbox0_cluster1: mailbox@31f81000 { 279 compatible = "ti,am654-mailbox"; 280 reg = <0x00 0x31f81000 0x00 0x200>; 281 #mbox-cells = <1>; 282 ti,mbox-num-users = <4>; 283 ti,mbox-num-fifos = <16>; 284 interrupt-parent = <&main_navss_intr>; 285 status = "disabled"; 286 }; 287 288 mailbox0_cluster2: mailbox@31f82000 { 289 compatible = "ti,am654-mailbox"; 290 reg = <0x00 0x31f82000 0x00 0x200>; 291 #mbox-cells = <1>; 292 ti,mbox-num-users = <4>; 293 ti,mbox-num-fifos = <16>; 294 interrupt-parent = <&main_navss_intr>; 295 status = "disabled"; 296 }; 297 298 mailbox0_cluster3: mailbox@31f83000 { 299 compatible = "ti,am654-mailbox"; 300 reg = <0x00 0x31f83000 0x00 0x200>; 301 #mbox-cells = <1>; 302 ti,mbox-num-users = <4>; 303 ti,mbox-num-fifos = <16>; 304 interrupt-parent = <&main_navss_intr>; 305 status = "disabled"; 306 }; 307 308 mailbox0_cluster4: mailbox@31f84000 { 309 compatible = "ti,am654-mailbox"; 310 reg = <0x00 0x31f84000 0x00 0x200>; 311 #mbox-cells = <1>; 312 ti,mbox-num-users = <4>; 313 ti,mbox-num-fifos = <16>; 314 interrupt-parent = <&main_navss_intr>; 315 status = "disabled"; 316 }; 317 318 mailbox0_cluster5: mailbox@31f85000 { 319 compatible = "ti,am654-mailbox"; 320 reg = <0x00 0x31f85000 0x00 0x200>; 321 #mbox-cells = <1>; 322 ti,mbox-num-users = <4>; 323 ti,mbox-num-fifos = <16>; 324 interrupt-parent = <&main_navss_intr>; 325 status = "disabled"; 326 }; 327 328 mailbox0_cluster6: mailbox@31f86000 { 329 compatible = "ti,am654-mailbox"; 330 reg = <0x00 0x31f86000 0x00 0x200>; 331 #mbox-cells = <1>; 332 ti,mbox-num-users = <4>; 333 ti,mbox-num-fifos = <16>; 334 interrupt-parent = <&main_navss_intr>; 335 status = "disabled"; 336 }; 337 338 mailbox0_cluster7: mailbox@31f87000 { 339 compatible = "ti,am654-mailbox"; 340 reg = <0x00 0x31f87000 0x00 0x200>; 341 #mbox-cells = <1>; 342 ti,mbox-num-users = <4>; 343 ti,mbox-num-fifos = <16>; 344 interrupt-parent = <&main_navss_intr>; 345 status = "disabled"; 346 }; 347 348 mailbox0_cluster8: mailbox@31f88000 { 349 compatible = "ti,am654-mailbox"; 350 reg = <0x00 0x31f88000 0x00 0x200>; 351 #mbox-cells = <1>; 352 ti,mbox-num-users = <4>; 353 ti,mbox-num-fifos = <16>; 354 interrupt-parent = <&main_navss_intr>; 355 status = "disabled"; 356 }; 357 358 mailbox0_cluster9: mailbox@31f89000 { 359 compatible = "ti,am654-mailbox"; 360 reg = <0x00 0x31f89000 0x00 0x200>; 361 #mbox-cells = <1>; 362 ti,mbox-num-users = <4>; 363 ti,mbox-num-fifos = <16>; 364 interrupt-parent = <&main_navss_intr>; 365 status = "disabled"; 366 }; 367 368 mailbox0_cluster10: mailbox@31f8a000 { 369 compatible = "ti,am654-mailbox"; 370 reg = <0x00 0x31f8a000 0x00 0x200>; 371 #mbox-cells = <1>; 372 ti,mbox-num-users = <4>; 373 ti,mbox-num-fifos = <16>; 374 interrupt-parent = <&main_navss_intr>; 375 status = "disabled"; 376 }; 377 378 mailbox0_cluster11: mailbox@31f8b000 { 379 compatible = "ti,am654-mailbox"; 380 reg = <0x00 0x31f8b000 0x00 0x200>; 381 #mbox-cells = <1>; 382 ti,mbox-num-users = <4>; 383 ti,mbox-num-fifos = <16>; 384 interrupt-parent = <&main_navss_intr>; 385 status = "disabled"; 386 }; 387 388 main_ringacc: ringacc@3c000000 { 389 compatible = "ti,am654-navss-ringacc"; 390 reg = <0x0 0x3c000000 0x0 0x400000>, 391 <0x0 0x38000000 0x0 0x400000>, 392 <0x0 0x31120000 0x0 0x100>, 393 <0x0 0x33000000 0x0 0x40000>, 394 <0x0 0x31080000 0x0 0x40000>; 395 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 396 ti,num-rings = <1024>; 397 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 398 ti,sci = <&dmsc>; 399 ti,sci-dev-id = <211>; 400 msi-parent = <&main_udmass_inta>; 401 }; 402 403 main_udmap: dma-controller@31150000 { 404 compatible = "ti,j721e-navss-main-udmap"; 405 reg = <0x0 0x31150000 0x0 0x100>, 406 <0x0 0x34000000 0x0 0x100000>, 407 <0x0 0x35000000 0x0 0x100000>, 408 <0x0 0x30b00000 0x0 0x20000>, 409 <0x0 0x30c00000 0x0 0x10000>, 410 <0x0 0x30d00000 0x0 0x8000>; 411 reg-names = "gcfg", "rchanrt", "tchanrt", 412 "tchan", "rchan", "rflow"; 413 msi-parent = <&main_udmass_inta>; 414 #dma-cells = <1>; 415 416 ti,sci = <&dmsc>; 417 ti,sci-dev-id = <212>; 418 ti,ringacc = <&main_ringacc>; 419 420 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 421 <0x0f>, /* TX_HCHAN */ 422 <0x10>; /* TX_UHCHAN */ 423 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 424 <0x0b>, /* RX_HCHAN */ 425 <0x0c>; /* RX_UHCHAN */ 426 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 427 }; 428 429 cpts@310d0000 { 430 compatible = "ti,j721e-cpts"; 431 reg = <0x0 0x310d0000 0x0 0x400>; 432 reg-names = "cpts"; 433 clocks = <&k3_clks 201 1>; 434 clock-names = "cpts"; 435 interrupts-extended = <&main_navss_intr 391>; 436 interrupt-names = "cpts"; 437 ti,cpts-periodic-outputs = <6>; 438 ti,cpts-ext-ts-inputs = <8>; 439 }; 440 }; 441 442 cpsw0: ethernet@c000000 { 443 compatible = "ti,j721e-cpswxg-nuss"; 444 #address-cells = <2>; 445 #size-cells = <2>; 446 reg = <0x0 0xc000000 0x0 0x200000>; 447 reg-names = "cpsw_nuss"; 448 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 449 clocks = <&k3_clks 19 89>; 450 clock-names = "fck"; 451 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 452 453 dmas = <&main_udmap 0xca00>, 454 <&main_udmap 0xca01>, 455 <&main_udmap 0xca02>, 456 <&main_udmap 0xca03>, 457 <&main_udmap 0xca04>, 458 <&main_udmap 0xca05>, 459 <&main_udmap 0xca06>, 460 <&main_udmap 0xca07>, 461 <&main_udmap 0x4a00>; 462 dma-names = "tx0", "tx1", "tx2", "tx3", 463 "tx4", "tx5", "tx6", "tx7", 464 "rx"; 465 466 status = "disabled"; 467 468 ethernet-ports { 469 #address-cells = <1>; 470 #size-cells = <0>; 471 cpsw0_port1: port@1 { 472 reg = <1>; 473 ti,mac-only; 474 label = "port1"; 475 status = "disabled"; 476 }; 477 478 cpsw0_port2: port@2 { 479 reg = <2>; 480 ti,mac-only; 481 label = "port2"; 482 status = "disabled"; 483 }; 484 485 cpsw0_port3: port@3 { 486 reg = <3>; 487 ti,mac-only; 488 label = "port3"; 489 status = "disabled"; 490 }; 491 492 cpsw0_port4: port@4 { 493 reg = <4>; 494 ti,mac-only; 495 label = "port4"; 496 status = "disabled"; 497 }; 498 499 cpsw0_port5: port@5 { 500 reg = <5>; 501 ti,mac-only; 502 label = "port5"; 503 status = "disabled"; 504 }; 505 506 cpsw0_port6: port@6 { 507 reg = <6>; 508 ti,mac-only; 509 label = "port6"; 510 status = "disabled"; 511 }; 512 513 cpsw0_port7: port@7 { 514 reg = <7>; 515 ti,mac-only; 516 label = "port7"; 517 status = "disabled"; 518 }; 519 520 cpsw0_port8: port@8 { 521 reg = <8>; 522 ti,mac-only; 523 label = "port8"; 524 status = "disabled"; 525 }; 526 }; 527 528 cpsw9g_mdio: mdio@f00 { 529 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 530 reg = <0x0 0xf00 0x0 0x100>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 clocks = <&k3_clks 19 89>; 534 clock-names = "fck"; 535 bus_freq = <1000000>; 536 status = "disabled"; 537 }; 538 539 cpts@3d000 { 540 compatible = "ti,j721e-cpts"; 541 reg = <0x0 0x3d000 0x0 0x400>; 542 clocks = <&k3_clks 19 16>; 543 clock-names = "cpts"; 544 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 545 interrupt-names = "cpts"; 546 ti,cpts-ext-ts-inputs = <4>; 547 ti,cpts-periodic-outputs = <2>; 548 }; 549 }; 550 551 main_crypto: crypto@4e00000 { 552 compatible = "ti,j721e-sa2ul"; 553 reg = <0x0 0x4e00000 0x0 0x1200>; 554 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 555 #address-cells = <2>; 556 #size-cells = <2>; 557 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 558 559 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 560 <&main_udmap 0x4001>; 561 dma-names = "tx", "rx1", "rx2"; 562 563 rng: rng@4e10000 { 564 compatible = "inside-secure,safexcel-eip76"; 565 reg = <0x0 0x4e10000 0x0 0x7d>; 566 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 567 }; 568 }; 569 570 main_pmx0: pinctrl@11c000 { 571 compatible = "pinctrl-single"; 572 /* Proxy 0 addressing */ 573 reg = <0x0 0x11c000 0x0 0x2b4>; 574 #pinctrl-cells = <1>; 575 pinctrl-single,register-width = <32>; 576 pinctrl-single,function-mask = <0xffffffff>; 577 }; 578 579 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 580 main_timerio_input: pinctrl@104200 { 581 compatible = "pinctrl-single"; 582 reg = <0x00 0x104200 0x00 0x50>; 583 #pinctrl-cells = <1>; 584 pinctrl-single,register-width = <32>; 585 pinctrl-single,function-mask = <0x00000007>; 586 }; 587 588 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 589 main_timerio_output: pinctrl@104280 { 590 compatible = "pinctrl-single"; 591 reg = <0x00 0x104280 0x00 0x20>; 592 #pinctrl-cells = <1>; 593 pinctrl-single,register-width = <32>; 594 pinctrl-single,function-mask = <0x0000001f>; 595 }; 596 597 ti_csi2rx0: ticsi2rx@4500000 { 598 compatible = "ti,j721e-csi2rx-shim"; 599 reg = <0x0 0x4500000 0x0 0x1000>; 600 ranges; 601 #address-cells = <2>; 602 #size-cells = <2>; 603 dmas = <&main_udmap 0x4940>; 604 dma-names = "rx0"; 605 power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; 606 status = "disabled"; 607 608 cdns_csi2rx0: csi-bridge@4504000 { 609 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 610 reg = <0x0 0x4504000 0x0 0x1000>; 611 clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, 612 <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; 613 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 614 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 615 phys = <&dphy0>; 616 phy-names = "dphy"; 617 618 ports { 619 #address-cells = <1>; 620 #size-cells = <0>; 621 622 csi0_port0: port@0 { 623 reg = <0>; 624 status = "disabled"; 625 }; 626 627 csi0_port1: port@1 { 628 reg = <1>; 629 status = "disabled"; 630 }; 631 632 csi0_port2: port@2 { 633 reg = <2>; 634 status = "disabled"; 635 }; 636 637 csi0_port3: port@3 { 638 reg = <3>; 639 status = "disabled"; 640 }; 641 642 csi0_port4: port@4 { 643 reg = <4>; 644 status = "disabled"; 645 }; 646 }; 647 }; 648 }; 649 650 ti_csi2rx1: ticsi2rx@4510000 { 651 compatible = "ti,j721e-csi2rx-shim"; 652 reg = <0x0 0x4510000 0x0 0x1000>; 653 ranges; 654 #address-cells = <2>; 655 #size-cells = <2>; 656 dmas = <&main_udmap 0x4960>; 657 dma-names = "rx0"; 658 power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; 659 status = "disabled"; 660 661 cdns_csi2rx1: csi-bridge@4514000 { 662 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 663 reg = <0x0 0x4514000 0x0 0x1000>; 664 clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, 665 <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; 666 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 667 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 668 phys = <&dphy1>; 669 phy-names = "dphy"; 670 671 ports { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 675 csi1_port0: port@0 { 676 reg = <0>; 677 status = "disabled"; 678 }; 679 680 csi1_port1: port@1 { 681 reg = <1>; 682 status = "disabled"; 683 }; 684 685 csi1_port2: port@2 { 686 reg = <2>; 687 status = "disabled"; 688 }; 689 690 csi1_port3: port@3 { 691 reg = <3>; 692 status = "disabled"; 693 }; 694 695 csi1_port4: port@4 { 696 reg = <4>; 697 status = "disabled"; 698 }; 699 }; 700 }; 701 }; 702 703 dphy0: phy@4580000 { 704 compatible = "cdns,dphy-rx"; 705 reg = <0x0 0x4580000 0x0 0x1100>; 706 #phy-cells = <0>; 707 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 708 status = "disabled"; 709 }; 710 711 dphy1: phy@4590000 { 712 compatible = "cdns,dphy-rx"; 713 reg = <0x0 0x4590000 0x0 0x1100>; 714 #phy-cells = <0>; 715 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 716 status = "disabled"; 717 }; 718 719 serdes_wiz0: wiz@5000000 { 720 compatible = "ti,j721e-wiz-16g"; 721 #address-cells = <1>; 722 #size-cells = <1>; 723 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 724 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>; 725 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 726 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 727 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 728 num-lanes = <2>; 729 #reset-cells = <1>; 730 ranges = <0x5000000 0x0 0x5000000 0x10000>; 731 732 wiz0_pll0_refclk: pll0-refclk { 733 clocks = <&k3_clks 292 11>, <&cmn_refclk>; 734 #clock-cells = <0>; 735 assigned-clocks = <&wiz0_pll0_refclk>; 736 assigned-clock-parents = <&k3_clks 292 11>; 737 }; 738 739 wiz0_pll1_refclk: pll1-refclk { 740 clocks = <&k3_clks 292 0>, <&cmn_refclk1>; 741 #clock-cells = <0>; 742 assigned-clocks = <&wiz0_pll1_refclk>; 743 assigned-clock-parents = <&k3_clks 292 0>; 744 }; 745 746 wiz0_refclk_dig: refclk-dig { 747 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>; 748 #clock-cells = <0>; 749 assigned-clocks = <&wiz0_refclk_dig>; 750 assigned-clock-parents = <&k3_clks 292 11>; 751 }; 752 753 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 754 clocks = <&wiz0_refclk_dig>; 755 #clock-cells = <0>; 756 }; 757 758 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 759 clocks = <&wiz0_pll1_refclk>; 760 #clock-cells = <0>; 761 }; 762 763 serdes0: serdes@5000000 { 764 compatible = "ti,sierra-phy-t0"; 765 reg-names = "serdes"; 766 reg = <0x5000000 0x10000>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 #clock-cells = <1>; 770 resets = <&serdes_wiz0 0>; 771 reset-names = "sierra_reset"; 772 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, 773 <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>; 774 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 775 "pll0_refclk", "pll1_refclk"; 776 }; 777 }; 778 779 serdes_wiz1: wiz@5010000 { 780 compatible = "ti,j721e-wiz-16g"; 781 #address-cells = <1>; 782 #size-cells = <1>; 783 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>; 784 clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>; 785 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 786 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>; 787 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>; 788 num-lanes = <2>; 789 #reset-cells = <1>; 790 ranges = <0x5010000 0x0 0x5010000 0x10000>; 791 792 wiz1_pll0_refclk: pll0-refclk { 793 clocks = <&k3_clks 293 13>, <&cmn_refclk>; 794 #clock-cells = <0>; 795 assigned-clocks = <&wiz1_pll0_refclk>; 796 assigned-clock-parents = <&k3_clks 293 13>; 797 }; 798 799 wiz1_pll1_refclk: pll1-refclk { 800 clocks = <&k3_clks 293 0>, <&cmn_refclk1>; 801 #clock-cells = <0>; 802 assigned-clocks = <&wiz1_pll1_refclk>; 803 assigned-clock-parents = <&k3_clks 293 0>; 804 }; 805 806 wiz1_refclk_dig: refclk-dig { 807 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>; 808 #clock-cells = <0>; 809 assigned-clocks = <&wiz1_refclk_dig>; 810 assigned-clock-parents = <&k3_clks 293 13>; 811 }; 812 813 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { 814 clocks = <&wiz1_refclk_dig>; 815 #clock-cells = <0>; 816 }; 817 818 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 819 clocks = <&wiz1_pll1_refclk>; 820 #clock-cells = <0>; 821 }; 822 823 serdes1: serdes@5010000 { 824 compatible = "ti,sierra-phy-t0"; 825 reg-names = "serdes"; 826 reg = <0x5010000 0x10000>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 #clock-cells = <1>; 830 resets = <&serdes_wiz1 0>; 831 reset-names = "sierra_reset"; 832 clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, 833 <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>; 834 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 835 "pll0_refclk", "pll1_refclk"; 836 }; 837 }; 838 839 serdes_wiz2: wiz@5020000 { 840 compatible = "ti,j721e-wiz-16g"; 841 #address-cells = <1>; 842 #size-cells = <1>; 843 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>; 844 clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>; 845 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 846 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>; 847 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>; 848 num-lanes = <2>; 849 #reset-cells = <1>; 850 ranges = <0x5020000 0x0 0x5020000 0x10000>; 851 852 wiz2_pll0_refclk: pll0-refclk { 853 clocks = <&k3_clks 294 11>, <&cmn_refclk>; 854 #clock-cells = <0>; 855 assigned-clocks = <&wiz2_pll0_refclk>; 856 assigned-clock-parents = <&k3_clks 294 11>; 857 }; 858 859 wiz2_pll1_refclk: pll1-refclk { 860 clocks = <&k3_clks 294 0>, <&cmn_refclk1>; 861 #clock-cells = <0>; 862 assigned-clocks = <&wiz2_pll1_refclk>; 863 assigned-clock-parents = <&k3_clks 294 0>; 864 }; 865 866 wiz2_refclk_dig: refclk-dig { 867 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>; 868 #clock-cells = <0>; 869 assigned-clocks = <&wiz2_refclk_dig>; 870 assigned-clock-parents = <&k3_clks 294 11>; 871 }; 872 873 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div { 874 clocks = <&wiz2_refclk_dig>; 875 #clock-cells = <0>; 876 }; 877 878 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 879 clocks = <&wiz2_pll1_refclk>; 880 #clock-cells = <0>; 881 }; 882 883 serdes2: serdes@5020000 { 884 compatible = "ti,sierra-phy-t0"; 885 reg-names = "serdes"; 886 reg = <0x5020000 0x10000>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 #clock-cells = <1>; 890 resets = <&serdes_wiz2 0>; 891 reset-names = "sierra_reset"; 892 clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, 893 <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>; 894 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 895 "pll0_refclk", "pll1_refclk"; 896 }; 897 }; 898 899 serdes_wiz3: wiz@5030000 { 900 compatible = "ti,j721e-wiz-16g"; 901 #address-cells = <1>; 902 #size-cells = <1>; 903 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>; 904 clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>; 905 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 906 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>; 907 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>; 908 num-lanes = <2>; 909 #reset-cells = <1>; 910 ranges = <0x5030000 0x0 0x5030000 0x10000>; 911 912 wiz3_pll0_refclk: pll0-refclk { 913 clocks = <&k3_clks 295 9>, <&cmn_refclk>; 914 #clock-cells = <0>; 915 assigned-clocks = <&wiz3_pll0_refclk>; 916 assigned-clock-parents = <&k3_clks 295 9>; 917 }; 918 919 wiz3_pll1_refclk: pll1-refclk { 920 clocks = <&k3_clks 295 0>, <&cmn_refclk1>; 921 #clock-cells = <0>; 922 assigned-clocks = <&wiz3_pll1_refclk>; 923 assigned-clock-parents = <&k3_clks 295 0>; 924 }; 925 926 wiz3_refclk_dig: refclk-dig { 927 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>; 928 #clock-cells = <0>; 929 assigned-clocks = <&wiz3_refclk_dig>; 930 assigned-clock-parents = <&k3_clks 295 9>; 931 }; 932 933 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div { 934 clocks = <&wiz3_refclk_dig>; 935 #clock-cells = <0>; 936 }; 937 938 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div { 939 clocks = <&wiz3_pll1_refclk>; 940 #clock-cells = <0>; 941 }; 942 943 serdes3: serdes@5030000 { 944 compatible = "ti,sierra-phy-t0"; 945 reg-names = "serdes"; 946 reg = <0x5030000 0x10000>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 #clock-cells = <1>; 950 resets = <&serdes_wiz3 0>; 951 reset-names = "sierra_reset"; 952 clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, 953 <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>; 954 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", 955 "pll0_refclk", "pll1_refclk"; 956 }; 957 }; 958 959 pcie0_rc: pcie@2900000 { 960 compatible = "ti,j721e-pcie-host"; 961 reg = <0x00 0x02900000 0x00 0x1000>, 962 <0x00 0x02907000 0x00 0x400>, 963 <0x00 0x0d000000 0x00 0x00800000>, 964 <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 965 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 966 interrupt-names = "link_state"; 967 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 968 device_type = "pci"; 969 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 970 max-link-speed = <3>; 971 num-lanes = <2>; 972 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 973 clocks = <&k3_clks 239 1>; 974 clock-names = "fck"; 975 #address-cells = <3>; 976 #size-cells = <2>; 977 bus-range = <0x0 0xff>; 978 vendor-id = <0x104c>; 979 device-id = <0xb00d>; 980 msi-map = <0x0 &gic_its 0x0 0x10000>; 981 dma-coherent; 982 ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 983 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 984 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 985 status = "disabled"; 986 }; 987 988 pcie1_rc: pcie@2910000 { 989 compatible = "ti,j721e-pcie-host"; 990 reg = <0x00 0x02910000 0x00 0x1000>, 991 <0x00 0x02917000 0x00 0x400>, 992 <0x00 0x0d800000 0x00 0x00800000>, 993 <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ 994 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 995 interrupt-names = "link_state"; 996 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 997 device_type = "pci"; 998 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 999 max-link-speed = <3>; 1000 num-lanes = <2>; 1001 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 1002 clocks = <&k3_clks 240 1>; 1003 clock-names = "fck"; 1004 #address-cells = <3>; 1005 #size-cells = <2>; 1006 bus-range = <0x0 0xff>; 1007 vendor-id = <0x104c>; 1008 device-id = <0xb00d>; 1009 msi-map = <0x0 &gic_its 0x10000 0x10000>; 1010 dma-coherent; 1011 ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */ 1012 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ 1013 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1014 status = "disabled"; 1015 }; 1016 1017 pcie2_rc: pcie@2920000 { 1018 compatible = "ti,j721e-pcie-host"; 1019 reg = <0x00 0x02920000 0x00 0x1000>, 1020 <0x00 0x02927000 0x00 0x400>, 1021 <0x00 0x0e000000 0x00 0x00800000>, 1022 <0x44 0x00000000 0x00 0x00001000>; 1023 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1024 interrupt-names = "link_state"; 1025 interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>; 1026 device_type = "pci"; 1027 ti,syscon-pcie-ctrl = <&pcie2_ctrl 0x0>; 1028 max-link-speed = <3>; 1029 num-lanes = <2>; 1030 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 1031 clocks = <&k3_clks 241 1>; 1032 clock-names = "fck"; 1033 #address-cells = <3>; 1034 #size-cells = <2>; 1035 bus-range = <0x0 0xff>; 1036 vendor-id = <0x104c>; 1037 device-id = <0xb00d>; 1038 msi-map = <0x0 &gic_its 0x20000 0x10000>; 1039 dma-coherent; 1040 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, 1041 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; 1042 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1043 status = "disabled"; 1044 }; 1045 1046 pcie3_rc: pcie@2930000 { 1047 compatible = "ti,j721e-pcie-host"; 1048 reg = <0x00 0x02930000 0x00 0x1000>, 1049 <0x00 0x02937000 0x00 0x400>, 1050 <0x00 0x0e800000 0x00 0x00800000>, 1051 <0x44 0x10000000 0x00 0x00001000>; 1052 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1053 interrupt-names = "link_state"; 1054 interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>; 1055 device_type = "pci"; 1056 ti,syscon-pcie-ctrl = <&pcie3_ctrl 0x0>; 1057 max-link-speed = <3>; 1058 num-lanes = <2>; 1059 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 1060 clocks = <&k3_clks 242 1>; 1061 clock-names = "fck"; 1062 #address-cells = <3>; 1063 #size-cells = <2>; 1064 bus-range = <0x0 0xff>; 1065 vendor-id = <0x104c>; 1066 device-id = <0xb00d>; 1067 msi-map = <0x0 &gic_its 0x30000 0x10000>; 1068 dma-coherent; 1069 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, 1070 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; 1071 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1072 status = "disabled"; 1073 }; 1074 1075 serdes_wiz4: wiz@5050000 { 1076 compatible = "ti,am64-wiz-10g"; 1077 #address-cells = <1>; 1078 #size-cells = <1>; 1079 power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; 1080 clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; 1081 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 1082 assigned-clocks = <&k3_clks 297 9>; 1083 assigned-clock-parents = <&k3_clks 297 10>; 1084 assigned-clock-rates = <19200000>; 1085 num-lanes = <4>; 1086 #reset-cells = <1>; 1087 #clock-cells = <1>; 1088 ranges = <0x05050000 0x00 0x05050000 0x010000>, 1089 <0x0a030a00 0x00 0x0a030a00 0x40>; 1090 1091 serdes4: serdes@5050000 { 1092 /* 1093 * Note: we also map DPTX PHY registers as the Torrent 1094 * needs to manage those. 1095 */ 1096 compatible = "ti,j721e-serdes-10g"; 1097 reg = <0x05050000 0x010000>, 1098 <0x0a030a00 0x40>; /* DPTX PHY */ 1099 reg-names = "torrent_phy", "dptx_phy"; 1100 1101 resets = <&serdes_wiz4 0>; 1102 reset-names = "torrent_reset"; 1103 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; 1104 clock-names = "refclk"; 1105 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1106 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1107 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1108 assigned-clock-parents = <&k3_clks 297 9>, 1109 <&k3_clks 297 9>, 1110 <&k3_clks 297 9>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 }; 1114 }; 1115 1116 main_timer0: timer@2400000 { 1117 compatible = "ti,am654-timer"; 1118 reg = <0x00 0x2400000 0x00 0x400>; 1119 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&k3_clks 49 1>; 1121 clock-names = "fck"; 1122 assigned-clocks = <&k3_clks 49 1>; 1123 assigned-clock-parents = <&k3_clks 49 2>; 1124 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; 1125 ti,timer-pwm; 1126 }; 1127 1128 main_timer1: timer@2410000 { 1129 compatible = "ti,am654-timer"; 1130 reg = <0x00 0x2410000 0x00 0x400>; 1131 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&k3_clks 50 1>; 1133 clock-names = "fck"; 1134 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; 1135 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; 1136 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; 1137 ti,timer-pwm; 1138 }; 1139 1140 main_timer2: timer@2420000 { 1141 compatible = "ti,am654-timer"; 1142 reg = <0x00 0x2420000 0x00 0x400>; 1143 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&k3_clks 51 1>; 1145 clock-names = "fck"; 1146 assigned-clocks = <&k3_clks 51 1>; 1147 assigned-clock-parents = <&k3_clks 51 2>; 1148 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1149 ti,timer-pwm; 1150 }; 1151 1152 main_timer3: timer@2430000 { 1153 compatible = "ti,am654-timer"; 1154 reg = <0x00 0x2430000 0x00 0x400>; 1155 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&k3_clks 52 1>; 1157 clock-names = "fck"; 1158 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; 1159 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; 1160 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1161 ti,timer-pwm; 1162 }; 1163 1164 main_timer4: timer@2440000 { 1165 compatible = "ti,am654-timer"; 1166 reg = <0x00 0x2440000 0x00 0x400>; 1167 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&k3_clks 53 1>; 1169 clock-names = "fck"; 1170 assigned-clocks = <&k3_clks 53 1>; 1171 assigned-clock-parents = <&k3_clks 53 2>; 1172 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1173 ti,timer-pwm; 1174 }; 1175 1176 main_timer5: timer@2450000 { 1177 compatible = "ti,am654-timer"; 1178 reg = <0x00 0x2450000 0x00 0x400>; 1179 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&k3_clks 54 1>; 1181 clock-names = "fck"; 1182 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; 1183 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; 1184 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1185 ti,timer-pwm; 1186 }; 1187 1188 main_timer6: timer@2460000 { 1189 compatible = "ti,am654-timer"; 1190 reg = <0x00 0x2460000 0x00 0x400>; 1191 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&k3_clks 55 1>; 1193 clock-names = "fck"; 1194 assigned-clocks = <&k3_clks 55 1>; 1195 assigned-clock-parents = <&k3_clks 55 2>; 1196 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; 1197 ti,timer-pwm; 1198 }; 1199 1200 main_timer7: timer@2470000 { 1201 compatible = "ti,am654-timer"; 1202 reg = <0x00 0x2470000 0x00 0x400>; 1203 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&k3_clks 57 1>; 1205 clock-names = "fck"; 1206 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; 1207 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; 1208 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 1209 ti,timer-pwm; 1210 }; 1211 1212 main_timer8: timer@2480000 { 1213 compatible = "ti,am654-timer"; 1214 reg = <0x00 0x2480000 0x00 0x400>; 1215 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&k3_clks 58 1>; 1217 clock-names = "fck"; 1218 assigned-clocks = <&k3_clks 58 1>; 1219 assigned-clock-parents = <&k3_clks 58 2>; 1220 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 1221 ti,timer-pwm; 1222 }; 1223 1224 main_timer9: timer@2490000 { 1225 compatible = "ti,am654-timer"; 1226 reg = <0x00 0x2490000 0x00 0x400>; 1227 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&k3_clks 59 1>; 1229 clock-names = "fck"; 1230 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; 1231 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; 1232 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 1233 ti,timer-pwm; 1234 }; 1235 1236 main_timer10: timer@24a0000 { 1237 compatible = "ti,am654-timer"; 1238 reg = <0x00 0x24a0000 0x00 0x400>; 1239 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&k3_clks 60 1>; 1241 clock-names = "fck"; 1242 assigned-clocks = <&k3_clks 60 1>; 1243 assigned-clock-parents = <&k3_clks 60 2>; 1244 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 1245 ti,timer-pwm; 1246 }; 1247 1248 main_timer11: timer@24b0000 { 1249 compatible = "ti,am654-timer"; 1250 reg = <0x00 0x24b0000 0x00 0x400>; 1251 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&k3_clks 62 1>; 1253 clock-names = "fck"; 1254 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; 1255 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; 1256 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1257 ti,timer-pwm; 1258 }; 1259 1260 main_timer12: timer@24c0000 { 1261 compatible = "ti,am654-timer"; 1262 reg = <0x00 0x24c0000 0x00 0x400>; 1263 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&k3_clks 63 1>; 1265 clock-names = "fck"; 1266 assigned-clocks = <&k3_clks 63 1>; 1267 assigned-clock-parents = <&k3_clks 63 2>; 1268 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1269 ti,timer-pwm; 1270 }; 1271 1272 main_timer13: timer@24d0000 { 1273 compatible = "ti,am654-timer"; 1274 reg = <0x00 0x24d0000 0x00 0x400>; 1275 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&k3_clks 64 1>; 1277 clock-names = "fck"; 1278 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; 1279 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; 1280 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1281 ti,timer-pwm; 1282 }; 1283 1284 main_timer14: timer@24e0000 { 1285 compatible = "ti,am654-timer"; 1286 reg = <0x00 0x24e0000 0x00 0x400>; 1287 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&k3_clks 65 1>; 1289 clock-names = "fck"; 1290 assigned-clocks = <&k3_clks 65 1>; 1291 assigned-clock-parents = <&k3_clks 65 2>; 1292 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; 1293 ti,timer-pwm; 1294 }; 1295 1296 main_timer15: timer@24f0000 { 1297 compatible = "ti,am654-timer"; 1298 reg = <0x00 0x24f0000 0x00 0x400>; 1299 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&k3_clks 66 1>; 1301 clock-names = "fck"; 1302 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; 1303 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; 1304 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; 1305 ti,timer-pwm; 1306 }; 1307 1308 main_timer16: timer@2500000 { 1309 compatible = "ti,am654-timer"; 1310 reg = <0x00 0x2500000 0x00 0x400>; 1311 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&k3_clks 67 1>; 1313 clock-names = "fck"; 1314 assigned-clocks = <&k3_clks 67 1>; 1315 assigned-clock-parents = <&k3_clks 67 2>; 1316 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 1317 ti,timer-pwm; 1318 }; 1319 1320 main_timer17: timer@2510000 { 1321 compatible = "ti,am654-timer"; 1322 reg = <0x00 0x2510000 0x00 0x400>; 1323 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1324 clocks = <&k3_clks 68 1>; 1325 clock-names = "fck"; 1326 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; 1327 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; 1328 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; 1329 ti,timer-pwm; 1330 }; 1331 1332 main_timer18: timer@2520000 { 1333 compatible = "ti,am654-timer"; 1334 reg = <0x00 0x2520000 0x00 0x400>; 1335 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1336 clocks = <&k3_clks 69 1>; 1337 clock-names = "fck"; 1338 assigned-clocks = <&k3_clks 69 1>; 1339 assigned-clock-parents = <&k3_clks 69 2>; 1340 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; 1341 ti,timer-pwm; 1342 }; 1343 1344 main_timer19: timer@2530000 { 1345 compatible = "ti,am654-timer"; 1346 reg = <0x00 0x2530000 0x00 0x400>; 1347 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&k3_clks 70 1>; 1349 clock-names = "fck"; 1350 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; 1351 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; 1352 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; 1353 ti,timer-pwm; 1354 }; 1355 1356 main_uart0: serial@2800000 { 1357 compatible = "ti,j721e-uart", "ti,am654-uart"; 1358 reg = <0x00 0x02800000 0x00 0x100>; 1359 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1360 clock-frequency = <48000000>; 1361 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 1362 clocks = <&k3_clks 146 0>; 1363 clock-names = "fclk"; 1364 status = "disabled"; 1365 }; 1366 1367 main_uart1: serial@2810000 { 1368 compatible = "ti,j721e-uart", "ti,am654-uart"; 1369 reg = <0x00 0x02810000 0x00 0x100>; 1370 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1371 clock-frequency = <48000000>; 1372 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 1373 clocks = <&k3_clks 278 0>; 1374 clock-names = "fclk"; 1375 status = "disabled"; 1376 }; 1377 1378 main_uart2: serial@2820000 { 1379 compatible = "ti,j721e-uart", "ti,am654-uart"; 1380 reg = <0x00 0x02820000 0x00 0x100>; 1381 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1382 clock-frequency = <48000000>; 1383 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 1384 clocks = <&k3_clks 279 0>; 1385 clock-names = "fclk"; 1386 status = "disabled"; 1387 }; 1388 1389 main_uart3: serial@2830000 { 1390 compatible = "ti,j721e-uart", "ti,am654-uart"; 1391 reg = <0x00 0x02830000 0x00 0x100>; 1392 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1393 clock-frequency = <48000000>; 1394 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 1395 clocks = <&k3_clks 280 0>; 1396 clock-names = "fclk"; 1397 status = "disabled"; 1398 }; 1399 1400 main_uart4: serial@2840000 { 1401 compatible = "ti,j721e-uart", "ti,am654-uart"; 1402 reg = <0x00 0x02840000 0x00 0x100>; 1403 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1404 clock-frequency = <48000000>; 1405 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 1406 clocks = <&k3_clks 281 0>; 1407 clock-names = "fclk"; 1408 status = "disabled"; 1409 }; 1410 1411 main_uart5: serial@2850000 { 1412 compatible = "ti,j721e-uart", "ti,am654-uart"; 1413 reg = <0x00 0x02850000 0x00 0x100>; 1414 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1415 clock-frequency = <48000000>; 1416 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 1417 clocks = <&k3_clks 282 0>; 1418 clock-names = "fclk"; 1419 status = "disabled"; 1420 }; 1421 1422 main_uart6: serial@2860000 { 1423 compatible = "ti,j721e-uart", "ti,am654-uart"; 1424 reg = <0x00 0x02860000 0x00 0x100>; 1425 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1426 clock-frequency = <48000000>; 1427 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 1428 clocks = <&k3_clks 283 0>; 1429 clock-names = "fclk"; 1430 status = "disabled"; 1431 }; 1432 1433 main_uart7: serial@2870000 { 1434 compatible = "ti,j721e-uart", "ti,am654-uart"; 1435 reg = <0x00 0x02870000 0x00 0x100>; 1436 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1437 clock-frequency = <48000000>; 1438 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 1439 clocks = <&k3_clks 284 0>; 1440 clock-names = "fclk"; 1441 status = "disabled"; 1442 }; 1443 1444 main_uart8: serial@2880000 { 1445 compatible = "ti,j721e-uart", "ti,am654-uart"; 1446 reg = <0x00 0x02880000 0x00 0x100>; 1447 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 1448 clock-frequency = <48000000>; 1449 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 1450 clocks = <&k3_clks 285 0>; 1451 clock-names = "fclk"; 1452 status = "disabled"; 1453 }; 1454 1455 main_uart9: serial@2890000 { 1456 compatible = "ti,j721e-uart", "ti,am654-uart"; 1457 reg = <0x00 0x02890000 0x00 0x100>; 1458 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1459 clock-frequency = <48000000>; 1460 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 1461 clocks = <&k3_clks 286 0>; 1462 clock-names = "fclk"; 1463 status = "disabled"; 1464 }; 1465 1466 main_gpio0: gpio@600000 { 1467 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1468 reg = <0x0 0x00600000 0x0 0x100>; 1469 gpio-controller; 1470 #gpio-cells = <2>; 1471 interrupt-parent = <&main_gpio_intr>; 1472 interrupts = <256>, <257>, <258>, <259>, 1473 <260>, <261>, <262>, <263>; 1474 interrupt-controller; 1475 #interrupt-cells = <2>; 1476 ti,ngpio = <128>; 1477 ti,davinci-gpio-unbanked = <0>; 1478 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 1479 clocks = <&k3_clks 105 0>; 1480 clock-names = "gpio"; 1481 status = "disabled"; 1482 }; 1483 1484 main_gpio1: gpio@601000 { 1485 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1486 reg = <0x0 0x00601000 0x0 0x100>; 1487 gpio-controller; 1488 #gpio-cells = <2>; 1489 interrupt-parent = <&main_gpio_intr>; 1490 interrupts = <288>, <289>, <290>; 1491 interrupt-controller; 1492 #interrupt-cells = <2>; 1493 ti,ngpio = <36>; 1494 ti,davinci-gpio-unbanked = <0>; 1495 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 1496 clocks = <&k3_clks 106 0>; 1497 clock-names = "gpio"; 1498 status = "disabled"; 1499 }; 1500 1501 main_gpio2: gpio@610000 { 1502 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1503 reg = <0x0 0x00610000 0x0 0x100>; 1504 gpio-controller; 1505 #gpio-cells = <2>; 1506 interrupt-parent = <&main_gpio_intr>; 1507 interrupts = <264>, <265>, <266>, <267>, 1508 <268>, <269>, <270>, <271>; 1509 interrupt-controller; 1510 #interrupt-cells = <2>; 1511 ti,ngpio = <128>; 1512 ti,davinci-gpio-unbanked = <0>; 1513 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 1514 clocks = <&k3_clks 107 0>; 1515 clock-names = "gpio"; 1516 status = "disabled"; 1517 }; 1518 1519 main_gpio3: gpio@611000 { 1520 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1521 reg = <0x0 0x00611000 0x0 0x100>; 1522 gpio-controller; 1523 #gpio-cells = <2>; 1524 interrupt-parent = <&main_gpio_intr>; 1525 interrupts = <292>, <293>, <294>; 1526 interrupt-controller; 1527 #interrupt-cells = <2>; 1528 ti,ngpio = <36>; 1529 ti,davinci-gpio-unbanked = <0>; 1530 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 1531 clocks = <&k3_clks 108 0>; 1532 clock-names = "gpio"; 1533 status = "disabled"; 1534 }; 1535 1536 main_gpio4: gpio@620000 { 1537 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1538 reg = <0x0 0x00620000 0x0 0x100>; 1539 gpio-controller; 1540 #gpio-cells = <2>; 1541 interrupt-parent = <&main_gpio_intr>; 1542 interrupts = <272>, <273>, <274>, <275>, 1543 <276>, <277>, <278>, <279>; 1544 interrupt-controller; 1545 #interrupt-cells = <2>; 1546 ti,ngpio = <128>; 1547 ti,davinci-gpio-unbanked = <0>; 1548 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 1549 clocks = <&k3_clks 109 0>; 1550 clock-names = "gpio"; 1551 status = "disabled"; 1552 }; 1553 1554 main_gpio5: gpio@621000 { 1555 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1556 reg = <0x0 0x00621000 0x0 0x100>; 1557 gpio-controller; 1558 #gpio-cells = <2>; 1559 interrupt-parent = <&main_gpio_intr>; 1560 interrupts = <296>, <297>, <298>; 1561 interrupt-controller; 1562 #interrupt-cells = <2>; 1563 ti,ngpio = <36>; 1564 ti,davinci-gpio-unbanked = <0>; 1565 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 1566 clocks = <&k3_clks 110 0>; 1567 clock-names = "gpio"; 1568 status = "disabled"; 1569 }; 1570 1571 main_gpio6: gpio@630000 { 1572 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1573 reg = <0x0 0x00630000 0x0 0x100>; 1574 gpio-controller; 1575 #gpio-cells = <2>; 1576 interrupt-parent = <&main_gpio_intr>; 1577 interrupts = <280>, <281>, <282>, <283>, 1578 <284>, <285>, <286>, <287>; 1579 interrupt-controller; 1580 #interrupt-cells = <2>; 1581 ti,ngpio = <128>; 1582 ti,davinci-gpio-unbanked = <0>; 1583 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 1584 clocks = <&k3_clks 111 0>; 1585 clock-names = "gpio"; 1586 status = "disabled"; 1587 }; 1588 1589 main_gpio7: gpio@631000 { 1590 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 1591 reg = <0x0 0x00631000 0x0 0x100>; 1592 gpio-controller; 1593 #gpio-cells = <2>; 1594 interrupt-parent = <&main_gpio_intr>; 1595 interrupts = <300>, <301>, <302>; 1596 interrupt-controller; 1597 #interrupt-cells = <2>; 1598 ti,ngpio = <36>; 1599 ti,davinci-gpio-unbanked = <0>; 1600 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 1601 clocks = <&k3_clks 112 0>; 1602 clock-names = "gpio"; 1603 status = "disabled"; 1604 }; 1605 1606 main_sdhci0: mmc@4f80000 { 1607 compatible = "ti,j721e-sdhci-8bit"; 1608 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>; 1609 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1610 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1611 clock-names = "clk_ahb", "clk_xin"; 1612 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>; 1613 assigned-clocks = <&k3_clks 91 1>; 1614 assigned-clock-parents = <&k3_clks 91 2>; 1615 bus-width = <8>; 1616 mmc-hs200-1_8v; 1617 mmc-ddr-1_8v; 1618 ti,otap-del-sel-legacy = <0x0>; 1619 ti,otap-del-sel-mmc-hs = <0x0>; 1620 ti,otap-del-sel-ddr52 = <0x5>; 1621 ti,otap-del-sel-hs200 = <0x6>; 1622 ti,otap-del-sel-hs400 = <0x0>; 1623 ti,itap-del-sel-legacy = <0x10>; 1624 ti,itap-del-sel-mmc-hs = <0xa>; 1625 ti,itap-del-sel-ddr52 = <0x3>; 1626 ti,trm-icp = <0x8>; 1627 dma-coherent; 1628 status = "disabled"; 1629 }; 1630 1631 main_sdhci1: mmc@4fb0000 { 1632 compatible = "ti,j721e-sdhci-4bit"; 1633 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>; 1634 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1635 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1636 clock-names = "clk_ahb", "clk_xin"; 1637 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>; 1638 assigned-clocks = <&k3_clks 92 0>; 1639 assigned-clock-parents = <&k3_clks 92 1>; 1640 ti,otap-del-sel-legacy = <0x0>; 1641 ti,otap-del-sel-sd-hs = <0x0>; 1642 ti,otap-del-sel-sdr12 = <0xf>; 1643 ti,otap-del-sel-sdr25 = <0xf>; 1644 ti,otap-del-sel-sdr50 = <0xc>; 1645 ti,otap-del-sel-ddr50 = <0xc>; 1646 ti,otap-del-sel-sdr104 = <0x5>; 1647 ti,itap-del-sel-legacy = <0x0>; 1648 ti,itap-del-sel-sd-hs = <0x0>; 1649 ti,itap-del-sel-sdr12 = <0x0>; 1650 ti,itap-del-sel-sdr25 = <0x0>; 1651 ti,itap-del-sel-ddr50 = <0x2>; 1652 ti,trm-icp = <0x8>; 1653 ti,clkbuf-sel = <0x7>; 1654 dma-coherent; 1655 sdhci-caps-mask = <0x2 0x0>; 1656 status = "disabled"; 1657 }; 1658 1659 main_sdhci2: mmc@4f98000 { 1660 compatible = "ti,j721e-sdhci-4bit"; 1661 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>; 1662 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1663 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1664 clock-names = "clk_ahb", "clk_xin"; 1665 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>; 1666 assigned-clocks = <&k3_clks 93 0>; 1667 assigned-clock-parents = <&k3_clks 93 1>; 1668 ti,otap-del-sel-legacy = <0x0>; 1669 ti,otap-del-sel-sd-hs = <0x0>; 1670 ti,otap-del-sel-sdr12 = <0xf>; 1671 ti,otap-del-sel-sdr25 = <0xf>; 1672 ti,otap-del-sel-sdr50 = <0xc>; 1673 ti,otap-del-sel-ddr50 = <0xc>; 1674 ti,otap-del-sel-sdr104 = <0x5>; 1675 ti,itap-del-sel-legacy = <0x0>; 1676 ti,itap-del-sel-sd-hs = <0x0>; 1677 ti,itap-del-sel-sdr12 = <0x0>; 1678 ti,itap-del-sel-sdr25 = <0x0>; 1679 ti,itap-del-sel-ddr50 = <0x2>; 1680 ti,trm-icp = <0x8>; 1681 ti,clkbuf-sel = <0x7>; 1682 dma-coherent; 1683 sdhci-caps-mask = <0x2 0x0>; 1684 status = "disabled"; 1685 }; 1686 1687 usbss0: cdns-usb@4104000 { 1688 compatible = "ti,j721e-usb"; 1689 reg = <0x00 0x4104000 0x00 0x100>; 1690 dma-coherent; 1691 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 1692 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 1693 clock-names = "ref", "lpm"; 1694 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 1695 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 1696 #address-cells = <2>; 1697 #size-cells = <2>; 1698 ranges; 1699 1700 usb0: usb@6000000 { 1701 compatible = "cdns,usb3"; 1702 reg = <0x00 0x6000000 0x00 0x10000>, 1703 <0x00 0x6010000 0x00 0x10000>, 1704 <0x00 0x6020000 0x00 0x10000>; 1705 reg-names = "otg", "xhci", "dev"; 1706 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1707 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1708 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1709 interrupt-names = "host", 1710 "peripheral", 1711 "otg"; 1712 maximum-speed = "super-speed"; 1713 dr_mode = "otg"; 1714 }; 1715 }; 1716 1717 usbss1: cdns-usb@4114000 { 1718 compatible = "ti,j721e-usb"; 1719 reg = <0x00 0x4114000 0x00 0x100>; 1720 dma-coherent; 1721 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>; 1722 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>; 1723 clock-names = "ref", "lpm"; 1724 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */ 1725 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */ 1726 #address-cells = <2>; 1727 #size-cells = <2>; 1728 ranges; 1729 1730 usb1: usb@6400000 { 1731 compatible = "cdns,usb3"; 1732 reg = <0x00 0x6400000 0x00 0x10000>, 1733 <0x00 0x6410000 0x00 0x10000>, 1734 <0x00 0x6420000 0x00 0x10000>; 1735 reg-names = "otg", "xhci", "dev"; 1736 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 1737 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 1738 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 1739 interrupt-names = "host", 1740 "peripheral", 1741 "otg"; 1742 maximum-speed = "super-speed"; 1743 dr_mode = "otg"; 1744 }; 1745 }; 1746 1747 main_i2c0: i2c@2000000 { 1748 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1749 reg = <0x0 0x2000000 0x0 0x100>; 1750 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 clock-names = "fck"; 1754 clocks = <&k3_clks 187 0>; 1755 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 1756 status = "disabled"; 1757 }; 1758 1759 main_i2c1: i2c@2010000 { 1760 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1761 reg = <0x0 0x2010000 0x0 0x100>; 1762 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 clock-names = "fck"; 1766 clocks = <&k3_clks 188 0>; 1767 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 1768 status = "disabled"; 1769 }; 1770 1771 main_i2c2: i2c@2020000 { 1772 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1773 reg = <0x0 0x2020000 0x0 0x100>; 1774 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 clock-names = "fck"; 1778 clocks = <&k3_clks 189 0>; 1779 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 1780 status = "disabled"; 1781 }; 1782 1783 main_i2c3: i2c@2030000 { 1784 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1785 reg = <0x0 0x2030000 0x0 0x100>; 1786 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 clock-names = "fck"; 1790 clocks = <&k3_clks 190 0>; 1791 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 1792 status = "disabled"; 1793 }; 1794 1795 main_i2c4: i2c@2040000 { 1796 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1797 reg = <0x0 0x2040000 0x0 0x100>; 1798 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 clock-names = "fck"; 1802 clocks = <&k3_clks 191 0>; 1803 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1804 status = "disabled"; 1805 }; 1806 1807 main_i2c5: i2c@2050000 { 1808 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1809 reg = <0x0 0x2050000 0x0 0x100>; 1810 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 clock-names = "fck"; 1814 clocks = <&k3_clks 192 0>; 1815 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1816 status = "disabled"; 1817 }; 1818 1819 main_i2c6: i2c@2060000 { 1820 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 1821 reg = <0x0 0x2060000 0x0 0x100>; 1822 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 clock-names = "fck"; 1826 clocks = <&k3_clks 193 0>; 1827 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 1828 status = "disabled"; 1829 }; 1830 1831 ufs_wrapper: ufs-wrapper@4e80000 { 1832 compatible = "ti,j721e-ufs"; 1833 reg = <0x0 0x4e80000 0x0 0x100>; 1834 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 1835 clocks = <&k3_clks 277 1>; 1836 assigned-clocks = <&k3_clks 277 1>; 1837 assigned-clock-parents = <&k3_clks 277 4>; 1838 ranges; 1839 #address-cells = <2>; 1840 #size-cells = <2>; 1841 1842 ufs@4e84000 { 1843 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 1844 reg = <0x0 0x4e84000 0x0 0x10000>; 1845 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1846 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>; 1847 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>; 1848 clock-names = "core_clk", "phy_clk", "ref_clk"; 1849 dma-coherent; 1850 }; 1851 }; 1852 1853 mhdp: dp-bridge@a000000 { 1854 compatible = "ti,j721e-mhdp8546"; 1855 /* 1856 * Note: we do not map DPTX PHY area, as that is handled by 1857 * the PHY driver. 1858 */ 1859 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ 1860 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ 1861 reg-names = "mhdptx", "j721e-intg"; 1862 1863 clocks = <&k3_clks 151 36>; 1864 1865 interrupt-parent = <&gic500>; 1866 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 1867 1868 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 1869 1870 dp0_ports: ports { 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 1874 port@0 { 1875 reg = <0>; 1876 }; 1877 1878 port@4 { 1879 reg = <4>; 1880 }; 1881 }; 1882 }; 1883 1884 dss: dss@4a00000 { 1885 compatible = "ti,j721e-dss"; 1886 reg = 1887 <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 1888 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 1889 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 1890 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 1891 1892 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 1893 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 1894 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 1895 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 1896 1897 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 1898 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 1899 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 1900 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 1901 1902 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 1903 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ 1904 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ 1905 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 1906 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 1907 1908 reg-names = "common_m", "common_s0", 1909 "common_s1", "common_s2", 1910 "vidl1", "vidl2","vid1","vid2", 1911 "ovr1", "ovr2", "ovr3", "ovr4", 1912 "vp1", "vp2", "vp3", "vp4", 1913 "wb"; 1914 1915 clocks = <&k3_clks 152 0>, 1916 <&k3_clks 152 1>, 1917 <&k3_clks 152 4>, 1918 <&k3_clks 152 9>, 1919 <&k3_clks 152 13>; 1920 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 1921 1922 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 1923 1924 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1928 interrupt-names = "common_m", 1929 "common_s0", 1930 "common_s1", 1931 "common_s2"; 1932 1933 dss_ports: ports { 1934 }; 1935 }; 1936 1937 mcasp0: mcasp@2b00000 { 1938 compatible = "ti,am33xx-mcasp-audio"; 1939 reg = <0x0 0x02b00000 0x0 0x2000>, 1940 <0x0 0x02b08000 0x0 0x1000>; 1941 reg-names = "mpu","dat"; 1942 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 1944 interrupt-names = "tx", "rx"; 1945 1946 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 1947 dma-names = "tx", "rx"; 1948 1949 clocks = <&k3_clks 174 1>; 1950 clock-names = "fck"; 1951 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>; 1952 status = "disabled"; 1953 }; 1954 1955 mcasp1: mcasp@2b10000 { 1956 compatible = "ti,am33xx-mcasp-audio"; 1957 reg = <0x0 0x02b10000 0x0 0x2000>, 1958 <0x0 0x02b18000 0x0 0x1000>; 1959 reg-names = "mpu","dat"; 1960 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 1962 interrupt-names = "tx", "rx"; 1963 1964 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 1965 dma-names = "tx", "rx"; 1966 1967 clocks = <&k3_clks 175 1>; 1968 clock-names = "fck"; 1969 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>; 1970 status = "disabled"; 1971 }; 1972 1973 mcasp2: mcasp@2b20000 { 1974 compatible = "ti,am33xx-mcasp-audio"; 1975 reg = <0x0 0x02b20000 0x0 0x2000>, 1976 <0x0 0x02b28000 0x0 0x1000>; 1977 reg-names = "mpu","dat"; 1978 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 1980 interrupt-names = "tx", "rx"; 1981 1982 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 1983 dma-names = "tx", "rx"; 1984 1985 clocks = <&k3_clks 176 1>; 1986 clock-names = "fck"; 1987 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>; 1988 status = "disabled"; 1989 }; 1990 1991 mcasp3: mcasp@2b30000 { 1992 compatible = "ti,am33xx-mcasp-audio"; 1993 reg = <0x0 0x02b30000 0x0 0x2000>, 1994 <0x0 0x02b38000 0x0 0x1000>; 1995 reg-names = "mpu","dat"; 1996 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 1997 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1998 interrupt-names = "tx", "rx"; 1999 2000 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 2001 dma-names = "tx", "rx"; 2002 2003 clocks = <&k3_clks 177 1>; 2004 clock-names = "fck"; 2005 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>; 2006 status = "disabled"; 2007 }; 2008 2009 mcasp4: mcasp@2b40000 { 2010 compatible = "ti,am33xx-mcasp-audio"; 2011 reg = <0x0 0x02b40000 0x0 0x2000>, 2012 <0x0 0x02b48000 0x0 0x1000>; 2013 reg-names = "mpu","dat"; 2014 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 2015 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 2016 interrupt-names = "tx", "rx"; 2017 2018 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; 2019 dma-names = "tx", "rx"; 2020 2021 clocks = <&k3_clks 178 1>; 2022 clock-names = "fck"; 2023 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 2024 status = "disabled"; 2025 }; 2026 2027 mcasp5: mcasp@2b50000 { 2028 compatible = "ti,am33xx-mcasp-audio"; 2029 reg = <0x0 0x02b50000 0x0 0x2000>, 2030 <0x0 0x02b58000 0x0 0x1000>; 2031 reg-names = "mpu","dat"; 2032 interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>; 2034 interrupt-names = "tx", "rx"; 2035 2036 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>; 2037 dma-names = "tx", "rx"; 2038 2039 clocks = <&k3_clks 179 1>; 2040 clock-names = "fck"; 2041 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 2042 status = "disabled"; 2043 }; 2044 2045 mcasp6: mcasp@2b60000 { 2046 compatible = "ti,am33xx-mcasp-audio"; 2047 reg = <0x0 0x02b60000 0x0 0x2000>, 2048 <0x0 0x02b68000 0x0 0x1000>; 2049 reg-names = "mpu","dat"; 2050 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 557 IRQ_TYPE_LEVEL_HIGH>; 2052 interrupt-names = "tx", "rx"; 2053 2054 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>; 2055 dma-names = "tx", "rx"; 2056 2057 clocks = <&k3_clks 180 1>; 2058 clock-names = "fck"; 2059 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>; 2060 status = "disabled"; 2061 }; 2062 2063 mcasp7: mcasp@2b70000 { 2064 compatible = "ti,am33xx-mcasp-audio"; 2065 reg = <0x0 0x02b70000 0x0 0x2000>, 2066 <0x0 0x02b78000 0x0 0x1000>; 2067 reg-names = "mpu","dat"; 2068 interrupts = <GIC_SPI 558 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>; 2070 interrupt-names = "tx", "rx"; 2071 2072 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>; 2073 dma-names = "tx", "rx"; 2074 2075 clocks = <&k3_clks 181 1>; 2076 clock-names = "fck"; 2077 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>; 2078 status = "disabled"; 2079 }; 2080 2081 mcasp8: mcasp@2b80000 { 2082 compatible = "ti,am33xx-mcasp-audio"; 2083 reg = <0x0 0x02b80000 0x0 0x2000>, 2084 <0x0 0x02b88000 0x0 0x1000>; 2085 reg-names = "mpu","dat"; 2086 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 2088 interrupt-names = "tx", "rx"; 2089 2090 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>; 2091 dma-names = "tx", "rx"; 2092 2093 clocks = <&k3_clks 182 1>; 2094 clock-names = "fck"; 2095 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 2096 status = "disabled"; 2097 }; 2098 2099 mcasp9: mcasp@2b90000 { 2100 compatible = "ti,am33xx-mcasp-audio"; 2101 reg = <0x0 0x02b90000 0x0 0x2000>, 2102 <0x0 0x02b98000 0x0 0x1000>; 2103 reg-names = "mpu","dat"; 2104 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 563 IRQ_TYPE_LEVEL_HIGH>; 2106 interrupt-names = "tx", "rx"; 2107 2108 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>; 2109 dma-names = "tx", "rx"; 2110 2111 clocks = <&k3_clks 183 1>; 2112 clock-names = "fck"; 2113 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>; 2114 status = "disabled"; 2115 }; 2116 2117 mcasp10: mcasp@2ba0000 { 2118 compatible = "ti,am33xx-mcasp-audio"; 2119 reg = <0x0 0x02ba0000 0x0 0x2000>, 2120 <0x0 0x02ba8000 0x0 0x1000>; 2121 reg-names = "mpu","dat"; 2122 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 2124 interrupt-names = "tx", "rx"; 2125 2126 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>; 2127 dma-names = "tx", "rx"; 2128 2129 clocks = <&k3_clks 184 1>; 2130 clock-names = "fck"; 2131 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 2132 status = "disabled"; 2133 }; 2134 2135 mcasp11: mcasp@2bb0000 { 2136 compatible = "ti,am33xx-mcasp-audio"; 2137 reg = <0x0 0x02bb0000 0x0 0x2000>, 2138 <0x0 0x02bb8000 0x0 0x1000>; 2139 reg-names = "mpu","dat"; 2140 interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; 2142 interrupt-names = "tx", "rx"; 2143 2144 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>; 2145 dma-names = "tx", "rx"; 2146 2147 clocks = <&k3_clks 185 1>; 2148 clock-names = "fck"; 2149 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 2150 status = "disabled"; 2151 }; 2152 2153 watchdog0: watchdog@2200000 { 2154 compatible = "ti,j7-rti-wdt"; 2155 reg = <0x0 0x2200000 0x0 0x100>; 2156 clocks = <&k3_clks 252 1>; 2157 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 2158 assigned-clocks = <&k3_clks 252 1>; 2159 assigned-clock-parents = <&k3_clks 252 5>; 2160 }; 2161 2162 watchdog1: watchdog@2210000 { 2163 compatible = "ti,j7-rti-wdt"; 2164 reg = <0x0 0x2210000 0x0 0x100>; 2165 clocks = <&k3_clks 253 1>; 2166 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 2167 assigned-clocks = <&k3_clks 253 1>; 2168 assigned-clock-parents = <&k3_clks 253 5>; 2169 }; 2170 2171 main_r5fss0: r5fss@5c00000 { 2172 compatible = "ti,j721e-r5fss"; 2173 ti,cluster-mode = <1>; 2174 #address-cells = <1>; 2175 #size-cells = <1>; 2176 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2177 <0x5d00000 0x00 0x5d00000 0x20000>; 2178 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 2179 2180 main_r5fss0_core0: r5f@5c00000 { 2181 compatible = "ti,j721e-r5f"; 2182 reg = <0x5c00000 0x00008000>, 2183 <0x5c10000 0x00008000>; 2184 reg-names = "atcm", "btcm"; 2185 ti,sci = <&dmsc>; 2186 ti,sci-dev-id = <245>; 2187 ti,sci-proc-ids = <0x06 0xff>; 2188 resets = <&k3_reset 245 1>; 2189 firmware-name = "j7-main-r5f0_0-fw"; 2190 ti,atcm-enable = <1>; 2191 ti,btcm-enable = <1>; 2192 ti,loczrama = <1>; 2193 }; 2194 2195 main_r5fss0_core1: r5f@5d00000 { 2196 compatible = "ti,j721e-r5f"; 2197 reg = <0x5d00000 0x00008000>, 2198 <0x5d10000 0x00008000>; 2199 reg-names = "atcm", "btcm"; 2200 ti,sci = <&dmsc>; 2201 ti,sci-dev-id = <246>; 2202 ti,sci-proc-ids = <0x07 0xff>; 2203 resets = <&k3_reset 246 1>; 2204 firmware-name = "j7-main-r5f0_1-fw"; 2205 ti,atcm-enable = <1>; 2206 ti,btcm-enable = <1>; 2207 ti,loczrama = <1>; 2208 }; 2209 }; 2210 2211 main_r5fss1: r5fss@5e00000 { 2212 compatible = "ti,j721e-r5fss"; 2213 ti,cluster-mode = <1>; 2214 #address-cells = <1>; 2215 #size-cells = <1>; 2216 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2217 <0x5f00000 0x00 0x5f00000 0x20000>; 2218 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>; 2219 2220 main_r5fss1_core0: r5f@5e00000 { 2221 compatible = "ti,j721e-r5f"; 2222 reg = <0x5e00000 0x00008000>, 2223 <0x5e10000 0x00008000>; 2224 reg-names = "atcm", "btcm"; 2225 ti,sci = <&dmsc>; 2226 ti,sci-dev-id = <247>; 2227 ti,sci-proc-ids = <0x08 0xff>; 2228 resets = <&k3_reset 247 1>; 2229 firmware-name = "j7-main-r5f1_0-fw"; 2230 ti,atcm-enable = <1>; 2231 ti,btcm-enable = <1>; 2232 ti,loczrama = <1>; 2233 }; 2234 2235 main_r5fss1_core1: r5f@5f00000 { 2236 compatible = "ti,j721e-r5f"; 2237 reg = <0x5f00000 0x00008000>, 2238 <0x5f10000 0x00008000>; 2239 reg-names = "atcm", "btcm"; 2240 ti,sci = <&dmsc>; 2241 ti,sci-dev-id = <248>; 2242 ti,sci-proc-ids = <0x09 0xff>; 2243 resets = <&k3_reset 248 1>; 2244 firmware-name = "j7-main-r5f1_1-fw"; 2245 ti,atcm-enable = <1>; 2246 ti,btcm-enable = <1>; 2247 ti,loczrama = <1>; 2248 }; 2249 }; 2250 2251 c66_0: dsp@4d80800000 { 2252 compatible = "ti,j721e-c66-dsp"; 2253 reg = <0x4d 0x80800000 0x00 0x00048000>, 2254 <0x4d 0x80e00000 0x00 0x00008000>, 2255 <0x4d 0x80f00000 0x00 0x00008000>; 2256 reg-names = "l2sram", "l1pram", "l1dram"; 2257 ti,sci = <&dmsc>; 2258 ti,sci-dev-id = <142>; 2259 ti,sci-proc-ids = <0x03 0xff>; 2260 resets = <&k3_reset 142 1>; 2261 firmware-name = "j7-c66_0-fw"; 2262 status = "disabled"; 2263 }; 2264 2265 c66_1: dsp@4d81800000 { 2266 compatible = "ti,j721e-c66-dsp"; 2267 reg = <0x4d 0x81800000 0x00 0x00048000>, 2268 <0x4d 0x81e00000 0x00 0x00008000>, 2269 <0x4d 0x81f00000 0x00 0x00008000>; 2270 reg-names = "l2sram", "l1pram", "l1dram"; 2271 ti,sci = <&dmsc>; 2272 ti,sci-dev-id = <143>; 2273 ti,sci-proc-ids = <0x04 0xff>; 2274 resets = <&k3_reset 143 1>; 2275 firmware-name = "j7-c66_1-fw"; 2276 status = "disabled"; 2277 }; 2278 2279 c71_0: dsp@64800000 { 2280 compatible = "ti,j721e-c71-dsp"; 2281 reg = <0x00 0x64800000 0x00 0x00080000>, 2282 <0x00 0x64e00000 0x00 0x0000c000>; 2283 reg-names = "l2sram", "l1dram"; 2284 ti,sci = <&dmsc>; 2285 ti,sci-dev-id = <15>; 2286 ti,sci-proc-ids = <0x30 0xff>; 2287 resets = <&k3_reset 15 1>; 2288 firmware-name = "j7-c71_0-fw"; 2289 status = "disabled"; 2290 }; 2291 2292 icssg0: icssg@b000000 { 2293 compatible = "ti,j721e-icssg"; 2294 reg = <0x00 0xb000000 0x00 0x80000>; 2295 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 2296 #address-cells = <1>; 2297 #size-cells = <1>; 2298 ranges = <0x0 0x00 0x0b000000 0x100000>; 2299 2300 icssg0_mem: memories@0 { 2301 reg = <0x0 0x2000>, 2302 <0x2000 0x2000>, 2303 <0x10000 0x10000>; 2304 reg-names = "dram0", "dram1", 2305 "shrdram2"; 2306 }; 2307 2308 icssg0_cfg: cfg@26000 { 2309 compatible = "ti,pruss-cfg", "syscon"; 2310 reg = <0x26000 0x200>; 2311 #address-cells = <1>; 2312 #size-cells = <1>; 2313 ranges = <0x0 0x26000 0x2000>; 2314 2315 clocks { 2316 #address-cells = <1>; 2317 #size-cells = <0>; 2318 2319 icssg0_coreclk_mux: coreclk-mux@3c { 2320 reg = <0x3c>; 2321 #clock-cells = <0>; 2322 clocks = <&k3_clks 119 24>, /* icssg0_core_clk */ 2323 <&k3_clks 119 1>; /* icssg0_iclk */ 2324 assigned-clocks = <&icssg0_coreclk_mux>; 2325 assigned-clock-parents = <&k3_clks 119 1>; 2326 }; 2327 2328 icssg0_iepclk_mux: iepclk-mux@30 { 2329 reg = <0x30>; 2330 #clock-cells = <0>; 2331 clocks = <&k3_clks 119 3>, /* icssg0_iep_clk */ 2332 <&icssg0_coreclk_mux>; /* core_clk */ 2333 assigned-clocks = <&icssg0_iepclk_mux>; 2334 assigned-clock-parents = <&icssg0_coreclk_mux>; 2335 }; 2336 }; 2337 }; 2338 2339 icssg0_mii_rt: mii-rt@32000 { 2340 compatible = "ti,pruss-mii", "syscon"; 2341 reg = <0x32000 0x100>; 2342 }; 2343 2344 icssg0_mii_g_rt: mii-g-rt@33000 { 2345 compatible = "ti,pruss-mii-g", "syscon"; 2346 reg = <0x33000 0x1000>; 2347 }; 2348 2349 icssg0_intc: interrupt-controller@20000 { 2350 compatible = "ti,icssg-intc"; 2351 reg = <0x20000 0x2000>; 2352 interrupt-controller; 2353 #interrupt-cells = <3>; 2354 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 2362 interrupt-names = "host_intr0", "host_intr1", 2363 "host_intr2", "host_intr3", 2364 "host_intr4", "host_intr5", 2365 "host_intr6", "host_intr7"; 2366 }; 2367 2368 pru0_0: pru@34000 { 2369 compatible = "ti,j721e-pru"; 2370 reg = <0x34000 0x3000>, 2371 <0x22000 0x100>, 2372 <0x22400 0x100>; 2373 reg-names = "iram", "control", "debug"; 2374 firmware-name = "j7-pru0_0-fw"; 2375 }; 2376 2377 rtu0_0: rtu@4000 { 2378 compatible = "ti,j721e-rtu"; 2379 reg = <0x4000 0x2000>, 2380 <0x23000 0x100>, 2381 <0x23400 0x100>; 2382 reg-names = "iram", "control", "debug"; 2383 firmware-name = "j7-rtu0_0-fw"; 2384 }; 2385 2386 tx_pru0_0: txpru@a000 { 2387 compatible = "ti,j721e-tx-pru"; 2388 reg = <0xa000 0x1800>, 2389 <0x25000 0x100>, 2390 <0x25400 0x100>; 2391 reg-names = "iram", "control", "debug"; 2392 firmware-name = "j7-txpru0_0-fw"; 2393 }; 2394 2395 pru0_1: pru@38000 { 2396 compatible = "ti,j721e-pru"; 2397 reg = <0x38000 0x3000>, 2398 <0x24000 0x100>, 2399 <0x24400 0x100>; 2400 reg-names = "iram", "control", "debug"; 2401 firmware-name = "j7-pru0_1-fw"; 2402 }; 2403 2404 rtu0_1: rtu@6000 { 2405 compatible = "ti,j721e-rtu"; 2406 reg = <0x6000 0x2000>, 2407 <0x23800 0x100>, 2408 <0x23c00 0x100>; 2409 reg-names = "iram", "control", "debug"; 2410 firmware-name = "j7-rtu0_1-fw"; 2411 }; 2412 2413 tx_pru0_1: txpru@c000 { 2414 compatible = "ti,j721e-tx-pru"; 2415 reg = <0xc000 0x1800>, 2416 <0x25800 0x100>, 2417 <0x25c00 0x100>; 2418 reg-names = "iram", "control", "debug"; 2419 firmware-name = "j7-txpru0_1-fw"; 2420 }; 2421 2422 icssg0_mdio: mdio@32400 { 2423 compatible = "ti,davinci_mdio"; 2424 reg = <0x32400 0x100>; 2425 clocks = <&k3_clks 119 1>; 2426 clock-names = "fck"; 2427 #address-cells = <1>; 2428 #size-cells = <0>; 2429 bus_freq = <1000000>; 2430 status = "disabled"; 2431 }; 2432 }; 2433 2434 icssg1: icssg@b100000 { 2435 compatible = "ti,j721e-icssg"; 2436 reg = <0x00 0xb100000 0x00 0x80000>; 2437 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 2438 #address-cells = <1>; 2439 #size-cells = <1>; 2440 ranges = <0x0 0x00 0x0b100000 0x100000>; 2441 2442 icssg1_mem: memories@b100000 { 2443 reg = <0x0 0x2000>, 2444 <0x2000 0x2000>, 2445 <0x10000 0x10000>; 2446 reg-names = "dram0", "dram1", 2447 "shrdram2"; 2448 }; 2449 2450 icssg1_cfg: cfg@26000 { 2451 compatible = "ti,pruss-cfg", "syscon"; 2452 reg = <0x26000 0x200>; 2453 #address-cells = <1>; 2454 #size-cells = <1>; 2455 ranges = <0x0 0x26000 0x2000>; 2456 2457 clocks { 2458 #address-cells = <1>; 2459 #size-cells = <0>; 2460 2461 icssg1_coreclk_mux: coreclk-mux@3c { 2462 reg = <0x3c>; 2463 #clock-cells = <0>; 2464 clocks = <&k3_clks 120 54>, /* icssg1_core_clk */ 2465 <&k3_clks 120 4>; /* icssg1_iclk */ 2466 assigned-clocks = <&icssg1_coreclk_mux>; 2467 assigned-clock-parents = <&k3_clks 120 4>; 2468 }; 2469 2470 icssg1_iepclk_mux: iepclk-mux@30 { 2471 reg = <0x30>; 2472 #clock-cells = <0>; 2473 clocks = <&k3_clks 120 9>, /* icssg1_iep_clk */ 2474 <&icssg1_coreclk_mux>; /* core_clk */ 2475 assigned-clocks = <&icssg1_iepclk_mux>; 2476 assigned-clock-parents = <&icssg1_coreclk_mux>; 2477 }; 2478 }; 2479 }; 2480 2481 icssg1_mii_rt: mii-rt@32000 { 2482 compatible = "ti,pruss-mii", "syscon"; 2483 reg = <0x32000 0x100>; 2484 }; 2485 2486 icssg1_mii_g_rt: mii-g-rt@33000 { 2487 compatible = "ti,pruss-mii-g", "syscon"; 2488 reg = <0x33000 0x1000>; 2489 }; 2490 2491 icssg1_intc: interrupt-controller@20000 { 2492 compatible = "ti,icssg-intc"; 2493 reg = <0x20000 0x2000>; 2494 interrupt-controller; 2495 #interrupt-cells = <3>; 2496 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2504 interrupt-names = "host_intr0", "host_intr1", 2505 "host_intr2", "host_intr3", 2506 "host_intr4", "host_intr5", 2507 "host_intr6", "host_intr7"; 2508 }; 2509 2510 pru1_0: pru@34000 { 2511 compatible = "ti,j721e-pru"; 2512 reg = <0x34000 0x4000>, 2513 <0x22000 0x100>, 2514 <0x22400 0x100>; 2515 reg-names = "iram", "control", "debug"; 2516 firmware-name = "j7-pru1_0-fw"; 2517 }; 2518 2519 rtu1_0: rtu@4000 { 2520 compatible = "ti,j721e-rtu"; 2521 reg = <0x4000 0x2000>, 2522 <0x23000 0x100>, 2523 <0x23400 0x100>; 2524 reg-names = "iram", "control", "debug"; 2525 firmware-name = "j7-rtu1_0-fw"; 2526 }; 2527 2528 tx_pru1_0: txpru@a000 { 2529 compatible = "ti,j721e-tx-pru"; 2530 reg = <0xa000 0x1800>, 2531 <0x25000 0x100>, 2532 <0x25400 0x100>; 2533 reg-names = "iram", "control", "debug"; 2534 firmware-name = "j7-txpru1_0-fw"; 2535 }; 2536 2537 pru1_1: pru@38000 { 2538 compatible = "ti,j721e-pru"; 2539 reg = <0x38000 0x4000>, 2540 <0x24000 0x100>, 2541 <0x24400 0x100>; 2542 reg-names = "iram", "control", "debug"; 2543 firmware-name = "j7-pru1_1-fw"; 2544 }; 2545 2546 rtu1_1: rtu@6000 { 2547 compatible = "ti,j721e-rtu"; 2548 reg = <0x6000 0x2000>, 2549 <0x23800 0x100>, 2550 <0x23c00 0x100>; 2551 reg-names = "iram", "control", "debug"; 2552 firmware-name = "j7-rtu1_1-fw"; 2553 }; 2554 2555 tx_pru1_1: txpru@c000 { 2556 compatible = "ti,j721e-tx-pru"; 2557 reg = <0xc000 0x1800>, 2558 <0x25800 0x100>, 2559 <0x25c00 0x100>; 2560 reg-names = "iram", "control", "debug"; 2561 firmware-name = "j7-txpru1_1-fw"; 2562 }; 2563 2564 icssg1_mdio: mdio@32400 { 2565 compatible = "ti,davinci_mdio"; 2566 reg = <0x32400 0x100>; 2567 clocks = <&k3_clks 120 4>; 2568 clock-names = "fck"; 2569 #address-cells = <1>; 2570 #size-cells = <0>; 2571 bus_freq = <1000000>; 2572 status = "disabled"; 2573 }; 2574 }; 2575 2576 main_mcan0: can@2701000 { 2577 compatible = "bosch,m_can"; 2578 reg = <0x00 0x02701000 0x00 0x200>, 2579 <0x00 0x02708000 0x00 0x8000>; 2580 reg-names = "m_can", "message_ram"; 2581 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 2582 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>; 2583 clock-names = "hclk", "cclk"; 2584 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2586 interrupt-names = "int0", "int1"; 2587 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2588 status = "disabled"; 2589 }; 2590 2591 main_mcan1: can@2711000 { 2592 compatible = "bosch,m_can"; 2593 reg = <0x00 0x02711000 0x00 0x200>, 2594 <0x00 0x02718000 0x00 0x8000>; 2595 reg-names = "m_can", "message_ram"; 2596 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 2597 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>; 2598 clock-names = "hclk", "cclk"; 2599 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 2601 interrupt-names = "int0", "int1"; 2602 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2603 status = "disabled"; 2604 }; 2605 2606 main_mcan2: can@2721000 { 2607 compatible = "bosch,m_can"; 2608 reg = <0x00 0x02721000 0x00 0x200>, 2609 <0x00 0x02728000 0x00 0x8000>; 2610 reg-names = "m_can", "message_ram"; 2611 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 2612 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>; 2613 clock-names = "hclk", "cclk"; 2614 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2616 interrupt-names = "int0", "int1"; 2617 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2618 status = "disabled"; 2619 }; 2620 2621 main_mcan3: can@2731000 { 2622 compatible = "bosch,m_can"; 2623 reg = <0x00 0x02731000 0x00 0x200>, 2624 <0x00 0x02738000 0x00 0x8000>; 2625 reg-names = "m_can", "message_ram"; 2626 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 2627 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>; 2628 clock-names = "hclk", "cclk"; 2629 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 2631 interrupt-names = "int0", "int1"; 2632 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2633 status = "disabled"; 2634 }; 2635 2636 main_mcan4: can@2741000 { 2637 compatible = "bosch,m_can"; 2638 reg = <0x00 0x02741000 0x00 0x200>, 2639 <0x00 0x02748000 0x00 0x8000>; 2640 reg-names = "m_can", "message_ram"; 2641 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 2642 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>; 2643 clock-names = "hclk", "cclk"; 2644 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2645 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2646 interrupt-names = "int0", "int1"; 2647 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2648 status = "disabled"; 2649 }; 2650 2651 main_mcan5: can@2751000 { 2652 compatible = "bosch,m_can"; 2653 reg = <0x00 0x02751000 0x00 0x200>, 2654 <0x00 0x02758000 0x00 0x8000>; 2655 reg-names = "m_can", "message_ram"; 2656 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 2657 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>; 2658 clock-names = "hclk", "cclk"; 2659 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2660 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2661 interrupt-names = "int0", "int1"; 2662 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2663 status = "disabled"; 2664 }; 2665 2666 main_mcan6: can@2761000 { 2667 compatible = "bosch,m_can"; 2668 reg = <0x00 0x02761000 0x00 0x200>, 2669 <0x00 0x02768000 0x00 0x8000>; 2670 reg-names = "m_can", "message_ram"; 2671 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 2672 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>; 2673 clock-names = "hclk", "cclk"; 2674 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2676 interrupt-names = "int0", "int1"; 2677 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2678 status = "disabled"; 2679 }; 2680 2681 main_mcan7: can@2771000 { 2682 compatible = "bosch,m_can"; 2683 reg = <0x00 0x02771000 0x00 0x200>, 2684 <0x00 0x02778000 0x00 0x8000>; 2685 reg-names = "m_can", "message_ram"; 2686 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 2687 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>; 2688 clock-names = "hclk", "cclk"; 2689 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2690 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2691 interrupt-names = "int0", "int1"; 2692 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2693 status = "disabled"; 2694 }; 2695 2696 main_mcan8: can@2781000 { 2697 compatible = "bosch,m_can"; 2698 reg = <0x00 0x02781000 0x00 0x200>, 2699 <0x00 0x02788000 0x00 0x8000>; 2700 reg-names = "m_can", "message_ram"; 2701 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 2702 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>; 2703 clock-names = "hclk", "cclk"; 2704 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 2706 interrupt-names = "int0", "int1"; 2707 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2708 status = "disabled"; 2709 }; 2710 2711 main_mcan9: can@2791000 { 2712 compatible = "bosch,m_can"; 2713 reg = <0x00 0x02791000 0x00 0x200>, 2714 <0x00 0x02798000 0x00 0x8000>; 2715 reg-names = "m_can", "message_ram"; 2716 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 2717 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>; 2718 clock-names = "hclk", "cclk"; 2719 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2721 interrupt-names = "int0", "int1"; 2722 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2723 status = "disabled"; 2724 }; 2725 2726 main_mcan10: can@27a1000 { 2727 compatible = "bosch,m_can"; 2728 reg = <0x00 0x027a1000 0x00 0x200>, 2729 <0x00 0x027a8000 0x00 0x8000>; 2730 reg-names = "m_can", "message_ram"; 2731 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 2732 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>; 2733 clock-names = "hclk", "cclk"; 2734 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 2735 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2736 interrupt-names = "int0", "int1"; 2737 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2738 status = "disabled"; 2739 }; 2740 2741 main_mcan11: can@27b1000 { 2742 compatible = "bosch,m_can"; 2743 reg = <0x00 0x027b1000 0x00 0x200>, 2744 <0x00 0x027b8000 0x00 0x8000>; 2745 reg-names = "m_can", "message_ram"; 2746 power-domains = <&k3_pds 169 TI_SCI_PD_EXCLUSIVE>; 2747 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>; 2748 clock-names = "hclk", "cclk"; 2749 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2751 interrupt-names = "int0", "int1"; 2752 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2753 status = "disabled"; 2754 }; 2755 2756 main_mcan12: can@27c1000 { 2757 compatible = "bosch,m_can"; 2758 reg = <0x00 0x027c1000 0x00 0x200>, 2759 <0x00 0x027c8000 0x00 0x8000>; 2760 reg-names = "m_can", "message_ram"; 2761 power-domains = <&k3_pds 170 TI_SCI_PD_EXCLUSIVE>; 2762 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>; 2763 clock-names = "hclk", "cclk"; 2764 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 2766 interrupt-names = "int0", "int1"; 2767 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2768 status = "disabled"; 2769 }; 2770 2771 main_mcan13: can@27d1000 { 2772 compatible = "bosch,m_can"; 2773 reg = <0x00 0x027d1000 0x00 0x200>, 2774 <0x00 0x027d8000 0x00 0x8000>; 2775 reg-names = "m_can", "message_ram"; 2776 power-domains = <&k3_pds 171 TI_SCI_PD_EXCLUSIVE>; 2777 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>; 2778 clock-names = "hclk", "cclk"; 2779 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2781 interrupt-names = "int0", "int1"; 2782 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2783 status = "disabled"; 2784 }; 2785 2786 main_spi0: spi@2100000 { 2787 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2788 reg = <0x00 0x02100000 0x00 0x400>; 2789 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2790 #address-cells = <1>; 2791 #size-cells = <0>; 2792 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2793 clocks = <&k3_clks 266 1>; 2794 status = "disabled"; 2795 }; 2796 2797 main_spi1: spi@2110000 { 2798 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2799 reg = <0x00 0x02110000 0x00 0x400>; 2800 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2801 #address-cells = <1>; 2802 #size-cells = <0>; 2803 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2804 clocks = <&k3_clks 267 1>; 2805 status = "disabled"; 2806 }; 2807 2808 main_spi2: spi@2120000 { 2809 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2810 reg = <0x00 0x02120000 0x00 0x400>; 2811 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2812 #address-cells = <1>; 2813 #size-cells = <0>; 2814 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2815 clocks = <&k3_clks 268 1>; 2816 status = "disabled"; 2817 }; 2818 2819 main_spi3: spi@2130000 { 2820 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2821 reg = <0x00 0x02130000 0x00 0x400>; 2822 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2823 #address-cells = <1>; 2824 #size-cells = <0>; 2825 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2826 clocks = <&k3_clks 269 1>; 2827 status = "disabled"; 2828 }; 2829 2830 main_spi4: spi@2140000 { 2831 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2832 reg = <0x00 0x02140000 0x00 0x400>; 2833 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2834 #address-cells = <1>; 2835 #size-cells = <0>; 2836 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2837 clocks = <&k3_clks 270 1>; 2838 status = "disabled"; 2839 }; 2840 2841 main_spi5: spi@2150000 { 2842 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2843 reg = <0x00 0x02150000 0x00 0x400>; 2844 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2845 #address-cells = <1>; 2846 #size-cells = <0>; 2847 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2848 clocks = <&k3_clks 271 1>; 2849 status = "disabled"; 2850 }; 2851 2852 main_spi6: spi@2160000 { 2853 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2854 reg = <0x00 0x02160000 0x00 0x400>; 2855 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2856 #address-cells = <1>; 2857 #size-cells = <0>; 2858 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2859 clocks = <&k3_clks 272 1>; 2860 status = "disabled"; 2861 }; 2862 2863 main_spi7: spi@2170000 { 2864 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2865 reg = <0x00 0x02170000 0x00 0x400>; 2866 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2867 #address-cells = <1>; 2868 #size-cells = <0>; 2869 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2870 clocks = <&k3_clks 273 1>; 2871 status = "disabled"; 2872 }; 2873 2874 main_esm: esm@700000 { 2875 compatible = "ti,j721e-esm"; 2876 reg = <0x0 0x700000 0x0 0x1000>; 2877 bootph-pre-ram; 2878 ti,esm-pins = <344>, <345>; 2879 }; 2880}; 2881