1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../base.h"
6 #include "../pci.h"
7 #include "../core.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "dm.h"
12 #include "fw.h"
13 #include "trx.h"
14
rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw * hw)15 static void rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
16 {
17 u32 ret_value;
18 struct rtl_priv *rtlpriv = rtl_priv(hw);
19 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
20
21 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
22 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
23
24 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
25 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
26 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
27
28 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
29 falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
30 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
31
32 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
33 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
34 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
35
36 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
37 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
38
39 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
40 falsealm_cnt->cnt_rate_illegal +
41 falsealm_cnt->cnt_crc8_fail +
42 falsealm_cnt->cnt_mcs_fail +
43 falsealm_cnt->cnt_fast_fsync_fail +
44 falsealm_cnt->cnt_sb_search_fail;
45
46 ret_value = rtl_get_bbreg(hw, DM_REG_SC_CNT_11N, MASKDWORD);
47 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
48 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
49
50 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1);
51 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1);
52
53 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_LSB_11N, MASKBYTE0);
54 falsealm_cnt->cnt_cck_fail = ret_value;
55
56 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_MSB_11N, MASKBYTE3);
57 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
58
59 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD);
60 falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
61 ((ret_value & 0xFF00) >> 8);
62
63 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
64 falsealm_cnt->cnt_sb_search_fail +
65 falsealm_cnt->cnt_parity_fail +
66 falsealm_cnt->cnt_rate_illegal +
67 falsealm_cnt->cnt_crc8_fail +
68 falsealm_cnt->cnt_mcs_fail +
69 falsealm_cnt->cnt_cck_fail;
70
71 falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
72 falsealm_cnt->cnt_cck_cca;
73
74 /*reset false alarm counter registers*/
75 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
76 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
77 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
78 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
79 /*update ofdm counter*/
80 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
81 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
82 /*reset CCK CCA counter*/
83 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0);
84 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2);
85 /*reset CCK FA counter*/
86 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0);
87 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
88
89 rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
90 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
91 falsealm_cnt->cnt_parity_fail,
92 falsealm_cnt->cnt_rate_illegal,
93 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
94
95 rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
96 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
97 falsealm_cnt->cnt_ofdm_fail,
98 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
99 }
100
rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw * hw)101 static void rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
102 {
103 struct rtl_priv *rtlpriv = rtl_priv(hw);
104 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
105 u8 cur_cck_cca_thresh;
106
107 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
108 if (dm_dig->rssi_val_min > 25) {
109 cur_cck_cca_thresh = 0xcd;
110 } else if ((dm_dig->rssi_val_min <= 25) &&
111 (dm_dig->rssi_val_min > 10)) {
112 cur_cck_cca_thresh = 0x83;
113 } else {
114 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
115 cur_cck_cca_thresh = 0x83;
116 else
117 cur_cck_cca_thresh = 0x40;
118 }
119 } else {
120 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
121 cur_cck_cca_thresh = 0x83;
122 else
123 cur_cck_cca_thresh = 0x40;
124 }
125 rtl92ee_dm_write_cck_cca_thres(hw, cur_cck_cca_thresh);
126 }
127
rtl92ee_dm_dig(struct ieee80211_hw * hw)128 static void rtl92ee_dm_dig(struct ieee80211_hw *hw)
129 {
130 struct rtl_priv *rtlpriv = rtl_priv(hw);
131 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
132 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
133 u8 dig_min_0, dig_maxofmin;
134 bool bfirstconnect , bfirstdisconnect;
135 u8 dm_dig_max, dm_dig_min;
136 u8 current_igi = dm_dig->cur_igvalue;
137 u8 offset;
138
139 /* AP,BT */
140 if (mac->act_scanning)
141 return;
142
143 dig_min_0 = dm_dig->dig_min_0;
144 bfirstconnect = (mac->link_state >= MAC80211_LINKED) &&
145 !dm_dig->media_connect_0;
146 bfirstdisconnect = (mac->link_state < MAC80211_LINKED) &&
147 dm_dig->media_connect_0;
148
149 dm_dig_max = 0x5a;
150 dm_dig_min = DM_DIG_MIN;
151 dig_maxofmin = DM_DIG_MAX_AP;
152
153 if (mac->link_state >= MAC80211_LINKED) {
154 if ((dm_dig->rssi_val_min + 10) > dm_dig_max)
155 dm_dig->rx_gain_max = dm_dig_max;
156 else if ((dm_dig->rssi_val_min + 10) < dm_dig_min)
157 dm_dig->rx_gain_max = dm_dig_min;
158 else
159 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 10;
160
161 if (rtlpriv->dm.one_entry_only) {
162 offset = 0;
163 if (dm_dig->rssi_val_min - offset < dm_dig_min)
164 dig_min_0 = dm_dig_min;
165 else if (dm_dig->rssi_val_min - offset >
166 dig_maxofmin)
167 dig_min_0 = dig_maxofmin;
168 else
169 dig_min_0 = dm_dig->rssi_val_min - offset;
170 } else {
171 dig_min_0 = dm_dig_min;
172 }
173
174 } else {
175 dm_dig->rx_gain_max = dm_dig_max;
176 dig_min_0 = dm_dig_min;
177 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
178 }
179
180 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
181 if (dm_dig->large_fa_hit != 3)
182 dm_dig->large_fa_hit++;
183 if (dm_dig->forbidden_igi < current_igi) {
184 dm_dig->forbidden_igi = current_igi;
185 dm_dig->large_fa_hit = 1;
186 }
187
188 if (dm_dig->large_fa_hit >= 3) {
189 if (dm_dig->forbidden_igi + 1 > dm_dig->rx_gain_max)
190 dm_dig->rx_gain_min =
191 dm_dig->rx_gain_max;
192 else
193 dm_dig->rx_gain_min =
194 dm_dig->forbidden_igi + 1;
195 dm_dig->recover_cnt = 3600;
196 }
197 } else {
198 if (dm_dig->recover_cnt != 0) {
199 dm_dig->recover_cnt--;
200 } else {
201 if (dm_dig->large_fa_hit < 3) {
202 if ((dm_dig->forbidden_igi - 1) <
203 dig_min_0) {
204 dm_dig->forbidden_igi = dig_min_0;
205 dm_dig->rx_gain_min =
206 dig_min_0;
207 } else {
208 dm_dig->forbidden_igi--;
209 dm_dig->rx_gain_min =
210 dm_dig->forbidden_igi + 1;
211 }
212 } else {
213 dm_dig->large_fa_hit = 0;
214 }
215 }
216 }
217
218 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5)
219 dm_dig->rx_gain_min = dm_dig_min;
220
221 if (dm_dig->rx_gain_min > dm_dig->rx_gain_max)
222 dm_dig->rx_gain_min = dm_dig->rx_gain_max;
223
224 if (mac->link_state >= MAC80211_LINKED) {
225 if (bfirstconnect) {
226 current_igi = min(dm_dig->rssi_val_min, dig_maxofmin);
227
228 dm_dig->large_fa_hit = 0;
229 } else {
230 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
231 current_igi += 4;
232 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
233 current_igi += 2;
234 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
235 current_igi -= 2;
236
237 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5 &&
238 rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
239 current_igi = dm_dig->rx_gain_min;
240 }
241 } else {
242 if (bfirstdisconnect) {
243 current_igi = dm_dig->rx_gain_min;
244 } else {
245 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
246 current_igi += 4;
247 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
248 current_igi += 2;
249 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
250 current_igi -= 2;
251 }
252 }
253
254 if (current_igi > dm_dig->rx_gain_max)
255 current_igi = dm_dig->rx_gain_max;
256 if (current_igi < dm_dig->rx_gain_min)
257 current_igi = dm_dig->rx_gain_min;
258
259 rtl92ee_dm_write_dig(hw , current_igi);
260 dm_dig->media_connect_0 = ((mac->link_state >= MAC80211_LINKED) ?
261 true : false);
262 dm_dig->dig_min_0 = dig_min_0;
263 }
264
rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw * hw,u8 cur_thres)265 void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 cur_thres)
266 {
267 struct rtl_priv *rtlpriv = rtl_priv(hw);
268 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
269
270 if (dm_dig->cur_cck_cca_thres != cur_thres)
271 rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11N, cur_thres);
272
273 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
274 dm_dig->cur_cck_cca_thres = cur_thres;
275 }
276
rtl92ee_dm_write_dig(struct ieee80211_hw * hw,u8 current_igi)277 void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
278 {
279 struct rtl_priv *rtlpriv = rtl_priv(hw);
280 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
281
282 if (dm_dig->stop_dig)
283 return;
284
285 if (dm_dig->cur_igvalue != current_igi) {
286 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi);
287 if (rtlpriv->phy.rf_type != RF_1T1R)
288 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, current_igi);
289 }
290 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
291 dm_dig->cur_igvalue = current_igi;
292 }
293
rtl92ee_rssi_dump_to_register(struct ieee80211_hw * hw)294 static void rtl92ee_rssi_dump_to_register(struct ieee80211_hw *hw)
295 {
296 struct rtl_priv *rtlpriv = rtl_priv(hw);
297
298 rtl_write_byte(rtlpriv, RA_RSSIDUMP,
299 rtlpriv->stats.rx_rssi_percentage[0]);
300 rtl_write_byte(rtlpriv, RB_RSSIDUMP,
301 rtlpriv->stats.rx_rssi_percentage[1]);
302 /*It seems the following values are not initialized.
303 *According to Windows code,
304 *these value will only be valid with JAGUAR chips
305 */
306 /* Rx EVM */
307 rtl_write_byte(rtlpriv, RS1_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[0]);
308 rtl_write_byte(rtlpriv, RS2_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[1]);
309 /* Rx SNR */
310 rtl_write_byte(rtlpriv, RA_RXSNRDUMP,
311 (u8)(rtlpriv->stats.rx_snr_db[0]));
312 rtl_write_byte(rtlpriv, RB_RXSNRDUMP,
313 (u8)(rtlpriv->stats.rx_snr_db[1]));
314 /* Rx Cfo_Short */
315 rtl_write_word(rtlpriv, RA_CFOSHORTDUMP,
316 rtlpriv->stats.rx_cfo_short[0]);
317 rtl_write_word(rtlpriv, RB_CFOSHORTDUMP,
318 rtlpriv->stats.rx_cfo_short[1]);
319 /* Rx Cfo_Tail */
320 rtl_write_word(rtlpriv, RA_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[0]);
321 rtl_write_word(rtlpriv, RB_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[1]);
322 }
323
rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw * hw)324 static void rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw *hw)
325 {
326 struct rtl_priv *rtlpriv = rtl_priv(hw);
327 struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
328 struct rtl_mac *mac = rtl_mac(rtlpriv);
329
330 /* Determine the minimum RSSI */
331 if ((mac->link_state < MAC80211_LINKED) &&
332 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
333 rtl_dm_dig->min_undec_pwdb_for_dm = 0;
334 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
335 "Not connected to any\n");
336 }
337 if (mac->link_state >= MAC80211_LINKED) {
338 if (mac->opmode == NL80211_IFTYPE_AP ||
339 mac->opmode == NL80211_IFTYPE_ADHOC) {
340 rtl_dm_dig->min_undec_pwdb_for_dm =
341 rtlpriv->dm.entry_min_undec_sm_pwdb;
342 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
343 "AP Client PWDB = 0x%lx\n",
344 rtlpriv->dm.entry_min_undec_sm_pwdb);
345 } else {
346 rtl_dm_dig->min_undec_pwdb_for_dm =
347 rtlpriv->dm.undec_sm_pwdb;
348 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
349 "STA Default Port PWDB = 0x%x\n",
350 rtl_dm_dig->min_undec_pwdb_for_dm);
351 }
352 } else {
353 rtl_dm_dig->min_undec_pwdb_for_dm =
354 rtlpriv->dm.entry_min_undec_sm_pwdb;
355 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
356 "AP Ext Port or disconnect PWDB = 0x%x\n",
357 rtl_dm_dig->min_undec_pwdb_for_dm);
358 }
359 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
360 "MinUndecoratedPWDBForDM =%d\n",
361 rtl_dm_dig->min_undec_pwdb_for_dm);
362 }
363
rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw * hw)364 static void rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw *hw)
365 {
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
368 struct rtl_mac *mac = rtl_mac(rtlpriv);
369 struct rtl_dm *dm = rtl_dm(rtlpriv);
370 struct rtl_sta_info *drv_priv;
371 u8 h2c[4] = { 0 };
372 long max = 0, min = 0xff;
373 u8 i = 0;
374
375 if (mac->opmode == NL80211_IFTYPE_AP ||
376 mac->opmode == NL80211_IFTYPE_ADHOC ||
377 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
378 /* AP & ADHOC & MESH */
379 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
380 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
381 struct rssi_sta *stat = &drv_priv->rssi_stat;
382
383 if (stat->undec_sm_pwdb < min)
384 min = stat->undec_sm_pwdb;
385 if (stat->undec_sm_pwdb > max)
386 max = stat->undec_sm_pwdb;
387
388 h2c[3] = 0;
389 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
390 h2c[1] = 0x20;
391 h2c[0] = ++i;
392 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
393 }
394 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
395
396 /* If associated entry is found */
397 if (max != 0) {
398 dm->entry_max_undec_sm_pwdb = max;
399 RTPRINT(rtlpriv, FDM, DM_PWDB,
400 "EntryMaxPWDB = 0x%lx(%ld)\n", max, max);
401 } else {
402 dm->entry_max_undec_sm_pwdb = 0;
403 }
404 /* If associated entry is found */
405 if (min != 0xff) {
406 dm->entry_min_undec_sm_pwdb = min;
407 RTPRINT(rtlpriv, FDM, DM_PWDB,
408 "EntryMinPWDB = 0x%lx(%ld)\n", min, min);
409 } else {
410 dm->entry_min_undec_sm_pwdb = 0;
411 }
412 }
413
414 /* Indicate Rx signal strength to FW. */
415 if (dm->useramask) {
416 h2c[3] = 0;
417 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
418 h2c[1] = 0x20;
419 h2c[0] = 0;
420 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
421 } else {
422 rtl_write_byte(rtlpriv, 0x4fe, dm->undec_sm_pwdb);
423 }
424 rtl92ee_rssi_dump_to_register(hw);
425 rtl92ee_dm_find_minimum_rssi(hw);
426 dm_dig->rssi_val_min = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
427 }
428
rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw * hw)429 static void rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw *hw)
430 {
431 struct rtl_priv *rtlpriv = rtl_priv(hw);
432 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
433
434 primarycca->dup_rts_flag = 0;
435 primarycca->intf_flag = 0;
436 primarycca->intf_type = 0;
437 primarycca->monitor_flag = 0;
438 primarycca->ch_offset = 0;
439 primarycca->mf_state = 0;
440 }
441
rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw * hw)442 static bool rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
443 {
444 struct rtl_priv *rtlpriv = rtl_priv(hw);
445
446 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
447 return true;
448
449 return false;
450 }
451
rtl92ee_dm_init_edca_turbo(struct ieee80211_hw * hw)452 void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw)
453 {
454 struct rtl_priv *rtlpriv = rtl_priv(hw);
455
456 rtlpriv->dm.current_turbo_edca = false;
457 rtlpriv->dm.is_cur_rdlstate = false;
458 rtlpriv->dm.is_any_nonbepkts = false;
459 }
460
rtl92ee_dm_check_edca_turbo(struct ieee80211_hw * hw)461 static void rtl92ee_dm_check_edca_turbo(struct ieee80211_hw *hw)
462 {
463 struct rtl_priv *rtlpriv = rtl_priv(hw);
464
465 static u64 last_txok_cnt;
466 static u64 last_rxok_cnt;
467 u64 cur_txok_cnt = 0;
468 u64 cur_rxok_cnt = 0;
469 u32 edca_be_ul = 0x5ea42b;
470 u32 edca_be_dl = 0x5ea42b; /*not sure*/
471 u32 edca_be = 0x5ea42b;
472 bool is_cur_rdlstate;
473 bool b_edca_turbo_on = false;
474
475 if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
476 rtlpriv->dm.is_any_nonbepkts = true;
477 rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
478
479 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
480 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
481
482 /*b_bias_on_rx = false;*/
483 b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
484 (!rtlpriv->dm.disable_framebursting)) ?
485 true : false;
486
487 if (rtl92ee_dm_is_edca_turbo_disable(hw))
488 goto check_exit;
489
490 if (b_edca_turbo_on) {
491 is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ?
492 true : false;
493
494 edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
495 rtl_write_dword(rtlpriv , REG_EDCA_BE_PARAM , edca_be);
496 rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
497 rtlpriv->dm.current_turbo_edca = true;
498 } else {
499 if (rtlpriv->dm.current_turbo_edca) {
500 u8 tmp = AC0_BE;
501
502 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
503 (u8 *)(&tmp));
504 }
505 rtlpriv->dm.current_turbo_edca = false;
506 }
507
508 check_exit:
509 rtlpriv->dm.is_any_nonbepkts = false;
510 last_txok_cnt = rtlpriv->stats.txbytesunicast;
511 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
512 }
513
rtl92ee_dm_dynamic_edcca(struct ieee80211_hw * hw)514 static void rtl92ee_dm_dynamic_edcca(struct ieee80211_hw *hw)
515 {
516 struct rtl_priv *rtlpriv = rtl_priv(hw);
517 u8 reg_c50 , reg_c58;
518 bool fw_current_in_ps_mode = false;
519
520 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
521 (u8 *)(&fw_current_in_ps_mode));
522 if (fw_current_in_ps_mode)
523 return;
524
525 reg_c50 = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
526 reg_c58 = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
527
528 if (reg_c50 > 0x28 && reg_c58 > 0x28) {
529 if (!rtlpriv->rtlhal.pre_edcca_enable) {
530 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x03);
531 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x00);
532 rtlpriv->rtlhal.pre_edcca_enable = true;
533 }
534 } else if (reg_c50 < 0x25 && reg_c58 < 0x25) {
535 if (rtlpriv->rtlhal.pre_edcca_enable) {
536 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x7f);
537 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x7f);
538 rtlpriv->rtlhal.pre_edcca_enable = false;
539 }
540 }
541 }
542
rtl92ee_dm_adaptivity(struct ieee80211_hw * hw)543 static void rtl92ee_dm_adaptivity(struct ieee80211_hw *hw)
544 {
545 rtl92ee_dm_dynamic_edcca(hw);
546 }
547
rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw * hw,u8 cur_mf_state)548 static void rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw *hw,
549 u8 cur_mf_state)
550 {
551 struct dynamic_primary_cca *primarycca = &rtl_priv(hw)->primarycca;
552
553 if (primarycca->mf_state != cur_mf_state)
554 rtl_set_bbreg(hw, DM_REG_L1SBD_PD_CH_11N, BIT(8) | BIT(7),
555 cur_mf_state);
556
557 primarycca->mf_state = cur_mf_state;
558 }
559
rtl92ee_dm_dynamic_primary_cca_check(struct ieee80211_hw * hw)560 static void rtl92ee_dm_dynamic_primary_cca_check(struct ieee80211_hw *hw)
561 {
562 struct rtl_priv *rtlpriv = rtl_priv(hw);
563 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
564 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
565 bool is40mhz = false;
566 u64 ofdm_cca, ofdm_fa, bw_usc_cnt, bw_lsc_cnt;
567 u8 sec_ch_offset;
568 u8 cur_mf_state;
569 static u8 count_down = MONITOR_TIME;
570
571 ofdm_cca = falsealm_cnt->cnt_ofdm_cca;
572 ofdm_fa = falsealm_cnt->cnt_ofdm_fail;
573 bw_usc_cnt = falsealm_cnt->cnt_bw_usc;
574 bw_lsc_cnt = falsealm_cnt->cnt_bw_lsc;
575 is40mhz = rtlpriv->mac80211.bw_40;
576 sec_ch_offset = rtlpriv->mac80211.cur_40_prime_sc;
577 /* NIC: 2: sec is below, 1: sec is above */
578
579 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) {
580 cur_mf_state = MF_USC_LSC;
581 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
582 return;
583 }
584
585 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
586 return;
587
588 if (is40mhz)
589 return;
590
591 if (primarycca->pricca_flag == 0) {
592 /* Primary channel is above
593 * NOTE: duplicate CTS can remove this condition
594 */
595 if (sec_ch_offset == 2) {
596 if ((ofdm_cca > OFDMCCA_TH) &&
597 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
598 (ofdm_fa > (ofdm_cca >> 1))) {
599 primarycca->intf_type = 1;
600 primarycca->intf_flag = 1;
601 cur_mf_state = MF_USC;
602 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
603 primarycca->pricca_flag = 1;
604 } else if ((ofdm_cca > OFDMCCA_TH) &&
605 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
606 (ofdm_fa < (ofdm_cca >> 1))) {
607 primarycca->intf_type = 2;
608 primarycca->intf_flag = 1;
609 cur_mf_state = MF_USC;
610 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
611 primarycca->pricca_flag = 1;
612 primarycca->dup_rts_flag = 1;
613 } else {
614 primarycca->intf_type = 0;
615 primarycca->intf_flag = 0;
616 cur_mf_state = MF_USC_LSC;
617 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
618 primarycca->dup_rts_flag = 0;
619 }
620 } else if (sec_ch_offset == 1) {
621 if ((ofdm_cca > OFDMCCA_TH) &&
622 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
623 (ofdm_fa > (ofdm_cca >> 1))) {
624 primarycca->intf_type = 1;
625 primarycca->intf_flag = 1;
626 cur_mf_state = MF_LSC;
627 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
628 primarycca->pricca_flag = 1;
629 } else if ((ofdm_cca > OFDMCCA_TH) &&
630 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
631 (ofdm_fa < (ofdm_cca >> 1))) {
632 primarycca->intf_type = 2;
633 primarycca->intf_flag = 1;
634 cur_mf_state = MF_LSC;
635 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
636 primarycca->pricca_flag = 1;
637 primarycca->dup_rts_flag = 1;
638 } else {
639 primarycca->intf_type = 0;
640 primarycca->intf_flag = 0;
641 cur_mf_state = MF_USC_LSC;
642 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
643 primarycca->dup_rts_flag = 0;
644 }
645 }
646 } else {/* PrimaryCCA->PriCCA_flag==1 */
647 count_down--;
648 if (count_down == 0) {
649 count_down = MONITOR_TIME;
650 primarycca->pricca_flag = 0;
651 cur_mf_state = MF_USC_LSC;
652 /* default */
653 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
654 primarycca->dup_rts_flag = 0;
655 primarycca->intf_type = 0;
656 primarycca->intf_flag = 0;
657 }
658 }
659 }
660
rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw * hw)661 static void rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
662 {
663 struct rtl_priv *rtlpriv = rtl_priv(hw);
664 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
665 u8 crystal_cap;
666 u32 packet_count;
667 int cfo_khz_a , cfo_khz_b , cfo_ave = 0, adjust_xtal = 0;
668 int cfo_ave_diff;
669
670 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
671 if (rtldm->atc_status == ATC_STATUS_OFF) {
672 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
673 ATC_STATUS_ON);
674 rtldm->atc_status = ATC_STATUS_ON;
675 }
676 /* Disable CFO tracking for BT */
677 if (rtlpriv->cfg->ops->get_btc_status()) {
678 if (!rtlpriv->btcoexist.btc_ops->
679 btc_is_bt_disabled(rtlpriv)) {
680 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
681 "odm_DynamicATCSwitch(): Disable CFO tracking for BT!!\n");
682 return;
683 }
684 }
685 /* Reset Crystal Cap */
686 if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap) {
687 rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
688 crystal_cap = rtldm->crystal_cap & 0x3f;
689 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
690 (crystal_cap | (crystal_cap << 6)));
691 }
692 } else {
693 cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
694 cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
695 packet_count = rtldm->packet_count;
696
697 if (packet_count == rtldm->packet_count_pre)
698 return;
699
700 rtldm->packet_count_pre = packet_count;
701
702 if (rtlpriv->phy.rf_type == RF_1T1R)
703 cfo_ave = cfo_khz_a;
704 else
705 cfo_ave = (int)(cfo_khz_a + cfo_khz_b) >> 1;
706
707 cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave) ?
708 (rtldm->cfo_ave_pre - cfo_ave) :
709 (cfo_ave - rtldm->cfo_ave_pre);
710
711 if (cfo_ave_diff > 20 && !rtldm->large_cfo_hit) {
712 rtldm->large_cfo_hit = true;
713 return;
714 }
715 rtldm->large_cfo_hit = false;
716
717 rtldm->cfo_ave_pre = cfo_ave;
718
719 if (cfo_ave >= -rtldm->cfo_threshold &&
720 cfo_ave <= rtldm->cfo_threshold && rtldm->is_freeze == 0) {
721 if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL) {
722 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
723 rtldm->is_freeze = 1;
724 } else {
725 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
726 }
727 }
728
729 if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
730 adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
731 else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) &&
732 rtlpriv->dm.crystal_cap > 0)
733 adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
734
735 if (adjust_xtal != 0) {
736 rtldm->is_freeze = 0;
737 rtldm->crystal_cap += adjust_xtal;
738
739 if (rtldm->crystal_cap > 0x3f)
740 rtldm->crystal_cap = 0x3f;
741 else if (rtldm->crystal_cap < 0)
742 rtldm->crystal_cap = 0;
743
744 crystal_cap = rtldm->crystal_cap & 0x3f;
745 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
746 (crystal_cap | (crystal_cap << 6)));
747 }
748
749 if (cfo_ave < CFO_THRESHOLD_ATC &&
750 cfo_ave > -CFO_THRESHOLD_ATC) {
751 if (rtldm->atc_status == ATC_STATUS_ON) {
752 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
753 ATC_STATUS_OFF);
754 rtldm->atc_status = ATC_STATUS_OFF;
755 }
756 } else {
757 if (rtldm->atc_status == ATC_STATUS_OFF) {
758 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
759 ATC_STATUS_ON);
760 rtldm->atc_status = ATC_STATUS_ON;
761 }
762 }
763 }
764 }
765
rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw * hw)766 static void rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw *hw)
767 {
768 struct rtl_priv *rtlpriv = rtl_priv(hw);
769 struct rtl_dm *dm = rtl_dm(rtlpriv);
770 u8 path;
771
772 dm->txpower_tracking = true;
773 dm->default_ofdm_index = 30;
774 dm->default_cck_index = 20;
775
776 dm->swing_idx_cck_base = dm->default_cck_index;
777 dm->cck_index = dm->default_cck_index;
778
779 for (path = RF90_PATH_A; path < MAX_RF_PATH; path++) {
780 dm->swing_idx_ofdm_base[path] = dm->default_ofdm_index;
781 dm->ofdm_index[path] = dm->default_ofdm_index;
782 dm->delta_power_index[path] = 0;
783 dm->delta_power_index_last[path] = 0;
784 dm->power_index_offset[path] = 0;
785 }
786 }
787
rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw * hw)788 void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
789 {
790 struct rtl_priv *rtlpriv = rtl_priv(hw);
791 struct rate_adaptive *p_ra = &rtlpriv->ra;
792
793 p_ra->ratr_state = DM_RATR_STA_INIT;
794 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
795
796 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
797 rtlpriv->dm.useramask = true;
798 else
799 rtlpriv->dm.useramask = false;
800
801 p_ra->ldpc_thres = 35;
802 p_ra->use_ldpc = false;
803 p_ra->high_rssi_thresh_for_ra = 50;
804 p_ra->low_rssi_thresh_for_ra40m = 20;
805 }
806
_rtl92ee_dm_ra_state_check(struct ieee80211_hw * hw,s32 rssi,u8 * ratr_state)807 static bool _rtl92ee_dm_ra_state_check(struct ieee80211_hw *hw,
808 s32 rssi, u8 *ratr_state)
809 {
810 struct rtl_priv *rtlpriv = rtl_priv(hw);
811 struct rate_adaptive *p_ra = &rtlpriv->ra;
812 const u8 go_up_gap = 5;
813 u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
814 u32 low_rssithresh_for_ra = p_ra->low_rssi_thresh_for_ra40m;
815 u8 state;
816
817 /* Threshold Adjustment:
818 * when RSSI state trends to go up one or two levels,
819 * make sure RSSI is high enough.
820 * Here GoUpGap is added to solve
821 * the boundary's level alternation issue.
822 */
823 switch (*ratr_state) {
824 case DM_RATR_STA_INIT:
825 case DM_RATR_STA_HIGH:
826 break;
827 case DM_RATR_STA_MIDDLE:
828 high_rssithresh_for_ra += go_up_gap;
829 break;
830 case DM_RATR_STA_LOW:
831 high_rssithresh_for_ra += go_up_gap;
832 low_rssithresh_for_ra += go_up_gap;
833 break;
834 default:
835 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
836 "wrong rssi level setting %d !\n", *ratr_state);
837 break;
838 }
839
840 /* Decide RATRState by RSSI. */
841 if (rssi > high_rssithresh_for_ra)
842 state = DM_RATR_STA_HIGH;
843 else if (rssi > low_rssithresh_for_ra)
844 state = DM_RATR_STA_MIDDLE;
845 else
846 state = DM_RATR_STA_LOW;
847
848 if (*ratr_state != state) {
849 *ratr_state = state;
850 return true;
851 }
852
853 return false;
854 }
855
rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw * hw)856 static void rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
857 {
858 struct rtl_priv *rtlpriv = rtl_priv(hw);
859 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
860 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
861 struct rate_adaptive *p_ra = &rtlpriv->ra;
862 struct ieee80211_sta *sta = NULL;
863
864 if (is_hal_stop(rtlhal)) {
865 rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
866 "driver is going to unload\n");
867 return;
868 }
869
870 if (!rtlpriv->dm.useramask) {
871 rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
872 "driver does not control rate adaptive mask\n");
873 return;
874 }
875
876 if (mac->link_state == MAC80211_LINKED &&
877 mac->opmode == NL80211_IFTYPE_STATION) {
878 if (rtlpriv->dm.undec_sm_pwdb < p_ra->ldpc_thres) {
879 p_ra->use_ldpc = true;
880 p_ra->lower_rts_rate = true;
881 } else if (rtlpriv->dm.undec_sm_pwdb >
882 (p_ra->ldpc_thres - 5)) {
883 p_ra->use_ldpc = false;
884 p_ra->lower_rts_rate = false;
885 }
886 if (_rtl92ee_dm_ra_state_check(hw, rtlpriv->dm.undec_sm_pwdb,
887 &p_ra->ratr_state)) {
888 rcu_read_lock();
889 sta = rtl_find_sta(hw, mac->bssid);
890 if (sta)
891 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
892 p_ra->ratr_state,
893 true);
894 rcu_read_unlock();
895
896 p_ra->pre_ratr_state = p_ra->ratr_state;
897 }
898 }
899 }
900
rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw * hw)901 static void rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
902 {
903 struct rtl_priv *rtlpriv = rtl_priv(hw);
904
905 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
906
907 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
908 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
909 }
910
rtl92ee_dm_init(struct ieee80211_hw * hw)911 void rtl92ee_dm_init(struct ieee80211_hw *hw)
912 {
913 struct rtl_priv *rtlpriv = rtl_priv(hw);
914 u32 cur_igvalue = rtl_get_bbreg(hw, DM_REG_IGI_A_11N, DM_BIT_IGI_11N);
915
916 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
917
918 rtl_dm_diginit(hw, cur_igvalue);
919 rtl92ee_dm_init_rate_adaptive_mask(hw);
920 rtl92ee_dm_init_primary_cca_check(hw);
921 rtl92ee_dm_init_edca_turbo(hw);
922 rtl92ee_dm_init_txpower_tracking(hw);
923 rtl92ee_dm_init_dynamic_atc_switch(hw);
924 }
925
rtl92ee_dm_common_info_self_update(struct ieee80211_hw * hw)926 static void rtl92ee_dm_common_info_self_update(struct ieee80211_hw *hw)
927 {
928 struct rtl_priv *rtlpriv = rtl_priv(hw);
929 u8 cnt;
930
931 rtlpriv->dm.one_entry_only = false;
932
933 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
934 rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
935 rtlpriv->dm.one_entry_only = true;
936 return;
937 }
938
939 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
940 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
941 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
942 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
943 cnt = list_count_nodes(&rtlpriv->entry_list);
944 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
945
946 if (cnt == 1)
947 rtlpriv->dm.one_entry_only = true;
948 }
949 }
950
rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw * hw,u8 rate,bool collision_state)951 void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
952 u8 rate, bool collision_state)
953 {
954 struct rtl_priv *rtlpriv = rtl_priv(hw);
955
956 if (rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS12) {
957 if (collision_state == 1) {
958 if (rate == DESC92C_RATEMCS12) {
959 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
960 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
961 0x07060501);
962 } else if (rate == DESC92C_RATEMCS11) {
963 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
964 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
965 0x07070605);
966 } else if (rate == DESC92C_RATEMCS10) {
967 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
968 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
969 0x08080706);
970 } else if (rate == DESC92C_RATEMCS9) {
971 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
972 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
973 0x08080707);
974 } else {
975 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
976 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
977 0x09090808);
978 }
979 } else { /* collision_state == 0 */
980 if (rate == DESC92C_RATEMCS12) {
981 rtl_write_dword(rtlpriv, REG_DARFRC,
982 0x05010000);
983 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
984 0x09080706);
985 } else if (rate == DESC92C_RATEMCS11) {
986 rtl_write_dword(rtlpriv, REG_DARFRC,
987 0x06050000);
988 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
989 0x09080807);
990 } else if (rate == DESC92C_RATEMCS10) {
991 rtl_write_dword(rtlpriv, REG_DARFRC,
992 0x07060000);
993 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
994 0x0a090908);
995 } else if (rate == DESC92C_RATEMCS9) {
996 rtl_write_dword(rtlpriv, REG_DARFRC,
997 0x07070000);
998 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
999 0x0a090808);
1000 } else {
1001 rtl_write_dword(rtlpriv, REG_DARFRC,
1002 0x08080000);
1003 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1004 0x0b0a0909);
1005 }
1006 }
1007 } else { /* MCS13~MCS15, 1SS, G-mode */
1008 if (collision_state == 1) {
1009 if (rate == DESC92C_RATEMCS15) {
1010 rtl_write_dword(rtlpriv, REG_DARFRC,
1011 0x00000000);
1012 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1013 0x05040302);
1014 } else if (rate == DESC92C_RATEMCS14) {
1015 rtl_write_dword(rtlpriv, REG_DARFRC,
1016 0x00000000);
1017 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1018 0x06050302);
1019 } else if (rate == DESC92C_RATEMCS13) {
1020 rtl_write_dword(rtlpriv, REG_DARFRC,
1021 0x00000000);
1022 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1023 0x07060502);
1024 } else {
1025 rtl_write_dword(rtlpriv, REG_DARFRC,
1026 0x00000000);
1027 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1028 0x06050402);
1029 }
1030 } else{ /* collision_state == 0 */
1031 if (rate == DESC92C_RATEMCS15) {
1032 rtl_write_dword(rtlpriv, REG_DARFRC,
1033 0x03020000);
1034 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1035 0x07060504);
1036 } else if (rate == DESC92C_RATEMCS14) {
1037 rtl_write_dword(rtlpriv, REG_DARFRC,
1038 0x03020000);
1039 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1040 0x08070605);
1041 } else if (rate == DESC92C_RATEMCS13) {
1042 rtl_write_dword(rtlpriv, REG_DARFRC,
1043 0x05020000);
1044 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1045 0x09080706);
1046 } else {
1047 rtl_write_dword(rtlpriv, REG_DARFRC,
1048 0x04020000);
1049 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1050 0x08070605);
1051 }
1052 }
1053 }
1054 }
1055
rtl92ee_dm_watchdog(struct ieee80211_hw * hw)1056 void rtl92ee_dm_watchdog(struct ieee80211_hw *hw)
1057 {
1058 struct rtl_priv *rtlpriv = rtl_priv(hw);
1059 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1060 bool fw_current_inpsmode = false;
1061 bool fw_ps_awake = true;
1062
1063 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1064 (u8 *)(&fw_current_inpsmode));
1065 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1066 (u8 *)(&fw_ps_awake));
1067 if (ppsc->p2p_ps_info.p2p_ps_mode)
1068 fw_ps_awake = false;
1069
1070 spin_lock(&rtlpriv->locks.rf_ps_lock);
1071 if ((ppsc->rfpwr_state == ERFON) &&
1072 ((!fw_current_inpsmode) && fw_ps_awake) &&
1073 (!ppsc->rfchange_inprogress)) {
1074 rtl92ee_dm_common_info_self_update(hw);
1075 rtl92ee_dm_false_alarm_counter_statistics(hw);
1076 rtl92ee_dm_check_rssi_monitor(hw);
1077 rtl92ee_dm_dig(hw);
1078 rtl92ee_dm_adaptivity(hw);
1079 rtl92ee_dm_cck_packet_detection_thresh(hw);
1080 rtl92ee_dm_refresh_rate_adaptive_mask(hw);
1081 rtl92ee_dm_check_edca_turbo(hw);
1082 rtl92ee_dm_dynamic_atc_switch(hw);
1083 rtl92ee_dm_dynamic_primary_cca_check(hw);
1084 }
1085 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1086 }
1087