1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2023, Linaro Ltd. All rights reserved.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/err.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16 #include <linux/string_choices.h>
17 #include <linux/usb/tcpm.h>
18 #include <linux/usb/typec_mux.h>
19 #include <linux/workqueue.h>
20
21 #include "qcom_pmic_typec.h"
22 #include "qcom_pmic_typec_port.h"
23
24 #define TYPEC_SNK_STATUS_REG 0x06
25 #define DETECTED_SNK_TYPE_MASK GENMASK(6, 0)
26 #define SNK_DAM_MASK GENMASK(6, 4)
27 #define SNK_DAM_500MA BIT(6)
28 #define SNK_DAM_1500MA BIT(5)
29 #define SNK_DAM_3000MA BIT(4)
30 #define SNK_RP_STD BIT(3)
31 #define SNK_RP_1P5 BIT(2)
32 #define SNK_RP_3P0 BIT(1)
33 #define SNK_RP_SHORT BIT(0)
34
35 #define TYPEC_SRC_STATUS_REG 0x08
36 #define DETECTED_SRC_TYPE_MASK GENMASK(4, 0)
37 #define SRC_HIGH_BATT BIT(5)
38 #define SRC_DEBUG_ACCESS BIT(4)
39 #define SRC_RD_OPEN BIT(3)
40 #define SRC_RD_RA_VCONN BIT(2)
41 #define SRC_RA_OPEN BIT(1)
42 #define AUDIO_ACCESS_RA_RA BIT(0)
43
44 #define TYPEC_STATE_MACHINE_STATUS_REG 0x09
45 #define TYPEC_ATTACH_DETACH_STATE BIT(5)
46
47 #define TYPEC_SM_STATUS_REG 0x0A
48 #define TYPEC_SM_VBUS_VSAFE5V BIT(5)
49 #define TYPEC_SM_VBUS_VSAFE0V BIT(6)
50 #define TYPEC_SM_USBIN_LT_LV BIT(7)
51
52 #define TYPEC_MISC_STATUS_REG 0x0B
53 #define TYPEC_WATER_DETECTION_STATUS BIT(7)
54 #define SNK_SRC_MODE BIT(6)
55 #define TYPEC_VBUS_DETECT BIT(5)
56 #define TYPEC_VBUS_ERROR_STATUS BIT(4)
57 #define TYPEC_DEBOUNCE_DONE BIT(3)
58 #define CC_ORIENTATION BIT(1)
59 #define CC_ATTACHED BIT(0)
60
61 #define LEGACY_CABLE_STATUS_REG 0x0D
62 #define TYPEC_LEGACY_CABLE_STATUS BIT(1)
63 #define TYPEC_NONCOMP_LEGACY_CABLE_STATUS BIT(0)
64
65 #define TYPEC_U_USB_STATUS_REG 0x0F
66 #define U_USB_GROUND_NOVBUS BIT(6)
67 #define U_USB_GROUND BIT(4)
68 #define U_USB_FMB1 BIT(3)
69 #define U_USB_FLOAT1 BIT(2)
70 #define U_USB_FMB2 BIT(1)
71 #define U_USB_FLOAT2 BIT(0)
72
73 #define TYPEC_MODE_CFG_REG 0x44
74 #define TYPEC_TRY_MODE_MASK GENMASK(4, 3)
75 #define EN_TRY_SNK BIT(4)
76 #define EN_TRY_SRC BIT(3)
77 #define TYPEC_POWER_ROLE_CMD_MASK GENMASK(2, 0)
78 #define EN_SRC_ONLY BIT(2)
79 #define EN_SNK_ONLY BIT(1)
80 #define TYPEC_DISABLE_CMD BIT(0)
81
82 #define TYPEC_VCONN_CONTROL_REG 0x46
83 #define VCONN_EN_ORIENTATION BIT(2)
84 #define VCONN_EN_VALUE BIT(1)
85 #define VCONN_EN_SRC BIT(0)
86
87 #define TYPEC_CCOUT_CONTROL_REG 0x48
88 #define TYPEC_CCOUT_BUFFER_EN BIT(2)
89 #define TYPEC_CCOUT_VALUE BIT(1)
90 #define TYPEC_CCOUT_SRC BIT(0)
91
92 #define DEBUG_ACCESS_SRC_CFG_REG 0x4C
93 #define EN_UNORIENTED_DEBUG_ACCESS_SRC BIT(0)
94
95 #define TYPE_C_CRUDE_SENSOR_CFG_REG 0x4e
96 #define EN_SRC_CRUDE_SENSOR BIT(1)
97 #define EN_SNK_CRUDE_SENSOR BIT(0)
98
99 #define TYPEC_EXIT_STATE_CFG_REG 0x50
100 #define BYPASS_VSAFE0V_DURING_ROLE_SWAP BIT(3)
101 #define SEL_SRC_UPPER_REF BIT(2)
102 #define USE_TPD_FOR_EXITING_ATTACHSRC BIT(1)
103 #define EXIT_SNK_BASED_ON_CC BIT(0)
104
105 #define TYPEC_CURRSRC_CFG_REG 0x52
106 #define TYPEC_SRC_RP_SEL_330UA BIT(1)
107 #define TYPEC_SRC_RP_SEL_180UA BIT(0)
108 #define TYPEC_SRC_RP_SEL_80UA 0
109 #define TYPEC_SRC_RP_SEL_MASK GENMASK(1, 0)
110
111 #define TYPEC_INTERRUPT_EN_CFG_1_REG 0x5E
112 #define TYPEC_LEGACY_CABLE_INT_EN BIT(7)
113 #define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN BIT(6)
114 #define TYPEC_TRYSOURCE_DETECT_INT_EN BIT(5)
115 #define TYPEC_TRYSINK_DETECT_INT_EN BIT(4)
116 #define TYPEC_CCOUT_DETACH_INT_EN BIT(3)
117 #define TYPEC_CCOUT_ATTACH_INT_EN BIT(2)
118 #define TYPEC_VBUS_DEASSERT_INT_EN BIT(1)
119 #define TYPEC_VBUS_ASSERT_INT_EN BIT(0)
120
121 #define TYPEC_INTERRUPT_EN_CFG_2_REG 0x60
122 #define TYPEC_SRC_BATT_HPWR_INT_EN BIT(6)
123 #define MICRO_USB_STATE_CHANGE_INT_EN BIT(5)
124 #define TYPEC_STATE_MACHINE_CHANGE_INT_EN BIT(4)
125 #define TYPEC_DEBUG_ACCESS_DETECT_INT_EN BIT(3)
126 #define TYPEC_WATER_DETECTION_INT_EN BIT(2)
127 #define TYPEC_VBUS_ERROR_INT_EN BIT(1)
128 #define TYPEC_DEBOUNCE_DONE_INT_EN BIT(0)
129
130 #define TYPEC_DEBOUNCE_OPTION_REG 0x62
131 #define REDUCE_TCCDEBOUNCE_TO_2MS BIT(2)
132
133 #define TYPE_C_SBU_CFG_REG 0x6A
134 #define SEL_SBU1_ISRC_VAL 0x04
135 #define SEL_SBU2_ISRC_VAL 0x01
136
137 #define TYPEC_U_USB_CFG_REG 0x70
138 #define EN_MICRO_USB_FACTORY_MODE BIT(1)
139 #define EN_MICRO_USB_MODE BIT(0)
140
141 #define TYPEC_PMI632_U_USB_WATER_PROTECTION_CFG_REG 0x72
142
143 #define TYPEC_U_USB_WATER_PROTECTION_CFG_REG 0x73
144 #define EN_MICRO_USB_WATER_PROTECTION BIT(4)
145 #define MICRO_USB_DETECTION_ON_TIME_CFG_MASK GENMASK(3, 2)
146 #define MICRO_USB_DETECTION_PERIOD_CFG_MASK GENMASK(1, 0)
147
148 #define TYPEC_PMI632_MICRO_USB_MODE_REG 0x73
149 #define MICRO_USB_MODE_ONLY BIT(0)
150
151 /* Interrupt numbers */
152 #define PMIC_TYPEC_OR_RID_IRQ 0x0
153 #define PMIC_TYPEC_VPD_IRQ 0x1
154 #define PMIC_TYPEC_CC_STATE_IRQ 0x2
155 #define PMIC_TYPEC_VCONN_OC_IRQ 0x3
156 #define PMIC_TYPEC_VBUS_IRQ 0x4
157 #define PMIC_TYPEC_ATTACH_DETACH_IRQ 0x5
158 #define PMIC_TYPEC_LEGACY_CABLE_IRQ 0x6
159 #define PMIC_TYPEC_TRY_SNK_SRC_IRQ 0x7
160
161 struct pmic_typec_port_irq_data {
162 int virq;
163 int irq;
164 struct pmic_typec_port *pmic_typec_port;
165 };
166
167 struct pmic_typec_port {
168 struct device *dev;
169 struct tcpm_port *tcpm_port;
170 struct regmap *regmap;
171 u32 base;
172 unsigned int nr_irqs;
173 struct pmic_typec_port_irq_data *irq_data;
174
175 struct regulator *vdd_vbus;
176 bool vbus_enabled;
177 struct mutex vbus_lock; /* VBUS state serialization */
178
179 int cc;
180 bool debouncing_cc;
181 struct delayed_work cc_debounce_dwork;
182
183 spinlock_t lock; /* Register atomicity */
184 };
185
186 static const char * const typec_cc_status_name[] = {
187 [TYPEC_CC_OPEN] = "Open",
188 [TYPEC_CC_RA] = "Ra",
189 [TYPEC_CC_RD] = "Rd",
190 [TYPEC_CC_RP_DEF] = "Rp-def",
191 [TYPEC_CC_RP_1_5] = "Rp-1.5",
192 [TYPEC_CC_RP_3_0] = "Rp-3.0",
193 };
194
195 static const char *rp_unknown = "unknown";
196
cc_to_name(enum typec_cc_status cc)197 static const char *cc_to_name(enum typec_cc_status cc)
198 {
199 if (cc > TYPEC_CC_RP_3_0)
200 return rp_unknown;
201
202 return typec_cc_status_name[cc];
203 }
204
205 static const char * const rp_sel_name[] = {
206 [TYPEC_SRC_RP_SEL_80UA] = "Rp-def-80uA",
207 [TYPEC_SRC_RP_SEL_180UA] = "Rp-1.5-180uA",
208 [TYPEC_SRC_RP_SEL_330UA] = "Rp-3.0-330uA",
209 };
210
rp_sel_to_name(int rp_sel)211 static const char *rp_sel_to_name(int rp_sel)
212 {
213 if (rp_sel > TYPEC_SRC_RP_SEL_330UA)
214 return rp_unknown;
215
216 return rp_sel_name[rp_sel];
217 }
218
219 #define misc_to_cc(msic) !!(misc & CC_ORIENTATION) ? "cc1" : "cc2"
220 #define misc_to_vconn(msic) !!(misc & CC_ORIENTATION) ? "cc2" : "cc1"
221
qcom_pmic_typec_port_cc_debounce(struct work_struct * work)222 static void qcom_pmic_typec_port_cc_debounce(struct work_struct *work)
223 {
224 struct pmic_typec_port *pmic_typec_port =
225 container_of(work, struct pmic_typec_port, cc_debounce_dwork.work);
226 unsigned long flags;
227
228 spin_lock_irqsave(&pmic_typec_port->lock, flags);
229 pmic_typec_port->debouncing_cc = false;
230 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
231
232 dev_dbg(pmic_typec_port->dev, "Debounce cc complete\n");
233 }
234
pmic_typec_port_isr(int irq,void * dev_id)235 static irqreturn_t pmic_typec_port_isr(int irq, void *dev_id)
236 {
237 struct pmic_typec_port_irq_data *irq_data = dev_id;
238 struct pmic_typec_port *pmic_typec_port = irq_data->pmic_typec_port;
239 u32 misc_stat;
240 bool vbus_change = false;
241 bool cc_change = false;
242 unsigned long flags;
243 int ret;
244
245 spin_lock_irqsave(&pmic_typec_port->lock, flags);
246
247 ret = regmap_read(pmic_typec_port->regmap,
248 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
249 &misc_stat);
250 if (ret)
251 goto done;
252
253 switch (irq_data->virq) {
254 case PMIC_TYPEC_VBUS_IRQ:
255 vbus_change = true;
256 break;
257 case PMIC_TYPEC_CC_STATE_IRQ:
258 case PMIC_TYPEC_ATTACH_DETACH_IRQ:
259 if (!pmic_typec_port->debouncing_cc)
260 cc_change = true;
261 break;
262 }
263
264 done:
265 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
266
267 if (vbus_change)
268 tcpm_vbus_change(pmic_typec_port->tcpm_port);
269
270 if (cc_change)
271 tcpm_cc_change(pmic_typec_port->tcpm_port);
272
273 return IRQ_HANDLED;
274 }
275
qcom_pmic_typec_port_vbus_detect(struct pmic_typec_port * pmic_typec_port)276 static int qcom_pmic_typec_port_vbus_detect(struct pmic_typec_port *pmic_typec_port)
277 {
278 struct device *dev = pmic_typec_port->dev;
279 unsigned int misc;
280 int ret;
281
282 ret = regmap_read(pmic_typec_port->regmap,
283 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
284 &misc);
285 if (ret)
286 misc = 0;
287
288 dev_dbg(dev, "get_vbus: 0x%08x detect %d\n", misc, !!(misc & TYPEC_VBUS_DETECT));
289
290 return !!(misc & TYPEC_VBUS_DETECT);
291 }
292
qcom_pmic_typec_port_vbus_toggle(struct pmic_typec_port * pmic_typec_port,bool on)293 static int qcom_pmic_typec_port_vbus_toggle(struct pmic_typec_port *pmic_typec_port, bool on)
294 {
295 u32 sm_stat;
296 u32 val;
297 int ret;
298
299 if (on) {
300 ret = regulator_enable(pmic_typec_port->vdd_vbus);
301 if (ret)
302 return ret;
303
304 val = TYPEC_SM_VBUS_VSAFE5V;
305 } else {
306 ret = regulator_disable(pmic_typec_port->vdd_vbus);
307 if (ret)
308 return ret;
309
310 val = TYPEC_SM_VBUS_VSAFE0V;
311 }
312
313 /* Poll waiting for transition to required vSafe5V or vSafe0V */
314 ret = regmap_read_poll_timeout(pmic_typec_port->regmap,
315 pmic_typec_port->base + TYPEC_SM_STATUS_REG,
316 sm_stat, sm_stat & val,
317 100, 250000);
318 if (ret)
319 dev_warn(pmic_typec_port->dev, "vbus vsafe%dv fail\n", on ? 5 : 0);
320
321 return 0;
322 }
323
qcom_pmic_typec_port_get_vbus(struct tcpc_dev * tcpc)324 static int qcom_pmic_typec_port_get_vbus(struct tcpc_dev *tcpc)
325 {
326 struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc);
327 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
328 int ret;
329
330 mutex_lock(&pmic_typec_port->vbus_lock);
331 ret = pmic_typec_port->vbus_enabled || qcom_pmic_typec_port_vbus_detect(pmic_typec_port);
332 mutex_unlock(&pmic_typec_port->vbus_lock);
333
334 return ret;
335 }
336
qcom_pmic_typec_port_set_vbus(struct tcpc_dev * tcpc,bool on,bool sink)337 static int qcom_pmic_typec_port_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink)
338 {
339 struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc);
340 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
341 int ret = 0;
342
343 mutex_lock(&pmic_typec_port->vbus_lock);
344 if (pmic_typec_port->vbus_enabled == on)
345 goto done;
346
347 ret = qcom_pmic_typec_port_vbus_toggle(pmic_typec_port, on);
348 if (ret)
349 goto done;
350
351 pmic_typec_port->vbus_enabled = on;
352 tcpm_vbus_change(tcpm->tcpm_port);
353
354 done:
355 dev_dbg(tcpm->dev, "set_vbus set: %d result %d\n", on, ret);
356 mutex_unlock(&pmic_typec_port->vbus_lock);
357
358 return ret;
359 }
360
qcom_pmic_typec_port_get_cc(struct tcpc_dev * tcpc,enum typec_cc_status * cc1,enum typec_cc_status * cc2)361 static int qcom_pmic_typec_port_get_cc(struct tcpc_dev *tcpc,
362 enum typec_cc_status *cc1,
363 enum typec_cc_status *cc2)
364 {
365 struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc);
366 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
367 struct device *dev = pmic_typec_port->dev;
368 unsigned int misc, val;
369 bool attached;
370 int ret = 0;
371
372 ret = regmap_read(pmic_typec_port->regmap,
373 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
374 if (ret)
375 goto done;
376
377 attached = !!(misc & CC_ATTACHED);
378
379 if (pmic_typec_port->debouncing_cc) {
380 ret = -EBUSY;
381 goto done;
382 }
383
384 *cc1 = TYPEC_CC_OPEN;
385 *cc2 = TYPEC_CC_OPEN;
386
387 if (!attached)
388 goto done;
389
390 if (misc & SNK_SRC_MODE) {
391 ret = regmap_read(pmic_typec_port->regmap,
392 pmic_typec_port->base + TYPEC_SRC_STATUS_REG,
393 &val);
394 if (ret)
395 goto done;
396 switch (val & DETECTED_SRC_TYPE_MASK) {
397 case AUDIO_ACCESS_RA_RA:
398 val = TYPEC_CC_RA;
399 *cc1 = TYPEC_CC_RA;
400 *cc2 = TYPEC_CC_RA;
401 break;
402 case SRC_RD_OPEN:
403 val = TYPEC_CC_RD;
404 break;
405 case SRC_RD_RA_VCONN:
406 val = TYPEC_CC_RD;
407 *cc1 = TYPEC_CC_RA;
408 *cc2 = TYPEC_CC_RA;
409 break;
410 default:
411 dev_warn(dev, "unexpected src status %.2x\n", val);
412 val = TYPEC_CC_RD;
413 break;
414 }
415 } else {
416 ret = regmap_read(pmic_typec_port->regmap,
417 pmic_typec_port->base + TYPEC_SNK_STATUS_REG,
418 &val);
419 if (ret)
420 goto done;
421 switch (val & DETECTED_SNK_TYPE_MASK) {
422 case SNK_RP_STD:
423 val = TYPEC_CC_RP_DEF;
424 break;
425 case SNK_RP_1P5:
426 val = TYPEC_CC_RP_1_5;
427 break;
428 case SNK_RP_3P0:
429 val = TYPEC_CC_RP_3_0;
430 break;
431 default:
432 dev_warn(dev, "unexpected snk status %.2x\n", val);
433 val = TYPEC_CC_RP_DEF;
434 break;
435 }
436 }
437
438 if (misc & CC_ORIENTATION)
439 *cc2 = val;
440 else
441 *cc1 = val;
442
443 done:
444 dev_dbg(dev, "get_cc: misc 0x%08x cc1 0x%08x %s cc2 0x%08x %s attached %d cc=%s\n",
445 misc, *cc1, cc_to_name(*cc1), *cc2, cc_to_name(*cc2), attached,
446 misc_to_cc(misc));
447
448 return ret;
449 }
450
qcom_pmic_set_cc_debounce(struct pmic_typec_port * pmic_typec_port)451 static void qcom_pmic_set_cc_debounce(struct pmic_typec_port *pmic_typec_port)
452 {
453 pmic_typec_port->debouncing_cc = true;
454 schedule_delayed_work(&pmic_typec_port->cc_debounce_dwork,
455 msecs_to_jiffies(2));
456 }
457
qcom_pmic_typec_port_set_cc(struct tcpc_dev * tcpc,enum typec_cc_status cc)458 static int qcom_pmic_typec_port_set_cc(struct tcpc_dev *tcpc,
459 enum typec_cc_status cc)
460 {
461 struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc);
462 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
463 struct device *dev = pmic_typec_port->dev;
464 unsigned int mode, currsrc;
465 unsigned int misc;
466 unsigned long flags;
467 int ret;
468
469 spin_lock_irqsave(&pmic_typec_port->lock, flags);
470
471 ret = regmap_read(pmic_typec_port->regmap,
472 pmic_typec_port->base + TYPEC_MISC_STATUS_REG,
473 &misc);
474 if (ret)
475 goto done;
476
477 mode = EN_SRC_ONLY;
478
479 switch (cc) {
480 case TYPEC_CC_OPEN:
481 currsrc = TYPEC_SRC_RP_SEL_80UA;
482 break;
483 case TYPEC_CC_RP_DEF:
484 currsrc = TYPEC_SRC_RP_SEL_80UA;
485 break;
486 case TYPEC_CC_RP_1_5:
487 currsrc = TYPEC_SRC_RP_SEL_180UA;
488 break;
489 case TYPEC_CC_RP_3_0:
490 currsrc = TYPEC_SRC_RP_SEL_330UA;
491 break;
492 case TYPEC_CC_RD:
493 currsrc = TYPEC_SRC_RP_SEL_80UA;
494 mode = EN_SNK_ONLY;
495 break;
496 default:
497 dev_warn(dev, "unexpected set_cc %d\n", cc);
498 ret = -EINVAL;
499 goto done;
500 }
501
502 if (mode == EN_SRC_ONLY) {
503 ret = regmap_write(pmic_typec_port->regmap,
504 pmic_typec_port->base + TYPEC_CURRSRC_CFG_REG,
505 currsrc);
506 if (ret)
507 goto done;
508 }
509
510 pmic_typec_port->cc = cc;
511 qcom_pmic_set_cc_debounce(pmic_typec_port);
512 ret = 0;
513
514 done:
515 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
516
517 dev_dbg(dev, "set_cc: currsrc=%x %s mode %s debounce %d attached %d cc=%s\n",
518 currsrc, rp_sel_to_name(currsrc),
519 mode == EN_SRC_ONLY ? "EN_SRC_ONLY" : "EN_SNK_ONLY",
520 pmic_typec_port->debouncing_cc, !!(misc & CC_ATTACHED),
521 misc_to_cc(misc));
522
523 return ret;
524 }
525
qcom_pmic_typec_port_set_polarity(struct tcpc_dev * tcpc,enum typec_cc_polarity pol)526 static int qcom_pmic_typec_port_set_polarity(struct tcpc_dev *tcpc,
527 enum typec_cc_polarity pol)
528 {
529 /* Polarity is set separately by phy-qcom-qmp.c */
530 return 0;
531 }
532
qcom_pmic_typec_port_set_vconn(struct tcpc_dev * tcpc,bool on)533 static int qcom_pmic_typec_port_set_vconn(struct tcpc_dev *tcpc, bool on)
534 {
535 struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc);
536 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
537 struct device *dev = pmic_typec_port->dev;
538 unsigned int orientation, misc, mask, value;
539 unsigned long flags;
540 int ret;
541
542 spin_lock_irqsave(&pmic_typec_port->lock, flags);
543
544 ret = regmap_read(pmic_typec_port->regmap,
545 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
546 if (ret)
547 goto done;
548
549 /* Set VCONN on the inversion of the active CC channel */
550 orientation = (misc & CC_ORIENTATION) ? 0 : VCONN_EN_ORIENTATION;
551 if (on) {
552 mask = VCONN_EN_ORIENTATION | VCONN_EN_VALUE;
553 value = orientation | VCONN_EN_VALUE | VCONN_EN_SRC;
554 } else {
555 mask = VCONN_EN_VALUE;
556 value = 0;
557 }
558
559 ret = regmap_update_bits(pmic_typec_port->regmap,
560 pmic_typec_port->base + TYPEC_VCONN_CONTROL_REG,
561 mask, value);
562 done:
563 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
564
565 dev_dbg(dev, "set_vconn: orientation %d control 0x%08x state %s cc %s vconn %s\n",
566 orientation, value, str_on_off(on), misc_to_vconn(misc),
567 misc_to_cc(misc));
568
569 return ret;
570 }
571
qcom_pmic_typec_port_start_toggling(struct tcpc_dev * tcpc,enum typec_port_type port_type,enum typec_cc_status cc)572 static int qcom_pmic_typec_port_start_toggling(struct tcpc_dev *tcpc,
573 enum typec_port_type port_type,
574 enum typec_cc_status cc)
575 {
576 struct pmic_typec *tcpm = tcpc_to_tcpm(tcpc);
577 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
578 struct device *dev = pmic_typec_port->dev;
579 unsigned int misc;
580 u8 mode = 0;
581 unsigned long flags;
582 int ret;
583
584 switch (port_type) {
585 case TYPEC_PORT_SRC:
586 mode = EN_SRC_ONLY;
587 break;
588 case TYPEC_PORT_SNK:
589 mode = EN_SNK_ONLY;
590 break;
591 case TYPEC_PORT_DRP:
592 mode = EN_TRY_SNK;
593 break;
594 }
595
596 spin_lock_irqsave(&pmic_typec_port->lock, flags);
597
598 ret = regmap_read(pmic_typec_port->regmap,
599 pmic_typec_port->base + TYPEC_MISC_STATUS_REG, &misc);
600 if (ret)
601 goto done;
602
603 dev_dbg(dev, "start_toggling: misc 0x%08x attached %d port_type %d current cc %d new %d\n",
604 misc, !!(misc & CC_ATTACHED), port_type, pmic_typec_port->cc, cc);
605
606 qcom_pmic_set_cc_debounce(pmic_typec_port);
607
608 /* force it to toggle at least once */
609 ret = regmap_write(pmic_typec_port->regmap,
610 pmic_typec_port->base + TYPEC_MODE_CFG_REG,
611 TYPEC_DISABLE_CMD);
612 if (ret)
613 goto done;
614
615 ret = regmap_write(pmic_typec_port->regmap,
616 pmic_typec_port->base + TYPEC_MODE_CFG_REG,
617 mode);
618 done:
619 spin_unlock_irqrestore(&pmic_typec_port->lock, flags);
620
621 return ret;
622 }
623
624 #define TYPEC_INTR_EN_CFG_1_MASK \
625 (TYPEC_LEGACY_CABLE_INT_EN | \
626 TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN | \
627 TYPEC_TRYSOURCE_DETECT_INT_EN | \
628 TYPEC_TRYSINK_DETECT_INT_EN | \
629 TYPEC_CCOUT_DETACH_INT_EN | \
630 TYPEC_CCOUT_ATTACH_INT_EN | \
631 TYPEC_VBUS_DEASSERT_INT_EN | \
632 TYPEC_VBUS_ASSERT_INT_EN)
633
634 #define TYPEC_INTR_EN_CFG_2_MASK \
635 (TYPEC_STATE_MACHINE_CHANGE_INT_EN | TYPEC_VBUS_ERROR_INT_EN | \
636 TYPEC_DEBOUNCE_DONE_INT_EN)
637
qcom_pmic_typec_port_start(struct pmic_typec * tcpm,struct tcpm_port * tcpm_port)638 static int qcom_pmic_typec_port_start(struct pmic_typec *tcpm,
639 struct tcpm_port *tcpm_port)
640 {
641 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
642 int i;
643 int mask;
644 int ret;
645
646 /* Configure interrupt sources */
647 ret = regmap_write(pmic_typec_port->regmap,
648 pmic_typec_port->base + TYPEC_INTERRUPT_EN_CFG_1_REG,
649 TYPEC_INTR_EN_CFG_1_MASK);
650 if (ret)
651 goto done;
652
653 ret = regmap_write(pmic_typec_port->regmap,
654 pmic_typec_port->base + TYPEC_INTERRUPT_EN_CFG_2_REG,
655 TYPEC_INTR_EN_CFG_2_MASK);
656 if (ret)
657 goto done;
658
659 /* start in TRY_SNK mode */
660 ret = regmap_write(pmic_typec_port->regmap,
661 pmic_typec_port->base + TYPEC_MODE_CFG_REG, EN_TRY_SNK);
662 if (ret)
663 goto done;
664
665 /* Configure VCONN for software control */
666 ret = regmap_update_bits(pmic_typec_port->regmap,
667 pmic_typec_port->base + TYPEC_VCONN_CONTROL_REG,
668 VCONN_EN_SRC | VCONN_EN_VALUE, VCONN_EN_SRC);
669 if (ret)
670 goto done;
671
672 /* Set CC threshold to 1.6 Volts | tPDdebounce = 10-20ms */
673 mask = SEL_SRC_UPPER_REF | USE_TPD_FOR_EXITING_ATTACHSRC;
674 ret = regmap_update_bits(pmic_typec_port->regmap,
675 pmic_typec_port->base + TYPEC_EXIT_STATE_CFG_REG,
676 mask, mask);
677 if (ret)
678 goto done;
679
680 pmic_typec_port->tcpm_port = tcpm_port;
681
682 for (i = 0; i < pmic_typec_port->nr_irqs; i++)
683 enable_irq(pmic_typec_port->irq_data[i].irq);
684
685 done:
686 return ret;
687 }
688
qcom_pmic_typec_port_stop(struct pmic_typec * tcpm)689 static void qcom_pmic_typec_port_stop(struct pmic_typec *tcpm)
690 {
691 struct pmic_typec_port *pmic_typec_port = tcpm->pmic_typec_port;
692 int i;
693
694 for (i = 0; i < pmic_typec_port->nr_irqs; i++)
695 disable_irq(pmic_typec_port->irq_data[i].irq);
696 }
697
qcom_pmic_typec_port_probe(struct platform_device * pdev,struct pmic_typec * tcpm,const struct pmic_typec_port_resources * res,struct regmap * regmap,u32 base)698 int qcom_pmic_typec_port_probe(struct platform_device *pdev,
699 struct pmic_typec *tcpm,
700 const struct pmic_typec_port_resources *res,
701 struct regmap *regmap,
702 u32 base)
703 {
704 struct device *dev = &pdev->dev;
705 struct pmic_typec_port_irq_data *irq_data;
706 struct pmic_typec_port *pmic_typec_port;
707 int i, ret, irq;
708
709 pmic_typec_port = devm_kzalloc(dev, sizeof(*pmic_typec_port), GFP_KERNEL);
710 if (!pmic_typec_port)
711 return -ENOMEM;
712
713 if (!res->nr_irqs || res->nr_irqs > PMIC_TYPEC_MAX_IRQS)
714 return -EINVAL;
715
716 irq_data = devm_kzalloc(dev, sizeof(*irq_data) * res->nr_irqs,
717 GFP_KERNEL);
718 if (!irq_data)
719 return -ENOMEM;
720
721 mutex_init(&pmic_typec_port->vbus_lock);
722
723 pmic_typec_port->vdd_vbus = devm_regulator_get(dev, "vdd-vbus");
724 if (IS_ERR(pmic_typec_port->vdd_vbus))
725 return PTR_ERR(pmic_typec_port->vdd_vbus);
726
727 pmic_typec_port->dev = dev;
728 pmic_typec_port->base = base;
729 pmic_typec_port->regmap = regmap;
730 pmic_typec_port->nr_irqs = res->nr_irqs;
731 pmic_typec_port->irq_data = irq_data;
732 spin_lock_init(&pmic_typec_port->lock);
733 INIT_DELAYED_WORK(&pmic_typec_port->cc_debounce_dwork,
734 qcom_pmic_typec_port_cc_debounce);
735
736 irq = platform_get_irq(pdev, 0);
737 if (irq < 0)
738 return irq;
739
740 for (i = 0; i < res->nr_irqs; i++, irq_data++) {
741 irq = platform_get_irq_byname(pdev,
742 res->irq_params[i].irq_name);
743 if (irq < 0)
744 return irq;
745
746 irq_data->pmic_typec_port = pmic_typec_port;
747 irq_data->irq = irq;
748 irq_data->virq = res->irq_params[i].virq;
749 ret = devm_request_threaded_irq(dev, irq, NULL, pmic_typec_port_isr,
750 IRQF_ONESHOT | IRQF_NO_AUTOEN,
751 res->irq_params[i].irq_name,
752 irq_data);
753 if (ret)
754 return ret;
755 }
756
757 tcpm->pmic_typec_port = pmic_typec_port;
758
759 tcpm->tcpc.get_vbus = qcom_pmic_typec_port_get_vbus;
760 tcpm->tcpc.set_vbus = qcom_pmic_typec_port_set_vbus;
761 tcpm->tcpc.set_cc = qcom_pmic_typec_port_set_cc;
762 tcpm->tcpc.get_cc = qcom_pmic_typec_port_get_cc;
763 tcpm->tcpc.set_polarity = qcom_pmic_typec_port_set_polarity;
764 tcpm->tcpc.set_vconn = qcom_pmic_typec_port_set_vconn;
765 tcpm->tcpc.start_toggling = qcom_pmic_typec_port_start_toggling;
766
767 tcpm->port_start = qcom_pmic_typec_port_start;
768 tcpm->port_stop = qcom_pmic_typec_port_stop;
769
770 return 0;
771 }
772
773 const struct pmic_typec_port_resources pm8150b_port_res = {
774 .irq_params = {
775 {
776 .irq_name = "vpd-detect",
777 .virq = PMIC_TYPEC_VPD_IRQ,
778 },
779
780 {
781 .irq_name = "cc-state-change",
782 .virq = PMIC_TYPEC_CC_STATE_IRQ,
783 },
784 {
785 .irq_name = "vconn-oc",
786 .virq = PMIC_TYPEC_VCONN_OC_IRQ,
787 },
788
789 {
790 .irq_name = "vbus-change",
791 .virq = PMIC_TYPEC_VBUS_IRQ,
792 },
793
794 {
795 .irq_name = "attach-detach",
796 .virq = PMIC_TYPEC_ATTACH_DETACH_IRQ,
797 },
798 {
799 .irq_name = "legacy-cable-detect",
800 .virq = PMIC_TYPEC_LEGACY_CABLE_IRQ,
801 },
802
803 {
804 .irq_name = "try-snk-src-detect",
805 .virq = PMIC_TYPEC_TRY_SNK_SRC_IRQ,
806 },
807 },
808 .nr_irqs = 7,
809 };
810