1 /* 2 * ARM VFP floating-point operations 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "internals.h" 23 #include "cpu-features.h" 24 #include "fpu/softfloat.h" 25 #include "qemu/log.h" 26 27 #define HELPER_H "tcg/helper.h" 28 #include "exec/helper-proto.h.inc" 29 30 /* 31 * Set the float_status behaviour to match the Arm defaults: 32 * * tininess-before-rounding 33 * * 2-input NaN propagation prefers SNaN over QNaN, and then 34 * operand A over operand B (see FPProcessNaNs() pseudocode) 35 * * 3-input NaN propagation prefers SNaN over QNaN, and then 36 * operand C over A over B (see FPProcessNaNs3() pseudocode, 37 * but note that for QEMU muladd is a * b + c, whereas for 38 * the pseudocode function the arguments are in the order c, a, b. 39 * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, 40 * and the input NaN if it is signalling 41 * * Default NaN has sign bit clear, msb frac bit set 42 */ 43 void arm_set_default_fp_behaviours(float_status *s) 44 { 45 set_float_detect_tininess(float_tininess_before_rounding, s); 46 set_float_ftz_detection(float_ftz_before_rounding, s); 47 set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); 48 set_float_3nan_prop_rule(float_3nan_prop_s_cab, s); 49 set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); 50 set_float_default_nan_pattern(0b01000000, s); 51 } 52 53 /* 54 * Set the float_status behaviour to match the FEAT_AFP 55 * FPCR.AH=1 requirements: 56 * * tininess-after-rounding 57 * * 2-input NaN propagation prefers the first NaN 58 * * 3-input NaN propagation prefers a over b over c 59 * * 0 * Inf + NaN always returns the input NaN and doesn't 60 * set Invalid for a QNaN 61 * * default NaN has sign bit set, msb frac bit set 62 */ 63 void arm_set_ah_fp_behaviours(float_status *s) 64 { 65 set_float_detect_tininess(float_tininess_after_rounding, s); 66 set_float_ftz_detection(float_ftz_after_rounding, s); 67 set_float_2nan_prop_rule(float_2nan_prop_ab, s); 68 set_float_3nan_prop_rule(float_3nan_prop_abc, s); 69 set_float_infzeronan_rule(float_infzeronan_dnan_never | 70 float_infzeronan_suppress_invalid, s); 71 set_float_default_nan_pattern(0b11000000, s); 72 } 73 74 /* Convert host exception flags to vfp form. */ 75 static inline uint32_t vfp_exceptbits_from_host(int host_bits, bool ah) 76 { 77 uint32_t target_bits = 0; 78 79 if (host_bits & float_flag_invalid) { 80 target_bits |= FPSR_IOC; 81 } 82 if (host_bits & float_flag_divbyzero) { 83 target_bits |= FPSR_DZC; 84 } 85 if (host_bits & float_flag_overflow) { 86 target_bits |= FPSR_OFC; 87 } 88 if (host_bits & (float_flag_underflow | float_flag_output_denormal_flushed)) { 89 target_bits |= FPSR_UFC; 90 } 91 if (host_bits & float_flag_inexact) { 92 target_bits |= FPSR_IXC; 93 } 94 if (host_bits & float_flag_input_denormal_flushed) { 95 target_bits |= FPSR_IDC; 96 } 97 /* 98 * With FPCR.AH, IDC is set when an input denormal is used, 99 * and flushing an output denormal to zero sets both IXC and UFC. 100 */ 101 if (ah && (host_bits & float_flag_input_denormal_used)) { 102 target_bits |= FPSR_IDC; 103 } 104 if (ah && (host_bits & float_flag_output_denormal_flushed)) { 105 target_bits |= FPSR_IXC; 106 } 107 return target_bits; 108 } 109 110 uint32_t vfp_get_fpsr_from_host(CPUARMState *env) 111 { 112 uint32_t a32_flags = 0, a64_flags = 0; 113 114 a32_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_A32]); 115 a32_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_STD]); 116 /* FZ16 does not generate an input denormal exception. */ 117 a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A32_F16]) 118 & ~float_flag_input_denormal_flushed); 119 a32_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_STD_F16]) 120 & ~float_flag_input_denormal_flushed); 121 122 a64_flags |= get_float_exception_flags(&env->vfp.fp_status[FPST_A64]); 123 a64_flags |= (get_float_exception_flags(&env->vfp.fp_status[FPST_A64_F16]) 124 & ~(float_flag_input_denormal_flushed | float_flag_input_denormal_used)); 125 /* 126 * We do not merge in flags from FPST_{AH,ZA} or FPST_{AH,ZA}_F16, because 127 * they are used for insns that must not set the cumulative exception bits. 128 */ 129 130 /* 131 * Flushing an input denormal *only* because FPCR.FIZ == 1 does 132 * not set FPSR.IDC; if FPCR.FZ is also set then this takes 133 * precedence and IDC is set (see the FPUnpackBase pseudocode). 134 * So squash it unless (FPCR.AH == 0 && FPCR.FZ == 1). 135 * We only do this for the a64 flags because FIZ has no effect 136 * on AArch32 even if it is set. 137 */ 138 if ((env->vfp.fpcr & (FPCR_FZ | FPCR_AH)) != FPCR_FZ) { 139 a64_flags &= ~float_flag_input_denormal_flushed; 140 } 141 return vfp_exceptbits_from_host(a64_flags, env->vfp.fpcr & FPCR_AH) | 142 vfp_exceptbits_from_host(a32_flags, false); 143 } 144 145 void vfp_clear_float_status_exc_flags(CPUARMState *env) 146 { 147 /* 148 * Clear out all the exception-flag information in the float_status 149 * values. The caller should have arranged for env->vfp.fpsr to 150 * be the architecturally up-to-date exception flag information first. 151 */ 152 set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32]); 153 set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64]); 154 set_float_exception_flags(0, &env->vfp.fp_status[FPST_A32_F16]); 155 set_float_exception_flags(0, &env->vfp.fp_status[FPST_A64_F16]); 156 set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD]); 157 set_float_exception_flags(0, &env->vfp.fp_status[FPST_STD_F16]); 158 set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH]); 159 set_float_exception_flags(0, &env->vfp.fp_status[FPST_AH_F16]); 160 } 161 162 static void vfp_sync_and_clear_float_status_exc_flags(CPUARMState *env) 163 { 164 /* 165 * Synchronize any pending exception-flag information in the 166 * float_status values into env->vfp.fpsr, and then clear out 167 * the float_status data. 168 */ 169 env->vfp.fpsr |= vfp_get_fpsr_from_host(env); 170 vfp_clear_float_status_exc_flags(env); 171 } 172 173 void vfp_set_fpcr_to_host(CPUARMState *env, uint32_t val, uint32_t mask) 174 { 175 uint64_t changed = env->vfp.fpcr; 176 177 changed ^= val; 178 changed &= mask; 179 if (changed & (3 << 22)) { 180 int i = (val >> 22) & 3; 181 switch (i) { 182 case FPROUNDING_TIEEVEN: 183 i = float_round_nearest_even; 184 break; 185 case FPROUNDING_POSINF: 186 i = float_round_up; 187 break; 188 case FPROUNDING_NEGINF: 189 i = float_round_down; 190 break; 191 case FPROUNDING_ZERO: 192 i = float_round_to_zero; 193 break; 194 } 195 set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32]); 196 set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64]); 197 set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A32_F16]); 198 set_float_rounding_mode(i, &env->vfp.fp_status[FPST_A64_F16]); 199 set_float_rounding_mode(i, &env->vfp.fp_status[FPST_ZA]); 200 set_float_rounding_mode(i, &env->vfp.fp_status[FPST_ZA_F16]); 201 } 202 if (changed & FPCR_FZ16) { 203 bool ftz_enabled = val & FPCR_FZ16; 204 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32_F16]); 205 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); 206 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); 207 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); 208 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_ZA_F16]); 209 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32_F16]); 210 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64_F16]); 211 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_STD_F16]); 212 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_AH_F16]); 213 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_ZA_F16]); 214 } 215 if (changed & FPCR_FZ) { 216 bool ftz_enabled = val & FPCR_FZ; 217 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32]); 218 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A64]); 219 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_ZA]); 220 /* FIZ is A64 only so FZ always makes A32 code flush inputs to zero */ 221 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status[FPST_A32]); 222 } 223 if (changed & (FPCR_FZ | FPCR_AH | FPCR_FIZ)) { 224 /* 225 * A64: Flush denormalized inputs to zero if FPCR.FIZ = 1, or 226 * both FPCR.AH = 0 and FPCR.FZ = 1. 227 */ 228 bool fitz_enabled = (val & FPCR_FIZ) || 229 (val & (FPCR_FZ | FPCR_AH)) == FPCR_FZ; 230 set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_A64]); 231 set_flush_inputs_to_zero(fitz_enabled, &env->vfp.fp_status[FPST_ZA]); 232 } 233 if (changed & FPCR_DN) { 234 bool dnan_enabled = val & FPCR_DN; 235 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32]); 236 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64]); 237 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A32_F16]); 238 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_A64_F16]); 239 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH]); 240 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status[FPST_AH_F16]); 241 } 242 if (changed & FPCR_AH) { 243 bool ah_enabled = val & FPCR_AH; 244 245 if (ah_enabled) { 246 /* Change behaviours for A64 FP operations */ 247 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 248 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 249 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); 250 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]); 251 } else { 252 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]); 253 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]); 254 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA]); 255 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_ZA_F16]); 256 } 257 } 258 /* 259 * If any bits changed that we look at in vfp_get_fpsr_from_host(), 260 * we must sync the float_status flags into vfp.fpsr now (under the 261 * old regime) before we update vfp.fpcr. 262 */ 263 if (changed & (FPCR_FZ | FPCR_AH | FPCR_FIZ)) { 264 vfp_sync_and_clear_float_status_exc_flags(env); 265 } 266 } 267 268 /* 269 * VFP support. We follow the convention used for VFP instructions: 270 * Single precision routines have a "s" suffix, double precision a 271 * "d" suffix. 272 */ 273 274 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) 275 276 #define VFP_BINOP(name) \ 277 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, float_status *fpst) \ 278 { \ 279 return float16_ ## name(a, b, fpst); \ 280 } \ 281 float32 VFP_HELPER(name, s)(float32 a, float32 b, float_status *fpst) \ 282 { \ 283 return float32_ ## name(a, b, fpst); \ 284 } \ 285 float64 VFP_HELPER(name, d)(float64 a, float64 b, float_status *fpst) \ 286 { \ 287 return float64_ ## name(a, b, fpst); \ 288 } 289 VFP_BINOP(add) 290 VFP_BINOP(sub) 291 VFP_BINOP(mul) 292 VFP_BINOP(div) 293 VFP_BINOP(min) 294 VFP_BINOP(max) 295 VFP_BINOP(minnum) 296 VFP_BINOP(maxnum) 297 #undef VFP_BINOP 298 299 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, float_status *fpst) 300 { 301 return float16_sqrt(a, fpst); 302 } 303 304 float32 VFP_HELPER(sqrt, s)(float32 a, float_status *fpst) 305 { 306 return float32_sqrt(a, fpst); 307 } 308 309 float64 VFP_HELPER(sqrt, d)(float64 a, float_status *fpst) 310 { 311 return float64_sqrt(a, fpst); 312 } 313 314 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp) 315 { 316 uint32_t flags; 317 switch (cmp) { 318 case float_relation_equal: 319 flags = 0x6; 320 break; 321 case float_relation_less: 322 flags = 0x8; 323 break; 324 case float_relation_greater: 325 flags = 0x2; 326 break; 327 case float_relation_unordered: 328 flags = 0x3; 329 break; 330 default: 331 g_assert_not_reached(); 332 } 333 env->vfp.fpsr = deposit64(env->vfp.fpsr, 28, 4, flags); /* NZCV */ 334 } 335 336 /* XXX: check quiet/signaling case */ 337 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \ 338 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 339 { \ 340 softfloat_to_vfp_compare(env, \ 341 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.fp_status[FPST])); \ 342 } \ 343 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \ 344 { \ 345 softfloat_to_vfp_compare(env, \ 346 FLOATTYPE ## _compare(a, b, &env->vfp.fp_status[FPST])); \ 347 } 348 DO_VFP_cmp(h, float16, dh_ctype_f16, FPST_A32_F16) 349 DO_VFP_cmp(s, float32, float32, FPST_A32) 350 DO_VFP_cmp(d, float64, float64, FPST_A32) 351 #undef DO_VFP_cmp 352 353 /* Integer to float and float to integer conversions */ 354 355 #define CONV_ITOF(name, ftype, fsz, sign) \ 356 ftype HELPER(name)(uint32_t x, float_status *fpst) \ 357 { \ 358 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \ 359 } 360 361 #define CONV_FTOI(name, ftype, fsz, sign, round) \ 362 sign##int32_t HELPER(name)(ftype x, float_status *fpst) \ 363 { \ 364 if (float##fsz##_is_any_nan(x)) { \ 365 float_raise(float_flag_invalid, fpst); \ 366 return 0; \ 367 } \ 368 return float##fsz##_to_##sign##int32##round(x, fpst); \ 369 } 370 371 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \ 372 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \ 373 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \ 374 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero) 375 376 FLOAT_CONVS(si, h, uint32_t, 16, ) 377 FLOAT_CONVS(si, s, float32, 32, ) 378 FLOAT_CONVS(si, d, float64, 64, ) 379 FLOAT_CONVS(ui, h, uint32_t, 16, u) 380 FLOAT_CONVS(ui, s, float32, 32, u) 381 FLOAT_CONVS(ui, d, float64, 64, u) 382 383 #undef CONV_ITOF 384 #undef CONV_FTOI 385 #undef FLOAT_CONVS 386 387 /* floating point conversion */ 388 float64 VFP_HELPER(fcvtd, s)(float32 x, float_status *status) 389 { 390 return float32_to_float64(x, status); 391 } 392 393 float32 VFP_HELPER(fcvts, d)(float64 x, float_status *status) 394 { 395 return float64_to_float32(x, status); 396 } 397 398 uint32_t HELPER(bfcvt)(float32 x, float_status *status) 399 { 400 return float32_to_bfloat16(x, status); 401 } 402 403 uint32_t HELPER(bfcvt_pair)(uint64_t pair, float_status *status) 404 { 405 bfloat16 lo = float32_to_bfloat16(extract64(pair, 0, 32), status); 406 bfloat16 hi = float32_to_bfloat16(extract64(pair, 32, 32), status); 407 return deposit32(lo, 16, 16, hi); 408 } 409 410 /* 411 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float 412 * must always round-to-nearest; the AArch64 ones honour the FPSCR 413 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to 414 * round-to-nearest so either helper will work.) AArch32 float-to-fix 415 * must round-to-zero. 416 */ 417 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 418 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \ 419 float_status *fpst) \ 420 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpst); } 421 422 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 423 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \ 424 uint32_t shift, \ 425 float_status *fpst) \ 426 { \ 427 ftype ret; \ 428 FloatRoundMode oldmode = fpst->float_rounding_mode; \ 429 fpst->float_rounding_mode = float_round_nearest_even; \ 430 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpst); \ 431 fpst->float_rounding_mode = oldmode; \ 432 return ret; \ 433 } 434 435 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \ 436 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \ 437 float_status *fpst) \ 438 { \ 439 if (unlikely(float##fsz##_is_any_nan(x))) { \ 440 float_raise(float_flag_invalid, fpst); \ 441 return 0; \ 442 } \ 443 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \ 444 } 445 446 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \ 447 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 448 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \ 449 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 450 float_round_to_zero, _round_to_zero) \ 451 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 452 get_float_rounding_mode(fpst), ) 453 454 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \ 455 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \ 456 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \ 457 get_float_rounding_mode(fpst), ) 458 459 VFP_CONV_FIX(sh, d, 64, float64, 64, int16) 460 VFP_CONV_FIX(sl, d, 64, float64, 64, int32) 461 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64) 462 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16) 463 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32) 464 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64) 465 VFP_CONV_FIX(sh, s, 32, float32, 32, int16) 466 VFP_CONV_FIX(sl, s, 32, float32, 32, int32) 467 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64) 468 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16) 469 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32) 470 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64) 471 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16) 472 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32) 473 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64) 474 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16) 475 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32) 476 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64) 477 VFP_CONV_FLOAT_FIX_ROUND(sq, d, 64, float64, 64, int64, 478 float_round_to_zero, _round_to_zero) 479 VFP_CONV_FLOAT_FIX_ROUND(uq, d, 64, float64, 64, uint64, 480 float_round_to_zero, _round_to_zero) 481 482 #undef VFP_CONV_FIX 483 #undef VFP_CONV_FIX_FLOAT 484 #undef VFP_CONV_FLOAT_FIX_ROUND 485 #undef VFP_CONV_FIX_A64 486 487 /* Set the current fp rounding mode and return the old one. 488 * The argument is a softfloat float_round_ value. 489 */ 490 uint32_t HELPER(set_rmode)(uint32_t rmode, float_status *fp_status) 491 { 492 uint32_t prev_rmode = get_float_rounding_mode(fp_status); 493 set_float_rounding_mode(rmode, fp_status); 494 495 return prev_rmode; 496 } 497 498 /* Half precision conversions. */ 499 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, float_status *fpst, 500 uint32_t ahp_mode) 501 { 502 /* Squash FZ16 to 0 for the duration of conversion. In this case, 503 * it would affect flushing input denormals. 504 */ 505 bool save = get_flush_inputs_to_zero(fpst); 506 set_flush_inputs_to_zero(false, fpst); 507 float32 r = float16_to_float32(a, !ahp_mode, fpst); 508 set_flush_inputs_to_zero(save, fpst); 509 return r; 510 } 511 512 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, float_status *fpst, 513 uint32_t ahp_mode) 514 { 515 /* Squash FZ16 to 0 for the duration of conversion. In this case, 516 * it would affect flushing output denormals. 517 */ 518 bool save = get_flush_to_zero(fpst); 519 set_flush_to_zero(false, fpst); 520 float16 r = float32_to_float16(a, !ahp_mode, fpst); 521 set_flush_to_zero(save, fpst); 522 return r; 523 } 524 525 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, float_status *fpst, 526 uint32_t ahp_mode) 527 { 528 /* Squash FZ16 to 0 for the duration of conversion. In this case, 529 * it would affect flushing input denormals. 530 */ 531 bool save = get_flush_inputs_to_zero(fpst); 532 set_flush_inputs_to_zero(false, fpst); 533 float64 r = float16_to_float64(a, !ahp_mode, fpst); 534 set_flush_inputs_to_zero(save, fpst); 535 return r; 536 } 537 538 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, float_status *fpst, 539 uint32_t ahp_mode) 540 { 541 /* Squash FZ16 to 0 for the duration of conversion. In this case, 542 * it would affect flushing output denormals. 543 */ 544 bool save = get_flush_to_zero(fpst); 545 set_flush_to_zero(false, fpst); 546 float16 r = float64_to_float16(a, !ahp_mode, fpst); 547 set_flush_to_zero(save, fpst); 548 return r; 549 } 550 551 /* NEON helpers. */ 552 553 /* Constants 256 and 512 are used in some helpers; we avoid relying on 554 * int->float conversions at run-time. */ 555 #define float64_256 make_float64(0x4070000000000000LL) 556 #define float64_512 make_float64(0x4080000000000000LL) 557 #define float16_maxnorm make_float16(0x7bff) 558 #define float32_maxnorm make_float32(0x7f7fffff) 559 #define float64_maxnorm make_float64(0x7fefffffffffffffLL) 560 561 /* Reciprocal functions 562 * 563 * The algorithm that must be used to calculate the estimate 564 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate 565 */ 566 567 /* See RecipEstimate() 568 * 569 * input is a 9 bit fixed point number 570 * input range 256 .. 511 for a number from 0.5 <= x < 1.0. 571 * result range 256 .. 511 for a number from 1.0 to 511/256. 572 */ 573 574 static int recip_estimate(int input) 575 { 576 int a, b, r; 577 assert(256 <= input && input < 512); 578 a = (input * 2) + 1; 579 b = (1 << 19) / a; 580 r = (b + 1) >> 1; 581 assert(256 <= r && r < 512); 582 return r; 583 } 584 585 /* 586 * Increased precision version: 587 * input is a 13 bit fixed point number 588 * input range 2048 .. 4095 for a number from 0.5 <= x < 1.0. 589 * result range 4096 .. 8191 for a number from 1.0 to 2.0 590 */ 591 static int recip_estimate_incprec(int input) 592 { 593 int a, b, r; 594 assert(2048 <= input && input < 4096); 595 a = (input * 2) + 1; 596 /* 597 * The pseudocode expresses this as an operation on infinite 598 * precision reals where it calculates 2^25 / a and then looks 599 * at the error between that and the rounded-down-to-integer 600 * value to see if it should instead round up. We instead 601 * follow the same approach as the pseudocode for the 8-bit 602 * precision version, and calculate (2 * (2^25 / a)) as an 603 * integer so we can do the "add one and halve" to round it. 604 * So the 1 << 26 here is correct. 605 */ 606 b = (1 << 26) / a; 607 r = (b + 1) >> 1; 608 assert(4096 <= r && r < 8192); 609 return r; 610 } 611 612 /* 613 * Common wrapper to call recip_estimate 614 * 615 * The parameters are exponent and 64 bit fraction (without implicit 616 * bit) where the binary point is nominally at bit 52. Returns a 617 * float64 which can then be rounded to the appropriate size by the 618 * callee. 619 */ 620 621 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac, 622 bool increasedprecision) 623 { 624 uint32_t scaled, estimate; 625 uint64_t result_frac; 626 int result_exp; 627 628 /* Handle sub-normals */ 629 if (*exp == 0) { 630 if (extract64(frac, 51, 1) == 0) { 631 *exp = -1; 632 frac <<= 2; 633 } else { 634 frac <<= 1; 635 } 636 } 637 638 if (increasedprecision) { 639 /* scaled = UInt('1':fraction<51:41>) */ 640 scaled = deposit32(1 << 11, 0, 11, extract64(frac, 41, 11)); 641 estimate = recip_estimate_incprec(scaled); 642 } else { 643 /* scaled = UInt('1':fraction<51:44>) */ 644 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 645 estimate = recip_estimate(scaled); 646 } 647 648 result_exp = exp_off - *exp; 649 if (increasedprecision) { 650 result_frac = deposit64(0, 40, 12, estimate); 651 } else { 652 result_frac = deposit64(0, 44, 8, estimate); 653 } 654 if (result_exp == 0) { 655 result_frac = deposit64(result_frac >> 1, 51, 1, 1); 656 } else if (result_exp == -1) { 657 result_frac = deposit64(result_frac >> 2, 50, 2, 1); 658 result_exp = 0; 659 } 660 661 *exp = result_exp; 662 663 return result_frac; 664 } 665 666 static bool round_to_inf(float_status *fpst, bool sign_bit) 667 { 668 switch (fpst->float_rounding_mode) { 669 case float_round_nearest_even: /* Round to Nearest */ 670 return true; 671 case float_round_up: /* Round to +Inf */ 672 return !sign_bit; 673 case float_round_down: /* Round to -Inf */ 674 return sign_bit; 675 case float_round_to_zero: /* Round to Zero */ 676 return false; 677 default: 678 g_assert_not_reached(); 679 } 680 } 681 682 uint32_t HELPER(recpe_f16)(uint32_t input, float_status *fpst) 683 { 684 float16 f16 = float16_squash_input_denormal(input, fpst); 685 uint32_t f16_val = float16_val(f16); 686 uint32_t f16_sign = float16_is_neg(f16); 687 int f16_exp = extract32(f16_val, 10, 5); 688 uint32_t f16_frac = extract32(f16_val, 0, 10); 689 uint64_t f64_frac; 690 691 if (float16_is_any_nan(f16)) { 692 float16 nan = f16; 693 if (float16_is_signaling_nan(f16, fpst)) { 694 float_raise(float_flag_invalid, fpst); 695 if (!fpst->default_nan_mode) { 696 nan = float16_silence_nan(f16, fpst); 697 } 698 } 699 if (fpst->default_nan_mode) { 700 nan = float16_default_nan(fpst); 701 } 702 return nan; 703 } else if (float16_is_infinity(f16)) { 704 return float16_set_sign(float16_zero, float16_is_neg(f16)); 705 } else if (float16_is_zero(f16)) { 706 float_raise(float_flag_divbyzero, fpst); 707 return float16_set_sign(float16_infinity, float16_is_neg(f16)); 708 } else if (float16_abs(f16) < (1 << 8)) { 709 /* Abs(value) < 2.0^-16 */ 710 float_raise(float_flag_overflow | float_flag_inexact, fpst); 711 if (round_to_inf(fpst, f16_sign)) { 712 return float16_set_sign(float16_infinity, f16_sign); 713 } else { 714 return float16_set_sign(float16_maxnorm, f16_sign); 715 } 716 } else if (f16_exp >= 29 && fpst->flush_to_zero) { 717 float_raise(float_flag_underflow, fpst); 718 return float16_set_sign(float16_zero, float16_is_neg(f16)); 719 } 720 721 f64_frac = call_recip_estimate(&f16_exp, 29, 722 ((uint64_t) f16_frac) << (52 - 10), false); 723 724 /* result = sign : result_exp<4:0> : fraction<51:42> */ 725 f16_val = deposit32(0, 15, 1, f16_sign); 726 f16_val = deposit32(f16_val, 10, 5, f16_exp); 727 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); 728 return make_float16(f16_val); 729 } 730 731 /* 732 * FEAT_RPRES means the f32 FRECPE has an "increased precision" variant 733 * which is used when FPCR.AH == 1. 734 */ 735 static float32 do_recpe_f32(float32 input, float_status *fpst, bool rpres) 736 { 737 float32 f32 = float32_squash_input_denormal(input, fpst); 738 uint32_t f32_val = float32_val(f32); 739 bool f32_sign = float32_is_neg(f32); 740 int f32_exp = extract32(f32_val, 23, 8); 741 uint32_t f32_frac = extract32(f32_val, 0, 23); 742 uint64_t f64_frac; 743 744 if (float32_is_any_nan(f32)) { 745 float32 nan = f32; 746 if (float32_is_signaling_nan(f32, fpst)) { 747 float_raise(float_flag_invalid, fpst); 748 if (!fpst->default_nan_mode) { 749 nan = float32_silence_nan(f32, fpst); 750 } 751 } 752 if (fpst->default_nan_mode) { 753 nan = float32_default_nan(fpst); 754 } 755 return nan; 756 } else if (float32_is_infinity(f32)) { 757 return float32_set_sign(float32_zero, float32_is_neg(f32)); 758 } else if (float32_is_zero(f32)) { 759 float_raise(float_flag_divbyzero, fpst); 760 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 761 } else if (float32_abs(f32) < (1ULL << 21)) { 762 /* Abs(value) < 2.0^-128 */ 763 float_raise(float_flag_overflow | float_flag_inexact, fpst); 764 if (round_to_inf(fpst, f32_sign)) { 765 return float32_set_sign(float32_infinity, f32_sign); 766 } else { 767 return float32_set_sign(float32_maxnorm, f32_sign); 768 } 769 } else if (f32_exp >= 253 && fpst->flush_to_zero) { 770 float_raise(float_flag_underflow, fpst); 771 return float32_set_sign(float32_zero, float32_is_neg(f32)); 772 } 773 774 f64_frac = call_recip_estimate(&f32_exp, 253, 775 ((uint64_t) f32_frac) << (52 - 23), rpres); 776 777 /* result = sign : result_exp<7:0> : fraction<51:29> */ 778 f32_val = deposit32(0, 31, 1, f32_sign); 779 f32_val = deposit32(f32_val, 23, 8, f32_exp); 780 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); 781 return make_float32(f32_val); 782 } 783 784 float32 HELPER(recpe_f32)(float32 input, float_status *fpst) 785 { 786 return do_recpe_f32(input, fpst, false); 787 } 788 789 float32 HELPER(recpe_rpres_f32)(float32 input, float_status *fpst) 790 { 791 return do_recpe_f32(input, fpst, true); 792 } 793 794 float64 HELPER(recpe_f64)(float64 input, float_status *fpst) 795 { 796 float64 f64 = float64_squash_input_denormal(input, fpst); 797 uint64_t f64_val = float64_val(f64); 798 bool f64_sign = float64_is_neg(f64); 799 int f64_exp = extract64(f64_val, 52, 11); 800 uint64_t f64_frac = extract64(f64_val, 0, 52); 801 802 /* Deal with any special cases */ 803 if (float64_is_any_nan(f64)) { 804 float64 nan = f64; 805 if (float64_is_signaling_nan(f64, fpst)) { 806 float_raise(float_flag_invalid, fpst); 807 if (!fpst->default_nan_mode) { 808 nan = float64_silence_nan(f64, fpst); 809 } 810 } 811 if (fpst->default_nan_mode) { 812 nan = float64_default_nan(fpst); 813 } 814 return nan; 815 } else if (float64_is_infinity(f64)) { 816 return float64_set_sign(float64_zero, float64_is_neg(f64)); 817 } else if (float64_is_zero(f64)) { 818 float_raise(float_flag_divbyzero, fpst); 819 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 820 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { 821 /* Abs(value) < 2.0^-1024 */ 822 float_raise(float_flag_overflow | float_flag_inexact, fpst); 823 if (round_to_inf(fpst, f64_sign)) { 824 return float64_set_sign(float64_infinity, f64_sign); 825 } else { 826 return float64_set_sign(float64_maxnorm, f64_sign); 827 } 828 } else if (f64_exp >= 2045 && fpst->flush_to_zero) { 829 float_raise(float_flag_underflow, fpst); 830 return float64_set_sign(float64_zero, float64_is_neg(f64)); 831 } 832 833 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac, false); 834 835 /* result = sign : result_exp<10:0> : fraction<51:0>; */ 836 f64_val = deposit64(0, 63, 1, f64_sign); 837 f64_val = deposit64(f64_val, 52, 11, f64_exp); 838 f64_val = deposit64(f64_val, 0, 52, f64_frac); 839 return make_float64(f64_val); 840 } 841 842 /* The algorithm that must be used to calculate the estimate 843 * is specified by the ARM ARM. 844 */ 845 846 static int do_recip_sqrt_estimate(int a) 847 { 848 int b, estimate; 849 850 assert(128 <= a && a < 512); 851 if (a < 256) { 852 a = a * 2 + 1; 853 } else { 854 a = (a >> 1) << 1; 855 a = (a + 1) * 2; 856 } 857 b = 512; 858 while (a * (b + 1) * (b + 1) < (1 << 28)) { 859 b += 1; 860 } 861 estimate = (b + 1) / 2; 862 assert(256 <= estimate && estimate < 512); 863 864 return estimate; 865 } 866 867 static int do_recip_sqrt_estimate_incprec(int a) 868 { 869 /* 870 * The Arm ARM describes the 12-bit precision version of RecipSqrtEstimate 871 * in terms of an infinite-precision floating point calculation of a 872 * square root. We implement this using the same kind of pure integer 873 * algorithm as the 8-bit mantissa, to get the same bit-for-bit result. 874 */ 875 int64_t b, estimate; 876 877 assert(1024 <= a && a < 4096); 878 if (a < 2048) { 879 a = a * 2 + 1; 880 } else { 881 a = (a >> 1) << 1; 882 a = (a + 1) * 2; 883 } 884 b = 8192; 885 while (a * (b + 1) * (b + 1) < (1ULL << 39)) { 886 b += 1; 887 } 888 estimate = (b + 1) / 2; 889 890 assert(4096 <= estimate && estimate < 8192); 891 892 return estimate; 893 } 894 895 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac, 896 bool increasedprecision) 897 { 898 int estimate; 899 uint32_t scaled; 900 901 if (*exp == 0) { 902 while (extract64(frac, 51, 1) == 0) { 903 frac = frac << 1; 904 *exp -= 1; 905 } 906 frac = extract64(frac, 0, 51) << 1; 907 } 908 909 if (increasedprecision) { 910 if (*exp & 1) { 911 /* scaled = UInt('01':fraction<51:42>) */ 912 scaled = deposit32(1 << 10, 0, 10, extract64(frac, 42, 10)); 913 } else { 914 /* scaled = UInt('1':fraction<51:41>) */ 915 scaled = deposit32(1 << 11, 0, 11, extract64(frac, 41, 11)); 916 } 917 estimate = do_recip_sqrt_estimate_incprec(scaled); 918 } else { 919 if (*exp & 1) { 920 /* scaled = UInt('01':fraction<51:45>) */ 921 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); 922 } else { 923 /* scaled = UInt('1':fraction<51:44>) */ 924 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); 925 } 926 estimate = do_recip_sqrt_estimate(scaled); 927 } 928 929 *exp = (exp_off - *exp) / 2; 930 if (increasedprecision) { 931 return extract64(estimate, 0, 12) << 40; 932 } else { 933 return extract64(estimate, 0, 8) << 44; 934 } 935 } 936 937 uint32_t HELPER(rsqrte_f16)(uint32_t input, float_status *s) 938 { 939 float16 f16 = float16_squash_input_denormal(input, s); 940 uint16_t val = float16_val(f16); 941 bool f16_sign = float16_is_neg(f16); 942 int f16_exp = extract32(val, 10, 5); 943 uint16_t f16_frac = extract32(val, 0, 10); 944 uint64_t f64_frac; 945 946 if (float16_is_any_nan(f16)) { 947 float16 nan = f16; 948 if (float16_is_signaling_nan(f16, s)) { 949 float_raise(float_flag_invalid, s); 950 if (!s->default_nan_mode) { 951 nan = float16_silence_nan(f16, s); 952 } 953 } 954 if (s->default_nan_mode) { 955 nan = float16_default_nan(s); 956 } 957 return nan; 958 } else if (float16_is_zero(f16)) { 959 float_raise(float_flag_divbyzero, s); 960 return float16_set_sign(float16_infinity, f16_sign); 961 } else if (f16_sign) { 962 float_raise(float_flag_invalid, s); 963 return float16_default_nan(s); 964 } else if (float16_is_infinity(f16)) { 965 return float16_zero; 966 } 967 968 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 969 * preserving the parity of the exponent. */ 970 971 f64_frac = ((uint64_t) f16_frac) << (52 - 10); 972 973 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac, false); 974 975 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ 976 val = deposit32(0, 15, 1, f16_sign); 977 val = deposit32(val, 10, 5, f16_exp); 978 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); 979 return make_float16(val); 980 } 981 982 /* 983 * FEAT_RPRES means the f32 FRSQRTE has an "increased precision" variant 984 * which is used when FPCR.AH == 1. 985 */ 986 static float32 do_rsqrte_f32(float32 input, float_status *s, bool rpres) 987 { 988 float32 f32 = float32_squash_input_denormal(input, s); 989 uint32_t val = float32_val(f32); 990 uint32_t f32_sign = float32_is_neg(f32); 991 int f32_exp = extract32(val, 23, 8); 992 uint32_t f32_frac = extract32(val, 0, 23); 993 uint64_t f64_frac; 994 995 if (float32_is_any_nan(f32)) { 996 float32 nan = f32; 997 if (float32_is_signaling_nan(f32, s)) { 998 float_raise(float_flag_invalid, s); 999 if (!s->default_nan_mode) { 1000 nan = float32_silence_nan(f32, s); 1001 } 1002 } 1003 if (s->default_nan_mode) { 1004 nan = float32_default_nan(s); 1005 } 1006 return nan; 1007 } else if (float32_is_zero(f32)) { 1008 float_raise(float_flag_divbyzero, s); 1009 return float32_set_sign(float32_infinity, float32_is_neg(f32)); 1010 } else if (float32_is_neg(f32)) { 1011 float_raise(float_flag_invalid, s); 1012 return float32_default_nan(s); 1013 } else if (float32_is_infinity(f32)) { 1014 return float32_zero; 1015 } 1016 1017 /* Scale and normalize to a double-precision value between 0.25 and 1.0, 1018 * preserving the parity of the exponent. */ 1019 1020 f64_frac = ((uint64_t) f32_frac) << 29; 1021 1022 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac, rpres); 1023 1024 /* 1025 * result = sign : result_exp<7:0> : estimate<7:0> : Zeros(15) 1026 * or for increased precision 1027 * result = sign : result_exp<7:0> : estimate<11:0> : Zeros(11) 1028 */ 1029 val = deposit32(0, 31, 1, f32_sign); 1030 val = deposit32(val, 23, 8, f32_exp); 1031 if (rpres) { 1032 val = deposit32(val, 11, 12, extract64(f64_frac, 52 - 12, 12)); 1033 } else { 1034 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); 1035 } 1036 return make_float32(val); 1037 } 1038 1039 float32 HELPER(rsqrte_f32)(float32 input, float_status *s) 1040 { 1041 return do_rsqrte_f32(input, s, false); 1042 } 1043 1044 float32 HELPER(rsqrte_rpres_f32)(float32 input, float_status *s) 1045 { 1046 return do_rsqrte_f32(input, s, true); 1047 } 1048 1049 float64 HELPER(rsqrte_f64)(float64 input, float_status *s) 1050 { 1051 float64 f64 = float64_squash_input_denormal(input, s); 1052 uint64_t val = float64_val(f64); 1053 bool f64_sign = float64_is_neg(f64); 1054 int f64_exp = extract64(val, 52, 11); 1055 uint64_t f64_frac = extract64(val, 0, 52); 1056 1057 if (float64_is_any_nan(f64)) { 1058 float64 nan = f64; 1059 if (float64_is_signaling_nan(f64, s)) { 1060 float_raise(float_flag_invalid, s); 1061 if (!s->default_nan_mode) { 1062 nan = float64_silence_nan(f64, s); 1063 } 1064 } 1065 if (s->default_nan_mode) { 1066 nan = float64_default_nan(s); 1067 } 1068 return nan; 1069 } else if (float64_is_zero(f64)) { 1070 float_raise(float_flag_divbyzero, s); 1071 return float64_set_sign(float64_infinity, float64_is_neg(f64)); 1072 } else if (float64_is_neg(f64)) { 1073 float_raise(float_flag_invalid, s); 1074 return float64_default_nan(s); 1075 } else if (float64_is_infinity(f64)) { 1076 return float64_zero; 1077 } 1078 1079 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac, false); 1080 1081 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ 1082 val = deposit64(0, 61, 1, f64_sign); 1083 val = deposit64(val, 52, 11, f64_exp); 1084 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); 1085 return make_float64(val); 1086 } 1087 1088 uint32_t HELPER(recpe_u32)(uint32_t a) 1089 { 1090 int input, estimate; 1091 1092 if ((a & 0x80000000) == 0) { 1093 return 0xffffffff; 1094 } 1095 1096 input = extract32(a, 23, 9); 1097 estimate = recip_estimate(input); 1098 1099 return deposit32(0, (32 - 9), 9, estimate); 1100 } 1101 1102 uint32_t HELPER(rsqrte_u32)(uint32_t a) 1103 { 1104 int estimate; 1105 1106 if ((a & 0xc0000000) == 0) { 1107 return 0xffffffff; 1108 } 1109 1110 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); 1111 1112 return deposit32(0, 23, 9, estimate); 1113 } 1114 1115 /* VFPv4 fused multiply-accumulate */ 1116 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b, 1117 dh_ctype_f16 c, float_status *fpst) 1118 { 1119 return float16_muladd(a, b, c, 0, fpst); 1120 } 1121 1122 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, 1123 float_status *fpst) 1124 { 1125 return float32_muladd(a, b, c, 0, fpst); 1126 } 1127 1128 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, 1129 float_status *fpst) 1130 { 1131 return float64_muladd(a, b, c, 0, fpst); 1132 } 1133 1134 /* ARMv8 round to integral */ 1135 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, float_status *fp_status) 1136 { 1137 return float16_round_to_int(x, fp_status); 1138 } 1139 1140 float32 HELPER(rints_exact)(float32 x, float_status *fp_status) 1141 { 1142 return float32_round_to_int(x, fp_status); 1143 } 1144 1145 float64 HELPER(rintd_exact)(float64 x, float_status *fp_status) 1146 { 1147 return float64_round_to_int(x, fp_status); 1148 } 1149 1150 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, float_status *fp_status) 1151 { 1152 int old_flags = get_float_exception_flags(fp_status), new_flags; 1153 float16 ret; 1154 1155 ret = float16_round_to_int(x, fp_status); 1156 1157 /* Suppress any inexact exceptions the conversion produced */ 1158 if (!(old_flags & float_flag_inexact)) { 1159 new_flags = get_float_exception_flags(fp_status); 1160 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1161 } 1162 1163 return ret; 1164 } 1165 1166 float32 HELPER(rints)(float32 x, float_status *fp_status) 1167 { 1168 int old_flags = get_float_exception_flags(fp_status), new_flags; 1169 float32 ret; 1170 1171 ret = float32_round_to_int(x, fp_status); 1172 1173 /* Suppress any inexact exceptions the conversion produced */ 1174 if (!(old_flags & float_flag_inexact)) { 1175 new_flags = get_float_exception_flags(fp_status); 1176 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1177 } 1178 1179 return ret; 1180 } 1181 1182 float64 HELPER(rintd)(float64 x, float_status *fp_status) 1183 { 1184 int old_flags = get_float_exception_flags(fp_status), new_flags; 1185 float64 ret; 1186 1187 ret = float64_round_to_int(x, fp_status); 1188 1189 /* Suppress any inexact exceptions the conversion produced */ 1190 if (!(old_flags & float_flag_inexact)) { 1191 new_flags = get_float_exception_flags(fp_status); 1192 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); 1193 } 1194 1195 return ret; 1196 } 1197 1198 /* Convert ARM rounding mode to softfloat */ 1199 const FloatRoundMode arm_rmode_to_sf_map[] = { 1200 [FPROUNDING_TIEEVEN] = float_round_nearest_even, 1201 [FPROUNDING_POSINF] = float_round_up, 1202 [FPROUNDING_NEGINF] = float_round_down, 1203 [FPROUNDING_ZERO] = float_round_to_zero, 1204 [FPROUNDING_TIEAWAY] = float_round_ties_away, 1205 [FPROUNDING_ODD] = float_round_to_odd, 1206 }; 1207 1208 /* 1209 * Implement float64 to int32_t conversion without saturation; 1210 * the result is supplied modulo 2^32. 1211 */ 1212 uint64_t HELPER(fjcvtzs)(float64 value, float_status *status) 1213 { 1214 uint32_t frac, e_old, e_new; 1215 bool inexact; 1216 1217 e_old = get_float_exception_flags(status); 1218 set_float_exception_flags(0, status); 1219 frac = float64_to_int32_modulo(value, float_round_to_zero, status); 1220 e_new = get_float_exception_flags(status); 1221 set_float_exception_flags(e_old | e_new, status); 1222 1223 /* Normal inexact, denormal with flush-to-zero, or overflow or NaN */ 1224 inexact = e_new & (float_flag_inexact | 1225 float_flag_input_denormal_flushed | 1226 float_flag_invalid); 1227 1228 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ 1229 inexact |= value == float64_chs(float64_zero); 1230 1231 /* Pack the result and the env->ZF representation of Z together. */ 1232 return deposit64(frac, 32, 32, inexact); 1233 } 1234 1235 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) 1236 { 1237 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status[FPST_A32]); 1238 uint32_t result = pair; 1239 uint32_t z = (pair >> 32) == 0; 1240 1241 /* Store Z, clear NCV, in FPSCR.NZCV. */ 1242 env->vfp.fpsr = (env->vfp.fpsr & ~FPSR_NZCV_MASK) | (z * FPSR_Z); 1243 1244 return result; 1245 } 1246 1247 /* Round a float32 to an integer that fits in int32_t or int64_t. */ 1248 static float32 frint_s(float32 f, float_status *fpst, int intsize) 1249 { 1250 int old_flags = get_float_exception_flags(fpst); 1251 uint32_t exp = extract32(f, 23, 8); 1252 1253 if (unlikely(exp == 0xff)) { 1254 /* NaN or Inf. */ 1255 goto overflow; 1256 } 1257 1258 /* Round and re-extract the exponent. */ 1259 f = float32_round_to_int(f, fpst); 1260 exp = extract32(f, 23, 8); 1261 1262 /* Validate the range of the result. */ 1263 if (exp < 126 + intsize) { 1264 /* abs(F) <= INT{N}_MAX */ 1265 return f; 1266 } 1267 if (exp == 126 + intsize) { 1268 uint32_t sign = extract32(f, 31, 1); 1269 uint32_t frac = extract32(f, 0, 23); 1270 if (sign && frac == 0) { 1271 /* F == INT{N}_MIN */ 1272 return f; 1273 } 1274 } 1275 1276 overflow: 1277 /* 1278 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1279 * inexact exception float32_round_to_int may have raised. 1280 */ 1281 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1282 return (0x100u + 126u + intsize) << 23; 1283 } 1284 1285 float32 HELPER(frint32_s)(float32 f, float_status *fpst) 1286 { 1287 return frint_s(f, fpst, 32); 1288 } 1289 1290 float32 HELPER(frint64_s)(float32 f, float_status *fpst) 1291 { 1292 return frint_s(f, fpst, 64); 1293 } 1294 1295 /* Round a float64 to an integer that fits in int32_t or int64_t. */ 1296 static float64 frint_d(float64 f, float_status *fpst, int intsize) 1297 { 1298 int old_flags = get_float_exception_flags(fpst); 1299 uint32_t exp = extract64(f, 52, 11); 1300 1301 if (unlikely(exp == 0x7ff)) { 1302 /* NaN or Inf. */ 1303 goto overflow; 1304 } 1305 1306 /* Round and re-extract the exponent. */ 1307 f = float64_round_to_int(f, fpst); 1308 exp = extract64(f, 52, 11); 1309 1310 /* Validate the range of the result. */ 1311 if (exp < 1022 + intsize) { 1312 /* abs(F) <= INT{N}_MAX */ 1313 return f; 1314 } 1315 if (exp == 1022 + intsize) { 1316 uint64_t sign = extract64(f, 63, 1); 1317 uint64_t frac = extract64(f, 0, 52); 1318 if (sign && frac == 0) { 1319 /* F == INT{N}_MIN */ 1320 return f; 1321 } 1322 } 1323 1324 overflow: 1325 /* 1326 * Raise Invalid and return INT{N}_MIN as a float. Revert any 1327 * inexact exception float64_round_to_int may have raised. 1328 */ 1329 set_float_exception_flags(old_flags | float_flag_invalid, fpst); 1330 return (uint64_t)(0x800 + 1022 + intsize) << 52; 1331 } 1332 1333 float64 HELPER(frint32_d)(float64 f, float_status *fpst) 1334 { 1335 return frint_d(f, fpst, 32); 1336 } 1337 1338 float64 HELPER(frint64_d)(float64 f, float_status *fpst) 1339 { 1340 return frint_d(f, fpst, 64); 1341 } 1342 1343 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg) 1344 { 1345 uint32_t syndrome; 1346 1347 switch (reg) { 1348 case ARM_VFP_MVFR0: 1349 case ARM_VFP_MVFR1: 1350 case ARM_VFP_MVFR2: 1351 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) { 1352 return; 1353 } 1354 break; 1355 case ARM_VFP_FPSID: 1356 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) { 1357 return; 1358 } 1359 break; 1360 default: 1361 g_assert_not_reached(); 1362 } 1363 1364 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT) 1365 | ARM_EL_IL 1366 | (1 << 24) | (0xe << 20) | (7 << 14) 1367 | (reg << 10) | (rt << 5) | 1); 1368 1369 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); 1370 } 1371 1372 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) 1373 { 1374 return vfp_get_fpscr(env); 1375 } 1376 1377 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) 1378 { 1379 vfp_set_fpscr(env, val); 1380 } 1381