1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2022 Intel Corporation */
3 #ifndef _ICP_QAT_HW_20_COMP_H_
4 #define _ICP_QAT_HW_20_COMP_H_
5
6 #include <linux/swab.h>
7
8 #include "icp_qat_hw_20_comp_defs.h"
9 #include "icp_qat_fw.h"
10
11 struct icp_qat_hw_comp_20_config_csr_lower {
12 enum icp_qat_hw_comp_20_extended_delay_match_mode edmm;
13 enum icp_qat_hw_comp_20_hw_comp_format algo;
14 enum icp_qat_hw_comp_20_search_depth sd;
15 enum icp_qat_hw_comp_20_hbs_control hbs;
16 enum icp_qat_hw_comp_20_abd abd;
17 enum icp_qat_hw_comp_20_lllbd_ctrl lllbd;
18 enum icp_qat_hw_comp_20_min_match_control mmctrl;
19 enum icp_qat_hw_comp_20_skip_hash_collision hash_col;
20 enum icp_qat_hw_comp_20_skip_hash_update hash_update;
21 enum icp_qat_hw_comp_20_byte_skip skip_ctrl;
22 };
23
24 static inline __u32
ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr)25 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr)
26 {
27 u32 val32 = 0;
28
29 QAT_FIELD_SET(val32, csr.algo,
30 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
31 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
32 QAT_FIELD_SET(val32, csr.sd,
33 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
34 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
35 QAT_FIELD_SET(val32, csr.edmm,
36 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
37 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
38 QAT_FIELD_SET(val32, csr.hbs,
39 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
40 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
41 QAT_FIELD_SET(val32, csr.lllbd,
42 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
43 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
44 QAT_FIELD_SET(val32, csr.mmctrl,
45 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
46 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
47 QAT_FIELD_SET(val32, csr.hash_col,
48 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
49 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
50 QAT_FIELD_SET(val32, csr.hash_update,
51 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
52 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
53 QAT_FIELD_SET(val32, csr.skip_ctrl,
54 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
55 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
56 QAT_FIELD_SET(val32, csr.abd, ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
57 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
58
59 return swab32(val32);
60 }
61
62 struct icp_qat_hw_comp_20_config_csr_upper {
63 enum icp_qat_hw_comp_20_scb_control scb_ctrl;
64 enum icp_qat_hw_comp_20_rmb_control rmb_ctrl;
65 enum icp_qat_hw_comp_20_som_control som_ctrl;
66 enum icp_qat_hw_comp_20_skip_hash_rd_control skip_hash_ctrl;
67 enum icp_qat_hw_comp_20_scb_unload_control scb_unload_ctrl;
68 enum icp_qat_hw_comp_20_disable_token_fusion_control disable_token_fusion_ctrl;
69 enum icp_qat_hw_comp_20_lbms lbms;
70 enum icp_qat_hw_comp_20_scb_mode_reset_mask scb_mode_reset;
71 __u16 lazy;
72 __u16 nice;
73 };
74
75 static inline __u32
ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_20_config_csr_upper csr)76 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_20_config_csr_upper csr)
77 {
78 u32 val32 = 0;
79
80 QAT_FIELD_SET(val32, csr.scb_ctrl,
81 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS,
82 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK);
83 QAT_FIELD_SET(val32, csr.rmb_ctrl,
84 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS,
85 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK);
86 QAT_FIELD_SET(val32, csr.som_ctrl,
87 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS,
88 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK);
89 QAT_FIELD_SET(val32, csr.skip_hash_ctrl,
90 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS,
91 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK);
92 QAT_FIELD_SET(val32, csr.scb_unload_ctrl,
93 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS,
94 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK);
95 QAT_FIELD_SET(val32, csr.disable_token_fusion_ctrl,
96 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS,
97 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK);
98 QAT_FIELD_SET(val32, csr.lbms,
99 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS,
100 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK);
101 QAT_FIELD_SET(val32, csr.scb_mode_reset,
102 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS,
103 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK);
104 QAT_FIELD_SET(val32, csr.lazy,
105 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS,
106 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK);
107 QAT_FIELD_SET(val32, csr.nice,
108 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS,
109 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK);
110
111 return swab32(val32);
112 }
113
114 struct icp_qat_hw_decomp_20_config_csr_lower {
115 enum icp_qat_hw_decomp_20_hbs_control hbs;
116 enum icp_qat_hw_decomp_20_lbms lbms;
117 enum icp_qat_hw_decomp_20_hw_comp_format algo;
118 enum icp_qat_hw_decomp_20_min_match_control mmctrl;
119 enum icp_qat_hw_decomp_20_lz4_block_checksum_present lbc;
120 };
121
122 static inline __u32
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_20_config_csr_lower csr)123 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_20_config_csr_lower csr)
124 {
125 u32 val32 = 0;
126
127 QAT_FIELD_SET(val32, csr.hbs,
128 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
129 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
130 QAT_FIELD_SET(val32, csr.lbms,
131 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS,
132 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK);
133 QAT_FIELD_SET(val32, csr.algo,
134 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS,
135 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK);
136 QAT_FIELD_SET(val32, csr.mmctrl,
137 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
138 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
139 QAT_FIELD_SET(val32, csr.lbc,
140 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS,
141 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK);
142
143 return swab32(val32);
144 }
145
146 struct icp_qat_hw_decomp_20_config_csr_upper {
147 enum icp_qat_hw_decomp_20_speculative_decoder_control sdc;
148 enum icp_qat_hw_decomp_20_mini_cam_control mcc;
149 };
150
151 static inline __u32
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_20_config_csr_upper csr)152 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_20_config_csr_upper csr)
153 {
154 u32 val32 = 0;
155
156 QAT_FIELD_SET(val32, csr.sdc,
157 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS,
158 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK);
159 QAT_FIELD_SET(val32, csr.mcc,
160 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS,
161 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK);
162
163 return swab32(val32);
164 }
165
166 #endif
167