1 /*
2 * CXL host parameter parsing routines
3 *
4 * Copyright (c) 2022 Huawei
5 * Modeled loosely on the NUMA options handling in hw/core/numa.c
6 */
7
8 #include "qemu/osdep.h"
9 #include "qemu/units.h"
10 #include "qemu/bitmap.h"
11 #include "qemu/error-report.h"
12 #include "qapi/error.h"
13 #include "system/qtest.h"
14 #include "hw/boards.h"
15
16 #include "qapi/qapi-visit-machine.h"
17 #include "hw/cxl/cxl.h"
18 #include "hw/cxl/cxl_host.h"
19 #include "hw/pci/pci_bus.h"
20 #include "hw/pci/pci_bridge.h"
21 #include "hw/pci/pci_host.h"
22 #include "hw/pci/pcie_port.h"
23 #include "hw/pci-bridge/pci_expander_bridge.h"
24
cxl_fixed_memory_window_config(CXLState * cxl_state,CXLFixedMemoryWindowOptions * object,Error ** errp)25 static void cxl_fixed_memory_window_config(CXLState *cxl_state,
26 CXLFixedMemoryWindowOptions *object,
27 Error **errp)
28 {
29 ERRP_GUARD();
30 g_autofree CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
31 strList *target;
32 int i;
33
34 for (target = object->targets; target; target = target->next) {
35 fw->num_targets++;
36 }
37
38 fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp);
39 if (*errp) {
40 return;
41 }
42
43 if (object->size % (256 * MiB)) {
44 error_setg(errp,
45 "Size of a CXL fixed memory window must be a multiple of 256MiB");
46 return;
47 }
48 fw->size = object->size;
49
50 if (object->has_interleave_granularity) {
51 fw->enc_int_gran =
52 cxl_interleave_granularity_enc(object->interleave_granularity,
53 errp);
54 if (*errp) {
55 return;
56 }
57 } else {
58 /* Default to 256 byte interleave */
59 fw->enc_int_gran = 0;
60 }
61
62 fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets));
63 for (i = 0, target = object->targets; target; i++, target = target->next) {
64 /* This link cannot be resolved yet, so stash the name for now */
65 fw->targets[i] = g_strdup(target->value);
66 }
67
68 cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows,
69 g_steal_pointer(&fw));
70 }
71
cxl_fmws_link_targets(CXLState * cxl_state,Error ** errp)72 void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
73 {
74 if (cxl_state && cxl_state->fixed_windows) {
75 GList *it;
76
77 for (it = cxl_state->fixed_windows; it; it = it->next) {
78 CXLFixedWindow *fw = it->data;
79 int i;
80
81 for (i = 0; i < fw->num_targets; i++) {
82 Object *o;
83 bool ambig;
84
85 o = object_resolve_path_type(fw->targets[i],
86 TYPE_PXB_CXL_DEV,
87 &ambig);
88 if (!o) {
89 error_setg(errp, "Could not resolve CXLFM target %s",
90 fw->targets[i]);
91 return;
92 }
93 fw->target_hbs[i] = PXB_CXL_DEV(o);
94 }
95 }
96 }
97 }
98
cxl_hdm_find_target(uint32_t * cache_mem,hwaddr addr,uint8_t * target)99 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
100 uint8_t *target)
101 {
102 int hdm_inc = R_CXL_HDM_DECODER1_BASE_LO - R_CXL_HDM_DECODER0_BASE_LO;
103 unsigned int hdm_count;
104 bool found = false;
105 int i;
106 uint32_t cap;
107
108 cap = ldl_le_p(cache_mem + R_CXL_HDM_DECODER_CAPABILITY);
109 hdm_count = cxl_decoder_count_dec(FIELD_EX32(cap,
110 CXL_HDM_DECODER_CAPABILITY,
111 DECODER_COUNT));
112 for (i = 0; i < hdm_count; i++) {
113 uint32_t ctrl, ig_enc, iw_enc, target_idx;
114 uint32_t low, high;
115 uint64_t base, size;
116
117 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_LO + i * hdm_inc);
118 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_BASE_HI + i * hdm_inc);
119 base = (low & 0xf0000000) | ((uint64_t)high << 32);
120 low = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_LO + i * hdm_inc);
121 high = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_SIZE_HI + i * hdm_inc);
122 size = (low & 0xf0000000) | ((uint64_t)high << 32);
123 if (addr < base || addr >= base + size) {
124 continue;
125 }
126
127 ctrl = ldl_le_p(cache_mem + R_CXL_HDM_DECODER0_CTRL + i * hdm_inc);
128 if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
129 return false;
130 }
131 found = true;
132 ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
133 iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
134 target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
135
136 if (target_idx < 4) {
137 uint32_t val = ldl_le_p(cache_mem +
138 R_CXL_HDM_DECODER0_TARGET_LIST_LO +
139 i * hdm_inc);
140 *target = extract32(val, target_idx * 8, 8);
141 } else {
142 uint32_t val = ldl_le_p(cache_mem +
143 R_CXL_HDM_DECODER0_TARGET_LIST_HI +
144 i * hdm_inc);
145 *target = extract32(val, (target_idx - 4) * 8, 8);
146 }
147 break;
148 }
149
150 return found;
151 }
152
cxl_cfmws_find_device(CXLFixedWindow * fw,hwaddr addr)153 static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
154 {
155 CXLComponentState *hb_cstate, *usp_cstate;
156 PCIHostState *hb;
157 CXLUpstreamPort *usp;
158 int rb_index;
159 uint32_t *cache_mem;
160 uint8_t target;
161 bool target_found;
162 PCIDevice *rp, *d;
163
164 /* Address is relative to memory region. Convert to HPA */
165 addr += fw->base;
166
167 rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
168 hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl_host_bridge);
169 if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
170 return NULL;
171 }
172
173 if (cxl_get_hb_passthrough(hb)) {
174 rp = pcie_find_port_first(hb->bus);
175 if (!rp) {
176 return NULL;
177 }
178 } else {
179 hb_cstate = cxl_get_hb_cstate(hb);
180 if (!hb_cstate) {
181 return NULL;
182 }
183
184 cache_mem = hb_cstate->crb.cache_mem_registers;
185
186 target_found = cxl_hdm_find_target(cache_mem, addr, &target);
187 if (!target_found) {
188 return NULL;
189 }
190
191 rp = pcie_find_port_by_pn(hb->bus, target);
192 if (!rp) {
193 return NULL;
194 }
195 }
196
197 d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
198 if (!d) {
199 return NULL;
200 }
201
202 if (object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
203 return d;
204 }
205
206 /*
207 * Could also be a switch. Note only one level of switching currently
208 * supported.
209 */
210 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_USP)) {
211 return NULL;
212 }
213 usp = CXL_USP(d);
214
215 usp_cstate = cxl_usp_to_cstate(usp);
216 if (!usp_cstate) {
217 return NULL;
218 }
219
220 cache_mem = usp_cstate->crb.cache_mem_registers;
221
222 target_found = cxl_hdm_find_target(cache_mem, addr, &target);
223 if (!target_found) {
224 return NULL;
225 }
226
227 d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target);
228 if (!d) {
229 return NULL;
230 }
231
232 d = pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devices[0];
233 if (!d) {
234 return NULL;
235 }
236
237 if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
238 return NULL;
239 }
240
241 return d;
242 }
243
cxl_read_cfmws(void * opaque,hwaddr addr,uint64_t * data,unsigned size,MemTxAttrs attrs)244 static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
245 unsigned size, MemTxAttrs attrs)
246 {
247 CXLFixedWindow *fw = opaque;
248 PCIDevice *d;
249
250 d = cxl_cfmws_find_device(fw, addr);
251 if (d == NULL) {
252 *data = 0;
253 /* Reads to invalid address return poison */
254 return MEMTX_ERROR;
255 }
256
257 return cxl_type3_read(d, addr + fw->base, data, size, attrs);
258 }
259
cxl_write_cfmws(void * opaque,hwaddr addr,uint64_t data,unsigned size,MemTxAttrs attrs)260 static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
261 uint64_t data, unsigned size,
262 MemTxAttrs attrs)
263 {
264 CXLFixedWindow *fw = opaque;
265 PCIDevice *d;
266
267 d = cxl_cfmws_find_device(fw, addr);
268 if (d == NULL) {
269 /* Writes to invalid address are silent */
270 return MEMTX_OK;
271 }
272
273 return cxl_type3_write(d, addr + fw->base, data, size, attrs);
274 }
275
276 const MemoryRegionOps cfmws_ops = {
277 .read_with_attrs = cxl_read_cfmws,
278 .write_with_attrs = cxl_write_cfmws,
279 .endianness = DEVICE_LITTLE_ENDIAN,
280 .valid = {
281 .min_access_size = 1,
282 .max_access_size = 8,
283 .unaligned = true,
284 },
285 .impl = {
286 .min_access_size = 1,
287 .max_access_size = 8,
288 .unaligned = true,
289 },
290 };
291
machine_get_cxl(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)292 static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
293 void *opaque, Error **errp)
294 {
295 CXLState *cxl_state = opaque;
296 bool value = cxl_state->is_enabled;
297
298 visit_type_bool(v, name, &value, errp);
299 }
300
machine_set_cxl(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)301 static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
302 void *opaque, Error **errp)
303 {
304 CXLState *cxl_state = opaque;
305 bool value;
306
307 if (!visit_type_bool(v, name, &value, errp)) {
308 return;
309 }
310 cxl_state->is_enabled = value;
311 }
312
machine_get_cfmw(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)313 static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
314 void *opaque, Error **errp)
315 {
316 CXLState *state = opaque;
317 CXLFixedMemoryWindowOptionsList **list = &state->cfmw_list;
318
319 visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
320 }
321
machine_set_cfmw(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)322 static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
323 void *opaque, Error **errp)
324 {
325 CXLState *state = opaque;
326 CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
327 CXLFixedMemoryWindowOptionsList *it;
328
329 visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
330 if (!cfmw_list) {
331 return;
332 }
333
334 for (it = cfmw_list; it; it = it->next) {
335 cxl_fixed_memory_window_config(state, it->value, errp);
336 }
337 state->cfmw_list = cfmw_list;
338 }
339
cxl_machine_init(Object * obj,CXLState * state)340 void cxl_machine_init(Object *obj, CXLState *state)
341 {
342 object_property_add(obj, "cxl", "bool", machine_get_cxl,
343 machine_set_cxl, NULL, state);
344 object_property_set_description(obj, "cxl",
345 "Set on/off to enable/disable "
346 "CXL instantiation");
347
348 object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
349 machine_get_cfmw, machine_set_cfmw,
350 NULL, state);
351 object_property_set_description(obj, "cxl-fmw",
352 "CXL Fixed Memory Windows (array)");
353 }
354
cxl_hook_up_pxb_registers(PCIBus * bus,CXLState * state,Error ** errp)355 void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
356 {
357 /* Walk the pci busses looking for pxb busses to hook up */
358 if (bus) {
359 QLIST_FOREACH(bus, &bus->child, sibling) {
360 if (!pci_bus_is_root(bus)) {
361 continue;
362 }
363 if (pci_bus_is_cxl(bus)) {
364 if (!state->is_enabled) {
365 error_setg(errp, "CXL host bridges present, but cxl=off");
366 return;
367 }
368 pxb_cxl_hook_up_registers(state, bus, errp);
369 }
370 }
371 }
372 }
373