1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name> 4 */ 5 6#include <dt-bindings/clock/spacemit,k1-syscon.h> 7 8/dts-v1/; 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 model = "SpacemiT K1"; 13 compatible = "spacemit,k1"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <24000000>; 19 20 cpu-map { 21 cluster0 { 22 core0 { 23 cpu = <&cpu_0>; 24 }; 25 core1 { 26 cpu = <&cpu_1>; 27 }; 28 core2 { 29 cpu = <&cpu_2>; 30 }; 31 core3 { 32 cpu = <&cpu_3>; 33 }; 34 }; 35 36 cluster1 { 37 core0 { 38 cpu = <&cpu_4>; 39 }; 40 core1 { 41 cpu = <&cpu_5>; 42 }; 43 core2 { 44 cpu = <&cpu_6>; 45 }; 46 core3 { 47 cpu = <&cpu_7>; 48 }; 49 }; 50 }; 51 52 cpu_0: cpu@0 { 53 compatible = "spacemit,x60", "riscv"; 54 device_type = "cpu"; 55 reg = <0>; 56 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 57 riscv,isa-base = "rv64i"; 58 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 59 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 60 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 61 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 62 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 63 riscv,cbom-block-size = <64>; 64 riscv,cbop-block-size = <64>; 65 riscv,cboz-block-size = <64>; 66 i-cache-block-size = <64>; 67 i-cache-size = <32768>; 68 i-cache-sets = <128>; 69 d-cache-block-size = <64>; 70 d-cache-size = <32768>; 71 d-cache-sets = <128>; 72 next-level-cache = <&cluster0_l2_cache>; 73 mmu-type = "riscv,sv39"; 74 75 cpu0_intc: interrupt-controller { 76 compatible = "riscv,cpu-intc"; 77 interrupt-controller; 78 #interrupt-cells = <1>; 79 }; 80 }; 81 82 cpu_1: cpu@1 { 83 compatible = "spacemit,x60", "riscv"; 84 device_type = "cpu"; 85 reg = <1>; 86 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 87 riscv,isa-base = "rv64i"; 88 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 89 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 90 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 91 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 92 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 93 riscv,cbom-block-size = <64>; 94 riscv,cbop-block-size = <64>; 95 riscv,cboz-block-size = <64>; 96 i-cache-block-size = <64>; 97 i-cache-size = <32768>; 98 i-cache-sets = <128>; 99 d-cache-block-size = <64>; 100 d-cache-size = <32768>; 101 d-cache-sets = <128>; 102 next-level-cache = <&cluster0_l2_cache>; 103 mmu-type = "riscv,sv39"; 104 105 cpu1_intc: interrupt-controller { 106 compatible = "riscv,cpu-intc"; 107 interrupt-controller; 108 #interrupt-cells = <1>; 109 }; 110 }; 111 112 cpu_2: cpu@2 { 113 compatible = "spacemit,x60", "riscv"; 114 device_type = "cpu"; 115 reg = <2>; 116 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 117 riscv,isa-base = "rv64i"; 118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 119 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 120 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 121 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 122 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 123 riscv,cbom-block-size = <64>; 124 riscv,cbop-block-size = <64>; 125 riscv,cboz-block-size = <64>; 126 i-cache-block-size = <64>; 127 i-cache-size = <32768>; 128 i-cache-sets = <128>; 129 d-cache-block-size = <64>; 130 d-cache-size = <32768>; 131 d-cache-sets = <128>; 132 next-level-cache = <&cluster0_l2_cache>; 133 mmu-type = "riscv,sv39"; 134 135 cpu2_intc: interrupt-controller { 136 compatible = "riscv,cpu-intc"; 137 interrupt-controller; 138 #interrupt-cells = <1>; 139 }; 140 }; 141 142 cpu_3: cpu@3 { 143 compatible = "spacemit,x60", "riscv"; 144 device_type = "cpu"; 145 reg = <3>; 146 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 147 riscv,isa-base = "rv64i"; 148 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 149 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 150 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 151 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 152 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 153 riscv,cbom-block-size = <64>; 154 riscv,cbop-block-size = <64>; 155 riscv,cboz-block-size = <64>; 156 i-cache-block-size = <64>; 157 i-cache-size = <32768>; 158 i-cache-sets = <128>; 159 d-cache-block-size = <64>; 160 d-cache-size = <32768>; 161 d-cache-sets = <128>; 162 next-level-cache = <&cluster0_l2_cache>; 163 mmu-type = "riscv,sv39"; 164 165 cpu3_intc: interrupt-controller { 166 compatible = "riscv,cpu-intc"; 167 interrupt-controller; 168 #interrupt-cells = <1>; 169 }; 170 }; 171 172 cpu_4: cpu@4 { 173 compatible = "spacemit,x60", "riscv"; 174 device_type = "cpu"; 175 reg = <4>; 176 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 177 riscv,isa-base = "rv64i"; 178 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 179 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 180 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 181 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 182 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 183 riscv,cbom-block-size = <64>; 184 riscv,cbop-block-size = <64>; 185 riscv,cboz-block-size = <64>; 186 i-cache-block-size = <64>; 187 i-cache-size = <32768>; 188 i-cache-sets = <128>; 189 d-cache-block-size = <64>; 190 d-cache-size = <32768>; 191 d-cache-sets = <128>; 192 next-level-cache = <&cluster1_l2_cache>; 193 mmu-type = "riscv,sv39"; 194 195 cpu4_intc: interrupt-controller { 196 compatible = "riscv,cpu-intc"; 197 interrupt-controller; 198 #interrupt-cells = <1>; 199 }; 200 }; 201 202 cpu_5: cpu@5 { 203 compatible = "spacemit,x60", "riscv"; 204 device_type = "cpu"; 205 reg = <5>; 206 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 207 riscv,isa-base = "rv64i"; 208 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 209 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 210 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 211 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 212 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 213 riscv,cbom-block-size = <64>; 214 riscv,cbop-block-size = <64>; 215 riscv,cboz-block-size = <64>; 216 i-cache-block-size = <64>; 217 i-cache-size = <32768>; 218 i-cache-sets = <128>; 219 d-cache-block-size = <64>; 220 d-cache-size = <32768>; 221 d-cache-sets = <128>; 222 next-level-cache = <&cluster1_l2_cache>; 223 mmu-type = "riscv,sv39"; 224 225 cpu5_intc: interrupt-controller { 226 compatible = "riscv,cpu-intc"; 227 interrupt-controller; 228 #interrupt-cells = <1>; 229 }; 230 }; 231 232 cpu_6: cpu@6 { 233 compatible = "spacemit,x60", "riscv"; 234 device_type = "cpu"; 235 reg = <6>; 236 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 237 riscv,isa-base = "rv64i"; 238 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 239 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 240 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 241 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 242 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 243 riscv,cbom-block-size = <64>; 244 riscv,cbop-block-size = <64>; 245 riscv,cboz-block-size = <64>; 246 i-cache-block-size = <64>; 247 i-cache-size = <32768>; 248 i-cache-sets = <128>; 249 d-cache-block-size = <64>; 250 d-cache-size = <32768>; 251 d-cache-sets = <128>; 252 next-level-cache = <&cluster1_l2_cache>; 253 mmu-type = "riscv,sv39"; 254 255 cpu6_intc: interrupt-controller { 256 compatible = "riscv,cpu-intc"; 257 interrupt-controller; 258 #interrupt-cells = <1>; 259 }; 260 }; 261 262 cpu_7: cpu@7 { 263 compatible = "spacemit,x60", "riscv"; 264 device_type = "cpu"; 265 reg = <7>; 266 riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; 267 riscv,isa-base = "rv64i"; 268 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", 269 "zicbop", "zicboz", "zicntr", "zicond", "zicsr", 270 "zifencei", "zihintpause", "zihpm", "zfh", "zba", 271 "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", 272 "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; 273 riscv,cbom-block-size = <64>; 274 riscv,cbop-block-size = <64>; 275 riscv,cboz-block-size = <64>; 276 i-cache-block-size = <64>; 277 i-cache-size = <32768>; 278 i-cache-sets = <128>; 279 d-cache-block-size = <64>; 280 d-cache-size = <32768>; 281 d-cache-sets = <128>; 282 next-level-cache = <&cluster1_l2_cache>; 283 mmu-type = "riscv,sv39"; 284 285 cpu7_intc: interrupt-controller { 286 compatible = "riscv,cpu-intc"; 287 interrupt-controller; 288 #interrupt-cells = <1>; 289 }; 290 }; 291 292 cluster0_l2_cache: l2-cache0 { 293 compatible = "cache"; 294 cache-block-size = <64>; 295 cache-level = <2>; 296 cache-size = <524288>; 297 cache-sets = <512>; 298 cache-unified; 299 }; 300 301 cluster1_l2_cache: l2-cache1 { 302 compatible = "cache"; 303 cache-block-size = <64>; 304 cache-level = <2>; 305 cache-size = <524288>; 306 cache-sets = <512>; 307 cache-unified; 308 }; 309 }; 310 311 clocks { 312 vctcxo_1m: clock-1m { 313 compatible = "fixed-clock"; 314 clock-frequency = <1000000>; 315 clock-output-names = "vctcxo_1m"; 316 #clock-cells = <0>; 317 }; 318 319 vctcxo_24m: clock-24m { 320 compatible = "fixed-clock"; 321 clock-frequency = <24000000>; 322 clock-output-names = "vctcxo_24m"; 323 #clock-cells = <0>; 324 }; 325 326 vctcxo_3m: clock-3m { 327 compatible = "fixed-clock"; 328 clock-frequency = <3000000>; 329 clock-output-names = "vctcxo_3m"; 330 #clock-cells = <0>; 331 }; 332 333 osc_32k: clock-32k { 334 compatible = "fixed-clock"; 335 clock-frequency = <32000>; 336 clock-output-names = "osc_32k"; 337 #clock-cells = <0>; 338 }; 339 }; 340 341 soc { 342 compatible = "simple-bus"; 343 interrupt-parent = <&plic>; 344 #address-cells = <2>; 345 #size-cells = <2>; 346 dma-noncoherent; 347 ranges; 348 349 syscon_rcpu: system-controller@c0880000 { 350 compatible = "spacemit,k1-syscon-rcpu"; 351 reg = <0x0 0xc0880000 0x0 0x2048>; 352 #reset-cells = <1>; 353 }; 354 355 syscon_rcpu2: system-controller@c0888000 { 356 compatible = "spacemit,k1-syscon-rcpu2"; 357 reg = <0x0 0xc0888000 0x0 0x28>; 358 #reset-cells = <1>; 359 }; 360 361 syscon_apbc: system-controller@d4015000 { 362 compatible = "spacemit,k1-syscon-apbc"; 363 reg = <0x0 0xd4015000 0x0 0x1000>; 364 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 365 <&vctcxo_24m>; 366 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 367 "vctcxo_24m"; 368 #clock-cells = <1>; 369 #reset-cells = <1>; 370 }; 371 372 gpio: gpio@d4019000 { 373 compatible = "spacemit,k1-gpio"; 374 reg = <0x0 0xd4019000 0x0 0x100>; 375 clocks = <&syscon_apbc CLK_GPIO>, 376 <&syscon_apbc CLK_GPIO_BUS>; 377 clock-names = "core", "bus"; 378 gpio-controller; 379 #gpio-cells = <3>; 380 interrupts = <58>; 381 interrupt-parent = <&plic>; 382 interrupt-controller; 383 #interrupt-cells = <3>; 384 gpio-ranges = <&pinctrl 0 0 0 32>, 385 <&pinctrl 1 0 32 32>, 386 <&pinctrl 2 0 64 32>, 387 <&pinctrl 3 0 96 32>; 388 }; 389 390 pwm0: pwm@d401a000 { 391 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 392 reg = <0x0 0xd401a000 0x0 0x10>; 393 #pwm-cells = <3>; 394 clocks = <&syscon_apbc CLK_PWM0>; 395 resets = <&syscon_apbc RESET_PWM0>; 396 status = "disabled"; 397 }; 398 399 pwm1: pwm@d401a400 { 400 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 401 reg = <0x0 0xd401a400 0x0 0x10>; 402 #pwm-cells = <3>; 403 clocks = <&syscon_apbc CLK_PWM1>; 404 resets = <&syscon_apbc RESET_PWM1>; 405 status = "disabled"; 406 }; 407 408 pwm2: pwm@d401a800 { 409 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 410 reg = <0x0 0xd401a800 0x0 0x10>; 411 #pwm-cells = <3>; 412 clocks = <&syscon_apbc CLK_PWM2>; 413 resets = <&syscon_apbc RESET_PWM2>; 414 status = "disabled"; 415 }; 416 417 pwm3: pwm@d401ac00 { 418 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 419 reg = <0x0 0xd401ac00 0x0 0x10>; 420 #pwm-cells = <3>; 421 clocks = <&syscon_apbc CLK_PWM3>; 422 resets = <&syscon_apbc RESET_PWM3>; 423 status = "disabled"; 424 }; 425 426 pwm4: pwm@d401b000 { 427 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 428 reg = <0x0 0xd401b000 0x0 0x10>; 429 #pwm-cells = <3>; 430 clocks = <&syscon_apbc CLK_PWM4>; 431 resets = <&syscon_apbc RESET_PWM4>; 432 status = "disabled"; 433 }; 434 435 pwm5: pwm@d401b400 { 436 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 437 reg = <0x0 0xd401b400 0x0 0x10>; 438 #pwm-cells = <3>; 439 clocks = <&syscon_apbc CLK_PWM5>; 440 resets = <&syscon_apbc RESET_PWM5>; 441 status = "disabled"; 442 }; 443 444 pwm6: pwm@d401b800 { 445 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 446 reg = <0x0 0xd401b800 0x0 0x10>; 447 #pwm-cells = <3>; 448 clocks = <&syscon_apbc CLK_PWM6>; 449 resets = <&syscon_apbc RESET_PWM6>; 450 status = "disabled"; 451 }; 452 453 pwm7: pwm@d401bc00 { 454 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 455 reg = <0x0 0xd401bc00 0x0 0x10>; 456 #pwm-cells = <3>; 457 clocks = <&syscon_apbc CLK_PWM7>; 458 resets = <&syscon_apbc RESET_PWM7>; 459 status = "disabled"; 460 }; 461 462 pinctrl: pinctrl@d401e000 { 463 compatible = "spacemit,k1-pinctrl"; 464 reg = <0x0 0xd401e000 0x0 0x400>; 465 clocks = <&syscon_apbc CLK_AIB>, 466 <&syscon_apbc CLK_AIB_BUS>; 467 clock-names = "func", "bus"; 468 }; 469 470 pwm8: pwm@d4020000 { 471 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 472 reg = <0x0 0xd4020000 0x0 0x10>; 473 #pwm-cells = <3>; 474 clocks = <&syscon_apbc CLK_PWM8>; 475 resets = <&syscon_apbc RESET_PWM8>; 476 status = "disabled"; 477 }; 478 479 pwm9: pwm@d4020400 { 480 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 481 reg = <0x0 0xd4020400 0x0 0x10>; 482 #pwm-cells = <3>; 483 clocks = <&syscon_apbc CLK_PWM9>; 484 resets = <&syscon_apbc RESET_PWM9>; 485 status = "disabled"; 486 }; 487 488 pwm10: pwm@d4020800 { 489 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 490 reg = <0x0 0xd4020800 0x0 0x10>; 491 #pwm-cells = <3>; 492 clocks = <&syscon_apbc CLK_PWM10>; 493 resets = <&syscon_apbc RESET_PWM10>; 494 status = "disabled"; 495 }; 496 497 pwm11: pwm@d4020c00 { 498 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 499 reg = <0x0 0xd4020c00 0x0 0x10>; 500 #pwm-cells = <3>; 501 clocks = <&syscon_apbc CLK_PWM11>; 502 resets = <&syscon_apbc RESET_PWM11>; 503 status = "disabled"; 504 }; 505 506 pwm12: pwm@d4021000 { 507 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 508 reg = <0x0 0xd4021000 0x0 0x10>; 509 #pwm-cells = <3>; 510 clocks = <&syscon_apbc CLK_PWM12>; 511 resets = <&syscon_apbc RESET_PWM12>; 512 status = "disabled"; 513 }; 514 515 pwm13: pwm@d4021400 { 516 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 517 reg = <0x0 0xd4021400 0x0 0x10>; 518 #pwm-cells = <3>; 519 clocks = <&syscon_apbc CLK_PWM13>; 520 resets = <&syscon_apbc RESET_PWM13>; 521 status = "disabled"; 522 }; 523 524 pwm14: pwm@d4021800 { 525 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 526 reg = <0x0 0xd4021800 0x0 0x10>; 527 #pwm-cells = <3>; 528 clocks = <&syscon_apbc CLK_PWM14>; 529 resets = <&syscon_apbc RESET_PWM14>; 530 status = "disabled"; 531 }; 532 533 pwm15: pwm@d4021c00 { 534 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 535 reg = <0x0 0xd4021c00 0x0 0x10>; 536 #pwm-cells = <3>; 537 clocks = <&syscon_apbc CLK_PWM15>; 538 resets = <&syscon_apbc RESET_PWM15>; 539 status = "disabled"; 540 }; 541 542 pwm16: pwm@d4022000 { 543 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 544 reg = <0x0 0xd4022000 0x0 0x10>; 545 #pwm-cells = <3>; 546 clocks = <&syscon_apbc CLK_PWM16>; 547 resets = <&syscon_apbc RESET_PWM16>; 548 status = "disabled"; 549 }; 550 551 pwm17: pwm@d4022400 { 552 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 553 reg = <0x0 0xd4022400 0x0 0x10>; 554 #pwm-cells = <3>; 555 clocks = <&syscon_apbc CLK_PWM17>; 556 resets = <&syscon_apbc RESET_PWM17>; 557 status = "disabled"; 558 }; 559 560 pwm18: pwm@d4022800 { 561 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 562 reg = <0x0 0xd4022800 0x0 0x10>; 563 #pwm-cells = <3>; 564 clocks = <&syscon_apbc CLK_PWM18>; 565 resets = <&syscon_apbc RESET_PWM18>; 566 status = "disabled"; 567 }; 568 569 pwm19: pwm@d4022c00 { 570 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm"; 571 reg = <0x0 0xd4022c00 0x0 0x10>; 572 #pwm-cells = <3>; 573 clocks = <&syscon_apbc CLK_PWM19>; 574 resets = <&syscon_apbc RESET_PWM19>; 575 status = "disabled"; 576 }; 577 578 syscon_mpmu: system-controller@d4050000 { 579 compatible = "spacemit,k1-syscon-mpmu"; 580 reg = <0x0 0xd4050000 0x0 0x209c>; 581 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 582 <&vctcxo_24m>; 583 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 584 "vctcxo_24m"; 585 #clock-cells = <1>; 586 #power-domain-cells = <1>; 587 #reset-cells = <1>; 588 }; 589 590 pll: clock-controller@d4090000 { 591 compatible = "spacemit,k1-pll"; 592 reg = <0x0 0xd4090000 0x0 0x1000>; 593 clocks = <&vctcxo_24m>; 594 spacemit,mpmu = <&syscon_mpmu>; 595 #clock-cells = <1>; 596 }; 597 598 syscon_apmu: system-controller@d4282800 { 599 compatible = "spacemit,k1-syscon-apmu"; 600 reg = <0x0 0xd4282800 0x0 0x400>; 601 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, 602 <&vctcxo_24m>; 603 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", 604 "vctcxo_24m"; 605 #clock-cells = <1>; 606 #power-domain-cells = <1>; 607 #reset-cells = <1>; 608 }; 609 610 plic: interrupt-controller@e0000000 { 611 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; 612 reg = <0x0 0xe0000000 0x0 0x4000000>; 613 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 614 <&cpu1_intc 11>, <&cpu1_intc 9>, 615 <&cpu2_intc 11>, <&cpu2_intc 9>, 616 <&cpu3_intc 11>, <&cpu3_intc 9>, 617 <&cpu4_intc 11>, <&cpu4_intc 9>, 618 <&cpu5_intc 11>, <&cpu5_intc 9>, 619 <&cpu6_intc 11>, <&cpu6_intc 9>, 620 <&cpu7_intc 11>, <&cpu7_intc 9>; 621 interrupt-controller; 622 #address-cells = <0>; 623 #interrupt-cells = <1>; 624 riscv,ndev = <159>; 625 }; 626 627 clint: timer@e4000000 { 628 compatible = "spacemit,k1-clint", "sifive,clint0"; 629 reg = <0x0 0xe4000000 0x0 0x10000>; 630 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 631 <&cpu1_intc 3>, <&cpu1_intc 7>, 632 <&cpu2_intc 3>, <&cpu2_intc 7>, 633 <&cpu3_intc 3>, <&cpu3_intc 7>, 634 <&cpu4_intc 3>, <&cpu4_intc 7>, 635 <&cpu5_intc 3>, <&cpu5_intc 7>, 636 <&cpu6_intc 3>, <&cpu6_intc 7>, 637 <&cpu7_intc 3>, <&cpu7_intc 7>; 638 }; 639 640 syscon_apbc2: system-controller@f0610000 { 641 compatible = "spacemit,k1-syscon-apbc2"; 642 reg = <0x0 0xf0610000 0x0 0x20>; 643 #reset-cells = <1>; 644 }; 645 646 camera-bus { 647 compatible = "simple-bus"; 648 ranges; 649 #address-cells = <2>; 650 #size-cells = <2>; 651 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 652 <0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>; 653 }; 654 655 dma-bus { 656 compatible = "simple-bus"; 657 ranges; 658 #address-cells = <2>; 659 #size-cells = <2>; 660 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 661 <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>; 662 663 uart0: serial@d4017000 { 664 compatible = "spacemit,k1-uart", 665 "intel,xscale-uart"; 666 reg = <0x0 0xd4017000 0x0 0x100>; 667 clocks = <&syscon_apbc CLK_UART0>, 668 <&syscon_apbc CLK_UART0_BUS>; 669 clock-names = "core", "bus"; 670 interrupts = <42>; 671 reg-shift = <2>; 672 reg-io-width = <4>; 673 status = "disabled"; 674 }; 675 676 uart2: serial@d4017100 { 677 compatible = "spacemit,k1-uart", 678 "intel,xscale-uart"; 679 reg = <0x0 0xd4017100 0x0 0x100>; 680 clocks = <&syscon_apbc CLK_UART2>, 681 <&syscon_apbc CLK_UART2_BUS>; 682 clock-names = "core", "bus"; 683 interrupts = <44>; 684 reg-shift = <2>; 685 reg-io-width = <4>; 686 status = "disabled"; 687 }; 688 689 uart3: serial@d4017200 { 690 compatible = "spacemit,k1-uart", 691 "intel,xscale-uart"; 692 reg = <0x0 0xd4017200 0x0 0x100>; 693 clocks = <&syscon_apbc CLK_UART3>, 694 <&syscon_apbc CLK_UART3_BUS>; 695 clock-names = "core", "bus"; 696 interrupts = <45>; 697 reg-shift = <2>; 698 reg-io-width = <4>; 699 status = "disabled"; 700 }; 701 702 uart4: serial@d4017300 { 703 compatible = "spacemit,k1-uart", 704 "intel,xscale-uart"; 705 reg = <0x0 0xd4017300 0x0 0x100>; 706 clocks = <&syscon_apbc CLK_UART4>, 707 <&syscon_apbc CLK_UART4_BUS>; 708 clock-names = "core", "bus"; 709 interrupts = <46>; 710 reg-shift = <2>; 711 reg-io-width = <4>; 712 status = "disabled"; 713 }; 714 715 uart5: serial@d4017400 { 716 compatible = "spacemit,k1-uart", 717 "intel,xscale-uart"; 718 reg = <0x0 0xd4017400 0x0 0x100>; 719 clocks = <&syscon_apbc CLK_UART5>, 720 <&syscon_apbc CLK_UART5_BUS>; 721 clock-names = "core", "bus"; 722 interrupts = <47>; 723 reg-shift = <2>; 724 reg-io-width = <4>; 725 status = "disabled"; 726 }; 727 728 uart6: serial@d4017500 { 729 compatible = "spacemit,k1-uart", 730 "intel,xscale-uart"; 731 reg = <0x0 0xd4017500 0x0 0x100>; 732 clocks = <&syscon_apbc CLK_UART6>, 733 <&syscon_apbc CLK_UART6_BUS>; 734 clock-names = "core", "bus"; 735 interrupts = <48>; 736 reg-shift = <2>; 737 reg-io-width = <4>; 738 status = "disabled"; 739 }; 740 741 uart7: serial@d4017600 { 742 compatible = "spacemit,k1-uart", 743 "intel,xscale-uart"; 744 reg = <0x0 0xd4017600 0x0 0x100>; 745 clocks = <&syscon_apbc CLK_UART7>, 746 <&syscon_apbc CLK_UART7_BUS>; 747 clock-names = "core", "bus"; 748 interrupts = <49>; 749 reg-shift = <2>; 750 reg-io-width = <4>; 751 status = "disabled"; 752 }; 753 754 uart8: serial@d4017700 { 755 compatible = "spacemit,k1-uart", 756 "intel,xscale-uart"; 757 reg = <0x0 0xd4017700 0x0 0x100>; 758 clocks = <&syscon_apbc CLK_UART8>, 759 <&syscon_apbc CLK_UART8_BUS>; 760 clock-names = "core", "bus"; 761 interrupts = <50>; 762 reg-shift = <2>; 763 reg-io-width = <4>; 764 status = "disabled"; 765 }; 766 767 uart9: serial@d4017800 { 768 compatible = "spacemit,k1-uart", 769 "intel,xscale-uart"; 770 reg = <0x0 0xd4017800 0x0 0x100>; 771 clocks = <&syscon_apbc CLK_UART9>, 772 <&syscon_apbc CLK_UART9_BUS>; 773 clock-names = "core", "bus"; 774 interrupts = <51>; 775 reg-shift = <2>; 776 reg-io-width = <4>; 777 status = "disabled"; 778 }; 779 780 sec_uart1: serial@f0612000 { 781 compatible = "spacemit,k1-uart", 782 "intel,xscale-uart"; 783 reg = <0x0 0xf0612000 0x0 0x100>; 784 interrupts = <43>; 785 clock-frequency = <14857000>; 786 reg-shift = <2>; 787 reg-io-width = <4>; 788 status = "reserved"; /* for TEE usage */ 789 }; 790 }; 791 792 multimedia-bus { 793 compatible = "simple-bus"; 794 ranges; 795 #address-cells = <2>; 796 #size-cells = <2>; 797 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 798 <0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>; 799 }; 800 801 network-bus { 802 compatible = "simple-bus"; 803 ranges; 804 #address-cells = <2>; 805 #size-cells = <2>; 806 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 807 <0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>; 808 }; 809 810 pcie-bus { 811 compatible = "simple-bus"; 812 ranges; 813 #address-cells = <2>; 814 #size-cells = <2>; 815 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, 816 <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; 817 }; 818 819 storage-bus { 820 compatible = "simple-bus"; 821 ranges; 822 #address-cells = <2>; 823 #size-cells = <2>; 824 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; 825 826 emmc: mmc@d4281000 { 827 compatible = "spacemit,k1-sdhci"; 828 reg = <0x0 0xd4281000 0x0 0x200>; 829 clocks = <&syscon_apmu CLK_SDH_AXI>, 830 <&syscon_apmu CLK_SDH2>; 831 clock-names = "core", "io"; 832 interrupts = <101>; 833 status = "disabled"; 834 }; 835 }; 836 }; 837}; 838