1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45 #include "pm80xx_tracepoints.h"
46
47 #define SMP_DIRECT 1
48 #define SMP_INDIRECT 2
49
50
pm80xx_bar4_shift(struct pm8001_hba_info * pm8001_ha,u32 shift_value)51 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
52 {
53 u32 reg_val;
54 unsigned long start;
55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
56 /* confirm the setting is written */
57 start = jiffies + HZ; /* 1 sec */
58 do {
59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
60 } while ((reg_val != shift_value) && time_before(jiffies, start));
61 if (reg_val != shift_value) {
62 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
63 reg_val);
64 return -1;
65 }
66 return 0;
67 }
68
pm80xx_pci_mem_copy(struct pm8001_hba_info * pm8001_ha,u32 soffset,__le32 * destination,u32 dw_count,u32 bus_base_number)69 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 __le32 *destination,
71 u32 dw_count, u32 bus_base_number)
72 {
73 u32 index, value, offset;
74
75 for (index = 0; index < dw_count; index += 4, destination++) {
76 offset = (soffset + index);
77 if (offset < (64 * 1024)) {
78 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
79 *destination = cpu_to_le32(value);
80 }
81 }
82 return;
83 }
84
pm80xx_get_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)85 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
86 struct device_attribute *attr, char *buf)
87 {
88 struct Scsi_Host *shost = class_to_shost(cdev);
89 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
90 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
91 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
92 u32 accum_len, reg_val, index, *temp;
93 u32 status = 1;
94 unsigned long start;
95 u8 *direct_data;
96 char *fatal_error_data = buf;
97 u32 length_to_read;
98 u32 offset;
99
100 pm8001_ha->forensic_info.data_buf.direct_data = buf;
101 if (pm8001_ha->chip_id == chip_8001) {
102 pm8001_ha->forensic_info.data_buf.direct_data +=
103 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
104 "Not supported for SPC controller");
105 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
106 (char *)buf;
107 }
108 /* initialize variables for very first call from host application */
109 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
110 pm8001_dbg(pm8001_ha, IO,
111 "forensic_info TYPE_NON_FATAL..............\n");
112 direct_data = (u8 *)fatal_error_data;
113 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
114 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
115 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
116 pm8001_ha->forensic_info.data_buf.read_len = 0;
117 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
118
119 /* Write signature to fatal dump table */
120 pm8001_mw32(fatal_table_address,
121 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
122
123 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
124 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
126 pm8001_ha->forensic_info.data_buf.read_len);
127 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
128 pm8001_ha->forensic_info.data_buf.direct_len);
129 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
130 pm8001_ha->forensic_info.data_buf.direct_offset);
131 }
132 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
133 /* start to get data */
134 /* Program the MEMBASE II Shifting Register with 0x00.*/
135 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
136 pm8001_ha->fatal_forensic_shift_offset);
137 pm8001_ha->forensic_last_offset = 0;
138 pm8001_ha->forensic_fatal_step = 0;
139 pm8001_ha->fatal_bar_loc = 0;
140 }
141
142 /* Read until accum_len is retrieved */
143 accum_len = pm8001_mr32(fatal_table_address,
144 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
145 /* Determine length of data between previously stored transfer length
146 * and current accumulated transfer length
147 */
148 length_to_read =
149 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
150 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
151 accum_len);
152 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
153 length_to_read);
154 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
155 pm8001_ha->forensic_last_offset);
156 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
157 pm8001_ha->forensic_info.data_buf.read_len);
158 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
159 pm8001_ha->forensic_info.data_buf.direct_len);
160 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
161 pm8001_ha->forensic_info.data_buf.direct_offset);
162
163 /* If accumulated length failed to read correctly fail the attempt.*/
164 if (accum_len == 0xFFFFFFFF) {
165 pm8001_dbg(pm8001_ha, IO,
166 "Possible PCI issue 0x%x not expected\n",
167 accum_len);
168 return status;
169 }
170 /* If accumulated length is zero fail the attempt */
171 if (accum_len == 0) {
172 pm8001_ha->forensic_info.data_buf.direct_data +=
173 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
174 "%08x ", 0xFFFFFFFF);
175 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
176 (char *)buf;
177 }
178 /* Accumulated length is good so start capturing the first data */
179 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
180 if (pm8001_ha->forensic_fatal_step == 0) {
181 moreData:
182 /* If data to read is less than SYSFS_OFFSET then reduce the
183 * length of dataLen
184 */
185 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
186 > length_to_read) {
187 pm8001_ha->forensic_info.data_buf.direct_len =
188 length_to_read -
189 pm8001_ha->forensic_last_offset;
190 } else {
191 pm8001_ha->forensic_info.data_buf.direct_len =
192 SYSFS_OFFSET;
193 }
194 if (pm8001_ha->forensic_info.data_buf.direct_data) {
195 /* Data is in bar, copy to host memory */
196 pm80xx_pci_mem_copy(pm8001_ha,
197 pm8001_ha->fatal_bar_loc,
198 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
199 pm8001_ha->forensic_info.data_buf.direct_len, 1);
200 }
201 pm8001_ha->fatal_bar_loc +=
202 pm8001_ha->forensic_info.data_buf.direct_len;
203 pm8001_ha->forensic_info.data_buf.direct_offset +=
204 pm8001_ha->forensic_info.data_buf.direct_len;
205 pm8001_ha->forensic_last_offset +=
206 pm8001_ha->forensic_info.data_buf.direct_len;
207 pm8001_ha->forensic_info.data_buf.read_len =
208 pm8001_ha->forensic_info.data_buf.direct_len;
209
210 if (pm8001_ha->forensic_last_offset >= length_to_read) {
211 pm8001_ha->forensic_info.data_buf.direct_data +=
212 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
213 "%08x ", 3);
214 for (index = 0; index <
215 (pm8001_ha->forensic_info.data_buf.direct_len
216 / 4); index++) {
217 pm8001_ha->forensic_info.data_buf.direct_data +=
218 sprintf(
219 pm8001_ha->forensic_info.data_buf.direct_data,
220 "%08x ", *(temp + index));
221 }
222
223 pm8001_ha->fatal_bar_loc = 0;
224 pm8001_ha->forensic_fatal_step = 1;
225 pm8001_ha->fatal_forensic_shift_offset = 0;
226 pm8001_ha->forensic_last_offset = 0;
227 status = 0;
228 offset = (int)
229 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
230 - (char *)buf);
231 pm8001_dbg(pm8001_ha, IO,
232 "get_fatal_spcv:return1 0x%x\n", offset);
233 return (char *)pm8001_ha->
234 forensic_info.data_buf.direct_data -
235 (char *)buf;
236 }
237 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
238 pm8001_ha->forensic_info.data_buf.direct_data +=
239 sprintf(pm8001_ha->
240 forensic_info.data_buf.direct_data,
241 "%08x ", 2);
242 for (index = 0; index <
243 (pm8001_ha->forensic_info.data_buf.direct_len
244 / 4); index++) {
245 pm8001_ha->forensic_info.data_buf.direct_data
246 += sprintf(pm8001_ha->
247 forensic_info.data_buf.direct_data,
248 "%08x ", *(temp + index));
249 }
250 status = 0;
251 offset = (int)
252 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
253 - (char *)buf);
254 pm8001_dbg(pm8001_ha, IO,
255 "get_fatal_spcv:return2 0x%x\n", offset);
256 return (char *)pm8001_ha->
257 forensic_info.data_buf.direct_data -
258 (char *)buf;
259 }
260
261 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
262 pm8001_ha->forensic_info.data_buf.direct_data +=
263 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
264 "%08x ", 2);
265 for (index = 0; index <
266 (pm8001_ha->forensic_info.data_buf.direct_len
267 / 4) ; index++) {
268 pm8001_ha->forensic_info.data_buf.direct_data +=
269 sprintf(pm8001_ha->
270 forensic_info.data_buf.direct_data,
271 "%08x ", *(temp + index));
272 }
273 pm8001_ha->fatal_forensic_shift_offset += 0x100;
274 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
275 pm8001_ha->fatal_forensic_shift_offset);
276 pm8001_ha->fatal_bar_loc = 0;
277 status = 0;
278 offset = (int)
279 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
280 - (char *)buf);
281 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
282 offset);
283 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
284 (char *)buf;
285 }
286 if (pm8001_ha->forensic_fatal_step == 1) {
287 /* store previous accumulated length before triggering next
288 * accumulated length update
289 */
290 pm8001_ha->forensic_preserved_accumulated_transfer =
291 pm8001_mr32(fatal_table_address,
292 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
293
294 /* continue capturing the fatal log until Dump status is 0x3 */
295 if (pm8001_mr32(fatal_table_address,
296 MPI_FATAL_EDUMP_TABLE_STATUS) <
297 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
298
299 /* reset fddstat bit by writing to zero*/
300 pm8001_mw32(fatal_table_address,
301 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
302
303 /* set dump control value to '1' so that new data will
304 * be transferred to shared memory
305 */
306 pm8001_mw32(fatal_table_address,
307 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
308 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
309
310 /*Poll FDDHSHK until clear */
311 start = jiffies + (2 * HZ); /* 2 sec */
312
313 do {
314 reg_val = pm8001_mr32(fatal_table_address,
315 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
316 } while ((reg_val) && time_before(jiffies, start));
317
318 if (reg_val != 0) {
319 pm8001_dbg(pm8001_ha, FAIL,
320 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
321 reg_val);
322 /* Fail the dump if a timeout occurs */
323 pm8001_ha->forensic_info.data_buf.direct_data +=
324 sprintf(
325 pm8001_ha->forensic_info.data_buf.direct_data,
326 "%08x ", 0xFFFFFFFF);
327 return((char *)
328 pm8001_ha->forensic_info.data_buf.direct_data
329 - (char *)buf);
330 }
331 /* Poll status register until set to 2 or
332 * 3 for up to 2 seconds
333 */
334 start = jiffies + (2 * HZ); /* 2 sec */
335
336 do {
337 reg_val = pm8001_mr32(fatal_table_address,
338 MPI_FATAL_EDUMP_TABLE_STATUS);
339 } while (((reg_val != 2) && (reg_val != 3)) &&
340 time_before(jiffies, start));
341
342 if (reg_val < 2) {
343 pm8001_dbg(pm8001_ha, FAIL,
344 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
345 reg_val);
346 /* Fail the dump if a timeout occurs */
347 pm8001_ha->forensic_info.data_buf.direct_data +=
348 sprintf(
349 pm8001_ha->forensic_info.data_buf.direct_data,
350 "%08x ", 0xFFFFFFFF);
351 return((char *)pm8001_ha->forensic_info.data_buf.direct_data -
352 (char *)buf);
353 }
354 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */
355 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */
356 pm8001_cw32(pm8001_ha, 0,
357 MEMBASE_II_SHIFT_REGISTER,
358 pm8001_ha->fatal_forensic_shift_offset);
359 }
360 /* Read the next block of the debug data.*/
361 length_to_read = pm8001_mr32(fatal_table_address,
362 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
363 pm8001_ha->forensic_preserved_accumulated_transfer;
364 if (length_to_read != 0x0) {
365 pm8001_ha->forensic_fatal_step = 0;
366 goto moreData;
367 } else {
368 pm8001_ha->forensic_info.data_buf.direct_data +=
369 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
370 "%08x ", 4);
371 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
372 pm8001_ha->forensic_info.data_buf.direct_len = 0;
373 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
374 pm8001_ha->forensic_info.data_buf.read_len = 0;
375 }
376 }
377 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
378 - (char *)buf);
379 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
380 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -
381 (char *)buf);
382 }
383
384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
385 * location by the firmware.
386 */
pm80xx_get_non_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)387 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
388 struct device_attribute *attr, char *buf)
389 {
390 struct Scsi_Host *shost = class_to_shost(cdev);
391 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
392 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
393 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
394 u32 accum_len = 0;
395 u32 total_len = 0;
396 u32 reg_val = 0;
397 u32 *temp = NULL;
398 u32 index = 0;
399 u32 output_length;
400 unsigned long start = 0;
401 char *buf_copy = buf;
402
403 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
404 if (++pm8001_ha->non_fatal_count == 1) {
405 if (pm8001_ha->chip_id == chip_8001) {
406 snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
407 PAGE_SIZE, "Not supported for SPC controller");
408 return 0;
409 }
410 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
411 /*
412 * Step 1: Write the host buffer parameters in the MPI Fatal and
413 * Non-Fatal Error Dump Capture Table.This is the buffer
414 * where debug data will be DMAed to.
415 */
416 pm8001_mw32(nonfatal_table_address,
417 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
418 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
419
420 pm8001_mw32(nonfatal_table_address,
421 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
422 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
423
424 pm8001_mw32(nonfatal_table_address,
425 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
426
427 /* Optionally, set the DUMPCTRL bit to 1 if the host
428 * keeps sending active I/Os while capturing the non-fatal
429 * debug data. Otherwise, leave this bit set to zero
430 */
431 pm8001_mw32(nonfatal_table_address,
432 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
433
434 /*
435 * Step 2: Clear Accumulative Length of Debug Data Transferred
436 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
437 * Capture Table to zero.
438 */
439 pm8001_mw32(nonfatal_table_address,
440 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
441
442 /* initiallize previous accumulated length to 0 */
443 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
444 pm8001_ha->non_fatal_read_length = 0;
445 }
446
447 total_len = pm8001_mr32(nonfatal_table_address,
448 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
449 /*
450 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
451 * field and then request that the SPCv controller transfer the debug
452 * data by setting bit 7 of the Inbound Doorbell Set Register.
453 */
454 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
455 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
456 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
457
458 /*
459 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
460 * 2 seconds) until register bit 7 is cleared.
461 * This step only indicates the request is accepted by the controller.
462 */
463 start = jiffies + (2 * HZ); /* 2 sec */
464 do {
465 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
466 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
467 } while ((reg_val != 0) && time_before(jiffies, start));
468
469 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
470 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
471 * the MPI Fatal and Non-Fatal Error Dump Capture Table.
472 */
473 start = jiffies + (2 * HZ); /* 2 sec */
474 do {
475 reg_val = pm8001_mr32(nonfatal_table_address,
476 MPI_FATAL_EDUMP_TABLE_STATUS);
477 } while ((!reg_val) && time_before(jiffies, start));
478
479 if ((reg_val == 0x00) ||
480 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
481 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
482 pm8001_ha->non_fatal_read_length = 0;
483 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
484 pm8001_ha->non_fatal_count = 0;
485 return (buf_copy - buf);
486 } else if (reg_val ==
487 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
488 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
489 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
490 (pm8001_ha->non_fatal_read_length >= total_len)) {
491 pm8001_ha->non_fatal_read_length = 0;
492 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
493 pm8001_ha->non_fatal_count = 0;
494 }
495 accum_len = pm8001_mr32(nonfatal_table_address,
496 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
497 output_length = accum_len -
498 pm8001_ha->forensic_preserved_accumulated_transfer;
499
500 for (index = 0; index < output_length/4; index++)
501 buf_copy += snprintf(buf_copy, PAGE_SIZE,
502 "%08x ", *(temp+index));
503
504 pm8001_ha->non_fatal_read_length += output_length;
505
506 /* store current accumulated length to use in next iteration as
507 * the previous accumulated length
508 */
509 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
510 return (buf_copy - buf);
511 }
512
513 /**
514 * read_main_config_table - read the configure table and save it.
515 * @pm8001_ha: our hba card information
516 */
read_main_config_table(struct pm8001_hba_info * pm8001_ha)517 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
518 {
519 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
520
521 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
522 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
523 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
524 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
525 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
526 pm8001_mr32(address, MAIN_FW_REVISION);
527 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
528 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
529 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
530 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
531 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
532 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
533 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
534 pm8001_mr32(address, MAIN_GST_OFFSET);
535 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
536 pm8001_mr32(address, MAIN_IBQ_OFFSET);
537 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
538 pm8001_mr32(address, MAIN_OBQ_OFFSET);
539
540 /* read Error Dump Offset and Length */
541 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
542 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
543 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
544 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
545 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
546 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
547 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
548 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
549
550 /* read GPIO LED settings from the configuration table */
551 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
552 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
553
554 /* read analog Setting offset from the configuration table */
555 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
556 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
557
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
559 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
561 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
562 /* read port recover and reset timeout */
563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
564 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
565 /* read ILA and inactive firmware version */
566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
567 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
569 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
570
571 pm8001_dbg(pm8001_ha, INIT,
572 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
576
577 pm8001_dbg(pm8001_ha, INIT,
578 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
584
585 pm8001_dbg(pm8001_ha, INIT,
586 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
589 }
590
591 /**
592 * read_general_status_table - read the general status table and save it.
593 * @pm8001_ha: our hba card information
594 */
read_general_status_table(struct pm8001_hba_info * pm8001_ha)595 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
596 {
597 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
598 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
599 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
600 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
601 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
602 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
603 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
604 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
605 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
606 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
607 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
608 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
609 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
610 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
611 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
612 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
613 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
614 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
615 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
616 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
617 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
618 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
619 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
620 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
621 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
622 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
623 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
624 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
625 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
626 }
627 /**
628 * read_phy_attr_table - read the phy attribute table and save it.
629 * @pm8001_ha: our hba card information
630 */
read_phy_attr_table(struct pm8001_hba_info * pm8001_ha)631 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
632 {
633 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
634 pm8001_ha->phy_attr_table.phystart1_16[0] =
635 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
636 pm8001_ha->phy_attr_table.phystart1_16[1] =
637 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
638 pm8001_ha->phy_attr_table.phystart1_16[2] =
639 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
640 pm8001_ha->phy_attr_table.phystart1_16[3] =
641 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
642 pm8001_ha->phy_attr_table.phystart1_16[4] =
643 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
644 pm8001_ha->phy_attr_table.phystart1_16[5] =
645 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
646 pm8001_ha->phy_attr_table.phystart1_16[6] =
647 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
648 pm8001_ha->phy_attr_table.phystart1_16[7] =
649 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
650 pm8001_ha->phy_attr_table.phystart1_16[8] =
651 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
652 pm8001_ha->phy_attr_table.phystart1_16[9] =
653 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
654 pm8001_ha->phy_attr_table.phystart1_16[10] =
655 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
656 pm8001_ha->phy_attr_table.phystart1_16[11] =
657 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
658 pm8001_ha->phy_attr_table.phystart1_16[12] =
659 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
660 pm8001_ha->phy_attr_table.phystart1_16[13] =
661 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
662 pm8001_ha->phy_attr_table.phystart1_16[14] =
663 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
664 pm8001_ha->phy_attr_table.phystart1_16[15] =
665 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
666
667 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
668 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
669 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
670 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
671 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
672 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
673 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
674 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
675 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
676 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
677 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
678 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
679 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
680 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
681 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
682 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
683 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
684 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
685 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
686 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
687 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
688 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
689 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
690 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
691 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
692 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
693 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
694 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
695 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
696 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
697 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
698 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
699
700 }
701
702 /**
703 * read_inbnd_queue_table - read the inbound queue table and save it.
704 * @pm8001_ha: our hba card information
705 */
read_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha)706 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
707 {
708 int i;
709 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
710 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
711 u32 offset = i * 0x20;
712 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
713 get_pci_bar_index(pm8001_mr32(address,
714 (offset + IB_PIPCI_BAR)));
715 pm8001_ha->inbnd_q_tbl[i].pi_offset =
716 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
717 }
718 }
719
720 /**
721 * read_outbnd_queue_table - read the outbound queue table and save it.
722 * @pm8001_ha: our hba card information
723 */
read_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha)724 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
725 {
726 int i;
727 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
728 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
729 u32 offset = i * 0x24;
730 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
731 get_pci_bar_index(pm8001_mr32(address,
732 (offset + OB_CIPCI_BAR)));
733 pm8001_ha->outbnd_q_tbl[i].ci_offset =
734 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
735 }
736 }
737
738 /**
739 * init_default_table_values - init the default table.
740 * @pm8001_ha: our hba card information
741 */
init_default_table_values(struct pm8001_hba_info * pm8001_ha)742 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
743 {
744 int i;
745 u32 offsetib, offsetob;
746 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
747 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
748 u32 ib_offset = pm8001_ha->ib_offset;
749 u32 ob_offset = pm8001_ha->ob_offset;
750 u32 ci_offset = pm8001_ha->ci_offset;
751 u32 pi_offset = pm8001_ha->pi_offset;
752
753 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
754 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
756 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
758 PM8001_EVENT_LOG_SIZE;
759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
761 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
763 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
765 PM8001_EVENT_LOG_SIZE;
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity =
767 pcs_event_log_severity;
768 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
769
770 /* Enable higher IQs and OQs, 32 to 63, bit 16 */
771 if (pm8001_ha->max_q_num > 32)
772 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
773 1 << 16;
774 /* Disable end to end CRC checking */
775 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
776
777 for (i = 0; i < pm8001_ha->max_q_num; i++) {
778 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
779 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
780 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
781 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
782 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
783 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
784 pm8001_ha->inbnd_q_tbl[i].base_virt =
785 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
786 pm8001_ha->inbnd_q_tbl[i].total_length =
787 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
788 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
789 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
790 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
791 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
792 pm8001_ha->inbnd_q_tbl[i].ci_virt =
793 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
794 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
795 offsetib = i * 0x20;
796 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
797 get_pci_bar_index(pm8001_mr32(addressib,
798 (offsetib + 0x14)));
799 pm8001_ha->inbnd_q_tbl[i].pi_offset =
800 pm8001_mr32(addressib, (offsetib + 0x18));
801 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
802 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
803
804 pm8001_dbg(pm8001_ha, DEV,
805 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
806 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
807 pm8001_ha->inbnd_q_tbl[i].pi_offset);
808 }
809 for (i = 0; i < pm8001_ha->max_q_num; i++) {
810 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
811 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
812 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
813 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
814 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
815 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
816 pm8001_ha->outbnd_q_tbl[i].base_virt =
817 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
818 pm8001_ha->outbnd_q_tbl[i].total_length =
819 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
820 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
821 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
822 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
823 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
824 /* interrupt vector based on oq */
825 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
826 pm8001_ha->outbnd_q_tbl[i].pi_virt =
827 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
828 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
829 offsetob = i * 0x24;
830 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
831 get_pci_bar_index(pm8001_mr32(addressob,
832 offsetob + 0x14));
833 pm8001_ha->outbnd_q_tbl[i].ci_offset =
834 pm8001_mr32(addressob, (offsetob + 0x18));
835 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
836 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
837
838 pm8001_dbg(pm8001_ha, DEV,
839 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
840 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
841 pm8001_ha->outbnd_q_tbl[i].ci_offset);
842 }
843 }
844
845 /**
846 * update_main_config_table - update the main default table to the HBA.
847 * @pm8001_ha: our hba card information
848 */
update_main_config_table(struct pm8001_hba_info * pm8001_ha)849 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
850 {
851 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
852 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
854 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
856 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
858 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
860 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
864 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
866 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
868 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
869 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
870 /* Update Fatal error interrupt vector */
871 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
872 ((pm8001_ha->max_q_num - 1) << 8);
873 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
874 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
875 pm8001_dbg(pm8001_ha, DEV,
876 "Updated Fatal error interrupt vector 0x%x\n",
877 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
878
879 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
880 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
881
882 /* SPCv specific */
883 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
884 /* Set GPIOLED to 0x2 for LED indicator */
885 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
886 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
887 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
888 pm8001_dbg(pm8001_ha, DEV,
889 "Programming DW 0x21 in main cfg table with 0x%x\n",
890 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
891
892 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
893 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
894 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
896
897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
898 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
899 PORT_RECOVERY_TIMEOUT;
900 if (pm8001_ha->chip_id == chip_8006) {
901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
902 0x0000ffff;
903 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
904 CHIP_8006_PORT_RECOVERY_TIMEOUT;
905 }
906 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
907 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
908 }
909
910 /**
911 * update_inbnd_queue_table - update the inbound queue table to the HBA.
912 * @pm8001_ha: our hba card information
913 * @number: entry in the queue
914 */
update_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)915 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
916 int number)
917 {
918 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
919 u16 offset = number * 0x20;
920 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
921 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
922 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
923 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
924 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
925 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
926 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
927 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
928 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
929 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
930
931 pm8001_dbg(pm8001_ha, DEV,
932 "IQ %d: Element pri size 0x%x\n",
933 number,
934 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
935
936 pm8001_dbg(pm8001_ha, DEV,
937 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
938 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
939 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
940
941 pm8001_dbg(pm8001_ha, DEV,
942 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
943 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
944 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
945 }
946
947 /**
948 * update_outbnd_queue_table - update the outbound queue table to the HBA.
949 * @pm8001_ha: our hba card information
950 * @number: entry in the queue
951 */
update_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)952 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
953 int number)
954 {
955 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
956 u16 offset = number * 0x24;
957 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
958 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
959 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
960 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
961 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
962 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
963 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
964 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
965 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
966 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
967 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
968 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
969
970 pm8001_dbg(pm8001_ha, DEV,
971 "OQ %d: Element pri size 0x%x\n",
972 number,
973 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
974
975 pm8001_dbg(pm8001_ha, DEV,
976 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
977 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
978 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
979
980 pm8001_dbg(pm8001_ha, DEV,
981 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
982 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
983 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
984 }
985
986 /**
987 * mpi_init_check - check firmware initialization status.
988 * @pm8001_ha: our hba card information
989 */
mpi_init_check(struct pm8001_hba_info * pm8001_ha)990 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
991 {
992 u32 max_wait_count;
993 u32 value;
994 u32 gst_len_mpistate;
995
996 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
997 table is updated */
998 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
999 /* wait until Inbound DoorBell Clear Register toggled */
1000 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1001 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1002 } else {
1003 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1004 }
1005 do {
1006 msleep(FW_READY_INTERVAL);
1007 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1008 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1009 } while ((value != 0) && (--max_wait_count));
1010
1011 if (!max_wait_count) {
1012 /* additional check */
1013 pm8001_dbg(pm8001_ha, FAIL,
1014 "Inb doorbell clear not toggled[value:%x]\n",
1015 value);
1016 return -EBUSY;
1017 }
1018 /* check the MPI-State for initialization up to 100ms*/
1019 max_wait_count = 5;/* 100 msec */
1020 do {
1021 msleep(FW_READY_INTERVAL);
1022 gst_len_mpistate =
1023 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1024 GST_GSTLEN_MPIS_OFFSET);
1025 } while ((GST_MPI_STATE_INIT !=
1026 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1027 if (!max_wait_count)
1028 return -EBUSY;
1029
1030 /* check MPI Initialization error */
1031 gst_len_mpistate = gst_len_mpistate >> 16;
1032 if (0x0000 != gst_len_mpistate)
1033 return -EBUSY;
1034
1035 /*
1036 * As per controller datasheet, after successful MPI
1037 * initialization minimum 500ms delay is required before
1038 * issuing commands.
1039 */
1040 msleep(500);
1041
1042 return 0;
1043 }
1044
1045 /**
1046 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1047 * This function sleeps hence it must not be used in atomic context.
1048 * @pm8001_ha: our hba card information
1049 */
check_fw_ready(struct pm8001_hba_info * pm8001_ha)1050 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1051 {
1052 u32 value;
1053 u32 max_wait_count;
1054 u32 max_wait_time;
1055 u32 expected_mask;
1056 int ret = 0;
1057
1058 /* reset / PCIe ready */
1059 max_wait_time = max_wait_count = 5; /* 100 milli sec */
1060 do {
1061 msleep(FW_READY_INTERVAL);
1062 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1063 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1064
1065 /* check ila, RAAE and iops status */
1066 if ((pm8001_ha->chip_id != chip_8008) &&
1067 (pm8001_ha->chip_id != chip_8009)) {
1068 max_wait_time = max_wait_count = 180; /* 3600 milli sec */
1069 expected_mask = SCRATCH_PAD_ILA_READY |
1070 SCRATCH_PAD_RAAE_READY |
1071 SCRATCH_PAD_IOP0_READY |
1072 SCRATCH_PAD_IOP1_READY;
1073 } else {
1074 max_wait_time = max_wait_count = 170; /* 3400 milli sec */
1075 expected_mask = SCRATCH_PAD_ILA_READY |
1076 SCRATCH_PAD_RAAE_READY |
1077 SCRATCH_PAD_IOP0_READY;
1078 }
1079 do {
1080 msleep(FW_READY_INTERVAL);
1081 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1082 } while (((value & expected_mask) !=
1083 expected_mask) && (--max_wait_count));
1084 if (!max_wait_count) {
1085 pm8001_dbg(pm8001_ha, INIT,
1086 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",
1087 max_wait_time * FW_READY_INTERVAL, value);
1088 ret = -1;
1089 } else {
1090 pm8001_dbg(pm8001_ha, MSG,
1091 "All FW components ready by %d ms\n",
1092 (max_wait_time - max_wait_count) * FW_READY_INTERVAL);
1093 }
1094 return ret;
1095 }
1096
init_pci_device_addresses(struct pm8001_hba_info * pm8001_ha)1097 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1098 {
1099 void __iomem *base_addr;
1100 u32 value;
1101 u32 offset;
1102 u32 pcibar;
1103 u32 pcilogic;
1104
1105 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1106
1107 /*
1108 * lower 26 bits of SCRATCHPAD0 register describes offset within the
1109 * PCIe BAR where the MPI configuration table is present
1110 */
1111 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1112
1113 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1114 offset, value);
1115 /*
1116 * Upper 6 bits describe the offset within PCI config space where BAR
1117 * is located.
1118 */
1119 pcilogic = (value & 0xFC000000) >> 26;
1120 pcibar = get_pci_bar_index(pcilogic);
1121 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1122
1123 /*
1124 * Make sure the offset falls inside the ioremapped PCI BAR
1125 */
1126 if (offset > pm8001_ha->io_mem[pcibar].memsize) {
1127 pm8001_dbg(pm8001_ha, FAIL,
1128 "Main cfg tbl offset outside %u > %u\n",
1129 offset, pm8001_ha->io_mem[pcibar].memsize);
1130 return -EBUSY;
1131 }
1132 pm8001_ha->main_cfg_tbl_addr = base_addr =
1133 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1134
1135 /*
1136 * Validate main configuration table address: first DWord should read
1137 * "PMCS"
1138 */
1139 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);
1140 if (memcmp(&value, "PMCS", 4) != 0) {
1141 pm8001_dbg(pm8001_ha, FAIL,
1142 "BAD main config signature 0x%x\n",
1143 value);
1144 return -EBUSY;
1145 }
1146 pm8001_dbg(pm8001_ha, INIT,
1147 "VALID main config signature 0x%x\n", value);
1148 pm8001_ha->general_stat_tbl_addr =
1149 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1150 0xFFFFFF);
1151 pm8001_ha->inbnd_q_tbl_addr =
1152 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1153 0xFFFFFF);
1154 pm8001_ha->outbnd_q_tbl_addr =
1155 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1156 0xFFFFFF);
1157 pm8001_ha->ivt_tbl_addr =
1158 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1159 0xFFFFFF);
1160 pm8001_ha->pspa_q_tbl_addr =
1161 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1162 0xFFFFFF);
1163 pm8001_ha->fatal_tbl_addr =
1164 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1165 0xFFFFFF);
1166
1167 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1168 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1169 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1170 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1171 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1172 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1173 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1174 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1175 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1176 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1177 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1178 pm8001_ha->main_cfg_tbl_addr,
1179 pm8001_ha->general_stat_tbl_addr);
1180 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1181 pm8001_ha->inbnd_q_tbl_addr,
1182 pm8001_ha->outbnd_q_tbl_addr);
1183 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1184 pm8001_ha->pspa_q_tbl_addr,
1185 pm8001_ha->ivt_tbl_addr);
1186 return 0;
1187 }
1188
1189 /**
1190 * pm80xx_set_thermal_config - support the thermal configuration
1191 * @pm8001_ha: our hba card information.
1192 */
1193 int
pm80xx_set_thermal_config(struct pm8001_hba_info * pm8001_ha)1194 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1195 {
1196 struct set_ctrl_cfg_req payload;
1197 int rc;
1198 u32 tag;
1199 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1200 u32 page_code;
1201
1202 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1203 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1204 if (rc)
1205 return rc;
1206
1207 payload.tag = cpu_to_le32(tag);
1208
1209 if (IS_SPCV_12G(pm8001_ha->pdev))
1210 page_code = THERMAL_PAGE_CODE_7H;
1211 else
1212 page_code = THERMAL_PAGE_CODE_8H;
1213
1214 payload.cfg_pg[0] =
1215 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
1216 (THERMAL_ENABLE << 8) | page_code);
1217 payload.cfg_pg[1] =
1218 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
1219
1220 pm8001_dbg(pm8001_ha, DEV,
1221 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1222 payload.cfg_pg[0], payload.cfg_pg[1]);
1223
1224 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1225 sizeof(payload), 0);
1226 if (rc)
1227 pm8001_tag_free(pm8001_ha, tag);
1228 return rc;
1229
1230 }
1231
1232 /**
1233 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1234 * Timer configuration page
1235 * @pm8001_ha: our hba card information.
1236 */
1237 static int
pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info * pm8001_ha)1238 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1239 {
1240 struct set_ctrl_cfg_req payload;
1241 SASProtocolTimerConfig_t SASConfigPage;
1242 int rc;
1243 u32 tag;
1244 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1245
1246 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1247 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1248
1249 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1250 if (rc)
1251 return rc;
1252
1253 payload.tag = cpu_to_le32(tag);
1254
1255 SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
1256 SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
1257 SASConfigPage.STP_SSP_MCT_TMO =
1258 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
1259 SASConfigPage.STP_FRM_TMO =
1260 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
1261 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
1262 SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
1263
1264 SASConfigPage.OPNRJT_RTRY_INTVL =
1265 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
1266 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
1267 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
1268 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
1269 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
1270 SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
1271
1272 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1273 le32_to_cpu(SASConfigPage.pageCode));
1274 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n",
1275 le32_to_cpu(SASConfigPage.MST_MSI));
1276 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n",
1277 le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
1278 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n",
1279 le32_to_cpu(SASConfigPage.STP_FRM_TMO));
1280 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n",
1281 le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
1282 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n",
1283 le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
1284 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n",
1285 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1286 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n",
1287 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1288 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n",
1289 le32_to_cpu(SASConfigPage.MAX_AIP));
1290
1291 memcpy(&payload.cfg_pg, &SASConfigPage,
1292 sizeof(SASProtocolTimerConfig_t));
1293
1294 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1295 sizeof(payload), 0);
1296 if (rc)
1297 pm8001_tag_free(pm8001_ha, tag);
1298
1299 return rc;
1300 }
1301
1302 /**
1303 * pm80xx_get_encrypt_info - Check for encryption
1304 * @pm8001_ha: our hba card information.
1305 */
1306 static int
pm80xx_get_encrypt_info(struct pm8001_hba_info * pm8001_ha)1307 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1308 {
1309 u32 scratch3_value;
1310 int ret = -1;
1311
1312 /* Read encryption status from SCRATCH PAD 3 */
1313 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1314
1315 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1316 SCRATCH_PAD3_ENC_READY) {
1317 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1318 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1319 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1320 SCRATCH_PAD3_SMF_ENABLED)
1321 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1322 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1323 SCRATCH_PAD3_SMA_ENABLED)
1324 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1325 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1326 SCRATCH_PAD3_SMB_ENABLED)
1327 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1328 pm8001_ha->encrypt_info.status = 0;
1329 pm8001_dbg(pm8001_ha, INIT,
1330 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1331 scratch3_value,
1332 pm8001_ha->encrypt_info.cipher_mode,
1333 pm8001_ha->encrypt_info.sec_mode,
1334 pm8001_ha->encrypt_info.status);
1335 ret = 0;
1336 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1337 SCRATCH_PAD3_ENC_DISABLED) {
1338 pm8001_dbg(pm8001_ha, INIT,
1339 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1340 scratch3_value);
1341 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1342 pm8001_ha->encrypt_info.cipher_mode = 0;
1343 pm8001_ha->encrypt_info.sec_mode = 0;
1344 ret = 0;
1345 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1346 SCRATCH_PAD3_ENC_DIS_ERR) {
1347 pm8001_ha->encrypt_info.status =
1348 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1349 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1350 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1351 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1352 SCRATCH_PAD3_SMF_ENABLED)
1353 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1354 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1355 SCRATCH_PAD3_SMA_ENABLED)
1356 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1357 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1358 SCRATCH_PAD3_SMB_ENABLED)
1359 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1360 pm8001_dbg(pm8001_ha, INIT,
1361 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1362 scratch3_value,
1363 pm8001_ha->encrypt_info.cipher_mode,
1364 pm8001_ha->encrypt_info.sec_mode,
1365 pm8001_ha->encrypt_info.status);
1366 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1367 SCRATCH_PAD3_ENC_ENA_ERR) {
1368
1369 pm8001_ha->encrypt_info.status =
1370 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1371 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1372 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1373 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1374 SCRATCH_PAD3_SMF_ENABLED)
1375 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1376 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1377 SCRATCH_PAD3_SMA_ENABLED)
1378 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1379 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1380 SCRATCH_PAD3_SMB_ENABLED)
1381 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1382
1383 pm8001_dbg(pm8001_ha, INIT,
1384 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1385 scratch3_value,
1386 pm8001_ha->encrypt_info.cipher_mode,
1387 pm8001_ha->encrypt_info.sec_mode,
1388 pm8001_ha->encrypt_info.status);
1389 }
1390 return ret;
1391 }
1392
1393 /**
1394 * pm80xx_encrypt_update - update flash with encryption information
1395 * @pm8001_ha: our hba card information.
1396 */
pm80xx_encrypt_update(struct pm8001_hba_info * pm8001_ha)1397 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1398 {
1399 struct kek_mgmt_req payload;
1400 int rc;
1401 u32 tag;
1402 u32 opc = OPC_INB_KEK_MANAGEMENT;
1403
1404 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1405 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1406 if (rc)
1407 return rc;
1408
1409 payload.tag = cpu_to_le32(tag);
1410 /* Currently only one key is used. New KEK index is 1.
1411 * Current KEK index is 1. Store KEK to NVRAM is 1.
1412 */
1413 payload.new_curidx_ksop =
1414 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
1415 KEK_MGMT_SUBOP_KEYCARDUPDATE));
1416
1417 pm8001_dbg(pm8001_ha, DEV,
1418 "Saving Encryption info to flash. payload 0x%x\n",
1419 le32_to_cpu(payload.new_curidx_ksop));
1420
1421 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1422 sizeof(payload), 0);
1423 if (rc)
1424 pm8001_tag_free(pm8001_ha, tag);
1425
1426 return rc;
1427 }
1428
1429 /**
1430 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1431 * @pm8001_ha: our hba card information
1432 */
pm80xx_chip_init(struct pm8001_hba_info * pm8001_ha)1433 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1434 {
1435 int ret;
1436 u8 i = 0;
1437
1438 /* check the firmware status */
1439 if (-1 == check_fw_ready(pm8001_ha)) {
1440 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1441 return -EBUSY;
1442 }
1443
1444 /* Initialize the controller fatal error flag */
1445 pm8001_ha->controller_fatal_error = false;
1446
1447 /* Initialize pci space address eg: mpi offset */
1448 ret = init_pci_device_addresses(pm8001_ha);
1449 if (ret) {
1450 pm8001_dbg(pm8001_ha, FAIL,
1451 "Failed to init pci addresses");
1452 return ret;
1453 }
1454 init_default_table_values(pm8001_ha);
1455 read_main_config_table(pm8001_ha);
1456 read_general_status_table(pm8001_ha);
1457 read_inbnd_queue_table(pm8001_ha);
1458 read_outbnd_queue_table(pm8001_ha);
1459 read_phy_attr_table(pm8001_ha);
1460
1461 /* update main config table ,inbound table and outbound table */
1462 update_main_config_table(pm8001_ha);
1463 for (i = 0; i < pm8001_ha->max_q_num; i++) {
1464 update_inbnd_queue_table(pm8001_ha, i);
1465 update_outbnd_queue_table(pm8001_ha, i);
1466 }
1467 /* notify firmware update finished and check initialization status */
1468 if (0 == mpi_init_check(pm8001_ha)) {
1469 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1470 } else
1471 return -EBUSY;
1472
1473 return 0;
1474 }
1475
pm80xx_chip_post_init(struct pm8001_hba_info * pm8001_ha)1476 static void pm80xx_chip_post_init(struct pm8001_hba_info *pm8001_ha)
1477 {
1478 /* send SAS protocol timer configuration page to FW */
1479 pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1480
1481 /* Check for encryption */
1482 if (pm8001_ha->chip->encrypt) {
1483 int ret;
1484
1485 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1486 ret = pm80xx_get_encrypt_info(pm8001_ha);
1487 if (ret == -1) {
1488 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1489 if (pm8001_ha->encrypt_info.status == 0x81) {
1490 pm8001_dbg(pm8001_ha, INIT,
1491 "Encryption enabled with error.Saving encryption key to flash\n");
1492 pm80xx_encrypt_update(pm8001_ha);
1493 }
1494 }
1495 }
1496 }
1497
mpi_uninit_check(struct pm8001_hba_info * pm8001_ha)1498 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1499 {
1500 u32 max_wait_count;
1501 u32 value;
1502 u32 gst_len_mpistate;
1503 int ret;
1504
1505 ret = init_pci_device_addresses(pm8001_ha);
1506 if (ret) {
1507 pm8001_dbg(pm8001_ha, FAIL,
1508 "Failed to init pci addresses");
1509 return ret;
1510 }
1511
1512 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1513 table is stop */
1514 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1515
1516 /* wait until Inbound DoorBell Clear Register toggled */
1517 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1518 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1519 } else {
1520 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1521 }
1522 do {
1523 msleep(FW_READY_INTERVAL);
1524 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1525 value &= SPCv_MSGU_CFG_TABLE_RESET;
1526 } while ((value != 0) && (--max_wait_count));
1527
1528 if (!max_wait_count) {
1529 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1530 return -1;
1531 }
1532
1533 /* check the MPI-State for termination in progress */
1534 /* wait until Inbound DoorBell Clear Register toggled */
1535 max_wait_count = 100; /* 2 sec for spcv/ve */
1536 do {
1537 msleep(FW_READY_INTERVAL);
1538 gst_len_mpistate =
1539 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1540 GST_GSTLEN_MPIS_OFFSET);
1541 if (GST_MPI_STATE_UNINIT ==
1542 (gst_len_mpistate & GST_MPI_STATE_MASK))
1543 break;
1544 } while (--max_wait_count);
1545 if (!max_wait_count) {
1546 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1547 gst_len_mpistate & GST_MPI_STATE_MASK);
1548 return -1;
1549 }
1550
1551 return 0;
1552 }
1553
1554 /**
1555 * pm80xx_fatal_error_uevent_emit - emits a single fatal error uevent
1556 * @pm8001_ha: our hba card information
1557 * @error_reporter: reporter of fatal error
1558 */
pm80xx_fatal_error_uevent_emit(struct pm8001_hba_info * pm8001_ha,enum fatal_error_reporter error_reporter)1559 void pm80xx_fatal_error_uevent_emit(struct pm8001_hba_info *pm8001_ha,
1560 enum fatal_error_reporter error_reporter)
1561 {
1562 struct kobj_uevent_env *env;
1563
1564 pm8001_dbg(pm8001_ha, FAIL, "emitting fatal error uevent");
1565
1566 env = kzalloc(sizeof(struct kobj_uevent_env), GFP_KERNEL);
1567 if (!env)
1568 return;
1569
1570 if (add_uevent_var(env, "DRIVER=%s", DRV_NAME))
1571 goto exit;
1572
1573 if (add_uevent_var(env, "HBA_NUM=%u", pm8001_ha->id))
1574 goto exit;
1575
1576 if (add_uevent_var(env, "EVENT_TYPE=FATAL_ERROR"))
1577 goto exit;
1578
1579 switch (error_reporter) {
1580 case REPORTER_DRIVER:
1581 if (add_uevent_var(env, "REPORTED_BY=DRIVER"))
1582 goto exit;
1583 break;
1584 case REPORTER_FIRMWARE:
1585 if (add_uevent_var(env, "REPORTED_BY=FIRMWARE"))
1586 goto exit;
1587 break;
1588 default:
1589 if (add_uevent_var(env, "REPORTED_BY=OTHER"))
1590 goto exit;
1591 break;
1592 }
1593
1594 kobject_uevent_env(&pm8001_ha->shost->shost_dev.kobj, KOBJ_CHANGE, env->envp);
1595
1596 exit:
1597 kfree(env);
1598 }
1599
1600 /**
1601 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1602 * @pm8001_ha: our hba card information
1603 *
1604 * Fatal errors are recoverable only after a host reboot.
1605 */
1606 int
pm80xx_fatal_errors(struct pm8001_hba_info * pm8001_ha)1607 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha)
1608 {
1609 int ret = 0;
1610 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,
1611 MSGU_SCRATCH_PAD_RSVD_0);
1612 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,
1613 MSGU_SCRATCH_PAD_RSVD_1);
1614 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1615 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1616 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1617
1618 if (pm8001_ha->chip_id != chip_8006 &&
1619 pm8001_ha->chip_id != chip_8074 &&
1620 pm8001_ha->chip_id != chip_8076) {
1621 return 0;
1622 }
1623
1624 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) {
1625 pm8001_dbg(pm8001_ha, FAIL,
1626 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n",
1627 scratch_pad1, scratch_pad2, scratch_pad3,
1628 scratch_pad_rsvd0, scratch_pad_rsvd1);
1629 pm80xx_fatal_error_uevent_emit(pm8001_ha, REPORTER_DRIVER);
1630 ret = 1;
1631 }
1632
1633 return ret;
1634 }
1635
1636 /**
1637 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1638 * FW register status are reset to the originated status.
1639 * @pm8001_ha: our hba card information
1640 */
1641
1642 static int
pm80xx_chip_soft_rst(struct pm8001_hba_info * pm8001_ha)1643 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1644 {
1645 u32 regval;
1646 u32 bootloader_state;
1647 u32 ibutton0, ibutton1;
1648
1649 /* Process MPI table uninitialization only if FW is ready */
1650 if (!pm8001_ha->controller_fatal_error) {
1651 /* Check if MPI is in ready state to reset */
1652 if (mpi_uninit_check(pm8001_ha) != 0) {
1653 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1654 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1655 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1656 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1657 pm8001_dbg(pm8001_ha, FAIL,
1658 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1659 r0, r1, r2, r3);
1660 /* if things aren't ready but the bootloader is ok then
1661 * try the reset anyway.
1662 */
1663 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1664 return -1;
1665 }
1666 }
1667 /* checked for reset register normal state; 0x0 */
1668 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1669 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1670 regval);
1671
1672 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1673 msleep(500);
1674
1675 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1676 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1677 regval);
1678
1679 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1680 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1681 pm8001_dbg(pm8001_ha, MSG,
1682 " soft reset successful [regval: 0x%x]\n",
1683 regval);
1684 } else {
1685 pm8001_dbg(pm8001_ha, MSG,
1686 " soft reset failed [regval: 0x%x]\n",
1687 regval);
1688
1689 /* check bootloader is successfully executed or in HDA mode */
1690 bootloader_state =
1691 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1692 SCRATCH_PAD1_BOOTSTATE_MASK;
1693
1694 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1695 pm8001_dbg(pm8001_ha, MSG,
1696 "Bootloader state - HDA mode SEEPROM\n");
1697 } else if (bootloader_state ==
1698 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1699 pm8001_dbg(pm8001_ha, MSG,
1700 "Bootloader state - HDA mode Bootstrap Pin\n");
1701 } else if (bootloader_state ==
1702 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1703 pm8001_dbg(pm8001_ha, MSG,
1704 "Bootloader state - HDA mode soft reset\n");
1705 } else if (bootloader_state ==
1706 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1707 pm8001_dbg(pm8001_ha, MSG,
1708 "Bootloader state-HDA mode critical error\n");
1709 }
1710 return -EBUSY;
1711 }
1712
1713 /* check the firmware status after reset */
1714 if (-1 == check_fw_ready(pm8001_ha)) {
1715 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1716 /* check iButton feature support for motherboard controller */
1717 if (pm8001_ha->pdev->subsystem_vendor !=
1718 PCI_VENDOR_ID_ADAPTEC2 &&
1719 pm8001_ha->pdev->subsystem_vendor !=
1720 PCI_VENDOR_ID_ATTO &&
1721 pm8001_ha->pdev->subsystem_vendor != 0) {
1722 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1723 MSGU_SCRATCH_PAD_RSVD_0);
1724 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1725 MSGU_SCRATCH_PAD_RSVD_1);
1726 if (!ibutton0 && !ibutton1) {
1727 pm8001_dbg(pm8001_ha, FAIL,
1728 "iButton Feature is not Available!!!\n");
1729 return -EBUSY;
1730 }
1731 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1732 pm8001_dbg(pm8001_ha, FAIL,
1733 "CRC Check for iButton Feature Failed!!!\n");
1734 return -EBUSY;
1735 }
1736 }
1737 }
1738 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1739 return 0;
1740 }
1741
pm80xx_hw_chip_rst(struct pm8001_hba_info * pm8001_ha)1742 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1743 {
1744 u32 i;
1745
1746 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1747
1748 /* do SPCv chip reset. */
1749 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1750 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1751
1752 /* Check this ..whether delay is required or no */
1753 /* delay 10 usec */
1754 udelay(10);
1755
1756 /* wait for 20 msec until the firmware gets reloaded */
1757 i = 20;
1758 do {
1759 mdelay(1);
1760 } while ((--i) != 0);
1761
1762 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1763 }
1764
1765 /**
1766 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1767 * @pm8001_ha: our hba card information
1768 * @vec: interrupt number to enable
1769 */
1770 static void
pm80xx_chip_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u8 vec)1771 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1772 {
1773 if (!pm8001_ha->use_msix) {
1774 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1775 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1776 return;
1777 }
1778
1779 if (vec < 32)
1780 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
1781 else
1782 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, 1U << (vec - 32));
1783 }
1784
1785 /**
1786 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1787 * @pm8001_ha: our hba card information
1788 * @vec: interrupt number to disable
1789 */
1790 static void
pm80xx_chip_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u8 vec)1791 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1792 {
1793 if (!pm8001_ha->use_msix) {
1794 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1795 return;
1796 }
1797
1798 if (vec == 0xFF) {
1799 /* disable all vectors 0-31, 32-63 */
1800 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
1801 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
1802 } else if (vec < 32) {
1803 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
1804 } else {
1805 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 1U << (vec - 32));
1806 }
1807 }
1808
1809 /**
1810 * mpi_ssp_completion - process the event that FW response to the SSP request.
1811 * @pm8001_ha: our hba card information
1812 * @piomb: the message contents of this outbound message.
1813 *
1814 * When FW has completed a ssp request for example a IO request, after it has
1815 * filled the SG data with the data, it will trigger this event representing
1816 * that he has finished the job; please check the corresponding buffer.
1817 * So we will tell the caller who maybe waiting the result to tell upper layer
1818 * that the task has been finished.
1819 */
1820 static void
mpi_ssp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)1821 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1822 {
1823 struct sas_task *t;
1824 struct pm8001_ccb_info *ccb;
1825 unsigned long flags;
1826 u32 status;
1827 u32 param;
1828 u32 tag;
1829 struct ssp_completion_resp *psspPayload;
1830 struct task_status_struct *ts;
1831 struct ssp_response_iu *iu;
1832 struct pm8001_device *pm8001_dev;
1833 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1834 status = le32_to_cpu(psspPayload->status);
1835 tag = le32_to_cpu(psspPayload->tag);
1836 ccb = &pm8001_ha->ccb_info[tag];
1837 if ((status == IO_ABORTED) && ccb->open_retry) {
1838 /* Being completed by another */
1839 ccb->open_retry = 0;
1840 return;
1841 }
1842 pm8001_dev = ccb->device;
1843 param = le32_to_cpu(psspPayload->param);
1844 t = ccb->task;
1845
1846 if (status && status != IO_UNDERFLOW)
1847 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1848 if (unlikely(!t || !t->lldd_task || !t->dev))
1849 return;
1850 ts = &t->task_status;
1851
1852 pm8001_dbg(pm8001_ha, DEV,
1853 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1854
1855 /* Print sas address of IO failed device */
1856 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1857 (status != IO_UNDERFLOW))
1858 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1859 SAS_ADDR(t->dev->sas_addr));
1860
1861 switch (status) {
1862 case IO_SUCCESS:
1863 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1864 param);
1865 if (param == 0) {
1866 ts->resp = SAS_TASK_COMPLETE;
1867 ts->stat = SAS_SAM_STAT_GOOD;
1868 } else {
1869 ts->resp = SAS_TASK_COMPLETE;
1870 ts->stat = SAS_PROTO_RESPONSE;
1871 ts->residual = param;
1872 iu = &psspPayload->ssp_resp_iu;
1873 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1874 }
1875 if (pm8001_dev)
1876 atomic_dec(&pm8001_dev->running_req);
1877 break;
1878 case IO_ABORTED:
1879 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1880 ts->resp = SAS_TASK_COMPLETE;
1881 ts->stat = SAS_ABORTED_TASK;
1882 if (pm8001_dev)
1883 atomic_dec(&pm8001_dev->running_req);
1884 break;
1885 case IO_UNDERFLOW:
1886 /* SSP Completion with error */
1887 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1888 param);
1889 ts->resp = SAS_TASK_COMPLETE;
1890 ts->stat = SAS_DATA_UNDERRUN;
1891 ts->residual = param;
1892 if (pm8001_dev)
1893 atomic_dec(&pm8001_dev->running_req);
1894 break;
1895 case IO_NO_DEVICE:
1896 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1897 ts->resp = SAS_TASK_UNDELIVERED;
1898 ts->stat = SAS_PHY_DOWN;
1899 if (pm8001_dev)
1900 atomic_dec(&pm8001_dev->running_req);
1901 break;
1902 case IO_XFER_ERROR_BREAK:
1903 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1904 ts->resp = SAS_TASK_COMPLETE;
1905 ts->stat = SAS_OPEN_REJECT;
1906 /* Force the midlayer to retry */
1907 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1908 if (pm8001_dev)
1909 atomic_dec(&pm8001_dev->running_req);
1910 break;
1911 case IO_XFER_ERROR_PHY_NOT_READY:
1912 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1913 ts->resp = SAS_TASK_COMPLETE;
1914 ts->stat = SAS_OPEN_REJECT;
1915 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1916 if (pm8001_dev)
1917 atomic_dec(&pm8001_dev->running_req);
1918 break;
1919 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1920 pm8001_dbg(pm8001_ha, IO,
1921 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
1922 ts->resp = SAS_TASK_COMPLETE;
1923 ts->stat = SAS_OPEN_REJECT;
1924 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1925 if (pm8001_dev)
1926 atomic_dec(&pm8001_dev->running_req);
1927 break;
1928 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1929 pm8001_dbg(pm8001_ha, IO,
1930 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1931 ts->resp = SAS_TASK_COMPLETE;
1932 ts->stat = SAS_OPEN_REJECT;
1933 ts->open_rej_reason = SAS_OREJ_EPROTO;
1934 if (pm8001_dev)
1935 atomic_dec(&pm8001_dev->running_req);
1936 break;
1937 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1938 pm8001_dbg(pm8001_ha, IO,
1939 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1940 ts->resp = SAS_TASK_COMPLETE;
1941 ts->stat = SAS_OPEN_REJECT;
1942 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1943 if (pm8001_dev)
1944 atomic_dec(&pm8001_dev->running_req);
1945 break;
1946 case IO_OPEN_CNX_ERROR_BREAK:
1947 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1948 ts->resp = SAS_TASK_COMPLETE;
1949 ts->stat = SAS_OPEN_REJECT;
1950 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1951 if (pm8001_dev)
1952 atomic_dec(&pm8001_dev->running_req);
1953 break;
1954 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1955 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1956 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1957 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1958 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1959 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1960 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1961 ts->resp = SAS_TASK_COMPLETE;
1962 ts->stat = SAS_OPEN_REJECT;
1963 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1964 if (!t->uldd_task)
1965 pm8001_handle_event(pm8001_ha,
1966 pm8001_dev,
1967 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1968 break;
1969 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1970 pm8001_dbg(pm8001_ha, IO,
1971 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
1972 ts->resp = SAS_TASK_COMPLETE;
1973 ts->stat = SAS_OPEN_REJECT;
1974 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1975 if (pm8001_dev)
1976 atomic_dec(&pm8001_dev->running_req);
1977 break;
1978 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1979 pm8001_dbg(pm8001_ha, IO,
1980 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
1981 ts->resp = SAS_TASK_COMPLETE;
1982 ts->stat = SAS_OPEN_REJECT;
1983 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1984 if (pm8001_dev)
1985 atomic_dec(&pm8001_dev->running_req);
1986 break;
1987 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1988 pm8001_dbg(pm8001_ha, IO,
1989 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
1990 ts->resp = SAS_TASK_UNDELIVERED;
1991 ts->stat = SAS_OPEN_REJECT;
1992 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1993 if (pm8001_dev)
1994 atomic_dec(&pm8001_dev->running_req);
1995 break;
1996 case IO_XFER_ERROR_NAK_RECEIVED:
1997 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
1998 ts->resp = SAS_TASK_COMPLETE;
1999 ts->stat = SAS_OPEN_REJECT;
2000 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2001 if (pm8001_dev)
2002 atomic_dec(&pm8001_dev->running_req);
2003 break;
2004 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2005 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2006 ts->resp = SAS_TASK_COMPLETE;
2007 ts->stat = SAS_NAK_R_ERR;
2008 if (pm8001_dev)
2009 atomic_dec(&pm8001_dev->running_req);
2010 break;
2011 case IO_XFER_ERROR_DMA:
2012 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2013 ts->resp = SAS_TASK_COMPLETE;
2014 ts->stat = SAS_OPEN_REJECT;
2015 if (pm8001_dev)
2016 atomic_dec(&pm8001_dev->running_req);
2017 break;
2018 case IO_XFER_OPEN_RETRY_TIMEOUT:
2019 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2020 ts->resp = SAS_TASK_COMPLETE;
2021 ts->stat = SAS_OPEN_REJECT;
2022 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2023 if (pm8001_dev)
2024 atomic_dec(&pm8001_dev->running_req);
2025 break;
2026 case IO_XFER_ERROR_OFFSET_MISMATCH:
2027 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2028 ts->resp = SAS_TASK_COMPLETE;
2029 ts->stat = SAS_OPEN_REJECT;
2030 if (pm8001_dev)
2031 atomic_dec(&pm8001_dev->running_req);
2032 break;
2033 case IO_PORT_IN_RESET:
2034 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2035 ts->resp = SAS_TASK_COMPLETE;
2036 ts->stat = SAS_OPEN_REJECT;
2037 if (pm8001_dev)
2038 atomic_dec(&pm8001_dev->running_req);
2039 break;
2040 case IO_DS_NON_OPERATIONAL:
2041 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2042 ts->resp = SAS_TASK_COMPLETE;
2043 ts->stat = SAS_OPEN_REJECT;
2044 if (!t->uldd_task)
2045 pm8001_handle_event(pm8001_ha,
2046 pm8001_dev,
2047 IO_DS_NON_OPERATIONAL);
2048 break;
2049 case IO_DS_IN_RECOVERY:
2050 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2051 ts->resp = SAS_TASK_COMPLETE;
2052 ts->stat = SAS_OPEN_REJECT;
2053 if (pm8001_dev)
2054 atomic_dec(&pm8001_dev->running_req);
2055 break;
2056 case IO_TM_TAG_NOT_FOUND:
2057 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2058 ts->resp = SAS_TASK_COMPLETE;
2059 ts->stat = SAS_OPEN_REJECT;
2060 if (pm8001_dev)
2061 atomic_dec(&pm8001_dev->running_req);
2062 break;
2063 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2064 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2065 ts->resp = SAS_TASK_COMPLETE;
2066 ts->stat = SAS_OPEN_REJECT;
2067 if (pm8001_dev)
2068 atomic_dec(&pm8001_dev->running_req);
2069 break;
2070 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2071 pm8001_dbg(pm8001_ha, IO,
2072 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2073 ts->resp = SAS_TASK_COMPLETE;
2074 ts->stat = SAS_OPEN_REJECT;
2075 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2076 if (pm8001_dev)
2077 atomic_dec(&pm8001_dev->running_req);
2078 break;
2079 default:
2080 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2081 /* not allowed case. Therefore, return failed status */
2082 ts->resp = SAS_TASK_COMPLETE;
2083 ts->stat = SAS_OPEN_REJECT;
2084 if (pm8001_dev)
2085 atomic_dec(&pm8001_dev->running_req);
2086 break;
2087 }
2088 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n",
2089 psspPayload->ssp_resp_iu.status);
2090 spin_lock_irqsave(&t->task_state_lock, flags);
2091 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2092 t->task_state_flags |= SAS_TASK_STATE_DONE;
2093 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2094 spin_unlock_irqrestore(&t->task_state_lock, flags);
2095 pm8001_dbg(pm8001_ha, FAIL,
2096 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2097 t, status, ts->resp, ts->stat);
2098 pm8001_ccb_task_free(pm8001_ha, ccb);
2099 if (t->slow_task)
2100 complete(&t->slow_task->completion);
2101 } else {
2102 spin_unlock_irqrestore(&t->task_state_lock, flags);
2103 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2104 }
2105 }
2106
2107 /*See the comments for mpi_ssp_completion */
mpi_ssp_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2108 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2109 {
2110 struct sas_task *t;
2111 unsigned long flags;
2112 struct task_status_struct *ts;
2113 struct pm8001_ccb_info *ccb;
2114 struct pm8001_device *pm8001_dev;
2115 struct ssp_event_resp *psspPayload =
2116 (struct ssp_event_resp *)(piomb + 4);
2117 u32 event = le32_to_cpu(psspPayload->event);
2118 u32 tag = le32_to_cpu(psspPayload->tag);
2119 u32 port_id = le32_to_cpu(psspPayload->port_id);
2120
2121 ccb = &pm8001_ha->ccb_info[tag];
2122 t = ccb->task;
2123 pm8001_dev = ccb->device;
2124 if (event)
2125 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2126 if (unlikely(!t || !t->lldd_task || !t->dev))
2127 return;
2128 ts = &t->task_status;
2129 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2130 port_id, tag, event);
2131 switch (event) {
2132 case IO_OVERFLOW:
2133 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2134 ts->resp = SAS_TASK_COMPLETE;
2135 ts->stat = SAS_DATA_OVERRUN;
2136 ts->residual = 0;
2137 if (pm8001_dev)
2138 atomic_dec(&pm8001_dev->running_req);
2139 break;
2140 case IO_XFER_ERROR_BREAK:
2141 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2142 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2143 return;
2144 case IO_XFER_ERROR_PHY_NOT_READY:
2145 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2146 ts->resp = SAS_TASK_COMPLETE;
2147 ts->stat = SAS_OPEN_REJECT;
2148 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2149 break;
2150 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2151 pm8001_dbg(pm8001_ha, IO,
2152 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2153 ts->resp = SAS_TASK_COMPLETE;
2154 ts->stat = SAS_OPEN_REJECT;
2155 ts->open_rej_reason = SAS_OREJ_EPROTO;
2156 break;
2157 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2158 pm8001_dbg(pm8001_ha, IO,
2159 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2160 ts->resp = SAS_TASK_COMPLETE;
2161 ts->stat = SAS_OPEN_REJECT;
2162 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2163 break;
2164 case IO_OPEN_CNX_ERROR_BREAK:
2165 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2166 ts->resp = SAS_TASK_COMPLETE;
2167 ts->stat = SAS_OPEN_REJECT;
2168 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2169 break;
2170 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2171 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2172 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2173 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2174 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2175 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2176 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2177 ts->resp = SAS_TASK_COMPLETE;
2178 ts->stat = SAS_OPEN_REJECT;
2179 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2180 if (!t->uldd_task)
2181 pm8001_handle_event(pm8001_ha,
2182 pm8001_dev,
2183 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2184 break;
2185 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2186 pm8001_dbg(pm8001_ha, IO,
2187 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2188 ts->resp = SAS_TASK_COMPLETE;
2189 ts->stat = SAS_OPEN_REJECT;
2190 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2191 break;
2192 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2193 pm8001_dbg(pm8001_ha, IO,
2194 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2195 ts->resp = SAS_TASK_COMPLETE;
2196 ts->stat = SAS_OPEN_REJECT;
2197 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2198 break;
2199 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2200 pm8001_dbg(pm8001_ha, IO,
2201 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2202 ts->resp = SAS_TASK_COMPLETE;
2203 ts->stat = SAS_OPEN_REJECT;
2204 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2205 break;
2206 case IO_XFER_ERROR_NAK_RECEIVED:
2207 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2208 ts->resp = SAS_TASK_COMPLETE;
2209 ts->stat = SAS_OPEN_REJECT;
2210 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2211 break;
2212 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2213 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2214 ts->resp = SAS_TASK_COMPLETE;
2215 ts->stat = SAS_NAK_R_ERR;
2216 break;
2217 case IO_XFER_OPEN_RETRY_TIMEOUT:
2218 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2219 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2220 return;
2221 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2222 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2223 ts->resp = SAS_TASK_COMPLETE;
2224 ts->stat = SAS_DATA_OVERRUN;
2225 break;
2226 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2227 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2228 ts->resp = SAS_TASK_COMPLETE;
2229 ts->stat = SAS_DATA_OVERRUN;
2230 break;
2231 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2232 pm8001_dbg(pm8001_ha, IO,
2233 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2234 ts->resp = SAS_TASK_COMPLETE;
2235 ts->stat = SAS_DATA_OVERRUN;
2236 break;
2237 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2238 pm8001_dbg(pm8001_ha, IO,
2239 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2240 ts->resp = SAS_TASK_COMPLETE;
2241 ts->stat = SAS_DATA_OVERRUN;
2242 break;
2243 case IO_XFER_ERROR_OFFSET_MISMATCH:
2244 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2245 ts->resp = SAS_TASK_COMPLETE;
2246 ts->stat = SAS_DATA_OVERRUN;
2247 break;
2248 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2249 pm8001_dbg(pm8001_ha, IO,
2250 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2251 ts->resp = SAS_TASK_COMPLETE;
2252 ts->stat = SAS_DATA_OVERRUN;
2253 break;
2254 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2255 pm8001_dbg(pm8001_ha, IOERR,
2256 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2257 /* TBC: used default set values */
2258 ts->resp = SAS_TASK_COMPLETE;
2259 ts->stat = SAS_DATA_OVERRUN;
2260 break;
2261 case IO_XFER_CMD_FRAME_ISSUED:
2262 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2263 return;
2264 default:
2265 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2266 /* not allowed case. Therefore, return failed status */
2267 ts->resp = SAS_TASK_COMPLETE;
2268 ts->stat = SAS_DATA_OVERRUN;
2269 break;
2270 }
2271 spin_lock_irqsave(&t->task_state_lock, flags);
2272 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2273 t->task_state_flags |= SAS_TASK_STATE_DONE;
2274 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2275 spin_unlock_irqrestore(&t->task_state_lock, flags);
2276 pm8001_dbg(pm8001_ha, FAIL,
2277 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2278 t, event, ts->resp, ts->stat);
2279 pm8001_ccb_task_free(pm8001_ha, ccb);
2280 } else {
2281 spin_unlock_irqrestore(&t->task_state_lock, flags);
2282 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2283 }
2284 }
2285
2286 /*See the comments for mpi_ssp_completion */
2287 static void
mpi_sata_completion(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)2288 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha,
2289 struct outbound_queue_table *circularQ, void *piomb)
2290 {
2291 struct sas_task *t;
2292 struct pm8001_ccb_info *ccb;
2293 u32 param;
2294 u32 status;
2295 u32 tag;
2296 int i, j, ata_tag = -1;
2297 u8 sata_addr_low[4];
2298 u32 temp_sata_addr_low, temp_sata_addr_hi;
2299 u8 sata_addr_hi[4];
2300 struct sata_completion_resp *psataPayload;
2301 struct task_status_struct *ts;
2302 struct ata_task_resp *resp ;
2303 u32 *sata_resp;
2304 struct pm8001_device *pm8001_dev;
2305 unsigned long flags;
2306 struct ata_queued_cmd *qc;
2307
2308 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2309 status = le32_to_cpu(psataPayload->status);
2310 param = le32_to_cpu(psataPayload->param);
2311 tag = le32_to_cpu(psataPayload->tag);
2312
2313 ccb = &pm8001_ha->ccb_info[tag];
2314 t = ccb->task;
2315 pm8001_dev = ccb->device;
2316
2317 if (t) {
2318 if (t->dev && (t->dev->lldd_dev)) {
2319 pm8001_dev = t->dev->lldd_dev;
2320 qc = t->uldd_task;
2321 ata_tag = qc ? qc->tag : -1;
2322 }
2323 } else {
2324 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n",
2325 ccb->ccb_tag);
2326 pm8001_ccb_free(pm8001_ha, ccb);
2327 return;
2328 }
2329
2330 if (pm8001_dev && unlikely(!t->lldd_task || !t->dev))
2331 return;
2332
2333 ts = &t->task_status;
2334 if (status != IO_SUCCESS) {
2335 pm8001_dbg(pm8001_ha, FAIL,
2336 "IO failed status %#x pm80xx tag %#x ata tag %d\n",
2337 status, tag, ata_tag);
2338 }
2339
2340 /* Print sas address of IO failed device */
2341 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2342 (status != IO_UNDERFLOW)) {
2343 if (!((t->dev->parent) &&
2344 (dev_is_expander(t->dev->parent->dev_type)))) {
2345 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2346 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2347 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
2348 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2349 memcpy(&temp_sata_addr_low, sata_addr_low,
2350 sizeof(sata_addr_low));
2351 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2352 sizeof(sata_addr_hi));
2353 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2354 |((temp_sata_addr_hi << 8) &
2355 0xff0000) |
2356 ((temp_sata_addr_hi >> 8)
2357 & 0xff00) |
2358 ((temp_sata_addr_hi << 24) &
2359 0xff000000));
2360 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2361 & 0xff) |
2362 ((temp_sata_addr_low << 8)
2363 & 0xff0000) |
2364 ((temp_sata_addr_low >> 8)
2365 & 0xff00) |
2366 ((temp_sata_addr_low << 24)
2367 & 0xff000000)) +
2368 pm8001_dev->attached_phy +
2369 0x10);
2370 pm8001_dbg(pm8001_ha, FAIL,
2371 "SAS Address of IO Failure Drive:%08x%08x\n",
2372 temp_sata_addr_hi,
2373 temp_sata_addr_low);
2374
2375 } else {
2376 pm8001_dbg(pm8001_ha, FAIL,
2377 "SAS Address of IO Failure Drive:%016llx\n",
2378 SAS_ADDR(t->dev->sas_addr));
2379 }
2380 }
2381 switch (status) {
2382 case IO_SUCCESS:
2383 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2384 if (param == 0) {
2385 ts->resp = SAS_TASK_COMPLETE;
2386 ts->stat = SAS_SAM_STAT_GOOD;
2387 } else {
2388 u8 len;
2389 ts->resp = SAS_TASK_COMPLETE;
2390 ts->stat = SAS_PROTO_RESPONSE;
2391 ts->residual = param;
2392 pm8001_dbg(pm8001_ha, IO,
2393 "SAS_PROTO_RESPONSE len = %d\n",
2394 param);
2395 sata_resp = &psataPayload->sata_resp[0];
2396 resp = (struct ata_task_resp *)ts->buf;
2397 if (t->ata_task.dma_xfer == 0 &&
2398 t->data_dir == DMA_FROM_DEVICE) {
2399 len = sizeof(struct pio_setup_fis);
2400 pm8001_dbg(pm8001_ha, IO,
2401 "PIO read len = %d\n", len);
2402 } else if (t->ata_task.use_ncq &&
2403 t->data_dir != DMA_NONE) {
2404 len = sizeof(struct set_dev_bits_fis);
2405 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2406 len);
2407 } else {
2408 len = sizeof(struct dev_to_host_fis);
2409 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2410 len);
2411 }
2412 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2413 resp->frame_len = len;
2414 memcpy(&resp->ending_fis[0], sata_resp, len);
2415 ts->buf_valid_size = sizeof(*resp);
2416 } else
2417 pm8001_dbg(pm8001_ha, IO,
2418 "response too large\n");
2419 }
2420 if (pm8001_dev)
2421 atomic_dec(&pm8001_dev->running_req);
2422 break;
2423 case IO_ABORTED:
2424 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2425 ts->resp = SAS_TASK_COMPLETE;
2426 ts->stat = SAS_ABORTED_TASK;
2427 if (pm8001_dev)
2428 atomic_dec(&pm8001_dev->running_req);
2429 break;
2430 /* following cases are to do cases */
2431 case IO_UNDERFLOW:
2432 /* SATA Completion with error */
2433 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2434 ts->resp = SAS_TASK_COMPLETE;
2435 ts->stat = SAS_DATA_UNDERRUN;
2436 ts->residual = param;
2437 if (pm8001_dev)
2438 atomic_dec(&pm8001_dev->running_req);
2439 break;
2440 case IO_NO_DEVICE:
2441 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2442 ts->resp = SAS_TASK_UNDELIVERED;
2443 ts->stat = SAS_PHY_DOWN;
2444 if (pm8001_dev)
2445 atomic_dec(&pm8001_dev->running_req);
2446 break;
2447 case IO_XFER_ERROR_BREAK:
2448 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2449 ts->resp = SAS_TASK_COMPLETE;
2450 ts->stat = SAS_INTERRUPTED;
2451 if (pm8001_dev)
2452 atomic_dec(&pm8001_dev->running_req);
2453 break;
2454 case IO_XFER_ERROR_PHY_NOT_READY:
2455 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2456 ts->resp = SAS_TASK_COMPLETE;
2457 ts->stat = SAS_OPEN_REJECT;
2458 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2459 if (pm8001_dev)
2460 atomic_dec(&pm8001_dev->running_req);
2461 break;
2462 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2463 pm8001_dbg(pm8001_ha, IO,
2464 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2465 ts->resp = SAS_TASK_COMPLETE;
2466 ts->stat = SAS_OPEN_REJECT;
2467 ts->open_rej_reason = SAS_OREJ_EPROTO;
2468 if (pm8001_dev)
2469 atomic_dec(&pm8001_dev->running_req);
2470 break;
2471 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2472 pm8001_dbg(pm8001_ha, IO,
2473 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2474 ts->resp = SAS_TASK_COMPLETE;
2475 ts->stat = SAS_OPEN_REJECT;
2476 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2477 if (pm8001_dev)
2478 atomic_dec(&pm8001_dev->running_req);
2479 break;
2480 case IO_OPEN_CNX_ERROR_BREAK:
2481 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2482 ts->resp = SAS_TASK_COMPLETE;
2483 ts->stat = SAS_OPEN_REJECT;
2484 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2485 if (pm8001_dev)
2486 atomic_dec(&pm8001_dev->running_req);
2487 break;
2488 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2489 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2490 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2491 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2492 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2493 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2494 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2495 ts->resp = SAS_TASK_COMPLETE;
2496 ts->stat = SAS_DEV_NO_RESPONSE;
2497 if (!t->uldd_task) {
2498 pm8001_handle_event(pm8001_ha,
2499 pm8001_dev,
2500 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2501 ts->resp = SAS_TASK_UNDELIVERED;
2502 ts->stat = SAS_QUEUE_FULL;
2503 spin_unlock_irqrestore(&circularQ->oq_lock,
2504 circularQ->lock_flags);
2505 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2506 spin_lock_irqsave(&circularQ->oq_lock,
2507 circularQ->lock_flags);
2508 return;
2509 }
2510 break;
2511 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2512 pm8001_dbg(pm8001_ha, IO,
2513 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2514 ts->resp = SAS_TASK_UNDELIVERED;
2515 ts->stat = SAS_OPEN_REJECT;
2516 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2517 if (!t->uldd_task) {
2518 pm8001_handle_event(pm8001_ha,
2519 pm8001_dev,
2520 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2521 ts->resp = SAS_TASK_UNDELIVERED;
2522 ts->stat = SAS_QUEUE_FULL;
2523 spin_unlock_irqrestore(&circularQ->oq_lock,
2524 circularQ->lock_flags);
2525 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2526 spin_lock_irqsave(&circularQ->oq_lock,
2527 circularQ->lock_flags);
2528 return;
2529 }
2530 break;
2531 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2532 pm8001_dbg(pm8001_ha, IO,
2533 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2534 ts->resp = SAS_TASK_COMPLETE;
2535 ts->stat = SAS_OPEN_REJECT;
2536 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2537 if (pm8001_dev)
2538 atomic_dec(&pm8001_dev->running_req);
2539 break;
2540 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2541 pm8001_dbg(pm8001_ha, IO,
2542 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2543 ts->resp = SAS_TASK_COMPLETE;
2544 ts->stat = SAS_DEV_NO_RESPONSE;
2545 if (!t->uldd_task) {
2546 pm8001_handle_event(pm8001_ha,
2547 pm8001_dev,
2548 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2549 ts->resp = SAS_TASK_UNDELIVERED;
2550 ts->stat = SAS_QUEUE_FULL;
2551 spin_unlock_irqrestore(&circularQ->oq_lock,
2552 circularQ->lock_flags);
2553 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2554 spin_lock_irqsave(&circularQ->oq_lock,
2555 circularQ->lock_flags);
2556 return;
2557 }
2558 break;
2559 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2560 pm8001_dbg(pm8001_ha, IO,
2561 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2562 ts->resp = SAS_TASK_COMPLETE;
2563 ts->stat = SAS_OPEN_REJECT;
2564 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2565 if (pm8001_dev)
2566 atomic_dec(&pm8001_dev->running_req);
2567 break;
2568 case IO_XFER_ERROR_NAK_RECEIVED:
2569 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2570 ts->resp = SAS_TASK_COMPLETE;
2571 ts->stat = SAS_NAK_R_ERR;
2572 if (pm8001_dev)
2573 atomic_dec(&pm8001_dev->running_req);
2574 break;
2575 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2576 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2577 ts->resp = SAS_TASK_COMPLETE;
2578 ts->stat = SAS_NAK_R_ERR;
2579 if (pm8001_dev)
2580 atomic_dec(&pm8001_dev->running_req);
2581 break;
2582 case IO_XFER_ERROR_DMA:
2583 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2584 ts->resp = SAS_TASK_COMPLETE;
2585 ts->stat = SAS_ABORTED_TASK;
2586 if (pm8001_dev)
2587 atomic_dec(&pm8001_dev->running_req);
2588 break;
2589 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2590 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2591 ts->resp = SAS_TASK_UNDELIVERED;
2592 ts->stat = SAS_DEV_NO_RESPONSE;
2593 if (pm8001_dev)
2594 atomic_dec(&pm8001_dev->running_req);
2595 break;
2596 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2597 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2598 ts->resp = SAS_TASK_COMPLETE;
2599 ts->stat = SAS_DATA_UNDERRUN;
2600 if (pm8001_dev)
2601 atomic_dec(&pm8001_dev->running_req);
2602 break;
2603 case IO_XFER_OPEN_RETRY_TIMEOUT:
2604 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2605 ts->resp = SAS_TASK_COMPLETE;
2606 ts->stat = SAS_OPEN_TO;
2607 if (pm8001_dev)
2608 atomic_dec(&pm8001_dev->running_req);
2609 break;
2610 case IO_PORT_IN_RESET:
2611 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2612 ts->resp = SAS_TASK_COMPLETE;
2613 ts->stat = SAS_DEV_NO_RESPONSE;
2614 if (pm8001_dev)
2615 atomic_dec(&pm8001_dev->running_req);
2616 break;
2617 case IO_DS_NON_OPERATIONAL:
2618 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2619 ts->resp = SAS_TASK_COMPLETE;
2620 ts->stat = SAS_DEV_NO_RESPONSE;
2621 if (!t->uldd_task) {
2622 pm8001_handle_event(pm8001_ha, pm8001_dev,
2623 IO_DS_NON_OPERATIONAL);
2624 ts->resp = SAS_TASK_UNDELIVERED;
2625 ts->stat = SAS_QUEUE_FULL;
2626 spin_unlock_irqrestore(&circularQ->oq_lock,
2627 circularQ->lock_flags);
2628 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2629 spin_lock_irqsave(&circularQ->oq_lock,
2630 circularQ->lock_flags);
2631 return;
2632 }
2633 break;
2634 case IO_DS_IN_RECOVERY:
2635 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2636 ts->resp = SAS_TASK_COMPLETE;
2637 ts->stat = SAS_DEV_NO_RESPONSE;
2638 if (pm8001_dev)
2639 atomic_dec(&pm8001_dev->running_req);
2640 break;
2641 case IO_DS_IN_ERROR:
2642 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2643 ts->resp = SAS_TASK_COMPLETE;
2644 ts->stat = SAS_DEV_NO_RESPONSE;
2645 if (!t->uldd_task) {
2646 pm8001_handle_event(pm8001_ha, pm8001_dev,
2647 IO_DS_IN_ERROR);
2648 ts->resp = SAS_TASK_UNDELIVERED;
2649 ts->stat = SAS_QUEUE_FULL;
2650 spin_unlock_irqrestore(&circularQ->oq_lock,
2651 circularQ->lock_flags);
2652 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2653 spin_lock_irqsave(&circularQ->oq_lock,
2654 circularQ->lock_flags);
2655 return;
2656 }
2657 break;
2658 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2659 pm8001_dbg(pm8001_ha, IO,
2660 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2661 ts->resp = SAS_TASK_COMPLETE;
2662 ts->stat = SAS_OPEN_REJECT;
2663 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2664 if (pm8001_dev)
2665 atomic_dec(&pm8001_dev->running_req);
2666 break;
2667 default:
2668 pm8001_dbg(pm8001_ha, DEVIO,
2669 "Unknown status device_id %u status 0x%x tag %d\n",
2670 pm8001_dev->device_id, status, tag);
2671 /* not allowed case. Therefore, return failed status */
2672 ts->resp = SAS_TASK_COMPLETE;
2673 ts->stat = SAS_DEV_NO_RESPONSE;
2674 if (pm8001_dev)
2675 atomic_dec(&pm8001_dev->running_req);
2676 break;
2677 }
2678 spin_lock_irqsave(&t->task_state_lock, flags);
2679 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2680 t->task_state_flags |= SAS_TASK_STATE_DONE;
2681 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2682 spin_unlock_irqrestore(&t->task_state_lock, flags);
2683 pm8001_dbg(pm8001_ha, FAIL,
2684 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2685 t, status, ts->resp, ts->stat);
2686 pm8001_ccb_task_free(pm8001_ha, ccb);
2687 if (t->slow_task)
2688 complete(&t->slow_task->completion);
2689 } else {
2690 spin_unlock_irqrestore(&t->task_state_lock, flags);
2691 spin_unlock_irqrestore(&circularQ->oq_lock,
2692 circularQ->lock_flags);
2693 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2694 spin_lock_irqsave(&circularQ->oq_lock,
2695 circularQ->lock_flags);
2696 }
2697 }
2698
2699 /*See the comments for mpi_ssp_completion */
mpi_sata_event(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)2700 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha,
2701 struct outbound_queue_table *circularQ, void *piomb)
2702 {
2703 struct sas_task *t;
2704 struct task_status_struct *ts;
2705 struct pm8001_ccb_info *ccb;
2706 struct pm8001_device *pm8001_dev;
2707 struct sata_event_resp *psataPayload =
2708 (struct sata_event_resp *)(piomb + 4);
2709 u32 event = le32_to_cpu(psataPayload->event);
2710 u32 tag = le32_to_cpu(psataPayload->tag);
2711 u32 port_id = le32_to_cpu(psataPayload->port_id);
2712 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2713
2714 if (event)
2715 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2716
2717 /* Check if this is NCQ error */
2718 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2719 /* tag value is invalid with this event */
2720 pm8001_dbg(pm8001_ha, FAIL, "NCQ ERROR for device %#x tag %#x\n",
2721 dev_id, tag);
2722
2723 /* find device using device id */
2724 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2725 /* send read log extension by aborting the link - libata does what we want */
2726 if (pm8001_dev) {
2727 pm80xx_show_pending_commands(pm8001_ha, pm8001_dev);
2728 pm8001_handle_event(pm8001_ha,
2729 pm8001_dev,
2730 IO_XFER_ERROR_ABORTED_NCQ_MODE);
2731 }
2732 return;
2733 }
2734
2735 ccb = &pm8001_ha->ccb_info[tag];
2736 t = ccb->task;
2737 pm8001_dev = ccb->device;
2738 if (unlikely(!t)) {
2739 pm8001_dbg(pm8001_ha, FAIL, "task null, freeing CCB tag %d\n",
2740 ccb->ccb_tag);
2741 pm8001_ccb_free(pm8001_ha, ccb);
2742 return;
2743 }
2744
2745 if (unlikely(!t->lldd_task || !t->dev))
2746 return;
2747
2748 ts = &t->task_status;
2749 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2750 port_id, tag, event);
2751 switch (event) {
2752 case IO_OVERFLOW:
2753 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2754 ts->resp = SAS_TASK_COMPLETE;
2755 ts->stat = SAS_DATA_OVERRUN;
2756 ts->residual = 0;
2757 break;
2758 case IO_XFER_ERROR_BREAK:
2759 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2760 ts->resp = SAS_TASK_COMPLETE;
2761 ts->stat = SAS_INTERRUPTED;
2762 break;
2763 case IO_XFER_ERROR_PHY_NOT_READY:
2764 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2765 ts->resp = SAS_TASK_COMPLETE;
2766 ts->stat = SAS_OPEN_REJECT;
2767 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2768 break;
2769 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2770 pm8001_dbg(pm8001_ha, IO,
2771 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2772 ts->resp = SAS_TASK_COMPLETE;
2773 ts->stat = SAS_OPEN_REJECT;
2774 ts->open_rej_reason = SAS_OREJ_EPROTO;
2775 break;
2776 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2777 pm8001_dbg(pm8001_ha, IO,
2778 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2779 ts->resp = SAS_TASK_COMPLETE;
2780 ts->stat = SAS_OPEN_REJECT;
2781 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2782 break;
2783 case IO_OPEN_CNX_ERROR_BREAK:
2784 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2785 ts->resp = SAS_TASK_COMPLETE;
2786 ts->stat = SAS_OPEN_REJECT;
2787 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2788 break;
2789 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2790 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2791 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2792 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2793 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2794 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2795 pm8001_dbg(pm8001_ha, FAIL,
2796 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2797 ts->resp = SAS_TASK_UNDELIVERED;
2798 ts->stat = SAS_DEV_NO_RESPONSE;
2799 if (!t->uldd_task) {
2800 pm8001_handle_event(pm8001_ha,
2801 pm8001_dev,
2802 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2803 ts->resp = SAS_TASK_COMPLETE;
2804 ts->stat = SAS_QUEUE_FULL;
2805 return;
2806 }
2807 break;
2808 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2809 pm8001_dbg(pm8001_ha, IO,
2810 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2811 ts->resp = SAS_TASK_UNDELIVERED;
2812 ts->stat = SAS_OPEN_REJECT;
2813 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2814 break;
2815 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2816 pm8001_dbg(pm8001_ha, IO,
2817 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2818 ts->resp = SAS_TASK_COMPLETE;
2819 ts->stat = SAS_OPEN_REJECT;
2820 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2821 break;
2822 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2823 pm8001_dbg(pm8001_ha, IO,
2824 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2825 ts->resp = SAS_TASK_COMPLETE;
2826 ts->stat = SAS_OPEN_REJECT;
2827 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2828 break;
2829 case IO_XFER_ERROR_NAK_RECEIVED:
2830 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2831 ts->resp = SAS_TASK_COMPLETE;
2832 ts->stat = SAS_NAK_R_ERR;
2833 break;
2834 case IO_XFER_ERROR_PEER_ABORTED:
2835 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2836 ts->resp = SAS_TASK_COMPLETE;
2837 ts->stat = SAS_NAK_R_ERR;
2838 break;
2839 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2840 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2841 ts->resp = SAS_TASK_COMPLETE;
2842 ts->stat = SAS_DATA_UNDERRUN;
2843 break;
2844 case IO_XFER_OPEN_RETRY_TIMEOUT:
2845 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2846 ts->resp = SAS_TASK_COMPLETE;
2847 ts->stat = SAS_OPEN_TO;
2848 break;
2849 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2850 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2851 ts->resp = SAS_TASK_COMPLETE;
2852 ts->stat = SAS_OPEN_TO;
2853 break;
2854 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2855 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2856 ts->resp = SAS_TASK_COMPLETE;
2857 ts->stat = SAS_OPEN_TO;
2858 break;
2859 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2860 pm8001_dbg(pm8001_ha, IO,
2861 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2862 ts->resp = SAS_TASK_COMPLETE;
2863 ts->stat = SAS_OPEN_TO;
2864 break;
2865 case IO_XFER_ERROR_OFFSET_MISMATCH:
2866 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2867 ts->resp = SAS_TASK_COMPLETE;
2868 ts->stat = SAS_OPEN_TO;
2869 break;
2870 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2871 pm8001_dbg(pm8001_ha, IO,
2872 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2873 ts->resp = SAS_TASK_COMPLETE;
2874 ts->stat = SAS_OPEN_TO;
2875 break;
2876 case IO_XFER_CMD_FRAME_ISSUED:
2877 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2878 break;
2879 case IO_XFER_PIO_SETUP_ERROR:
2880 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2881 ts->resp = SAS_TASK_COMPLETE;
2882 ts->stat = SAS_OPEN_TO;
2883 break;
2884 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2885 pm8001_dbg(pm8001_ha, FAIL,
2886 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2887 /* TBC: used default set values */
2888 ts->resp = SAS_TASK_COMPLETE;
2889 ts->stat = SAS_OPEN_TO;
2890 break;
2891 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2892 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
2893 /* TBC: used default set values */
2894 ts->resp = SAS_TASK_COMPLETE;
2895 ts->stat = SAS_OPEN_TO;
2896 break;
2897 default:
2898 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
2899 /* not allowed case. Therefore, return failed status */
2900 ts->resp = SAS_TASK_COMPLETE;
2901 ts->stat = SAS_OPEN_TO;
2902 break;
2903 }
2904 }
2905
2906 /*See the comments for mpi_ssp_completion */
2907 static void
mpi_smp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2908 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2909 {
2910 u32 param, i;
2911 struct sas_task *t;
2912 struct pm8001_ccb_info *ccb;
2913 unsigned long flags;
2914 u32 status;
2915 u32 tag;
2916 struct smp_completion_resp *psmpPayload;
2917 struct task_status_struct *ts;
2918 struct pm8001_device *pm8001_dev;
2919
2920 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2921 status = le32_to_cpu(psmpPayload->status);
2922 tag = le32_to_cpu(psmpPayload->tag);
2923
2924 ccb = &pm8001_ha->ccb_info[tag];
2925 param = le32_to_cpu(psmpPayload->param);
2926 t = ccb->task;
2927 ts = &t->task_status;
2928 pm8001_dev = ccb->device;
2929 if (status)
2930 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2931 if (unlikely(!t || !t->lldd_task || !t->dev))
2932 return;
2933
2934 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
2935
2936 switch (status) {
2937
2938 case IO_SUCCESS:
2939 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2940 ts->resp = SAS_TASK_COMPLETE;
2941 ts->stat = SAS_SAM_STAT_GOOD;
2942 if (pm8001_dev)
2943 atomic_dec(&pm8001_dev->running_req);
2944 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2945 struct scatterlist *sg_resp = &t->smp_task.smp_resp;
2946 u8 *payload;
2947 void *to;
2948
2949 pm8001_dbg(pm8001_ha, IO,
2950 "DIRECT RESPONSE Length:%d\n",
2951 param);
2952 to = kmap_atomic(sg_page(sg_resp));
2953 payload = to + sg_resp->offset;
2954 for (i = 0; i < param; i++) {
2955 *(payload + i) = psmpPayload->_r_a[i];
2956 pm8001_dbg(pm8001_ha, IO,
2957 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2958 i, *(payload + i),
2959 psmpPayload->_r_a[i]);
2960 }
2961 kunmap_atomic(to);
2962 }
2963 break;
2964 case IO_ABORTED:
2965 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2966 ts->resp = SAS_TASK_COMPLETE;
2967 ts->stat = SAS_ABORTED_TASK;
2968 if (pm8001_dev)
2969 atomic_dec(&pm8001_dev->running_req);
2970 break;
2971 case IO_OVERFLOW:
2972 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2973 ts->resp = SAS_TASK_COMPLETE;
2974 ts->stat = SAS_DATA_OVERRUN;
2975 ts->residual = 0;
2976 if (pm8001_dev)
2977 atomic_dec(&pm8001_dev->running_req);
2978 break;
2979 case IO_NO_DEVICE:
2980 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2981 ts->resp = SAS_TASK_COMPLETE;
2982 ts->stat = SAS_PHY_DOWN;
2983 break;
2984 case IO_ERROR_HW_TIMEOUT:
2985 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2986 ts->resp = SAS_TASK_COMPLETE;
2987 ts->stat = SAS_SAM_STAT_BUSY;
2988 break;
2989 case IO_XFER_ERROR_BREAK:
2990 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2991 ts->resp = SAS_TASK_COMPLETE;
2992 ts->stat = SAS_SAM_STAT_BUSY;
2993 break;
2994 case IO_XFER_ERROR_PHY_NOT_READY:
2995 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2996 ts->resp = SAS_TASK_COMPLETE;
2997 ts->stat = SAS_SAM_STAT_BUSY;
2998 break;
2999 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3000 pm8001_dbg(pm8001_ha, IO,
3001 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3002 ts->resp = SAS_TASK_COMPLETE;
3003 ts->stat = SAS_OPEN_REJECT;
3004 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3005 break;
3006 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3007 pm8001_dbg(pm8001_ha, IO,
3008 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3009 ts->resp = SAS_TASK_COMPLETE;
3010 ts->stat = SAS_OPEN_REJECT;
3011 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3012 break;
3013 case IO_OPEN_CNX_ERROR_BREAK:
3014 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3015 ts->resp = SAS_TASK_COMPLETE;
3016 ts->stat = SAS_OPEN_REJECT;
3017 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3018 break;
3019 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3020 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3021 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3022 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3023 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3024 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3025 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3026 ts->resp = SAS_TASK_COMPLETE;
3027 ts->stat = SAS_OPEN_REJECT;
3028 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3029 pm8001_handle_event(pm8001_ha,
3030 pm8001_dev,
3031 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3032 break;
3033 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3034 pm8001_dbg(pm8001_ha, IO,
3035 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3036 ts->resp = SAS_TASK_COMPLETE;
3037 ts->stat = SAS_OPEN_REJECT;
3038 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3039 break;
3040 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3041 pm8001_dbg(pm8001_ha, IO,
3042 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3043 ts->resp = SAS_TASK_COMPLETE;
3044 ts->stat = SAS_OPEN_REJECT;
3045 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3046 break;
3047 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3048 pm8001_dbg(pm8001_ha, IO,
3049 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3050 ts->resp = SAS_TASK_COMPLETE;
3051 ts->stat = SAS_OPEN_REJECT;
3052 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3053 break;
3054 case IO_XFER_ERROR_RX_FRAME:
3055 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3056 ts->resp = SAS_TASK_COMPLETE;
3057 ts->stat = SAS_DEV_NO_RESPONSE;
3058 break;
3059 case IO_XFER_OPEN_RETRY_TIMEOUT:
3060 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3061 ts->resp = SAS_TASK_COMPLETE;
3062 ts->stat = SAS_OPEN_REJECT;
3063 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3064 break;
3065 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3066 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3067 ts->resp = SAS_TASK_COMPLETE;
3068 ts->stat = SAS_QUEUE_FULL;
3069 break;
3070 case IO_PORT_IN_RESET:
3071 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3072 ts->resp = SAS_TASK_COMPLETE;
3073 ts->stat = SAS_OPEN_REJECT;
3074 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3075 break;
3076 case IO_DS_NON_OPERATIONAL:
3077 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3078 ts->resp = SAS_TASK_COMPLETE;
3079 ts->stat = SAS_DEV_NO_RESPONSE;
3080 break;
3081 case IO_DS_IN_RECOVERY:
3082 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3083 ts->resp = SAS_TASK_COMPLETE;
3084 ts->stat = SAS_OPEN_REJECT;
3085 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3086 break;
3087 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3088 pm8001_dbg(pm8001_ha, IO,
3089 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3090 ts->resp = SAS_TASK_COMPLETE;
3091 ts->stat = SAS_OPEN_REJECT;
3092 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3093 break;
3094 default:
3095 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3096 ts->resp = SAS_TASK_COMPLETE;
3097 ts->stat = SAS_DEV_NO_RESPONSE;
3098 /* not allowed case. Therefore, return failed status */
3099 break;
3100 }
3101 spin_lock_irqsave(&t->task_state_lock, flags);
3102 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3103 t->task_state_flags |= SAS_TASK_STATE_DONE;
3104 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3105 spin_unlock_irqrestore(&t->task_state_lock, flags);
3106 pm8001_dbg(pm8001_ha, FAIL,
3107 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3108 t, status, ts->resp, ts->stat);
3109 pm8001_ccb_task_free(pm8001_ha, ccb);
3110 } else {
3111 spin_unlock_irqrestore(&t->task_state_lock, flags);
3112 pm8001_ccb_task_free(pm8001_ha, ccb);
3113 mb();/* in order to force CPU ordering */
3114 t->task_done(t);
3115 }
3116 }
3117
3118 /**
3119 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3120 * @pm8001_ha: our hba card information
3121 * @Qnum: the outbound queue message number.
3122 * @SEA: source of event to ack
3123 * @port_id: port id.
3124 * @phyId: phy id.
3125 * @param0: parameter 0.
3126 * @param1: parameter 1.
3127 */
pm80xx_hw_event_ack_req(struct pm8001_hba_info * pm8001_ha,u32 Qnum,u32 SEA,u32 port_id,u32 phyId,u32 param0,u32 param1)3128 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3129 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3130 {
3131 struct hw_event_ack_req payload;
3132 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3133
3134 memset((u8 *)&payload, 0, sizeof(payload));
3135 payload.tag = cpu_to_le32(1);
3136 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3137 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3138 payload.param0 = cpu_to_le32(param0);
3139 payload.param1 = cpu_to_le32(param1);
3140
3141 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload,
3142 sizeof(payload), 0);
3143 }
3144
3145 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3146 u32 phyId, u32 phy_op);
3147
hw_event_port_recover(struct pm8001_hba_info * pm8001_ha,void * piomb)3148 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3149 void *piomb)
3150 {
3151 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3152 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3153 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3154 u32 lr_status_evt_portid =
3155 le32_to_cpu(pPayload->lr_status_evt_portid);
3156 u8 deviceType = pPayload->sas_identify.dev_type;
3157 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3158 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3159 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3160 struct pm8001_port *port = &pm8001_ha->port[port_id];
3161
3162 if (deviceType == SAS_END_DEVICE) {
3163 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3164 PHY_NOTIFY_ENABLE_SPINUP);
3165 }
3166
3167 port->wide_port_phymap |= (1U << phy_id);
3168 pm8001_get_lrate_mode(phy, link_rate);
3169 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3170 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3171 phy->phy_attached = 1;
3172 }
3173
3174 /**
3175 * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3176 * @pm8001_ha: our hba card information
3177 * @piomb: IO message buffer
3178 */
3179 static void
hw_event_sas_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3180 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3181 {
3182 struct hw_event_resp *pPayload =
3183 (struct hw_event_resp *)(piomb + 4);
3184 u32 lr_status_evt_portid =
3185 le32_to_cpu(pPayload->lr_status_evt_portid);
3186 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3187
3188 u8 link_rate =
3189 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3190 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3191 u8 phy_id =
3192 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3193 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3194
3195 struct pm8001_port *port = &pm8001_ha->port[port_id];
3196 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3197 unsigned long flags;
3198 u8 deviceType = pPayload->sas_identify.dev_type;
3199 phy->port = port;
3200 port->port_id = port_id;
3201 port->port_state = portstate;
3202 port->wide_port_phymap |= (1U << phy_id);
3203 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3204 pm8001_dbg(pm8001_ha, MSG,
3205 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3206 port_id, phy_id, link_rate, portstate, deviceType);
3207
3208 switch (deviceType) {
3209 case SAS_PHY_UNUSED:
3210 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3211 break;
3212 case SAS_END_DEVICE:
3213 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3214 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3215 PHY_NOTIFY_ENABLE_SPINUP);
3216 port->port_attached = 1;
3217 pm8001_get_lrate_mode(phy, link_rate);
3218 break;
3219 case SAS_EDGE_EXPANDER_DEVICE:
3220 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3221 port->port_attached = 1;
3222 pm8001_get_lrate_mode(phy, link_rate);
3223 break;
3224 case SAS_FANOUT_EXPANDER_DEVICE:
3225 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3226 port->port_attached = 1;
3227 pm8001_get_lrate_mode(phy, link_rate);
3228 break;
3229 default:
3230 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3231 deviceType);
3232 break;
3233 }
3234 phy->phy_type |= PORT_TYPE_SAS;
3235 phy->identify.device_type = deviceType;
3236 phy->phy_attached = 1;
3237 if (phy->identify.device_type == SAS_END_DEVICE)
3238 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3239 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3240 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3241 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3242 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3243 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3244 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3245 sizeof(struct sas_identify_frame)-4);
3246 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3247 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3248 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3249 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3250 mdelay(200); /* delay a moment to wait for disk to spin up */
3251 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3252 }
3253
3254 /**
3255 * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3256 * @pm8001_ha: our hba card information
3257 * @piomb: IO message buffer
3258 */
3259 static void
hw_event_sata_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3260 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3261 {
3262 struct hw_event_resp *pPayload =
3263 (struct hw_event_resp *)(piomb + 4);
3264 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3265 u32 lr_status_evt_portid =
3266 le32_to_cpu(pPayload->lr_status_evt_portid);
3267 u8 link_rate =
3268 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3269 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3270 u8 phy_id =
3271 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3272
3273 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3274
3275 struct pm8001_port *port = &pm8001_ha->port[port_id];
3276 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3277 unsigned long flags;
3278 pm8001_dbg(pm8001_ha, EVENT,
3279 "HW_EVENT_SATA_PHY_UP phyid:%#x port_id:%#x link_rate:%d portstate:%#x\n",
3280 phy_id, port_id, link_rate, portstate);
3281
3282 phy->port = port;
3283 port->port_id = port_id;
3284 port->port_state = portstate;
3285 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3286 port->port_attached = 1;
3287 pm8001_get_lrate_mode(phy, link_rate);
3288 phy->phy_type |= PORT_TYPE_SATA;
3289 phy->phy_attached = 1;
3290 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3291 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3292 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3293 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3294 sizeof(struct dev_to_host_fis));
3295 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3296 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3297 phy->identify.device_type = SAS_SATA_DEV;
3298 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3299 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3300 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3301 }
3302
3303 /**
3304 * hw_event_phy_down - we should notify the libsas the phy is down.
3305 * @pm8001_ha: our hba card information
3306 * @piomb: IO message buffer
3307 */
3308 static void
hw_event_phy_down(struct pm8001_hba_info * pm8001_ha,void * piomb)3309 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3310 {
3311 struct hw_event_resp *pPayload =
3312 (struct hw_event_resp *)(piomb + 4);
3313
3314 u32 lr_status_evt_portid =
3315 le32_to_cpu(pPayload->lr_status_evt_portid);
3316 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3317 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3318 u8 phy_id =
3319 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3320 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3321
3322 struct pm8001_port *port = &pm8001_ha->port[port_id];
3323 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3324 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3325 port->port_state = portstate;
3326 phy->identify.device_type = 0;
3327 phy->phy_attached = 0;
3328 switch (portstate) {
3329 case PORT_VALID:
3330 pm8001_dbg(pm8001_ha, EVENT,
3331 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_VALID\n",
3332 phy_id, port_id);
3333 break;
3334 case PORT_INVALID:
3335 pm8001_dbg(pm8001_ha, EVENT,
3336 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_INVALID\n",
3337 phy_id, port_id);
3338 pm8001_dbg(pm8001_ha, MSG,
3339 " Last phy Down and port invalid\n");
3340 if (port_sata) {
3341 phy->phy_type = 0;
3342 port->port_attached = 0;
3343 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3344 port_id, phy_id, 0, 0);
3345 }
3346 sas_phy_disconnected(&phy->sas_phy);
3347 break;
3348 case PORT_IN_RESET:
3349 pm8001_dbg(pm8001_ha, EVENT,
3350 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_IN_RESET\n",
3351 phy_id, port_id);
3352 break;
3353 case PORT_NOT_ESTABLISHED:
3354 pm8001_dbg(pm8001_ha, EVENT,
3355 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_NOT_ESTABLISHED\n",
3356 phy_id, port_id);
3357 port->port_attached = 0;
3358 break;
3359 case PORT_LOSTCOMM:
3360 pm8001_dbg(pm8001_ha, EVENT,
3361 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate: PORT_LOSTCOMM\n",
3362 phy_id, port_id);
3363 pm8001_dbg(pm8001_ha, MSG, " Last phy Down and port invalid\n");
3364 if (port_sata) {
3365 port->port_attached = 0;
3366 phy->phy_type = 0;
3367 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3368 port_id, phy_id, 0, 0);
3369 }
3370 sas_phy_disconnected(&phy->sas_phy);
3371 break;
3372 default:
3373 port->port_attached = 0;
3374 pm8001_dbg(pm8001_ha, EVENT,
3375 "HW_EVENT_PHY_DOWN phyid:%#x port_id:%#x portstate:%#x\n",
3376 phy_id, port_id, portstate);
3377 break;
3378
3379 }
3380 if (port_sata && (portstate != PORT_IN_RESET))
3381 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3382 GFP_ATOMIC);
3383 }
3384
mpi_phy_start_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3385 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3386 {
3387 struct phy_start_resp *pPayload =
3388 (struct phy_start_resp *)(piomb + 4);
3389 u32 status =
3390 le32_to_cpu(pPayload->status);
3391 u32 phy_id =
3392 le32_to_cpu(pPayload->phyid) & 0xFF;
3393 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3394 u32 tag = le32_to_cpu(pPayload->tag);
3395
3396 pm8001_dbg(pm8001_ha, INIT,
3397 "phy start resp status:0x%x, phyid:0x%x, tag 0x%x\n",
3398 status, phy_id, tag);
3399 if (status == 0)
3400 phy->phy_state = PHY_LINK_DOWN;
3401
3402 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3403 phy->enable_completion != NULL) {
3404 complete(phy->enable_completion);
3405 phy->enable_completion = NULL;
3406 }
3407
3408 pm8001_tag_free(pm8001_ha, tag);
3409 return 0;
3410
3411 }
3412
3413 /**
3414 * mpi_thermal_hw_event - a thermal hw event has come.
3415 * @pm8001_ha: our hba card information
3416 * @piomb: IO message buffer
3417 */
mpi_thermal_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3418 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3419 {
3420 struct thermal_hw_event *pPayload =
3421 (struct thermal_hw_event *)(piomb + 4);
3422
3423 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3424 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3425
3426 if (thermal_event & 0x40) {
3427 pm8001_dbg(pm8001_ha, IO,
3428 "Thermal Event: Local high temperature violated!\n");
3429 pm8001_dbg(pm8001_ha, IO,
3430 "Thermal Event: Measured local high temperature %d\n",
3431 ((rht_lht & 0xFF00) >> 8));
3432 }
3433 if (thermal_event & 0x10) {
3434 pm8001_dbg(pm8001_ha, IO,
3435 "Thermal Event: Remote high temperature violated!\n");
3436 pm8001_dbg(pm8001_ha, IO,
3437 "Thermal Event: Measured remote high temperature %d\n",
3438 ((rht_lht & 0xFF000000) >> 24));
3439 }
3440 return 0;
3441 }
3442
3443 /**
3444 * mpi_hw_event - The hw event has come.
3445 * @pm8001_ha: our hba card information
3446 * @piomb: IO message buffer
3447 */
mpi_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3448 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3449 {
3450 unsigned long flags, i;
3451 struct hw_event_resp *pPayload =
3452 (struct hw_event_resp *)(piomb + 4);
3453 u32 lr_status_evt_portid =
3454 le32_to_cpu(pPayload->lr_status_evt_portid);
3455 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3456 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3457 u8 phy_id =
3458 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3459 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3460 u16 eventType =
3461 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3462 u8 status =
3463 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3464 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3465 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3466 struct pm8001_port *port = &pm8001_ha->port[port_id];
3467 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3468 pm8001_dbg(pm8001_ha, DEV,
3469 "portid:%d phyid:%d event:0x%x status:0x%x\n",
3470 port_id, phy_id, eventType, status);
3471
3472 switch (eventType) {
3473
3474 case HW_EVENT_SAS_PHY_UP:
3475 pm8001_dbg(pm8001_ha, EVENT,
3476 "HW_EVENT_SAS_PHY_UP phyid:%#x port_id:%#x\n",
3477 phy_id, port_id);
3478 hw_event_sas_phy_up(pm8001_ha, piomb);
3479 break;
3480 case HW_EVENT_SATA_PHY_UP:
3481 hw_event_sata_phy_up(pm8001_ha, piomb);
3482 break;
3483 case HW_EVENT_SATA_SPINUP_HOLD:
3484 pm8001_dbg(pm8001_ha, EVENT,
3485 "HW_EVENT_SATA_SPINUP_HOLD phyid:%#x port_id:%#x\n",
3486 phy_id, port_id);
3487 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3488 GFP_ATOMIC);
3489 break;
3490 case HW_EVENT_PHY_DOWN:
3491 hw_event_phy_down(pm8001_ha, piomb);
3492 phy->phy_state = PHY_LINK_DISABLE;
3493 break;
3494 case HW_EVENT_PORT_INVALID:
3495 pm8001_dbg(pm8001_ha, EVENT,
3496 "HW_EVENT_PORT_INVALID phyid:%#x port_id:%#x\n",
3497 phy_id, port_id);
3498 sas_phy_disconnected(sas_phy);
3499 phy->phy_attached = 0;
3500 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3501 GFP_ATOMIC);
3502 break;
3503 /* the broadcast change primitive received, tell the LIBSAS this event
3504 to revalidate the sas domain*/
3505 case HW_EVENT_BROADCAST_CHANGE:
3506 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3507 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3508 port_id, phy_id, 1, 0);
3509 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3510 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3511 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3512 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3513 GFP_ATOMIC);
3514 break;
3515 case HW_EVENT_PHY_ERROR:
3516 pm8001_dbg(pm8001_ha, EVENT,
3517 "HW_EVENT_PHY_ERROR phyid:%#x port_id:%#x\n",
3518 phy_id, port_id);
3519 sas_phy_disconnected(&phy->sas_phy);
3520 phy->phy_attached = 0;
3521 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3522 break;
3523 case HW_EVENT_BROADCAST_EXP:
3524 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3525 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3526 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3527 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3528 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3529 GFP_ATOMIC);
3530 break;
3531 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3532 pm8001_dbg(pm8001_ha, EVENT,
3533 "HW_EVENT_LINK_ERR_INVALID_DWORD phyid:%#x port_id:%#x\n",
3534 phy_id, port_id);
3535 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3536 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3537 break;
3538 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3539 pm8001_dbg(pm8001_ha, EVENT,
3540 "HW_EVENT_LINK_ERR_DISPARITY_ERROR phyid:%#x port_id:%#x\n",
3541 phy_id, port_id);
3542 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3543 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3544 port_id, phy_id, 0, 0);
3545 break;
3546 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3547 pm8001_dbg(pm8001_ha, EVENT,
3548 "HW_EVENT_LINK_ERR_CODE_VIOLATION phyid:%#x port_id:%#x\n",
3549 phy_id, port_id);
3550 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3551 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3552 port_id, phy_id, 0, 0);
3553 break;
3554 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3555 pm8001_dbg(pm8001_ha, EVENT,
3556 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH phyid:%#x port_id:%#x\n",
3557 phy_id, port_id);
3558 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3559 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3560 port_id, phy_id, 0, 0);
3561 break;
3562 case HW_EVENT_MALFUNCTION:
3563 pm8001_dbg(pm8001_ha, EVENT,
3564 "HW_EVENT_MALFUNCTION phyid:%#x\n", phy_id);
3565 break;
3566 case HW_EVENT_BROADCAST_SES:
3567 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3568 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3569 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3570 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3571 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3572 GFP_ATOMIC);
3573 break;
3574 case HW_EVENT_INBOUND_CRC_ERROR:
3575 pm8001_dbg(pm8001_ha, EVENT,
3576 "HW_EVENT_INBOUND_CRC_ERROR phyid:%#x port_id:%#x\n",
3577 phy_id, port_id);
3578 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3579 HW_EVENT_INBOUND_CRC_ERROR,
3580 port_id, phy_id, 0, 0);
3581 break;
3582 case HW_EVENT_HARD_RESET_RECEIVED:
3583 pm8001_dbg(pm8001_ha, EVENT,
3584 "HW_EVENT_HARD_RESET_RECEIVED phyid:%#x\n", phy_id);
3585 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3586 break;
3587 case HW_EVENT_ID_FRAME_TIMEOUT:
3588 pm8001_dbg(pm8001_ha, EVENT,
3589 "HW_EVENT_ID_FRAME_TIMEOUT phyid:%#x\n", phy_id);
3590 sas_phy_disconnected(sas_phy);
3591 phy->phy_attached = 0;
3592 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3593 GFP_ATOMIC);
3594 break;
3595 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3596 pm8001_dbg(pm8001_ha, EVENT,
3597 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED phyid:%#x port_id:%#x\n",
3598 phy_id, port_id);
3599 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3600 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3601 port_id, phy_id, 0, 0);
3602 sas_phy_disconnected(sas_phy);
3603 phy->phy_attached = 0;
3604 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3605 GFP_ATOMIC);
3606 break;
3607 case HW_EVENT_PORT_RESET_TIMER_TMO:
3608 pm8001_dbg(pm8001_ha, EVENT,
3609 "HW_EVENT_PORT_RESET_TIMER_TMO phyid:%#x port_id:%#x portstate:%#x\n",
3610 phy_id, port_id, portstate);
3611 if (!pm8001_ha->phy[phy_id].reset_completion) {
3612 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3613 port_id, phy_id, 0, 0);
3614 }
3615 sas_phy_disconnected(sas_phy);
3616 phy->phy_attached = 0;
3617 port->port_state = portstate;
3618 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3619 GFP_ATOMIC);
3620 if (pm8001_ha->phy[phy_id].reset_completion) {
3621 pm8001_ha->phy[phy_id].port_reset_status =
3622 PORT_RESET_TMO;
3623 complete(pm8001_ha->phy[phy_id].reset_completion);
3624 pm8001_ha->phy[phy_id].reset_completion = NULL;
3625 }
3626 break;
3627 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3628 pm8001_dbg(pm8001_ha, EVENT,
3629 "HW_EVENT_PORT_RECOVERY_TIMER_TMO phyid:%#x port_id:%#x\n",
3630 phy_id, port_id);
3631 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3632 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3633 port_id, phy_id, 0, 0);
3634 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3635 if (port->wide_port_phymap & (1 << i)) {
3636 phy = &pm8001_ha->phy[i];
3637 sas_notify_phy_event(&phy->sas_phy,
3638 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
3639 port->wide_port_phymap &= ~(1 << i);
3640 }
3641 }
3642 break;
3643 case HW_EVENT_PORT_RECOVER:
3644 pm8001_dbg(pm8001_ha, EVENT,
3645 "HW_EVENT_PORT_RECOVER phyid:%#x port_id:%#x\n",
3646 phy_id, port_id);
3647 hw_event_port_recover(pm8001_ha, piomb);
3648 break;
3649 case HW_EVENT_PORT_RESET_COMPLETE:
3650 pm8001_dbg(pm8001_ha, EVENT,
3651 "HW_EVENT_PORT_RESET_COMPLETE phyid:%#x port_id:%#x portstate:%#x\n",
3652 phy_id, port_id, portstate);
3653 if (pm8001_ha->phy[phy_id].reset_completion) {
3654 pm8001_ha->phy[phy_id].port_reset_status =
3655 PORT_RESET_SUCCESS;
3656 complete(pm8001_ha->phy[phy_id].reset_completion);
3657 pm8001_ha->phy[phy_id].reset_completion = NULL;
3658 }
3659 phy->phy_attached = 1;
3660 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3661 port->port_state = portstate;
3662 break;
3663 case EVENT_BROADCAST_ASYNCH_EVENT:
3664 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3665 break;
3666 default:
3667 pm8001_dbg(pm8001_ha, DEVIO,
3668 "Unknown event portid:%d phyid:%d event:0x%x status:0x%x\n",
3669 port_id, phy_id, eventType, status);
3670 break;
3671 }
3672 return 0;
3673 }
3674
3675 /**
3676 * mpi_phy_stop_resp - SPCv specific
3677 * @pm8001_ha: our hba card information
3678 * @piomb: IO message buffer
3679 */
mpi_phy_stop_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3680 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3681 {
3682 struct phy_stop_resp *pPayload =
3683 (struct phy_stop_resp *)(piomb + 4);
3684 u32 status =
3685 le32_to_cpu(pPayload->status);
3686 u32 phyid =
3687 le32_to_cpu(pPayload->phyid) & 0xFF;
3688 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3689 u32 tag = le32_to_cpu(pPayload->tag);
3690
3691 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x tag 0x%x\n", phyid,
3692 status, tag);
3693 if (status == PHY_STOP_SUCCESS ||
3694 status == PHY_STOP_ERR_DEVICE_ATTACHED) {
3695 phy->phy_state = PHY_LINK_DISABLE;
3696 phy->sas_phy.phy->negotiated_linkrate = SAS_PHY_DISABLED;
3697 phy->sas_phy.linkrate = SAS_PHY_DISABLED;
3698 }
3699
3700 pm8001_tag_free(pm8001_ha, tag);
3701 return 0;
3702 }
3703
3704 /**
3705 * mpi_set_controller_config_resp - SPCv specific
3706 * @pm8001_ha: our hba card information
3707 * @piomb: IO message buffer
3708 */
mpi_set_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3709 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3710 void *piomb)
3711 {
3712 struct set_ctrl_cfg_resp *pPayload =
3713 (struct set_ctrl_cfg_resp *)(piomb + 4);
3714 u32 status = le32_to_cpu(pPayload->status);
3715 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3716 u32 tag = le32_to_cpu(pPayload->tag);
3717
3718 pm8001_dbg(pm8001_ha, MSG,
3719 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x tag 0x%x\n",
3720 status, err_qlfr_pgcd, tag);
3721 pm8001_tag_free(pm8001_ha, tag);
3722 return 0;
3723 }
3724
3725 /**
3726 * mpi_get_controller_config_resp - SPCv specific
3727 * @pm8001_ha: our hba card information
3728 * @piomb: IO message buffer
3729 */
mpi_get_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3730 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3731 void *piomb)
3732 {
3733 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3734
3735 return 0;
3736 }
3737
3738 /**
3739 * mpi_get_phy_profile_resp - SPCv specific
3740 * @pm8001_ha: our hba card information
3741 * @piomb: IO message buffer
3742 */
mpi_get_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3743 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3744 void *piomb)
3745 {
3746 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3747
3748 return 0;
3749 }
3750
3751 /**
3752 * mpi_flash_op_ext_resp - SPCv specific
3753 * @pm8001_ha: our hba card information
3754 * @piomb: IO message buffer
3755 */
mpi_flash_op_ext_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3756 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3757 {
3758 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3759
3760 return 0;
3761 }
3762
3763 /**
3764 * mpi_set_phy_profile_resp - SPCv specific
3765 * @pm8001_ha: our hba card information
3766 * @piomb: IO message buffer
3767 */
mpi_set_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3768 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3769 void *piomb)
3770 {
3771 u32 tag;
3772 u8 page_code;
3773 int rc = 0;
3774 struct set_phy_profile_resp *pPayload =
3775 (struct set_phy_profile_resp *)(piomb + 4);
3776 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3777 u32 status = le32_to_cpu(pPayload->status);
3778
3779 tag = le32_to_cpu(pPayload->tag);
3780 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3781 if (status) {
3782 /* status is FAILED */
3783 pm8001_dbg(pm8001_ha, FAIL,
3784 "PhyProfile command failed with status 0x%08X\n",
3785 status);
3786 rc = -1;
3787 } else {
3788 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3789 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3790 page_code);
3791 rc = -1;
3792 }
3793 }
3794 pm8001_tag_free(pm8001_ha, tag);
3795 return rc;
3796 }
3797
3798 /**
3799 * mpi_kek_management_resp - SPCv specific
3800 * @pm8001_ha: our hba card information
3801 * @piomb: IO message buffer
3802 */
mpi_kek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3803 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3804 void *piomb)
3805 {
3806 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3807
3808 u32 status = le32_to_cpu(pPayload->status);
3809 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3810 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3811
3812 pm8001_dbg(pm8001_ha, MSG,
3813 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3814 status, kidx_new_curr_ksop, err_qlfr);
3815
3816 return 0;
3817 }
3818
3819 /**
3820 * mpi_dek_management_resp - SPCv specific
3821 * @pm8001_ha: our hba card information
3822 * @piomb: IO message buffer
3823 */
mpi_dek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3824 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3825 void *piomb)
3826 {
3827 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3828
3829 return 0;
3830 }
3831
3832 /**
3833 * ssp_coalesced_comp_resp - SPCv specific
3834 * @pm8001_ha: our hba card information
3835 * @piomb: IO message buffer
3836 */
ssp_coalesced_comp_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3837 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3838 void *piomb)
3839 {
3840 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3841
3842 return 0;
3843 }
3844
3845 /**
3846 * process_one_iomb - process one outbound Queue memory block
3847 * @pm8001_ha: our hba card information
3848 * @circularQ: outbound circular queue
3849 * @piomb: IO message buffer
3850 */
process_one_iomb(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)3851 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha,
3852 struct outbound_queue_table *circularQ, void *piomb)
3853 {
3854 __le32 pHeader = *(__le32 *)piomb;
3855 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3856
3857 switch (opc) {
3858 case OPC_OUB_ECHO:
3859 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3860 break;
3861 case OPC_OUB_HW_EVENT:
3862 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3863 mpi_hw_event(pm8001_ha, piomb);
3864 break;
3865 case OPC_OUB_THERM_HW_EVENT:
3866 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3867 mpi_thermal_hw_event(pm8001_ha, piomb);
3868 break;
3869 case OPC_OUB_SSP_COMP:
3870 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3871 mpi_ssp_completion(pm8001_ha, piomb);
3872 break;
3873 case OPC_OUB_SMP_COMP:
3874 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3875 mpi_smp_completion(pm8001_ha, piomb);
3876 break;
3877 case OPC_OUB_LOCAL_PHY_CNTRL:
3878 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3879 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3880 break;
3881 case OPC_OUB_DEV_REGIST:
3882 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3883 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3884 break;
3885 case OPC_OUB_DEREG_DEV:
3886 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3887 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3888 break;
3889 case OPC_OUB_GET_DEV_HANDLE:
3890 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3891 break;
3892 case OPC_OUB_SATA_COMP:
3893 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3894 mpi_sata_completion(pm8001_ha, circularQ, piomb);
3895 break;
3896 case OPC_OUB_SATA_EVENT:
3897 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3898 mpi_sata_event(pm8001_ha, circularQ, piomb);
3899 break;
3900 case OPC_OUB_SSP_EVENT:
3901 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3902 mpi_ssp_event(pm8001_ha, piomb);
3903 break;
3904 case OPC_OUB_DEV_HANDLE_ARRIV:
3905 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3906 /*This is for target*/
3907 break;
3908 case OPC_OUB_SSP_RECV_EVENT:
3909 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3910 /*This is for target*/
3911 break;
3912 case OPC_OUB_FW_FLASH_UPDATE:
3913 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3914 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3915 break;
3916 case OPC_OUB_GPIO_RESPONSE:
3917 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3918 break;
3919 case OPC_OUB_GPIO_EVENT:
3920 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3921 break;
3922 case OPC_OUB_GENERAL_EVENT:
3923 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3924 pm8001_mpi_general_event(pm8001_ha, piomb);
3925 break;
3926 case OPC_OUB_SSP_ABORT_RSP:
3927 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3928 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3929 break;
3930 case OPC_OUB_SATA_ABORT_RSP:
3931 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3932 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3933 break;
3934 case OPC_OUB_SAS_DIAG_MODE_START_END:
3935 pm8001_dbg(pm8001_ha, MSG,
3936 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3937 break;
3938 case OPC_OUB_SAS_DIAG_EXECUTE:
3939 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3940 break;
3941 case OPC_OUB_GET_TIME_STAMP:
3942 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3943 break;
3944 case OPC_OUB_SAS_HW_EVENT_ACK:
3945 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3946 break;
3947 case OPC_OUB_PORT_CONTROL:
3948 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3949 break;
3950 case OPC_OUB_SMP_ABORT_RSP:
3951 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3952 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3953 break;
3954 case OPC_OUB_GET_NVMD_DATA:
3955 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3956 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3957 break;
3958 case OPC_OUB_SET_NVMD_DATA:
3959 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3960 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3961 break;
3962 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3963 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3964 break;
3965 case OPC_OUB_SET_DEVICE_STATE:
3966 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3967 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3968 break;
3969 case OPC_OUB_GET_DEVICE_STATE:
3970 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3971 break;
3972 case OPC_OUB_SET_DEV_INFO:
3973 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3974 break;
3975 /* spcv specific commands */
3976 case OPC_OUB_PHY_START_RESP:
3977 pm8001_dbg(pm8001_ha, MSG,
3978 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
3979 mpi_phy_start_resp(pm8001_ha, piomb);
3980 break;
3981 case OPC_OUB_PHY_STOP_RESP:
3982 pm8001_dbg(pm8001_ha, MSG,
3983 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
3984 mpi_phy_stop_resp(pm8001_ha, piomb);
3985 break;
3986 case OPC_OUB_SET_CONTROLLER_CONFIG:
3987 pm8001_dbg(pm8001_ha, MSG,
3988 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
3989 mpi_set_controller_config_resp(pm8001_ha, piomb);
3990 break;
3991 case OPC_OUB_GET_CONTROLLER_CONFIG:
3992 pm8001_dbg(pm8001_ha, MSG,
3993 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
3994 mpi_get_controller_config_resp(pm8001_ha, piomb);
3995 break;
3996 case OPC_OUB_GET_PHY_PROFILE:
3997 pm8001_dbg(pm8001_ha, MSG,
3998 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
3999 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4000 break;
4001 case OPC_OUB_FLASH_OP_EXT:
4002 pm8001_dbg(pm8001_ha, MSG,
4003 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
4004 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4005 break;
4006 case OPC_OUB_SET_PHY_PROFILE:
4007 pm8001_dbg(pm8001_ha, MSG,
4008 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
4009 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4010 break;
4011 case OPC_OUB_KEK_MANAGEMENT_RESP:
4012 pm8001_dbg(pm8001_ha, MSG,
4013 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4014 mpi_kek_management_resp(pm8001_ha, piomb);
4015 break;
4016 case OPC_OUB_DEK_MANAGEMENT_RESP:
4017 pm8001_dbg(pm8001_ha, MSG,
4018 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4019 mpi_dek_management_resp(pm8001_ha, piomb);
4020 break;
4021 case OPC_OUB_SSP_COALESCED_COMP_RESP:
4022 pm8001_dbg(pm8001_ha, MSG,
4023 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4024 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4025 break;
4026 default:
4027 pm8001_dbg(pm8001_ha, DEVIO,
4028 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4029 break;
4030 }
4031 }
4032
print_scratchpad_registers(struct pm8001_hba_info * pm8001_ha)4033 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4034 {
4035 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4036 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4037 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4038 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4039 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4040 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4041 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4042 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4043 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4044 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4045 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4046 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4047 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4048 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4049 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4050 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4051 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4052 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4053 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4054 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4055 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4056 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0));
4057 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4058 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1));
4059 }
4060
process_oq(struct pm8001_hba_info * pm8001_ha,u8 vec)4061 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4062 {
4063 struct outbound_queue_table *circularQ;
4064 void *pMsg1 = NULL;
4065 u8 bc;
4066 u32 ret = MPI_IO_STATUS_FAIL;
4067 u32 regval;
4068
4069 /*
4070 * Fatal errors are programmed to be signalled in irq vector
4071 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
4072 * fatal_err_interrupt
4073 */
4074 if (vec == (pm8001_ha->max_q_num - 1)) {
4075 u32 mipsall_ready;
4076
4077 if (pm8001_ha->chip_id == chip_8008 ||
4078 pm8001_ha->chip_id == chip_8009)
4079 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
4080 else
4081 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
4082
4083 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4084 if ((regval & mipsall_ready) != mipsall_ready) {
4085 pm8001_ha->controller_fatal_error = true;
4086 pm8001_dbg(pm8001_ha, FAIL,
4087 "Firmware Fatal error! Regval:0x%x\n",
4088 regval);
4089 pm80xx_fatal_error_uevent_emit(pm8001_ha, REPORTER_FIRMWARE);
4090 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR);
4091 print_scratchpad_registers(pm8001_ha);
4092 return ret;
4093 } else {
4094 /*read scratchpad rsvd 0 register*/
4095 regval = pm8001_cr32(pm8001_ha, 0,
4096 MSGU_SCRATCH_PAD_RSVD_0);
4097 switch (regval) {
4098 case NON_FATAL_SPBC_LBUS_ECC_ERR:
4099 case NON_FATAL_BDMA_ERR:
4100 case NON_FATAL_THERM_OVERTEMP_ERR:
4101 /*Clear the register*/
4102 pm8001_cw32(pm8001_ha, 0,
4103 MSGU_SCRATCH_PAD_RSVD_0,
4104 0x00000000);
4105 break;
4106 default:
4107 break;
4108 }
4109 }
4110 }
4111 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4112 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);
4113 do {
4114 /* spurious interrupt during setup if kexec-ing and
4115 * driver doing a doorbell access w/ the pre-kexec oq
4116 * interrupt setup.
4117 */
4118 if (!circularQ->pi_virt)
4119 break;
4120 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4121 if (MPI_IO_STATUS_SUCCESS == ret) {
4122 /* process the outbound message */
4123 process_one_iomb(pm8001_ha, circularQ,
4124 (void *)(pMsg1 - 4));
4125 /* free the message from the outbound circular buffer */
4126 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4127 circularQ, bc);
4128 }
4129 if (MPI_IO_STATUS_BUSY == ret) {
4130 /* Update the producer index from SPC */
4131 circularQ->producer_index =
4132 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4133 if (le32_to_cpu(circularQ->producer_index) ==
4134 circularQ->consumer_idx)
4135 /* OQ is empty */
4136 break;
4137 }
4138 } while (1);
4139 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);
4140 return ret;
4141 }
4142
4143 /* DMA_... to our direction translation. */
4144 static const u8 data_dir_flags[] = {
4145 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4146 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4147 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4148 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4149 };
4150
build_smp_cmd(u32 deviceID,__le32 hTag,struct smp_req * psmp_cmd,int mode,int length)4151 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4152 struct smp_req *psmp_cmd, int mode, int length)
4153 {
4154 psmp_cmd->tag = hTag;
4155 psmp_cmd->device_id = cpu_to_le32(deviceID);
4156 if (mode == SMP_DIRECT) {
4157 length = length - 4; /* subtract crc */
4158 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4159 } else {
4160 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4161 }
4162 }
4163
4164 /**
4165 * pm80xx_chip_smp_req - send an SMP task to FW
4166 * @pm8001_ha: our hba card information.
4167 * @ccb: the ccb information this request used.
4168 */
pm80xx_chip_smp_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4169 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4170 struct pm8001_ccb_info *ccb)
4171 {
4172 int elem, rc;
4173 struct sas_task *task = ccb->task;
4174 struct domain_device *dev = task->dev;
4175 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4176 struct scatterlist *sg_req, *sg_resp, *smp_req;
4177 u32 req_len, resp_len;
4178 struct smp_req smp_cmd;
4179 u32 opc;
4180 u32 i, length;
4181 u8 *payload;
4182 u8 *to;
4183
4184 memset(&smp_cmd, 0, sizeof(smp_cmd));
4185 /*
4186 * DMA-map SMP request, response buffers
4187 */
4188 sg_req = &task->smp_task.smp_req;
4189 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4190 if (!elem)
4191 return -ENOMEM;
4192 req_len = sg_dma_len(sg_req);
4193
4194 sg_resp = &task->smp_task.smp_resp;
4195 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4196 if (!elem) {
4197 rc = -ENOMEM;
4198 goto err_out;
4199 }
4200 resp_len = sg_dma_len(sg_resp);
4201 /* must be in dwords */
4202 if ((req_len & 0x3) || (resp_len & 0x3)) {
4203 rc = -EINVAL;
4204 goto err_out_2;
4205 }
4206
4207 opc = OPC_INB_SMP_REQUEST;
4208 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4209
4210 length = sg_req->length;
4211 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4212 if (!(length - 8))
4213 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4214 else
4215 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4216
4217
4218 smp_req = &task->smp_task.smp_req;
4219 to = kmap_atomic(sg_page(smp_req));
4220 payload = to + smp_req->offset;
4221
4222 /* INDIRECT MODE command settings. Use DMA */
4223 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4224 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4225 /* for SPCv indirect mode. Place the top 4 bytes of
4226 * SMP Request header here. */
4227 for (i = 0; i < 4; i++)
4228 smp_cmd.smp_req16[i] = *(payload + i);
4229 /* exclude top 4 bytes for SMP req header */
4230 smp_cmd.long_smp_req.long_req_addr =
4231 cpu_to_le64((u64)sg_dma_address
4232 (&task->smp_task.smp_req) + 4);
4233 /* exclude 4 bytes for SMP req header and CRC */
4234 smp_cmd.long_smp_req.long_req_size =
4235 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4236 smp_cmd.long_smp_req.long_resp_addr =
4237 cpu_to_le64((u64)sg_dma_address
4238 (&task->smp_task.smp_resp));
4239 smp_cmd.long_smp_req.long_resp_size =
4240 cpu_to_le32((u32)sg_dma_len
4241 (&task->smp_task.smp_resp)-4);
4242 } else { /* DIRECT MODE */
4243 smp_cmd.long_smp_req.long_req_addr =
4244 cpu_to_le64((u64)sg_dma_address
4245 (&task->smp_task.smp_req));
4246 smp_cmd.long_smp_req.long_req_size =
4247 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4248 smp_cmd.long_smp_req.long_resp_addr =
4249 cpu_to_le64((u64)sg_dma_address
4250 (&task->smp_task.smp_resp));
4251 smp_cmd.long_smp_req.long_resp_size =
4252 cpu_to_le32
4253 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4254 }
4255 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4256 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4257 for (i = 0; i < length; i++)
4258 if (i < 16) {
4259 smp_cmd.smp_req16[i] = *(payload + i);
4260 pm8001_dbg(pm8001_ha, IO,
4261 "Byte[%d]:%x (DMA data:%x)\n",
4262 i, smp_cmd.smp_req16[i],
4263 *(payload));
4264 } else {
4265 smp_cmd.smp_req[i] = *(payload + i);
4266 pm8001_dbg(pm8001_ha, IO,
4267 "Byte[%d]:%x (DMA data:%x)\n",
4268 i, smp_cmd.smp_req[i],
4269 *(payload));
4270 }
4271 }
4272 kunmap_atomic(to);
4273 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4274 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4275 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd,
4276 sizeof(smp_cmd), 0);
4277 if (rc)
4278 goto err_out_2;
4279 return 0;
4280
4281 err_out_2:
4282 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4283 DMA_FROM_DEVICE);
4284 err_out:
4285 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4286 DMA_TO_DEVICE);
4287 return rc;
4288 }
4289
check_enc_sas_cmd(struct sas_task * task)4290 static int check_enc_sas_cmd(struct sas_task *task)
4291 {
4292 u8 cmd = task->ssp_task.cmd->cmnd[0];
4293
4294 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4295 return 1;
4296 else
4297 return 0;
4298 }
4299
check_enc_sat_cmd(struct sas_task * task)4300 static int check_enc_sat_cmd(struct sas_task *task)
4301 {
4302 int ret = 0;
4303 switch (task->ata_task.fis.command) {
4304 case ATA_CMD_FPDMA_READ:
4305 case ATA_CMD_READ_EXT:
4306 case ATA_CMD_READ:
4307 case ATA_CMD_FPDMA_WRITE:
4308 case ATA_CMD_WRITE_EXT:
4309 case ATA_CMD_WRITE:
4310 case ATA_CMD_PIO_READ:
4311 case ATA_CMD_PIO_READ_EXT:
4312 case ATA_CMD_PIO_WRITE:
4313 case ATA_CMD_PIO_WRITE_EXT:
4314 ret = 1;
4315 break;
4316 default:
4317 ret = 0;
4318 break;
4319 }
4320 return ret;
4321 }
4322
pm80xx_chip_get_q_index(struct sas_task * task)4323 static u32 pm80xx_chip_get_q_index(struct sas_task *task)
4324 {
4325 struct request *rq = sas_task_find_rq(task);
4326
4327 if (!rq)
4328 return 0;
4329
4330 return blk_mq_unique_tag_to_hwq(blk_mq_unique_tag(rq));
4331 }
4332
4333 /**
4334 * pm80xx_chip_ssp_io_req - send an SSP task to FW
4335 * @pm8001_ha: our hba card information.
4336 * @ccb: the ccb information this request used.
4337 */
pm80xx_chip_ssp_io_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4338 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4339 struct pm8001_ccb_info *ccb)
4340 {
4341 struct sas_task *task = ccb->task;
4342 struct domain_device *dev = task->dev;
4343 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4344 struct ssp_ini_io_start_req ssp_cmd;
4345 u32 tag = ccb->ccb_tag;
4346 u64 phys_addr, end_addr;
4347 u32 end_addr_high, end_addr_low;
4348 u32 q_index;
4349 u32 opc = OPC_INB_SSPINIIOSTART;
4350
4351 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4352 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4353
4354 /* data address domain added for spcv; set to 0 by host,
4355 * used internally by controller
4356 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4357 */
4358 ssp_cmd.dad_dir_m_tlr =
4359 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4360 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4361 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4362 ssp_cmd.tag = cpu_to_le32(tag);
4363 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4364 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4365 task->ssp_task.cmd->cmd_len);
4366 q_index = pm80xx_chip_get_q_index(task);
4367
4368 /* Check if encryption is set */
4369 if (pm8001_ha->chip->encrypt &&
4370 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4371 pm8001_dbg(pm8001_ha, IO,
4372 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4373 task->ssp_task.cmd->cmnd[0]);
4374 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4375 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4376 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4377 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4378
4379 /* fill in PRD (scatter/gather) table, if any */
4380 if (task->num_scatter > 1) {
4381 pm8001_chip_make_sg(task->scatter,
4382 ccb->n_elem, ccb->buf_prd);
4383 phys_addr = ccb->ccb_dma_handle;
4384 ssp_cmd.enc_addr_low =
4385 cpu_to_le32(lower_32_bits(phys_addr));
4386 ssp_cmd.enc_addr_high =
4387 cpu_to_le32(upper_32_bits(phys_addr));
4388 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4389 } else if (task->num_scatter == 1) {
4390 u64 dma_addr = sg_dma_address(task->scatter);
4391
4392 ssp_cmd.enc_addr_low =
4393 cpu_to_le32(lower_32_bits(dma_addr));
4394 ssp_cmd.enc_addr_high =
4395 cpu_to_le32(upper_32_bits(dma_addr));
4396 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4397 ssp_cmd.enc_esgl = 0;
4398
4399 /* Check 4G Boundary */
4400 end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
4401 end_addr_low = lower_32_bits(end_addr);
4402 end_addr_high = upper_32_bits(end_addr);
4403
4404 if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
4405 pm8001_dbg(pm8001_ha, FAIL,
4406 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4407 dma_addr,
4408 le32_to_cpu(ssp_cmd.enc_len),
4409 end_addr_high, end_addr_low);
4410 pm8001_chip_make_sg(task->scatter, 1,
4411 ccb->buf_prd);
4412 phys_addr = ccb->ccb_dma_handle;
4413 ssp_cmd.enc_addr_low =
4414 cpu_to_le32(lower_32_bits(phys_addr));
4415 ssp_cmd.enc_addr_high =
4416 cpu_to_le32(upper_32_bits(phys_addr));
4417 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
4418 }
4419 } else if (task->num_scatter == 0) {
4420 ssp_cmd.enc_addr_low = 0;
4421 ssp_cmd.enc_addr_high = 0;
4422 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4423 ssp_cmd.enc_esgl = 0;
4424 }
4425
4426 /* XTS mode. All other fields are 0 */
4427 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
4428
4429 /* set tweak values. Should be the start lba */
4430 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4431 (task->ssp_task.cmd->cmnd[3] << 16) |
4432 (task->ssp_task.cmd->cmnd[4] << 8) |
4433 (task->ssp_task.cmd->cmnd[5]));
4434 } else {
4435 pm8001_dbg(pm8001_ha, IO,
4436 "Sending Normal SAS command 0x%x inb q %x\n",
4437 task->ssp_task.cmd->cmnd[0], q_index);
4438 /* fill in PRD (scatter/gather) table, if any */
4439 if (task->num_scatter > 1) {
4440 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4441 ccb->buf_prd);
4442 phys_addr = ccb->ccb_dma_handle;
4443 ssp_cmd.addr_low =
4444 cpu_to_le32(lower_32_bits(phys_addr));
4445 ssp_cmd.addr_high =
4446 cpu_to_le32(upper_32_bits(phys_addr));
4447 ssp_cmd.esgl = cpu_to_le32(1<<31);
4448 } else if (task->num_scatter == 1) {
4449 u64 dma_addr = sg_dma_address(task->scatter);
4450
4451 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4452 ssp_cmd.addr_high =
4453 cpu_to_le32(upper_32_bits(dma_addr));
4454 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4455 ssp_cmd.esgl = 0;
4456
4457 /* Check 4G Boundary */
4458 end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
4459 end_addr_low = lower_32_bits(end_addr);
4460 end_addr_high = upper_32_bits(end_addr);
4461 if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
4462 pm8001_dbg(pm8001_ha, FAIL,
4463 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4464 dma_addr,
4465 le32_to_cpu(ssp_cmd.len),
4466 end_addr_high, end_addr_low);
4467 pm8001_chip_make_sg(task->scatter, 1,
4468 ccb->buf_prd);
4469 phys_addr = ccb->ccb_dma_handle;
4470 ssp_cmd.addr_low =
4471 cpu_to_le32(lower_32_bits(phys_addr));
4472 ssp_cmd.addr_high =
4473 cpu_to_le32(upper_32_bits(phys_addr));
4474 ssp_cmd.esgl = cpu_to_le32(1<<31);
4475 }
4476 } else if (task->num_scatter == 0) {
4477 ssp_cmd.addr_low = 0;
4478 ssp_cmd.addr_high = 0;
4479 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4480 ssp_cmd.esgl = 0;
4481 }
4482 }
4483
4484 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd,
4485 sizeof(ssp_cmd), q_index);
4486 }
4487
pm80xx_chip_sata_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4488 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4489 struct pm8001_ccb_info *ccb)
4490 {
4491 struct sas_task *task = ccb->task;
4492 struct domain_device *dev = task->dev;
4493 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4494 struct ata_queued_cmd *qc = task->uldd_task;
4495 u32 tag = ccb->ccb_tag, q_index;
4496 struct sata_start_req sata_cmd;
4497 u32 hdr_tag, ncg_tag = 0;
4498 u64 phys_addr, end_addr;
4499 u32 end_addr_high, end_addr_low;
4500 u32 ATAP = 0x0;
4501 u32 dir, retfis = 0;
4502 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4503 memset(&sata_cmd, 0, sizeof(sata_cmd));
4504
4505 q_index = pm80xx_chip_get_q_index(task);
4506
4507 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4508 ATAP = 0x04; /* no data*/
4509 pm8001_dbg(pm8001_ha, IO, "no data\n");
4510 } else if (likely(!task->ata_task.device_control_reg_update)) {
4511 if (task->ata_task.use_ncq &&
4512 dev->sata_dev.class != ATA_DEV_ATAPI) {
4513 ATAP = 0x07; /* FPDMA */
4514 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4515 } else if (task->ata_task.dma_xfer) {
4516 ATAP = 0x06; /* DMA */
4517 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4518 } else {
4519 ATAP = 0x05; /* PIO*/
4520 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4521 }
4522 }
4523 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4524 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4525 ncg_tag = hdr_tag;
4526 }
4527 dir = data_dir_flags[task->data_dir] << 8;
4528 sata_cmd.tag = cpu_to_le32(tag);
4529 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4530 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4531 if (task->ata_task.return_fis_on_success)
4532 retfis = 1;
4533 sata_cmd.sata_fis = task->ata_task.fis;
4534 if (likely(!task->ata_task.device_control_reg_update))
4535 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4536 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4537
4538 /* Check if encryption is set */
4539 if (pm8001_ha->chip->encrypt &&
4540 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4541 pm8001_dbg(pm8001_ha, IO,
4542 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4543 sata_cmd.sata_fis.command);
4544 opc = OPC_INB_SATA_DIF_ENC_IO;
4545 /* set encryption bit; dad (bits 0-1) is 0 */
4546 sata_cmd.retfis_ncqtag_atap_dir_m_dad =
4547 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) |
4548 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4549 /* fill in PRD (scatter/gather) table, if any */
4550 if (task->num_scatter > 1) {
4551 pm8001_chip_make_sg(task->scatter,
4552 ccb->n_elem, ccb->buf_prd);
4553 phys_addr = ccb->ccb_dma_handle;
4554 sata_cmd.enc_addr_low =
4555 cpu_to_le32(lower_32_bits(phys_addr));
4556 sata_cmd.enc_addr_high =
4557 cpu_to_le32(upper_32_bits(phys_addr));
4558 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4559 } else if (task->num_scatter == 1) {
4560 u64 dma_addr = sg_dma_address(task->scatter);
4561
4562 sata_cmd.enc_addr_low =
4563 cpu_to_le32(lower_32_bits(dma_addr));
4564 sata_cmd.enc_addr_high =
4565 cpu_to_le32(upper_32_bits(dma_addr));
4566 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4567 sata_cmd.enc_esgl = 0;
4568
4569 /* Check 4G Boundary */
4570 end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
4571 end_addr_low = lower_32_bits(end_addr);
4572 end_addr_high = upper_32_bits(end_addr);
4573 if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
4574 pm8001_dbg(pm8001_ha, FAIL,
4575 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4576 dma_addr,
4577 le32_to_cpu(sata_cmd.enc_len),
4578 end_addr_high, end_addr_low);
4579 pm8001_chip_make_sg(task->scatter, 1,
4580 ccb->buf_prd);
4581 phys_addr = ccb->ccb_dma_handle;
4582 sata_cmd.enc_addr_low =
4583 cpu_to_le32(lower_32_bits(phys_addr));
4584 sata_cmd.enc_addr_high =
4585 cpu_to_le32(upper_32_bits(phys_addr));
4586 sata_cmd.enc_esgl =
4587 cpu_to_le32(1 << 31);
4588 }
4589 } else if (task->num_scatter == 0) {
4590 sata_cmd.enc_addr_low = 0;
4591 sata_cmd.enc_addr_high = 0;
4592 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4593 sata_cmd.enc_esgl = 0;
4594 }
4595 /* XTS mode. All other fields are 0 */
4596 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
4597
4598 /* set tweak values. Should be the start lba */
4599 sata_cmd.twk_val0 =
4600 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4601 (sata_cmd.sata_fis.lbah << 16) |
4602 (sata_cmd.sata_fis.lbam << 8) |
4603 (sata_cmd.sata_fis.lbal));
4604 sata_cmd.twk_val1 =
4605 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4606 (sata_cmd.sata_fis.lbam_exp));
4607 } else {
4608 pm8001_dbg(pm8001_ha, IO,
4609 "Sending Normal SATA command 0x%x inb %x\n",
4610 sata_cmd.sata_fis.command, q_index);
4611 /* dad (bits 0-1) is 0 */
4612 sata_cmd.retfis_ncqtag_atap_dir_m_dad =
4613 cpu_to_le32((retfis << 24) | ((ncg_tag & 0xff) << 16) |
4614 ((ATAP & 0x3f) << 10) | dir);
4615 /* fill in PRD (scatter/gather) table, if any */
4616 if (task->num_scatter > 1) {
4617 pm8001_chip_make_sg(task->scatter,
4618 ccb->n_elem, ccb->buf_prd);
4619 phys_addr = ccb->ccb_dma_handle;
4620 sata_cmd.addr_low = lower_32_bits(phys_addr);
4621 sata_cmd.addr_high = upper_32_bits(phys_addr);
4622 sata_cmd.esgl = cpu_to_le32(1U << 31);
4623 } else if (task->num_scatter == 1) {
4624 u64 dma_addr = sg_dma_address(task->scatter);
4625
4626 sata_cmd.addr_low = lower_32_bits(dma_addr);
4627 sata_cmd.addr_high = upper_32_bits(dma_addr);
4628 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4629 sata_cmd.esgl = 0;
4630
4631 /* Check 4G Boundary */
4632 end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
4633 end_addr_low = lower_32_bits(end_addr);
4634 end_addr_high = upper_32_bits(end_addr);
4635 if (end_addr_high != sata_cmd.addr_high) {
4636 pm8001_dbg(pm8001_ha, FAIL,
4637 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4638 dma_addr,
4639 le32_to_cpu(sata_cmd.len),
4640 end_addr_high, end_addr_low);
4641 pm8001_chip_make_sg(task->scatter, 1,
4642 ccb->buf_prd);
4643 phys_addr = ccb->ccb_dma_handle;
4644 sata_cmd.addr_low = lower_32_bits(phys_addr);
4645 sata_cmd.addr_high = upper_32_bits(phys_addr);
4646 sata_cmd.esgl = cpu_to_le32(1U << 31);
4647 }
4648 } else if (task->num_scatter == 0) {
4649 sata_cmd.addr_low = 0;
4650 sata_cmd.addr_high = 0;
4651 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4652 sata_cmd.esgl = 0;
4653 }
4654
4655 /* scsi cdb */
4656 sata_cmd.atapi_scsi_cdb[0] =
4657 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4658 (task->ata_task.atapi_packet[1] << 8) |
4659 (task->ata_task.atapi_packet[2] << 16) |
4660 (task->ata_task.atapi_packet[3] << 24)));
4661 sata_cmd.atapi_scsi_cdb[1] =
4662 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4663 (task->ata_task.atapi_packet[5] << 8) |
4664 (task->ata_task.atapi_packet[6] << 16) |
4665 (task->ata_task.atapi_packet[7] << 24)));
4666 sata_cmd.atapi_scsi_cdb[2] =
4667 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4668 (task->ata_task.atapi_packet[9] << 8) |
4669 (task->ata_task.atapi_packet[10] << 16) |
4670 (task->ata_task.atapi_packet[11] << 24)));
4671 sata_cmd.atapi_scsi_cdb[3] =
4672 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4673 (task->ata_task.atapi_packet[13] << 8) |
4674 (task->ata_task.atapi_packet[14] << 16) |
4675 (task->ata_task.atapi_packet[15] << 24)));
4676 }
4677
4678 trace_pm80xx_request_issue(pm8001_ha->id,
4679 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,
4680 ccb->ccb_tag, opc,
4681 qc ? qc->tf.command : 0, // ata opcode
4682 ccb->device ? atomic_read(&ccb->device->running_req) : 0);
4683 return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd,
4684 sizeof(sata_cmd), q_index);
4685 }
4686
4687 /**
4688 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4689 * @pm8001_ha: our hba card information.
4690 * @phy_id: the phy id which we wanted to start up.
4691 */
4692 static int
pm80xx_chip_phy_start_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4693 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4694 {
4695 struct phy_start_req payload;
4696 int ret;
4697 u32 tag;
4698 u32 opcode = OPC_INB_PHYSTART;
4699
4700 ret = pm8001_tag_alloc(pm8001_ha, &tag);
4701 if (ret) {
4702 pm8001_dbg(pm8001_ha, FAIL, "Tag allocation failed\n");
4703 return ret;
4704 }
4705
4706 memset(&payload, 0, sizeof(payload));
4707 payload.tag = cpu_to_le32(tag);
4708
4709 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4710
4711 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4712 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4713 /* SSC Disable and SAS Analog ST configuration */
4714 /*
4715 payload.ase_sh_lm_slr_phyid =
4716 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4717 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4718 phy_id);
4719 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4720 */
4721
4722 payload.sas_identify.dev_type = SAS_END_DEVICE;
4723 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4724 memcpy(payload.sas_identify.sas_addr,
4725 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
4726 payload.sas_identify.phy_id = phy_id;
4727
4728 ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4729 sizeof(payload), 0);
4730 if (ret < 0)
4731 pm8001_tag_free(pm8001_ha, tag);
4732
4733 return ret;
4734 }
4735
4736 /**
4737 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4738 * @pm8001_ha: our hba card information.
4739 * @phy_id: the phy id which we wanted to start up.
4740 */
pm80xx_chip_phy_stop_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4741 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4742 u8 phy_id)
4743 {
4744 struct phy_stop_req payload;
4745 int ret;
4746 u32 tag;
4747 u32 opcode = OPC_INB_PHYSTOP;
4748
4749 ret = pm8001_tag_alloc(pm8001_ha, &tag);
4750 if (ret) {
4751 pm8001_dbg(pm8001_ha, FAIL, "Tag allocation failed\n");
4752 return ret;
4753 }
4754
4755 memset(&payload, 0, sizeof(payload));
4756 payload.tag = cpu_to_le32(tag);
4757 payload.phy_id = cpu_to_le32(phy_id);
4758
4759 ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4760 sizeof(payload), 0);
4761 if (ret < 0)
4762 pm8001_tag_free(pm8001_ha, tag);
4763
4764 return ret;
4765 }
4766
4767 /*
4768 * see comments on pm8001_mpi_reg_resp.
4769 */
pm80xx_chip_reg_dev_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 flag)4770 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4771 struct pm8001_device *pm8001_dev, u32 flag)
4772 {
4773 struct reg_dev_req payload;
4774 u32 opc;
4775 u32 stp_sspsmp_sata = 0x4;
4776 u32 linkrate, phy_id;
4777 int rc;
4778 struct pm8001_ccb_info *ccb;
4779 u8 retryFlag = 0x1;
4780 u16 firstBurstSize = 0;
4781 u16 ITNT = 2000;
4782 struct domain_device *dev = pm8001_dev->sas_device;
4783 struct domain_device *parent_dev = dev->parent;
4784 struct pm8001_port *port = dev->port->lldd_port;
4785
4786 memset(&payload, 0, sizeof(payload));
4787 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4788 if (!ccb)
4789 return -SAS_QUEUE_FULL;
4790
4791 payload.tag = cpu_to_le32(ccb->ccb_tag);
4792
4793 if (flag == 1) {
4794 stp_sspsmp_sata = 0x02; /*direct attached sata */
4795 } else {
4796 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4797 stp_sspsmp_sata = 0x00; /* stp*/
4798 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4799 dev_is_expander(pm8001_dev->dev_type))
4800 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4801 }
4802 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4803 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4804 else
4805 phy_id = pm8001_dev->attached_phy;
4806
4807 opc = OPC_INB_REG_DEV;
4808
4809 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4810 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4811
4812 payload.phyid_portid =
4813 cpu_to_le32(((port->port_id) & 0xFF) |
4814 ((phy_id & 0xFF) << 8));
4815
4816 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4817 ((linkrate & 0x0F) << 24) |
4818 ((stp_sspsmp_sata & 0x03) << 28));
4819 payload.firstburstsize_ITNexustimeout =
4820 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4821
4822 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4823 SAS_ADDR_SIZE);
4824
4825 pm8001_dbg(pm8001_ha, INIT,
4826 "register device req phy_id 0x%x port_id 0x%x\n", phy_id,
4827 (port->port_id & 0xFF));
4828 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4829 sizeof(payload), 0);
4830 if (rc)
4831 pm8001_ccb_free(pm8001_ha, ccb);
4832
4833 return rc;
4834 }
4835
4836 /**
4837 * pm80xx_chip_phy_ctl_req - support the local phy operation
4838 * @pm8001_ha: our hba card information.
4839 * @phyId: the phy id which we wanted to operate
4840 * @phy_op: phy operation to request
4841 */
pm80xx_chip_phy_ctl_req(struct pm8001_hba_info * pm8001_ha,u32 phyId,u32 phy_op)4842 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4843 u32 phyId, u32 phy_op)
4844 {
4845 u32 tag;
4846 int rc;
4847 struct local_phy_ctl_req payload;
4848 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4849
4850 memset(&payload, 0, sizeof(payload));
4851 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4852 if (rc)
4853 return rc;
4854
4855 payload.tag = cpu_to_le32(tag);
4856 payload.phyop_phyid =
4857 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4858
4859 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4860 sizeof(payload), 0);
4861 if (rc)
4862 pm8001_tag_free(pm8001_ha, tag);
4863
4864 return rc;
4865 }
4866
pm80xx_chip_is_our_interrupt(struct pm8001_hba_info * pm8001_ha)4867 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4868 {
4869 u32 value;
4870
4871 if (pm8001_ha->use_msix)
4872 return 1;
4873
4874 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4875 if (value)
4876 return 1;
4877 return 0;
4878 }
4879
4880 /**
4881 * pm80xx_chip_isr - PM8001 isr handler.
4882 * @pm8001_ha: our hba card information.
4883 * @vec: irq number.
4884 */
4885 static irqreturn_t
pm80xx_chip_isr(struct pm8001_hba_info * pm8001_ha,u8 vec)4886 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4887 {
4888 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4889 pm8001_dbg(pm8001_ha, DEVIO,
4890 "irq vec %d, ODMR:0x%x\n",
4891 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4892 process_oq(pm8001_ha, vec);
4893 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4894 return IRQ_HANDLED;
4895 }
4896
mpi_set_phy_profile_req(struct pm8001_hba_info * pm8001_ha,u32 operation,u32 phyid,u32 length,u32 * buf)4897 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4898 u32 operation, u32 phyid,
4899 u32 length, u32 *buf)
4900 {
4901 u32 tag, i, j = 0;
4902 int rc;
4903 struct set_phy_profile_req payload;
4904 u32 opc = OPC_INB_SET_PHY_PROFILE;
4905
4906 memset(&payload, 0, sizeof(payload));
4907 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4908 if (rc) {
4909 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4910 return;
4911 }
4912
4913 payload.tag = cpu_to_le32(tag);
4914 payload.ppc_phyid =
4915 cpu_to_le32(((operation & 0xF) << 8) | (phyid & 0xFF));
4916 pm8001_dbg(pm8001_ha, DISC,
4917 " phy profile command for phy %x ,length is %d\n",
4918 le32_to_cpu(payload.ppc_phyid), length);
4919 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4920 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4921 j++;
4922 }
4923 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4924 sizeof(payload), 0);
4925 if (rc)
4926 pm8001_tag_free(pm8001_ha, tag);
4927 }
4928
pm8001_set_phy_profile(struct pm8001_hba_info * pm8001_ha,u32 length,u8 * buf)4929 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4930 u32 length, u8 *buf)
4931 {
4932 u32 i;
4933
4934 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4935 mpi_set_phy_profile_req(pm8001_ha,
4936 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4937 length = length + PHY_DWORD_LENGTH;
4938 }
4939 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
4940 }
4941
pm8001_set_phy_profile_single(struct pm8001_hba_info * pm8001_ha,u32 phy,u32 length,u32 * buf)4942 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4943 u32 phy, u32 length, u32 *buf)
4944 {
4945 u32 tag, opc;
4946 int rc, i;
4947 struct set_phy_profile_req payload;
4948
4949 memset(&payload, 0, sizeof(payload));
4950
4951 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4952 if (rc) {
4953 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
4954 return;
4955 }
4956
4957 opc = OPC_INB_SET_PHY_PROFILE;
4958
4959 payload.tag = cpu_to_le32(tag);
4960 payload.ppc_phyid =
4961 cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4962 | (phy & 0xFF));
4963
4964 for (i = 0; i < length; i++)
4965 payload.reserved[i] = cpu_to_le32(*(buf + i));
4966
4967 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4968 sizeof(payload), 0);
4969 if (rc)
4970 pm8001_tag_free(pm8001_ha, tag);
4971
4972 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
4973 }
4974 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4975 .name = "pmc80xx",
4976 .chip_init = pm80xx_chip_init,
4977 .chip_post_init = pm80xx_chip_post_init,
4978 .chip_soft_rst = pm80xx_chip_soft_rst,
4979 .chip_rst = pm80xx_hw_chip_rst,
4980 .chip_iounmap = pm8001_chip_iounmap,
4981 .isr = pm80xx_chip_isr,
4982 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
4983 .isr_process_oq = process_oq,
4984 .interrupt_enable = pm80xx_chip_interrupt_enable,
4985 .interrupt_disable = pm80xx_chip_interrupt_disable,
4986 .make_prd = pm8001_chip_make_sg,
4987 .smp_req = pm80xx_chip_smp_req,
4988 .ssp_io_req = pm80xx_chip_ssp_io_req,
4989 .sata_req = pm80xx_chip_sata_req,
4990 .phy_start_req = pm80xx_chip_phy_start_req,
4991 .phy_stop_req = pm80xx_chip_phy_stop_req,
4992 .reg_dev_req = pm80xx_chip_reg_dev_req,
4993 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4994 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4995 .task_abort = pm8001_chip_abort_task,
4996 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4997 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4998 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4999 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5000 .set_dev_state_req = pm8001_chip_set_dev_state_req,
5001 .fatal_errors = pm80xx_fatal_errors,
5002 .hw_event_ack_req = pm80xx_hw_event_ack_req,
5003 };
5004