1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
4 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
5 * Thomas Sailer <sailer@ife.ee.ethz.ch>
6 */
7
8 /* Power-Management-Code ( CONFIG_PM )
9 * for ens1371 only ( FIXME )
10 * derived from cs4281.c, atiixp.c and via82xx.c
11 * using https://www.kernel.org/doc/html/latest/sound/kernel-api/writing-an-alsa-driver.html
12 * by Kurt J. Bosch
13 */
14
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/gameport.h>
22 #include <linux/module.h>
23 #include <linux/mutex.h>
24
25 #include <sound/core.h>
26 #include <sound/control.h>
27 #include <sound/pcm.h>
28 #include <sound/rawmidi.h>
29 #ifdef CHIP1371
30 #include <sound/ac97_codec.h>
31 #else
32 #include <sound/ak4531_codec.h>
33 #endif
34 #include <sound/initval.h>
35 #include <sound/asoundef.h>
36
37 #ifndef CHIP1371
38 #undef CHIP1370
39 #define CHIP1370
40 #endif
41
42 #ifdef CHIP1370
43 #define DRIVER_NAME "ENS1370"
44 #define CHIP_NAME "ES1370" /* it can be ENS but just to keep compatibility... */
45 #else
46 #define DRIVER_NAME "ENS1371"
47 #define CHIP_NAME "ES1371"
48 #endif
49
50
51 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
52 MODULE_LICENSE("GPL");
53 #ifdef CHIP1370
54 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
55 #endif
56 #ifdef CHIP1371
57 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
58 #endif
59
60 #if IS_REACHABLE(CONFIG_GAMEPORT)
61 #define SUPPORT_JOYSTICK
62 #endif
63
64 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
65 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
66 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
67 #ifdef SUPPORT_JOYSTICK
68 #ifdef CHIP1371
69 static int joystick_port[SNDRV_CARDS];
70 #else
71 static bool joystick[SNDRV_CARDS];
72 #endif
73 #endif
74 #ifdef CHIP1371
75 static int spdif[SNDRV_CARDS];
76 static int lineio[SNDRV_CARDS];
77 #endif
78
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
85 #ifdef SUPPORT_JOYSTICK
86 #ifdef CHIP1371
87 module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
88 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
89 #else
90 module_param_array(joystick, bool, NULL, 0444);
91 MODULE_PARM_DESC(joystick, "Enable joystick.");
92 #endif
93 #endif /* SUPPORT_JOYSTICK */
94 #ifdef CHIP1371
95 module_param_array(spdif, int, NULL, 0444);
96 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
97 module_param_array(lineio, int, NULL, 0444);
98 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
99 #endif
100
101 /* ES1371 chip ID */
102 /* This is a little confusing because all ES1371 compatible chips have the
103 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
104 This is only significant if you want to enable features on the later parts.
105 Yes, I know it's stupid and why didn't we use the sub IDs?
106 */
107 #define ES1371REV_ES1373_A 0x04
108 #define ES1371REV_ES1373_B 0x06
109 #define ES1371REV_CT5880_A 0x07
110 #define CT5880REV_CT5880_C 0x02
111 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
112 #define CT5880REV_CT5880_E 0x04 /* mw */
113 #define ES1371REV_ES1371_B 0x09
114 #define EV1938REV_EV1938_A 0x00
115 #define ES1371REV_ES1373_8 0x08
116
117 /*
118 * Direct registers
119 */
120
121 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
122
123 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
124 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
125 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
126 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
127 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
128 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
129 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
130 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
131 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
132 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
133 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
134 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
135 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
136 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
137 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
138 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
139 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
140 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
141 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
142 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
143 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
144 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
145 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
146 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
147 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
148 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
149 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
150 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
151 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
152 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
153 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
154 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */
155 #define ES_BREQ (1<<7) /* memory bus request enable */
156 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
157 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
158 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */
159 #define ES_UART_EN (1<<3) /* UART enable */
160 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */
161 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
162 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
163 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
164 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
165 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
166 #define ES_INTR (1<<31) /* Interrupt is pending */
167 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
168 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
169 #define ES_1373_REAR_BIT26 (1<<26)
170 #define ES_1373_REAR_BIT24 (1<<24)
171 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
172 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
173 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
174 #define ES_1371_TEST (1<<16) /* test ASIC */
175 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
176 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
177 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */
178 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
179 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
180 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
181 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
182 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */
183 #define ES_MCCB (1<<4) /* CCB interrupt pending */
184 #define ES_UART (1<<3) /* UART interrupt pending */
185 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
186 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
187 #define ES_ADC (1<<0) /* ADC channel interrupt pending */
188 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
189 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
190 #define ES_RXINT (1<<7) /* RX interrupt occurred */
191 #define ES_TXINT (1<<2) /* TX interrupt occurred */
192 #define ES_TXRDY (1<<1) /* transmitter ready */
193 #define ES_RXRDY (1<<0) /* receiver ready */
194 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
195 #define ES_RXINTEN (1<<7) /* RX interrupt enable */
196 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
197 #define ES_TXINTENM (0x03<<5) /* mask for above */
198 #define ES_TXINTENI(i) (((i)>>5)&0x03)
199 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
200 #define ES_CNTRLM (0x03<<0) /* mask for above */
201 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
202 #define ES_TEST_MODE (1<<0) /* test mode enabled */
203 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
204 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
205 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
206 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
207 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
208 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
209 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
210 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */
211 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
212 #define EV_1938_CODEC_MAGIC (1<<26)
213 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
214 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
215 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
216 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
217
218 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
219 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
220 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
221 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
222 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
223 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
224 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
225 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
226 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
227 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
228 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
229 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
230 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
231
232 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
233 #define ES_1371_JFAST (1<<31) /* fast joystick timing */
234 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
235 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
236 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
237 #define ES_1371_VMPUM (0x03<<27) /* mask for above */
238 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
239 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
240 #define ES_1371_VCDCM (0x03<<25) /* mask for above */
241 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
242 #define ES_1371_FIRQ (1<<24) /* force an interrupt */
243 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
244 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
245 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
246 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
247 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
248 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
249 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
250 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
251 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
252 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
253 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
254 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
255
256 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
257
258 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
259 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
260 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
261 #define ES_P2_END_INCM (0x07<<19) /* mask for above */
262 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
263 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
264 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */
265 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
266 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
267 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
268 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
269 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
270 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
271 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
272 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
273 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
274 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
275 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
276 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
277 #define ES_R1_MODEM (0x03<<4) /* mask for above */
278 #define ES_R1_MODEI(i) (((i)>>4)&0x03)
279 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
280 #define ES_P2_MODEM (0x03<<2) /* mask for above */
281 #define ES_P2_MODEI(i) (((i)>>2)&0x03)
282 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
283 #define ES_P1_MODEM (0x03<<0) /* mask for above */
284 #define ES_P1_MODEI(i) (((i)>>0)&0x03)
285
286 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
287 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
288 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
289 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
290 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
291 #define ES_REG_COUNTM (0xffff<<0)
292 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
293
294 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
295 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
296 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
297 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
298 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
299 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
300 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
301 #define ES_REG_FCURR_COUNTM (0xffff<<16)
302 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
303 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
304 #define ES_REG_FSIZEM (0xffff<<0)
305 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
306 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
307 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
308
309 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
310 #define ES_REG_UF_VALID (1<<8)
311 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
312 #define ES_REG_UF_BYTEM (0xff<<0)
313 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
314
315
316 /*
317 * Pages
318 */
319
320 #define ES_PAGE_DAC 0x0c
321 #define ES_PAGE_ADC 0x0d
322 #define ES_PAGE_UART 0x0e
323 #define ES_PAGE_UART1 0x0f
324
325 /*
326 * Sample rate converter addresses
327 */
328
329 #define ES_SMPREG_DAC1 0x70
330 #define ES_SMPREG_DAC2 0x74
331 #define ES_SMPREG_ADC 0x78
332 #define ES_SMPREG_VOL_ADC 0x6c
333 #define ES_SMPREG_VOL_DAC1 0x7c
334 #define ES_SMPREG_VOL_DAC2 0x7e
335 #define ES_SMPREG_TRUNC_N 0x00
336 #define ES_SMPREG_INT_REGS 0x01
337 #define ES_SMPREG_ACCUM_FRAC 0x02
338 #define ES_SMPREG_VFREQ_FRAC 0x03
339
340 /*
341 * Some contants
342 */
343
344 #define ES_1370_SRCLOCK 1411200
345 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
346
347 /*
348 * Open modes
349 */
350
351 #define ES_MODE_PLAY1 0x0001
352 #define ES_MODE_PLAY2 0x0002
353 #define ES_MODE_CAPTURE 0x0004
354
355 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */
356 #define ES_MODE_INPUT 0x0002 /* for MIDI */
357
358 /*
359
360 */
361
362 struct ensoniq {
363 spinlock_t reg_lock;
364 struct mutex src_mutex;
365
366 int irq;
367
368 unsigned long playback1size;
369 unsigned long playback2size;
370 unsigned long capture3size;
371
372 unsigned long port;
373 unsigned int mode;
374 unsigned int uartm; /* UART mode */
375
376 unsigned int ctrl; /* control register */
377 unsigned int sctrl; /* serial control register */
378 unsigned int cssr; /* control status register */
379 unsigned int uartc; /* uart control register */
380 unsigned int rev; /* chip revision */
381
382 union {
383 #ifdef CHIP1371
384 struct {
385 struct snd_ac97 *ac97;
386 } es1371;
387 #else
388 struct {
389 int pclkdiv_lock;
390 struct snd_ak4531 *ak4531;
391 } es1370;
392 #endif
393 } u;
394
395 struct pci_dev *pci;
396 struct snd_card *card;
397 struct snd_pcm *pcm1; /* DAC1/ADC PCM */
398 struct snd_pcm *pcm2; /* DAC2 PCM */
399 struct snd_pcm_substream *playback1_substream;
400 struct snd_pcm_substream *playback2_substream;
401 struct snd_pcm_substream *capture_substream;
402 unsigned int p1_dma_size;
403 unsigned int p2_dma_size;
404 unsigned int c_dma_size;
405 unsigned int p1_period_size;
406 unsigned int p2_period_size;
407 unsigned int c_period_size;
408 struct snd_rawmidi *rmidi;
409 struct snd_rawmidi_substream *midi_input;
410 struct snd_rawmidi_substream *midi_output;
411
412 unsigned int spdif;
413 unsigned int spdif_default;
414 unsigned int spdif_stream;
415
416 #ifdef CHIP1370
417 struct snd_dma_buffer *dma_bug;
418 #endif
419
420 #ifdef SUPPORT_JOYSTICK
421 struct gameport *gameport;
422 #endif
423 };
424
425 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id);
426
427 static const struct pci_device_id snd_audiopci_ids[] = {
428 #ifdef CHIP1370
429 { PCI_VDEVICE(ENSONIQ, 0x5000), 0, }, /* ES1370 */
430 #endif
431 #ifdef CHIP1371
432 { PCI_VDEVICE(ENSONIQ, 0x1371), 0, }, /* ES1371 */
433 { PCI_VDEVICE(ENSONIQ, 0x5880), 0, }, /* ES1373 - CT5880 */
434 { PCI_VDEVICE(ECTIVA, 0x8938), 0, }, /* Ectiva EV1938 */
435 #endif
436 { 0, }
437 };
438
439 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
440
441 /*
442 * constants
443 */
444
445 #define POLL_COUNT 0xa000
446
447 #ifdef CHIP1370
448 static const unsigned int snd_es1370_fixed_rates[] =
449 {5512, 11025, 22050, 44100};
450 static const struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
451 .count = 4,
452 .list = snd_es1370_fixed_rates,
453 .mask = 0,
454 };
455 static const struct snd_ratnum es1370_clock = {
456 .num = ES_1370_SRCLOCK,
457 .den_min = 29,
458 .den_max = 353,
459 .den_step = 1,
460 };
461 static const struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
462 .nrats = 1,
463 .rats = &es1370_clock,
464 };
465 #else
466 static const struct snd_ratden es1371_dac_clock = {
467 .num_min = 3000 * (1 << 15),
468 .num_max = 48000 * (1 << 15),
469 .num_step = 3000,
470 .den = 1 << 15,
471 };
472 static const struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
473 .nrats = 1,
474 .rats = &es1371_dac_clock,
475 };
476 static const struct snd_ratnum es1371_adc_clock = {
477 .num = 48000 << 15,
478 .den_min = 32768,
479 .den_max = 393216,
480 .den_step = 1,
481 };
482 static const struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
483 .nrats = 1,
484 .rats = &es1371_adc_clock,
485 };
486 #endif
487 static const unsigned int snd_ensoniq_sample_shift[] =
488 {0, 1, 1, 2};
489
490 /*
491 * common I/O routines
492 */
493
494 #ifdef CHIP1371
495
snd_es1371_wait_src_ready(struct ensoniq * ensoniq)496 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
497 {
498 unsigned int t, r = 0;
499
500 for (t = 0; t < POLL_COUNT; t++) {
501 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
502 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
503 return r;
504 cond_resched();
505 }
506 dev_err(ensoniq->card->dev, "wait src ready timeout 0x%lx [0x%x]\n",
507 ES_REG(ensoniq, 1371_SMPRATE), r);
508 return 0;
509 }
510
snd_es1371_src_read(struct ensoniq * ensoniq,unsigned short reg)511 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
512 {
513 unsigned int temp, i, orig, r;
514
515 /* wait for ready */
516 temp = orig = snd_es1371_wait_src_ready(ensoniq);
517
518 /* expose the SRC state bits */
519 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
520 ES_1371_DIS_P2 | ES_1371_DIS_R1);
521 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
522 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
523
524 /* now, wait for busy and the correct time to read */
525 temp = snd_es1371_wait_src_ready(ensoniq);
526
527 if ((temp & 0x00870000) != 0x00010000) {
528 /* wait for the right state */
529 for (i = 0; i < POLL_COUNT; i++) {
530 temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
531 if ((temp & 0x00870000) == 0x00010000)
532 break;
533 }
534 }
535
536 /* hide the state bits */
537 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
538 ES_1371_DIS_P2 | ES_1371_DIS_R1);
539 r |= ES_1371_SRC_RAM_ADDRO(reg);
540 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
541
542 return temp;
543 }
544
snd_es1371_src_write(struct ensoniq * ensoniq,unsigned short reg,unsigned short data)545 static void snd_es1371_src_write(struct ensoniq * ensoniq,
546 unsigned short reg, unsigned short data)
547 {
548 unsigned int r;
549
550 r = snd_es1371_wait_src_ready(ensoniq) &
551 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
552 ES_1371_DIS_P2 | ES_1371_DIS_R1);
553 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
554 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
555 }
556
557 #endif /* CHIP1371 */
558
559 #ifdef CHIP1370
560
snd_es1370_codec_write(struct snd_ak4531 * ak4531,unsigned short reg,unsigned short val)561 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
562 unsigned short reg, unsigned short val)
563 {
564 struct ensoniq *ensoniq = ak4531->private_data;
565 unsigned long end_time = jiffies + HZ / 10;
566
567 #if 0
568 dev_dbg(ensoniq->card->dev,
569 "CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
570 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
571 #endif
572 do {
573 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
574 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
575 return;
576 }
577 schedule_timeout_uninterruptible(1);
578 } while (time_after(end_time, jiffies));
579 dev_err(ensoniq->card->dev, "codec write timeout, status = 0x%x\n",
580 inl(ES_REG(ensoniq, STATUS)));
581 }
582
583 #endif /* CHIP1370 */
584
585 #ifdef CHIP1371
586
is_ev1938(struct ensoniq * ensoniq)587 static inline bool is_ev1938(struct ensoniq *ensoniq)
588 {
589 return ensoniq->pci->device == 0x8938;
590 }
591
snd_es1371_codec_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)592 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
593 unsigned short reg, unsigned short val)
594 {
595 struct ensoniq *ensoniq = ac97->private_data;
596 unsigned int t, x, flag;
597
598 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
599 guard(mutex)(&ensoniq->src_mutex);
600 for (t = 0; t < POLL_COUNT; t++) {
601 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
602 /* save the current state for latter */
603 x = snd_es1371_wait_src_ready(ensoniq);
604 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
605 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
606 ES_REG(ensoniq, 1371_SMPRATE));
607 /* wait for not busy (state 0) first to avoid
608 transition states */
609 for (t = 0; t < POLL_COUNT; t++) {
610 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
611 0x00000000)
612 break;
613 }
614 /* wait for a SAFE time to write addr/data and then do it, dammit */
615 for (t = 0; t < POLL_COUNT; t++) {
616 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
617 0x00010000)
618 break;
619 }
620 outl(ES_1371_CODEC_WRITE(reg, val) | flag,
621 ES_REG(ensoniq, 1371_CODEC));
622 /* restore SRC reg */
623 snd_es1371_wait_src_ready(ensoniq);
624 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
625 return;
626 }
627 }
628 dev_err(ensoniq->card->dev, "codec write timeout at 0x%lx [0x%x]\n",
629 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
630 }
631
snd_es1371_codec_read(struct snd_ac97 * ac97,unsigned short reg)632 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
633 unsigned short reg)
634 {
635 struct ensoniq *ensoniq = ac97->private_data;
636 unsigned int t, x, flag, fail = 0;
637
638 flag = is_ev1938(ensoniq) ? EV_1938_CODEC_MAGIC : 0;
639 __again:
640 mutex_lock(&ensoniq->src_mutex);
641 for (t = 0; t < POLL_COUNT; t++) {
642 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
643 /* save the current state for latter */
644 x = snd_es1371_wait_src_ready(ensoniq);
645 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
646 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
647 ES_REG(ensoniq, 1371_SMPRATE));
648 /* wait for not busy (state 0) first to avoid
649 transition states */
650 for (t = 0; t < POLL_COUNT; t++) {
651 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
652 0x00000000)
653 break;
654 }
655 /* wait for a SAFE time to write addr/data and then do it, dammit */
656 for (t = 0; t < POLL_COUNT; t++) {
657 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
658 0x00010000)
659 break;
660 }
661 outl(ES_1371_CODEC_READS(reg) | flag,
662 ES_REG(ensoniq, 1371_CODEC));
663 /* restore SRC reg */
664 snd_es1371_wait_src_ready(ensoniq);
665 outl(x, ES_REG(ensoniq, 1371_SMPRATE));
666 /* wait for WIP again */
667 for (t = 0; t < POLL_COUNT; t++) {
668 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
669 break;
670 }
671 /* now wait for the stinkin' data (RDY) */
672 for (t = 0; t < POLL_COUNT; t++) {
673 x = inl(ES_REG(ensoniq, 1371_CODEC));
674 if (x & ES_1371_CODEC_RDY) {
675 if (is_ev1938(ensoniq)) {
676 for (t = 0; t < 100; t++)
677 inl(ES_REG(ensoniq, CONTROL));
678 x = inl(ES_REG(ensoniq, 1371_CODEC));
679 }
680 mutex_unlock(&ensoniq->src_mutex);
681 return ES_1371_CODEC_READ(x);
682 }
683 }
684 mutex_unlock(&ensoniq->src_mutex);
685 if (++fail > 10) {
686 dev_err(ensoniq->card->dev,
687 "codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n",
688 ES_REG(ensoniq, 1371_CODEC), reg,
689 inl(ES_REG(ensoniq, 1371_CODEC)));
690 return 0;
691 }
692 goto __again;
693 }
694 }
695 mutex_unlock(&ensoniq->src_mutex);
696 dev_err(ensoniq->card->dev, "codec read timeout at 0x%lx [0x%x]\n",
697 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
698 return 0;
699 }
700
snd_es1371_codec_wait(struct snd_ac97 * ac97)701 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
702 {
703 msleep(750);
704 snd_es1371_codec_read(ac97, AC97_RESET);
705 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
706 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
707 msleep(50);
708 }
709
snd_es1371_adc_rate(struct ensoniq * ensoniq,unsigned int rate)710 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
711 {
712 unsigned int n, truncm, freq;
713
714 guard(mutex)(&ensoniq->src_mutex);
715 n = rate / 3000;
716 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
717 n--;
718 truncm = (21 * n - 1) | 1;
719 freq = ((48000UL << 15) / rate) * n;
720 if (rate >= 24000) {
721 if (truncm > 239)
722 truncm = 239;
723 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
724 (((239 - truncm) >> 1) << 9) | (n << 4));
725 } else {
726 if (truncm > 119)
727 truncm = 119;
728 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
729 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
730 }
731 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
732 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
733 ES_SMPREG_INT_REGS) & 0x00ff) |
734 ((freq >> 5) & 0xfc00));
735 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
736 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
737 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
738 }
739
snd_es1371_dac1_rate(struct ensoniq * ensoniq,unsigned int rate)740 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
741 {
742 unsigned int freq, r;
743
744 guard(mutex)(&ensoniq->src_mutex);
745 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
746 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
747 ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
748 ES_1371_DIS_P1;
749 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
750 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
751 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
752 ES_SMPREG_INT_REGS) & 0x00ff) |
753 ((freq >> 5) & 0xfc00));
754 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
755 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
756 ES_1371_DIS_P2 | ES_1371_DIS_R1));
757 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
758 }
759
snd_es1371_dac2_rate(struct ensoniq * ensoniq,unsigned int rate)760 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
761 {
762 unsigned int freq, r;
763
764 guard(mutex)(&ensoniq->src_mutex);
765 freq = DIV_ROUND_CLOSEST(rate << 15, 3000);
766 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
767 ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
768 ES_1371_DIS_P2;
769 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
770 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
771 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
772 ES_SMPREG_INT_REGS) & 0x00ff) |
773 ((freq >> 5) & 0xfc00));
774 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
775 freq & 0x7fff);
776 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
777 ES_1371_DIS_P1 | ES_1371_DIS_R1));
778 outl(r, ES_REG(ensoniq, 1371_SMPRATE));
779 }
780
781 #endif /* CHIP1371 */
782
snd_ensoniq_trigger(struct snd_pcm_substream * substream,int cmd)783 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
784 {
785 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
786 switch (cmd) {
787 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
788 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
789 {
790 unsigned int what = 0;
791 struct snd_pcm_substream *s;
792 snd_pcm_group_for_each_entry(s, substream) {
793 if (s == ensoniq->playback1_substream) {
794 what |= ES_P1_PAUSE;
795 snd_pcm_trigger_done(s, substream);
796 } else if (s == ensoniq->playback2_substream) {
797 what |= ES_P2_PAUSE;
798 snd_pcm_trigger_done(s, substream);
799 } else if (s == ensoniq->capture_substream)
800 return -EINVAL;
801 }
802 scoped_guard(spinlock, &ensoniq->reg_lock) {
803 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
804 ensoniq->sctrl |= what;
805 else
806 ensoniq->sctrl &= ~what;
807 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
808 }
809 break;
810 }
811 case SNDRV_PCM_TRIGGER_START:
812 case SNDRV_PCM_TRIGGER_STOP:
813 {
814 unsigned int what = 0;
815 struct snd_pcm_substream *s;
816 snd_pcm_group_for_each_entry(s, substream) {
817 if (s == ensoniq->playback1_substream) {
818 what |= ES_DAC1_EN;
819 snd_pcm_trigger_done(s, substream);
820 } else if (s == ensoniq->playback2_substream) {
821 what |= ES_DAC2_EN;
822 snd_pcm_trigger_done(s, substream);
823 } else if (s == ensoniq->capture_substream) {
824 what |= ES_ADC_EN;
825 snd_pcm_trigger_done(s, substream);
826 }
827 }
828 scoped_guard(spinlock, &ensoniq->reg_lock) {
829 if (cmd == SNDRV_PCM_TRIGGER_START)
830 ensoniq->ctrl |= what;
831 else
832 ensoniq->ctrl &= ~what;
833 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
834 }
835 break;
836 }
837 default:
838 return -EINVAL;
839 }
840 return 0;
841 }
842
843 /*
844 * PCM part
845 */
846
snd_ensoniq_playback1_prepare(struct snd_pcm_substream * substream)847 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
848 {
849 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
850 struct snd_pcm_runtime *runtime = substream->runtime;
851 unsigned int mode = 0;
852
853 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
854 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
855 if (snd_pcm_format_width(runtime->format) == 16)
856 mode |= 0x02;
857 if (runtime->channels > 1)
858 mode |= 0x01;
859 scoped_guard(spinlock_irq, &ensoniq->reg_lock) {
860 ensoniq->ctrl &= ~ES_DAC1_EN;
861 #ifdef CHIP1371
862 /* 48k doesn't need SRC (it breaks AC3-passthru) */
863 if (runtime->rate == 48000)
864 ensoniq->ctrl |= ES_1373_BYPASS_P1;
865 else
866 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
867 #endif
868 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
869 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
870 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
871 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
872 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
873 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
874 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
875 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
876 ES_REG(ensoniq, DAC1_COUNT));
877 #ifdef CHIP1370
878 ensoniq->ctrl &= ~ES_1370_WTSRSELM;
879 switch (runtime->rate) {
880 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
881 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
882 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
883 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
884 default: snd_BUG();
885 }
886 #endif
887 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
888 }
889 #ifndef CHIP1370
890 snd_es1371_dac1_rate(ensoniq, runtime->rate);
891 #endif
892 return 0;
893 }
894
snd_ensoniq_playback2_prepare(struct snd_pcm_substream * substream)895 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
896 {
897 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
898 struct snd_pcm_runtime *runtime = substream->runtime;
899 unsigned int mode = 0;
900
901 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
902 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
903 if (snd_pcm_format_width(runtime->format) == 16)
904 mode |= 0x02;
905 if (runtime->channels > 1)
906 mode |= 0x01;
907 scoped_guard(spinlock_irq, &ensoniq->reg_lock) {
908 ensoniq->ctrl &= ~ES_DAC2_EN;
909 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
910 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
911 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
912 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
913 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
914 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
915 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
916 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
917 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
918 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
919 ES_REG(ensoniq, DAC2_COUNT));
920 #ifdef CHIP1370
921 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
922 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
923 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
924 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
925 }
926 #endif
927 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
928 }
929 #ifndef CHIP1370
930 snd_es1371_dac2_rate(ensoniq, runtime->rate);
931 #endif
932 return 0;
933 }
934
snd_ensoniq_capture_prepare(struct snd_pcm_substream * substream)935 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
936 {
937 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
938 struct snd_pcm_runtime *runtime = substream->runtime;
939 unsigned int mode = 0;
940
941 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
942 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
943 if (snd_pcm_format_width(runtime->format) == 16)
944 mode |= 0x02;
945 if (runtime->channels > 1)
946 mode |= 0x01;
947 scoped_guard(spinlock_irq, &ensoniq->reg_lock) {
948 ensoniq->ctrl &= ~ES_ADC_EN;
949 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
950 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
951 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
952 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
953 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
954 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
955 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
956 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
957 ES_REG(ensoniq, ADC_COUNT));
958 #ifdef CHIP1370
959 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
960 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
961 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
962 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
963 }
964 #endif
965 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
966 }
967 #ifndef CHIP1370
968 snd_es1371_adc_rate(ensoniq, runtime->rate);
969 #endif
970 return 0;
971 }
972
snd_ensoniq_playback1_pointer(struct snd_pcm_substream * substream)973 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
974 {
975 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
976 size_t ptr;
977
978 guard(spinlock)(&ensoniq->reg_lock);
979 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
980 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
981 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
982 return bytes_to_frames(substream->runtime, ptr);
983 } else {
984 return 0;
985 }
986 }
987
snd_ensoniq_playback2_pointer(struct snd_pcm_substream * substream)988 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
989 {
990 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
991 size_t ptr;
992
993 guard(spinlock)(&ensoniq->reg_lock);
994 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
995 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
996 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
997 return bytes_to_frames(substream->runtime, ptr);
998 } else {
999 return 0;
1000 }
1001 }
1002
snd_ensoniq_capture_pointer(struct snd_pcm_substream * substream)1003 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1004 {
1005 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1006 size_t ptr;
1007
1008 guard(spinlock)(&ensoniq->reg_lock);
1009 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1010 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1011 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1012 return bytes_to_frames(substream->runtime, ptr);
1013 } else {
1014 return 0;
1015 }
1016 }
1017
1018 static const struct snd_pcm_hardware snd_ensoniq_playback1 =
1019 {
1020 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1021 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1022 SNDRV_PCM_INFO_MMAP_VALID |
1023 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1024 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1025 .rates =
1026 #ifndef CHIP1370
1027 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1028 #else
1029 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */
1030 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1031 SNDRV_PCM_RATE_44100),
1032 #endif
1033 .rate_min = 4000,
1034 .rate_max = 48000,
1035 .channels_min = 1,
1036 .channels_max = 2,
1037 .buffer_bytes_max = (128*1024),
1038 .period_bytes_min = 64,
1039 .period_bytes_max = (128*1024),
1040 .periods_min = 1,
1041 .periods_max = 1024,
1042 .fifo_size = 0,
1043 };
1044
1045 static const struct snd_pcm_hardware snd_ensoniq_playback2 =
1046 {
1047 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1048 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1049 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1050 SNDRV_PCM_INFO_SYNC_START),
1051 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1052 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1053 .rate_min = 4000,
1054 .rate_max = 48000,
1055 .channels_min = 1,
1056 .channels_max = 2,
1057 .buffer_bytes_max = (128*1024),
1058 .period_bytes_min = 64,
1059 .period_bytes_max = (128*1024),
1060 .periods_min = 1,
1061 .periods_max = 1024,
1062 .fifo_size = 0,
1063 };
1064
1065 static const struct snd_pcm_hardware snd_ensoniq_capture =
1066 {
1067 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1068 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1069 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1070 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1071 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1072 .rate_min = 4000,
1073 .rate_max = 48000,
1074 .channels_min = 1,
1075 .channels_max = 2,
1076 .buffer_bytes_max = (128*1024),
1077 .period_bytes_min = 64,
1078 .period_bytes_max = (128*1024),
1079 .periods_min = 1,
1080 .periods_max = 1024,
1081 .fifo_size = 0,
1082 };
1083
snd_ensoniq_playback1_open(struct snd_pcm_substream * substream)1084 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1085 {
1086 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1087 struct snd_pcm_runtime *runtime = substream->runtime;
1088
1089 ensoniq->mode |= ES_MODE_PLAY1;
1090 ensoniq->playback1_substream = substream;
1091 runtime->hw = snd_ensoniq_playback1;
1092 snd_pcm_set_sync(substream);
1093 scoped_guard(spinlock_irq, &ensoniq->reg_lock) {
1094 if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1095 ensoniq->spdif_stream = ensoniq->spdif_default;
1096 }
1097 #ifdef CHIP1370
1098 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1099 &snd_es1370_hw_constraints_rates);
1100 #else
1101 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1102 &snd_es1371_hw_constraints_dac_clock);
1103 #endif
1104 return 0;
1105 }
1106
snd_ensoniq_playback2_open(struct snd_pcm_substream * substream)1107 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1108 {
1109 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1110 struct snd_pcm_runtime *runtime = substream->runtime;
1111
1112 ensoniq->mode |= ES_MODE_PLAY2;
1113 ensoniq->playback2_substream = substream;
1114 runtime->hw = snd_ensoniq_playback2;
1115 snd_pcm_set_sync(substream);
1116 scoped_guard(spinlock_irq, &ensoniq->reg_lock) {
1117 if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1118 ensoniq->spdif_stream = ensoniq->spdif_default;
1119 }
1120 #ifdef CHIP1370
1121 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1122 &snd_es1370_hw_constraints_clock);
1123 #else
1124 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1125 &snd_es1371_hw_constraints_dac_clock);
1126 #endif
1127 return 0;
1128 }
1129
snd_ensoniq_capture_open(struct snd_pcm_substream * substream)1130 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1131 {
1132 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1133 struct snd_pcm_runtime *runtime = substream->runtime;
1134
1135 ensoniq->mode |= ES_MODE_CAPTURE;
1136 ensoniq->capture_substream = substream;
1137 runtime->hw = snd_ensoniq_capture;
1138 snd_pcm_set_sync(substream);
1139 #ifdef CHIP1370
1140 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1141 &snd_es1370_hw_constraints_clock);
1142 #else
1143 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1144 &snd_es1371_hw_constraints_adc_clock);
1145 #endif
1146 return 0;
1147 }
1148
snd_ensoniq_playback1_close(struct snd_pcm_substream * substream)1149 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1150 {
1151 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1152
1153 ensoniq->playback1_substream = NULL;
1154 ensoniq->mode &= ~ES_MODE_PLAY1;
1155 return 0;
1156 }
1157
snd_ensoniq_playback2_close(struct snd_pcm_substream * substream)1158 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1159 {
1160 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1161
1162 ensoniq->playback2_substream = NULL;
1163 guard(spinlock_irq)(&ensoniq->reg_lock);
1164 #ifdef CHIP1370
1165 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1166 #endif
1167 ensoniq->mode &= ~ES_MODE_PLAY2;
1168 return 0;
1169 }
1170
snd_ensoniq_capture_close(struct snd_pcm_substream * substream)1171 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1172 {
1173 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1174
1175 ensoniq->capture_substream = NULL;
1176 guard(spinlock_irq)(&ensoniq->reg_lock);
1177 #ifdef CHIP1370
1178 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1179 #endif
1180 ensoniq->mode &= ~ES_MODE_CAPTURE;
1181 return 0;
1182 }
1183
1184 static const struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1185 .open = snd_ensoniq_playback1_open,
1186 .close = snd_ensoniq_playback1_close,
1187 .prepare = snd_ensoniq_playback1_prepare,
1188 .trigger = snd_ensoniq_trigger,
1189 .pointer = snd_ensoniq_playback1_pointer,
1190 };
1191
1192 static const struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1193 .open = snd_ensoniq_playback2_open,
1194 .close = snd_ensoniq_playback2_close,
1195 .prepare = snd_ensoniq_playback2_prepare,
1196 .trigger = snd_ensoniq_trigger,
1197 .pointer = snd_ensoniq_playback2_pointer,
1198 };
1199
1200 static const struct snd_pcm_ops snd_ensoniq_capture_ops = {
1201 .open = snd_ensoniq_capture_open,
1202 .close = snd_ensoniq_capture_close,
1203 .prepare = snd_ensoniq_capture_prepare,
1204 .trigger = snd_ensoniq_trigger,
1205 .pointer = snd_ensoniq_capture_pointer,
1206 };
1207
1208 static const struct snd_pcm_chmap_elem surround_map[] = {
1209 { .channels = 1,
1210 .map = { SNDRV_CHMAP_MONO } },
1211 { .channels = 2,
1212 .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
1213 { }
1214 };
1215
snd_ensoniq_pcm(struct ensoniq * ensoniq,int device)1216 static int snd_ensoniq_pcm(struct ensoniq *ensoniq, int device)
1217 {
1218 struct snd_pcm *pcm;
1219 int err;
1220
1221 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/1", device, 1, 1, &pcm);
1222 if (err < 0)
1223 return err;
1224
1225 #ifdef CHIP1370
1226 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1227 #else
1228 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1229 #endif
1230 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1231
1232 pcm->private_data = ensoniq;
1233 pcm->info_flags = 0;
1234 strscpy(pcm->name, CHIP_NAME " DAC2/ADC");
1235 ensoniq->pcm1 = pcm;
1236
1237 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1238 &ensoniq->pci->dev, 64*1024, 128*1024);
1239
1240 #ifdef CHIP1370
1241 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1242 surround_map, 2, 0, NULL);
1243 #else
1244 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1245 snd_pcm_std_chmaps, 2, 0, NULL);
1246 #endif
1247 return err;
1248 }
1249
snd_ensoniq_pcm2(struct ensoniq * ensoniq,int device)1250 static int snd_ensoniq_pcm2(struct ensoniq *ensoniq, int device)
1251 {
1252 struct snd_pcm *pcm;
1253 int err;
1254
1255 err = snd_pcm_new(ensoniq->card, CHIP_NAME "/2", device, 1, 0, &pcm);
1256 if (err < 0)
1257 return err;
1258
1259 #ifdef CHIP1370
1260 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1261 #else
1262 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1263 #endif
1264 pcm->private_data = ensoniq;
1265 pcm->info_flags = 0;
1266 strscpy(pcm->name, CHIP_NAME " DAC1");
1267 ensoniq->pcm2 = pcm;
1268
1269 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
1270 &ensoniq->pci->dev, 64*1024, 128*1024);
1271
1272 #ifdef CHIP1370
1273 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1274 snd_pcm_std_chmaps, 2, 0, NULL);
1275 #else
1276 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1277 surround_map, 2, 0, NULL);
1278 #endif
1279 return err;
1280 }
1281
1282 /*
1283 * Mixer section
1284 */
1285
1286 /*
1287 * ENS1371 mixer (including SPDIF interface)
1288 */
1289 #ifdef CHIP1371
snd_ens1373_spdif_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1290 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1291 struct snd_ctl_elem_info *uinfo)
1292 {
1293 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1294 uinfo->count = 1;
1295 return 0;
1296 }
1297
snd_ens1373_spdif_default_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1298 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1299 struct snd_ctl_elem_value *ucontrol)
1300 {
1301 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1302
1303 guard(spinlock_irq)(&ensoniq->reg_lock);
1304 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1305 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1306 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1307 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1308 return 0;
1309 }
1310
snd_ens1373_spdif_default_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1311 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1312 struct snd_ctl_elem_value *ucontrol)
1313 {
1314 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1315 unsigned int val;
1316 int change;
1317
1318 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1319 ((u32)ucontrol->value.iec958.status[1] << 8) |
1320 ((u32)ucontrol->value.iec958.status[2] << 16) |
1321 ((u32)ucontrol->value.iec958.status[3] << 24);
1322 guard(spinlock_irq)(&ensoniq->reg_lock);
1323 change = ensoniq->spdif_default != val;
1324 ensoniq->spdif_default = val;
1325 if (change && ensoniq->playback1_substream == NULL &&
1326 ensoniq->playback2_substream == NULL)
1327 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1328 return change;
1329 }
1330
snd_ens1373_spdif_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1331 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1332 struct snd_ctl_elem_value *ucontrol)
1333 {
1334 ucontrol->value.iec958.status[0] = 0xff;
1335 ucontrol->value.iec958.status[1] = 0xff;
1336 ucontrol->value.iec958.status[2] = 0xff;
1337 ucontrol->value.iec958.status[3] = 0xff;
1338 return 0;
1339 }
1340
snd_ens1373_spdif_stream_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1341 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1342 struct snd_ctl_elem_value *ucontrol)
1343 {
1344 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1345
1346 guard(spinlock_irq)(&ensoniq->reg_lock);
1347 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1348 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1349 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1350 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1351 return 0;
1352 }
1353
snd_ens1373_spdif_stream_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1354 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1355 struct snd_ctl_elem_value *ucontrol)
1356 {
1357 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1358 unsigned int val;
1359 int change;
1360
1361 val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1362 ((u32)ucontrol->value.iec958.status[1] << 8) |
1363 ((u32)ucontrol->value.iec958.status[2] << 16) |
1364 ((u32)ucontrol->value.iec958.status[3] << 24);
1365 guard(spinlock_irq)(&ensoniq->reg_lock);
1366 change = ensoniq->spdif_stream != val;
1367 ensoniq->spdif_stream = val;
1368 if (change && (ensoniq->playback1_substream != NULL ||
1369 ensoniq->playback2_substream != NULL))
1370 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1371 return change;
1372 }
1373
1374 #define ES1371_SPDIF(xname) \
1375 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1376 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1377
1378 #define snd_es1371_spdif_info snd_ctl_boolean_mono_info
1379
snd_es1371_spdif_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1380 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1381 struct snd_ctl_elem_value *ucontrol)
1382 {
1383 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1384
1385 guard(spinlock_irq)(&ensoniq->reg_lock);
1386 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1387 return 0;
1388 }
1389
snd_es1371_spdif_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1390 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1391 struct snd_ctl_elem_value *ucontrol)
1392 {
1393 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1394 unsigned int nval1, nval2;
1395 int change;
1396
1397 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1398 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1399 guard(spinlock_irq)(&ensoniq->reg_lock);
1400 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1401 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1402 ensoniq->ctrl |= nval1;
1403 ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1404 ensoniq->cssr |= nval2;
1405 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1406 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1407 return change;
1408 }
1409
1410
1411 /* spdif controls */
1412 static const struct snd_kcontrol_new snd_es1371_mixer_spdif[] = {
1413 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1414 {
1415 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1416 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1417 .info = snd_ens1373_spdif_info,
1418 .get = snd_ens1373_spdif_default_get,
1419 .put = snd_ens1373_spdif_default_put,
1420 },
1421 {
1422 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1423 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1424 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1425 .info = snd_ens1373_spdif_info,
1426 .get = snd_ens1373_spdif_mask_get
1427 },
1428 {
1429 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1430 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1431 .info = snd_ens1373_spdif_info,
1432 .get = snd_ens1373_spdif_stream_get,
1433 .put = snd_ens1373_spdif_stream_put
1434 },
1435 };
1436
1437
1438 #define snd_es1373_rear_info snd_ctl_boolean_mono_info
1439
snd_es1373_rear_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1440 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1441 struct snd_ctl_elem_value *ucontrol)
1442 {
1443 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1444 int val = 0;
1445
1446 guard(spinlock_irq)(&ensoniq->reg_lock);
1447 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1448 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1449 val = 1;
1450 ucontrol->value.integer.value[0] = val;
1451 return 0;
1452 }
1453
snd_es1373_rear_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1454 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1455 struct snd_ctl_elem_value *ucontrol)
1456 {
1457 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1458 unsigned int nval1;
1459 int change;
1460
1461 nval1 = ucontrol->value.integer.value[0] ?
1462 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1463 guard(spinlock_irq)(&ensoniq->reg_lock);
1464 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1465 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1466 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1467 ensoniq->cssr |= nval1;
1468 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1469 return change;
1470 }
1471
1472 static const struct snd_kcontrol_new snd_ens1373_rear =
1473 {
1474 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1475 .name = "AC97 2ch->4ch Copy Switch",
1476 .info = snd_es1373_rear_info,
1477 .get = snd_es1373_rear_get,
1478 .put = snd_es1373_rear_put,
1479 };
1480
1481 #define snd_es1373_line_info snd_ctl_boolean_mono_info
1482
snd_es1373_line_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1483 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1484 struct snd_ctl_elem_value *ucontrol)
1485 {
1486 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1487 int val = 0;
1488
1489 guard(spinlock_irq)(&ensoniq->reg_lock);
1490 if (ensoniq->ctrl & ES_1371_GPIO_OUT(4))
1491 val = 1;
1492 ucontrol->value.integer.value[0] = val;
1493 return 0;
1494 }
1495
snd_es1373_line_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1496 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1497 struct snd_ctl_elem_value *ucontrol)
1498 {
1499 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1500 int changed;
1501 unsigned int ctrl;
1502
1503 guard(spinlock_irq)(&ensoniq->reg_lock);
1504 ctrl = ensoniq->ctrl;
1505 if (ucontrol->value.integer.value[0])
1506 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1507 else
1508 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1509 changed = (ctrl != ensoniq->ctrl);
1510 if (changed)
1511 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1512 return changed;
1513 }
1514
1515 static const struct snd_kcontrol_new snd_ens1373_line =
1516 {
1517 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1518 .name = "Line In->Rear Out Switch",
1519 .info = snd_es1373_line_info,
1520 .get = snd_es1373_line_get,
1521 .put = snd_es1373_line_put,
1522 };
1523
snd_ensoniq_mixer_free_ac97(struct snd_ac97 * ac97)1524 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1525 {
1526 struct ensoniq *ensoniq = ac97->private_data;
1527 ensoniq->u.es1371.ac97 = NULL;
1528 }
1529
1530 struct es1371_quirk {
1531 unsigned short vid; /* vendor ID */
1532 unsigned short did; /* device ID */
1533 unsigned char rev; /* revision */
1534 };
1535
es1371_quirk_lookup(struct ensoniq * ensoniq,const struct es1371_quirk * list)1536 static int es1371_quirk_lookup(struct ensoniq *ensoniq,
1537 const struct es1371_quirk *list)
1538 {
1539 while (list->vid != (unsigned short)PCI_ANY_ID) {
1540 if (ensoniq->pci->vendor == list->vid &&
1541 ensoniq->pci->device == list->did &&
1542 ensoniq->rev == list->rev)
1543 return 1;
1544 list++;
1545 }
1546 return 0;
1547 }
1548
1549 static const struct es1371_quirk es1371_spdif_present[] = {
1550 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1551 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1552 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1553 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1554 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1555 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1556 };
1557
1558 static const struct snd_pci_quirk ens1373_line_quirk[] = {
1559 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */
1560 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */
1561 { } /* end */
1562 };
1563
snd_ensoniq_1371_mixer(struct ensoniq * ensoniq,int has_spdif,int has_line)1564 static int snd_ensoniq_1371_mixer(struct ensoniq *ensoniq,
1565 int has_spdif, int has_line)
1566 {
1567 struct snd_card *card = ensoniq->card;
1568 struct snd_ac97_bus *pbus;
1569 struct snd_ac97_template ac97;
1570 int err;
1571 static const struct snd_ac97_bus_ops ops = {
1572 .write = snd_es1371_codec_write,
1573 .read = snd_es1371_codec_read,
1574 .wait = snd_es1371_codec_wait,
1575 };
1576
1577 err = snd_ac97_bus(card, 0, &ops, NULL, &pbus);
1578 if (err < 0)
1579 return err;
1580
1581 memset(&ac97, 0, sizeof(ac97));
1582 ac97.private_data = ensoniq;
1583 ac97.private_free = snd_ensoniq_mixer_free_ac97;
1584 ac97.pci = ensoniq->pci;
1585 ac97.scaps = AC97_SCAP_AUDIO;
1586 err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97);
1587 if (err < 0)
1588 return err;
1589 if (has_spdif > 0 ||
1590 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) {
1591 struct snd_kcontrol *kctl;
1592 int i, is_spdif = 0;
1593
1594 ensoniq->spdif_default = ensoniq->spdif_stream =
1595 SNDRV_PCM_DEFAULT_CON_SPDIF;
1596 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1597
1598 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1599 is_spdif++;
1600
1601 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1602 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1603 if (!kctl)
1604 return -ENOMEM;
1605 kctl->id.index = is_spdif;
1606 err = snd_ctl_add(card, kctl);
1607 if (err < 0)
1608 return err;
1609 }
1610 }
1611 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1612 /* mirror rear to front speakers */
1613 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1614 ensoniq->cssr |= ES_1373_REAR_BIT26;
1615 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1616 if (err < 0)
1617 return err;
1618 }
1619 if (has_line > 0 ||
1620 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) {
1621 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line,
1622 ensoniq));
1623 if (err < 0)
1624 return err;
1625 }
1626
1627 return 0;
1628 }
1629
1630 #endif /* CHIP1371 */
1631
1632 /* generic control callbacks for ens1370 */
1633 #ifdef CHIP1370
1634 #define ENSONIQ_CONTROL(xname, mask) \
1635 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1636 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1637 .private_value = mask }
1638
1639 #define snd_ensoniq_control_info snd_ctl_boolean_mono_info
1640
snd_ensoniq_control_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1641 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1642 struct snd_ctl_elem_value *ucontrol)
1643 {
1644 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1645 int mask = kcontrol->private_value;
1646
1647 guard(spinlock_irq)(&ensoniq->reg_lock);
1648 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1649 return 0;
1650 }
1651
snd_ensoniq_control_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1652 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1653 struct snd_ctl_elem_value *ucontrol)
1654 {
1655 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1656 int mask = kcontrol->private_value;
1657 unsigned int nval;
1658 int change;
1659
1660 nval = ucontrol->value.integer.value[0] ? mask : 0;
1661 guard(spinlock_irq)(&ensoniq->reg_lock);
1662 change = (ensoniq->ctrl & mask) != nval;
1663 ensoniq->ctrl &= ~mask;
1664 ensoniq->ctrl |= nval;
1665 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1666 return change;
1667 }
1668
1669 /*
1670 * ENS1370 mixer
1671 */
1672
1673 static const struct snd_kcontrol_new snd_es1370_controls[2] = {
1674 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1675 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1676 };
1677
1678 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1679
snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 * ak4531)1680 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1681 {
1682 struct ensoniq *ensoniq = ak4531->private_data;
1683 ensoniq->u.es1370.ak4531 = NULL;
1684 }
1685
snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)1686 static int snd_ensoniq_1370_mixer(struct ensoniq *ensoniq)
1687 {
1688 struct snd_card *card = ensoniq->card;
1689 struct snd_ak4531 ak4531;
1690 unsigned int idx;
1691 int err;
1692
1693 /* try reset AK4531 */
1694 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1695 inw(ES_REG(ensoniq, 1370_CODEC));
1696 udelay(100);
1697 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1698 inw(ES_REG(ensoniq, 1370_CODEC));
1699 udelay(100);
1700
1701 memset(&ak4531, 0, sizeof(ak4531));
1702 ak4531.write = snd_es1370_codec_write;
1703 ak4531.private_data = ensoniq;
1704 ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1705 err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531);
1706 if (err < 0)
1707 return err;
1708 for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1709 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1710 if (err < 0)
1711 return err;
1712 }
1713 return 0;
1714 }
1715
1716 #endif /* CHIP1370 */
1717
1718 #ifdef SUPPORT_JOYSTICK
1719
1720 #ifdef CHIP1371
snd_ensoniq_get_joystick_port(struct ensoniq * ensoniq,int dev)1721 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1722 {
1723 switch (joystick_port[dev]) {
1724 case 0: /* disabled */
1725 case 1: /* auto-detect */
1726 case 0x200:
1727 case 0x208:
1728 case 0x210:
1729 case 0x218:
1730 return joystick_port[dev];
1731
1732 default:
1733 dev_err(ensoniq->card->dev,
1734 "invalid joystick port %#x", joystick_port[dev]);
1735 return 0;
1736 }
1737 }
1738 #else
snd_ensoniq_get_joystick_port(struct ensoniq * ensoniq,int dev)1739 static int snd_ensoniq_get_joystick_port(struct ensoniq *ensoniq, int dev)
1740 {
1741 return joystick[dev] ? 0x200 : 0;
1742 }
1743 #endif
1744
snd_ensoniq_create_gameport(struct ensoniq * ensoniq,int dev)1745 static int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1746 {
1747 struct gameport *gp;
1748 int io_port;
1749
1750 io_port = snd_ensoniq_get_joystick_port(ensoniq, dev);
1751
1752 switch (io_port) {
1753 case 0:
1754 return -ENOSYS;
1755
1756 case 1: /* auto_detect */
1757 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1758 if (request_region(io_port, 8, "ens137x: gameport"))
1759 break;
1760 if (io_port > 0x218) {
1761 dev_warn(ensoniq->card->dev,
1762 "no gameport ports available\n");
1763 return -EBUSY;
1764 }
1765 break;
1766
1767 default:
1768 if (!request_region(io_port, 8, "ens137x: gameport")) {
1769 dev_warn(ensoniq->card->dev,
1770 "gameport io port %#x in use\n",
1771 io_port);
1772 return -EBUSY;
1773 }
1774 break;
1775 }
1776
1777 ensoniq->gameport = gp = gameport_allocate_port();
1778 if (!gp) {
1779 dev_err(ensoniq->card->dev,
1780 "cannot allocate memory for gameport\n");
1781 release_region(io_port, 8);
1782 return -ENOMEM;
1783 }
1784
1785 gameport_set_name(gp, "ES137x");
1786 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1787 gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1788 gp->io = io_port;
1789
1790 ensoniq->ctrl |= ES_JYSTK_EN;
1791 #ifdef CHIP1371
1792 ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1793 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1794 #endif
1795 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1796
1797 gameport_register_port(ensoniq->gameport);
1798
1799 return 0;
1800 }
1801
snd_ensoniq_free_gameport(struct ensoniq * ensoniq)1802 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1803 {
1804 if (ensoniq->gameport) {
1805 int port = ensoniq->gameport->io;
1806
1807 gameport_unregister_port(ensoniq->gameport);
1808 ensoniq->gameport = NULL;
1809 ensoniq->ctrl &= ~ES_JYSTK_EN;
1810 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1811 release_region(port, 8);
1812 }
1813 }
1814 #else
snd_ensoniq_create_gameport(struct ensoniq * ensoniq,long port)1815 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
snd_ensoniq_free_gameport(struct ensoniq * ensoniq)1816 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1817 #endif /* SUPPORT_JOYSTICK */
1818
1819 /*
1820
1821 */
1822
snd_ensoniq_proc_read(struct snd_info_entry * entry,struct snd_info_buffer * buffer)1823 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1824 struct snd_info_buffer *buffer)
1825 {
1826 struct ensoniq *ensoniq = entry->private_data;
1827
1828 snd_iprintf(buffer, "Ensoniq AudioPCI " CHIP_NAME "\n\n");
1829 snd_iprintf(buffer, "Joystick enable : %s\n",
1830 str_on_off(ensoniq->ctrl & ES_JYSTK_EN));
1831 #ifdef CHIP1370
1832 snd_iprintf(buffer, "MIC +5V bias : %s\n",
1833 str_on_off(ensoniq->ctrl & ES_1370_XCTL1));
1834 snd_iprintf(buffer, "Line In to AOUT : %s\n",
1835 str_on_off(ensoniq->ctrl & ES_1370_XCTL0));
1836 #else
1837 snd_iprintf(buffer, "Joystick port : 0x%x\n",
1838 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1839 #endif
1840 }
1841
snd_ensoniq_proc_init(struct ensoniq * ensoniq)1842 static void snd_ensoniq_proc_init(struct ensoniq *ensoniq)
1843 {
1844 snd_card_ro_proc_new(ensoniq->card, "audiopci", ensoniq,
1845 snd_ensoniq_proc_read);
1846 }
1847
1848 /*
1849
1850 */
1851
snd_ensoniq_free(struct snd_card * card)1852 static void snd_ensoniq_free(struct snd_card *card)
1853 {
1854 struct ensoniq *ensoniq = card->private_data;
1855
1856 snd_ensoniq_free_gameport(ensoniq);
1857 #ifdef CHIP1370
1858 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1859 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1860 #else
1861 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */
1862 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */
1863 #endif
1864 }
1865
1866 #ifdef CHIP1371
1867 static const struct snd_pci_quirk es1371_amplifier_hack[] = {
1868 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */
1869 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */
1870 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */
1871 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */
1872 { } /* end */
1873 };
1874
1875 static const struct es1371_quirk es1371_ac97_reset_hack[] = {
1876 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1877 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1878 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1879 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1880 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1881 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1882 };
1883 #endif
1884
snd_ensoniq_chip_init(struct ensoniq * ensoniq)1885 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1886 {
1887 #ifdef CHIP1371
1888 int idx;
1889 #endif
1890 /* this code was part of snd_ensoniq_create before intruduction
1891 * of suspend/resume
1892 */
1893 #ifdef CHIP1370
1894 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1895 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1896 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1897 outl(ensoniq->dma_bug->addr, ES_REG(ensoniq, PHANTOM_FRAME));
1898 outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1899 #else
1900 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1901 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1902 outl(0, ES_REG(ensoniq, 1371_LEGACY));
1903 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) {
1904 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1905 /* need to delay around 20ms(bleech) to give
1906 some CODECs enough time to wakeup */
1907 msleep(20);
1908 }
1909 /* AC'97 warm reset to start the bitclk */
1910 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
1911 inl(ES_REG(ensoniq, CONTROL));
1912 udelay(20);
1913 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1914 /* Init the sample rate converter */
1915 snd_es1371_wait_src_ready(ensoniq);
1916 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
1917 for (idx = 0; idx < 0x80; idx++)
1918 snd_es1371_src_write(ensoniq, idx, 0);
1919 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
1920 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
1921 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
1922 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
1923 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
1924 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
1925 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
1926 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
1927 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
1928 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
1929 snd_es1371_adc_rate(ensoniq, 22050);
1930 snd_es1371_dac1_rate(ensoniq, 22050);
1931 snd_es1371_dac2_rate(ensoniq, 22050);
1932 /* WARNING:
1933 * enabling the sample rate converter without properly programming
1934 * its parameters causes the chip to lock up (the SRC busy bit will
1935 * be stuck high, and I've found no way to rectify this other than
1936 * power cycle) - Thomas Sailer
1937 */
1938 snd_es1371_wait_src_ready(ensoniq);
1939 outl(0, ES_REG(ensoniq, 1371_SMPRATE));
1940 /* try reset codec directly */
1941 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
1942 #endif
1943 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
1944 outb(0x00, ES_REG(ensoniq, UART_RES));
1945 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1946 }
1947
snd_ensoniq_suspend(struct device * dev)1948 static int snd_ensoniq_suspend(struct device *dev)
1949 {
1950 struct snd_card *card = dev_get_drvdata(dev);
1951 struct ensoniq *ensoniq = card->private_data;
1952
1953 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1954
1955 #ifdef CHIP1371
1956 snd_ac97_suspend(ensoniq->u.es1371.ac97);
1957 #else
1958 /* try to reset AK4531 */
1959 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1960 inw(ES_REG(ensoniq, 1370_CODEC));
1961 udelay(100);
1962 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1963 inw(ES_REG(ensoniq, 1370_CODEC));
1964 udelay(100);
1965 snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
1966 #endif
1967 return 0;
1968 }
1969
snd_ensoniq_resume(struct device * dev)1970 static int snd_ensoniq_resume(struct device *dev)
1971 {
1972 struct snd_card *card = dev_get_drvdata(dev);
1973 struct ensoniq *ensoniq = card->private_data;
1974
1975 snd_ensoniq_chip_init(ensoniq);
1976
1977 #ifdef CHIP1371
1978 snd_ac97_resume(ensoniq->u.es1371.ac97);
1979 #else
1980 snd_ak4531_resume(ensoniq->u.es1370.ak4531);
1981 #endif
1982 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1983 return 0;
1984 }
1985
1986 static DEFINE_SIMPLE_DEV_PM_OPS(snd_ensoniq_pm, snd_ensoniq_suspend, snd_ensoniq_resume);
1987
snd_ensoniq_create(struct snd_card * card,struct pci_dev * pci)1988 static int snd_ensoniq_create(struct snd_card *card,
1989 struct pci_dev *pci)
1990 {
1991 struct ensoniq *ensoniq = card->private_data;
1992 int err;
1993
1994 err = pcim_enable_device(pci);
1995 if (err < 0)
1996 return err;
1997 spin_lock_init(&ensoniq->reg_lock);
1998 mutex_init(&ensoniq->src_mutex);
1999 ensoniq->card = card;
2000 ensoniq->pci = pci;
2001 ensoniq->irq = -1;
2002 err = pcim_request_all_regions(pci, "Ensoniq AudioPCI");
2003 if (err < 0)
2004 return err;
2005 ensoniq->port = pci_resource_start(pci, 0);
2006 if (devm_request_irq(&pci->dev, pci->irq, snd_audiopci_interrupt,
2007 IRQF_SHARED, KBUILD_MODNAME, ensoniq)) {
2008 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2009 return -EBUSY;
2010 }
2011 ensoniq->irq = pci->irq;
2012 card->sync_irq = ensoniq->irq;
2013 #ifdef CHIP1370
2014 ensoniq->dma_bug =
2015 snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, 16);
2016 if (!ensoniq->dma_bug)
2017 return -ENOMEM;
2018 #endif
2019 pci_set_master(pci);
2020 ensoniq->rev = pci->revision;
2021 #ifdef CHIP1370
2022 #if 0
2023 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2024 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2025 #else /* get microphone working */
2026 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2027 #endif
2028 ensoniq->sctrl = 0;
2029 #else
2030 ensoniq->ctrl = 0;
2031 ensoniq->sctrl = 0;
2032 ensoniq->cssr = 0;
2033 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack))
2034 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2035
2036 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack))
2037 ensoniq->cssr |= ES_1371_ST_AC97_RST;
2038 #endif
2039
2040 card->private_free = snd_ensoniq_free;
2041 snd_ensoniq_chip_init(ensoniq);
2042
2043 snd_ensoniq_proc_init(ensoniq);
2044 return 0;
2045 }
2046
2047 /*
2048 * MIDI section
2049 */
2050
snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)2051 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2052 {
2053 struct snd_rawmidi *rmidi = ensoniq->rmidi;
2054 unsigned char status, mask, byte;
2055
2056 if (rmidi == NULL)
2057 return;
2058 /* do Rx at first */
2059 scoped_guard(spinlock, &ensoniq->reg_lock) {
2060 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2061 while (mask) {
2062 status = inb(ES_REG(ensoniq, UART_STATUS));
2063 if ((status & mask) == 0)
2064 break;
2065 byte = inb(ES_REG(ensoniq, UART_DATA));
2066 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2067 }
2068 }
2069
2070 /* do Tx at second */
2071 guard(spinlock)(&ensoniq->reg_lock);
2072 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2073 while (mask) {
2074 status = inb(ES_REG(ensoniq, UART_STATUS));
2075 if ((status & mask) == 0)
2076 break;
2077 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2078 ensoniq->uartc &= ~ES_TXINTENM;
2079 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2080 mask &= ~ES_TXRDY;
2081 } else {
2082 outb(byte, ES_REG(ensoniq, UART_DATA));
2083 }
2084 }
2085 }
2086
snd_ensoniq_midi_input_open(struct snd_rawmidi_substream * substream)2087 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2088 {
2089 struct ensoniq *ensoniq = substream->rmidi->private_data;
2090
2091 guard(spinlock_irq)(&ensoniq->reg_lock);
2092 ensoniq->uartm |= ES_MODE_INPUT;
2093 ensoniq->midi_input = substream;
2094 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2095 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2096 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2097 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2098 }
2099 return 0;
2100 }
2101
snd_ensoniq_midi_input_close(struct snd_rawmidi_substream * substream)2102 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2103 {
2104 struct ensoniq *ensoniq = substream->rmidi->private_data;
2105
2106 guard(spinlock_irq)(&ensoniq->reg_lock);
2107 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2108 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2109 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2110 } else {
2111 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2112 }
2113 ensoniq->midi_input = NULL;
2114 ensoniq->uartm &= ~ES_MODE_INPUT;
2115 return 0;
2116 }
2117
snd_ensoniq_midi_output_open(struct snd_rawmidi_substream * substream)2118 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2119 {
2120 struct ensoniq *ensoniq = substream->rmidi->private_data;
2121
2122 guard(spinlock_irq)(&ensoniq->reg_lock);
2123 ensoniq->uartm |= ES_MODE_OUTPUT;
2124 ensoniq->midi_output = substream;
2125 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2126 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2127 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2128 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2129 }
2130 return 0;
2131 }
2132
snd_ensoniq_midi_output_close(struct snd_rawmidi_substream * substream)2133 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2134 {
2135 struct ensoniq *ensoniq = substream->rmidi->private_data;
2136
2137 guard(spinlock_irq)(&ensoniq->reg_lock);
2138 if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2139 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2140 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2141 } else {
2142 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2143 }
2144 ensoniq->midi_output = NULL;
2145 ensoniq->uartm &= ~ES_MODE_OUTPUT;
2146 return 0;
2147 }
2148
snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream * substream,int up)2149 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2150 {
2151 struct ensoniq *ensoniq = substream->rmidi->private_data;
2152 int idx;
2153
2154 guard(spinlock_irqsave)(&ensoniq->reg_lock);
2155 if (up) {
2156 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2157 /* empty input FIFO */
2158 for (idx = 0; idx < 32; idx++)
2159 inb(ES_REG(ensoniq, UART_DATA));
2160 ensoniq->uartc |= ES_RXINTEN;
2161 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2162 }
2163 } else {
2164 if (ensoniq->uartc & ES_RXINTEN) {
2165 ensoniq->uartc &= ~ES_RXINTEN;
2166 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2167 }
2168 }
2169 }
2170
snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream * substream,int up)2171 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2172 {
2173 struct ensoniq *ensoniq = substream->rmidi->private_data;
2174 unsigned char byte;
2175
2176 guard(spinlock_irqsave)(&ensoniq->reg_lock);
2177 if (up) {
2178 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2179 ensoniq->uartc |= ES_TXINTENO(1);
2180 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2181 while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2182 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2183 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2184 ensoniq->uartc &= ~ES_TXINTENM;
2185 } else {
2186 outb(byte, ES_REG(ensoniq, UART_DATA));
2187 }
2188 }
2189 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2190 }
2191 } else {
2192 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2193 ensoniq->uartc &= ~ES_TXINTENM;
2194 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2195 }
2196 }
2197 }
2198
2199 static const struct snd_rawmidi_ops snd_ensoniq_midi_output =
2200 {
2201 .open = snd_ensoniq_midi_output_open,
2202 .close = snd_ensoniq_midi_output_close,
2203 .trigger = snd_ensoniq_midi_output_trigger,
2204 };
2205
2206 static const struct snd_rawmidi_ops snd_ensoniq_midi_input =
2207 {
2208 .open = snd_ensoniq_midi_input_open,
2209 .close = snd_ensoniq_midi_input_close,
2210 .trigger = snd_ensoniq_midi_input_trigger,
2211 };
2212
snd_ensoniq_midi(struct ensoniq * ensoniq,int device)2213 static int snd_ensoniq_midi(struct ensoniq *ensoniq, int device)
2214 {
2215 struct snd_rawmidi *rmidi;
2216 int err;
2217
2218 err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi);
2219 if (err < 0)
2220 return err;
2221 strscpy(rmidi->name, CHIP_NAME);
2222 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2223 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2224 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2225 SNDRV_RAWMIDI_INFO_DUPLEX;
2226 rmidi->private_data = ensoniq;
2227 ensoniq->rmidi = rmidi;
2228 return 0;
2229 }
2230
2231 /*
2232 * Interrupt handler
2233 */
2234
snd_audiopci_interrupt(int irq,void * dev_id)2235 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id)
2236 {
2237 struct ensoniq *ensoniq = dev_id;
2238 unsigned int status, sctrl;
2239
2240 if (ensoniq == NULL)
2241 return IRQ_NONE;
2242
2243 status = inl(ES_REG(ensoniq, STATUS));
2244 if (!(status & ES_INTR))
2245 return IRQ_NONE;
2246
2247 scoped_guard(spinlock, &ensoniq->reg_lock) {
2248 sctrl = ensoniq->sctrl;
2249 if (status & ES_DAC1)
2250 sctrl &= ~ES_P1_INT_EN;
2251 if (status & ES_DAC2)
2252 sctrl &= ~ES_P2_INT_EN;
2253 if (status & ES_ADC)
2254 sctrl &= ~ES_R1_INT_EN;
2255 outl(sctrl, ES_REG(ensoniq, SERIAL));
2256 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2257 }
2258
2259 if (status & ES_UART)
2260 snd_ensoniq_midi_interrupt(ensoniq);
2261 if ((status & ES_DAC2) && ensoniq->playback2_substream)
2262 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2263 if ((status & ES_ADC) && ensoniq->capture_substream)
2264 snd_pcm_period_elapsed(ensoniq->capture_substream);
2265 if ((status & ES_DAC1) && ensoniq->playback1_substream)
2266 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2267 return IRQ_HANDLED;
2268 }
2269
__snd_audiopci_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2270 static int __snd_audiopci_probe(struct pci_dev *pci,
2271 const struct pci_device_id *pci_id)
2272 {
2273 static int dev;
2274 struct snd_card *card;
2275 struct ensoniq *ensoniq;
2276 int err;
2277
2278 if (dev >= SNDRV_CARDS)
2279 return -ENODEV;
2280 if (!enable[dev]) {
2281 dev++;
2282 return -ENOENT;
2283 }
2284
2285 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2286 sizeof(*ensoniq), &card);
2287 if (err < 0)
2288 return err;
2289 ensoniq = card->private_data;
2290
2291 err = snd_ensoniq_create(card, pci);
2292 if (err < 0)
2293 return err;
2294
2295 #ifdef CHIP1370
2296 err = snd_ensoniq_1370_mixer(ensoniq);
2297 if (err < 0)
2298 return err;
2299 #endif
2300 #ifdef CHIP1371
2301 err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev]);
2302 if (err < 0)
2303 return err;
2304 #endif
2305 err = snd_ensoniq_pcm(ensoniq, 0);
2306 if (err < 0)
2307 return err;
2308 err = snd_ensoniq_pcm2(ensoniq, 1);
2309 if (err < 0)
2310 return err;
2311 err = snd_ensoniq_midi(ensoniq, 0);
2312 if (err < 0)
2313 return err;
2314
2315 snd_ensoniq_create_gameport(ensoniq, dev);
2316
2317 strscpy(card->driver, DRIVER_NAME);
2318
2319 strscpy(card->shortname, "Ensoniq AudioPCI");
2320 sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2321 card->shortname,
2322 card->driver,
2323 ensoniq->port,
2324 ensoniq->irq);
2325
2326 err = snd_card_register(card);
2327 if (err < 0)
2328 return err;
2329
2330 pci_set_drvdata(pci, card);
2331 dev++;
2332 return 0;
2333 }
2334
snd_audiopci_probe(struct pci_dev * pci,const struct pci_device_id * pci_id)2335 static int snd_audiopci_probe(struct pci_dev *pci,
2336 const struct pci_device_id *pci_id)
2337 {
2338 return snd_card_free_on_error(&pci->dev, __snd_audiopci_probe(pci, pci_id));
2339 }
2340
2341 static struct pci_driver ens137x_driver = {
2342 .name = KBUILD_MODNAME,
2343 .id_table = snd_audiopci_ids,
2344 .probe = snd_audiopci_probe,
2345 .driver = {
2346 .pm = &snd_ensoniq_pm,
2347 },
2348 };
2349
2350 module_pci_driver(ens137x_driver);
2351