1/* 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015 Broadcom. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/memreserve/ 0x81000000 0x00200000; 34 35#include <dt-bindings/interrupt-controller/arm-gic.h> 36#include <dt-bindings/clock/bcm-ns2.h> 37 38/ { 39 compatible = "brcm,ns2"; 40 interrupt-parent = <&gic>; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 A57_0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a57"; 51 reg = <0 0>; 52 enable-method = "psci"; 53 next-level-cache = <&CLUSTER0_L2>; 54 }; 55 56 A57_1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a57"; 59 reg = <0 1>; 60 enable-method = "psci"; 61 next-level-cache = <&CLUSTER0_L2>; 62 }; 63 64 A57_2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a57"; 67 reg = <0 2>; 68 enable-method = "psci"; 69 next-level-cache = <&CLUSTER0_L2>; 70 }; 71 72 A57_3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a57"; 75 reg = <0 3>; 76 enable-method = "psci"; 77 next-level-cache = <&CLUSTER0_L2>; 78 }; 79 80 CLUSTER0_L2: l2-cache@0 { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 }; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | 95 IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | 97 IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | 99 IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | 101 IRQ_TYPE_LEVEL_LOW)>; 102 }; 103 104 pmu { 105 compatible = "arm,cortex-a57-pmu"; 106 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 110 interrupt-affinity = <&A57_0>, 111 <&A57_1>, 112 <&A57_2>, 113 <&A57_3>; 114 }; 115 116 osc: clock-25000000 { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 clock-frequency = <25000000>; 120 }; 121 122 iprocmed: iprocmed { 123 #clock-cells = <0>; 124 compatible = "fixed-factor-clock"; 125 clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; 126 clock-div = <2>; 127 clock-mult = <1>; 128 }; 129 130 iprocslow: iprocslow { 131 #clock-cells = <0>; 132 compatible = "fixed-factor-clock"; 133 clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; 134 clock-div = <4>; 135 clock-mult = <1>; 136 }; 137 138 pcie0: pcie@20020000 { 139 compatible = "brcm,iproc-pcie"; 140 reg = <0 0x20020000 0 0x1000>; 141 dma-coherent; 142 143 #interrupt-cells = <1>; 144 interrupt-map-mask = <0 0 0 0>; 145 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 146 147 linux,pci-domain = <0>; 148 149 bus-range = <0x00 0xff>; 150 151 #address-cells = <3>; 152 #size-cells = <2>; 153 device_type = "pci"; 154 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; 155 156 brcm,pcie-ob; 157 brcm,pcie-ob-axi-offset = <0x00000000>; 158 159 status = "disabled"; 160 161 phys = <&pci_phy0>; 162 phy-names = "pcie-phy"; 163 164 msi-parent = <&v2m0>; 165 }; 166 167 pcie4: pcie@50020000 { 168 compatible = "brcm,iproc-pcie"; 169 reg = <0 0x50020000 0 0x1000>; 170 dma-coherent; 171 172 #interrupt-cells = <1>; 173 interrupt-map-mask = <0 0 0 0>; 174 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 175 176 linux,pci-domain = <4>; 177 178 bus-range = <0x00 0xff>; 179 180 #address-cells = <3>; 181 #size-cells = <2>; 182 device_type = "pci"; 183 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; 184 185 brcm,pcie-ob; 186 brcm,pcie-ob-axi-offset = <0x30000000>; 187 188 status = "disabled"; 189 190 phys = <&pci_phy1>; 191 phy-names = "pcie-phy"; 192 193 msi-parent = <&v2m0>; 194 }; 195 196 pcie8: pcie@60c00000 { 197 compatible = "brcm,iproc-pcie-paxc"; 198 reg = <0 0x60c00000 0 0x1000>; 199 dma-coherent; 200 linux,pci-domain = <8>; 201 202 bus-range = <0x0 0x1>; 203 204 #address-cells = <3>; 205 #size-cells = <2>; 206 device_type = "pci"; 207 ranges = <0x83000000 0 0x00000000 0 0x60000000 0 0x00c00000>; 208 209 status = "disabled"; 210 211 msi-parent = <&v2m0>; 212 }; 213 214 soc: soc { 215 compatible = "simple-bus"; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges = <0 0 0 0xffffffff>; 219 220 enet: ethernet@61000000 { 221 compatible = "brcm,ns2-amac"; 222 reg = <0x61000000 0x1000>, 223 <0x61090000 0x1000>, 224 <0x61030000 0x100>; 225 reg-names = "amac_base", "idm_base", "nicpm_base"; 226 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 227 dma-coherent; 228 phy-handle = <&gphy0>; 229 phy-mode = "rgmii"; 230 status = "disabled"; 231 }; 232 233 pdc0: iproc-pdc0@612c0000 { 234 compatible = "brcm,iproc-pdc-mbox"; 235 reg = <0x612c0000 0x445>; /* PDC FS0 regs */ 236 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 237 #mbox-cells = <1>; 238 dma-coherent; 239 brcm,rx-status-len = <32>; 240 brcm,use-bcm-hdr; 241 }; 242 243 crypto0: crypto@612d0000 { 244 compatible = "brcm,spum-crypto"; 245 reg = <0x612d0000 0x900>; 246 mboxes = <&pdc0 0>; 247 }; 248 249 pdc1: iproc-pdc1@612e0000 { 250 compatible = "brcm,iproc-pdc-mbox"; 251 reg = <0x612e0000 0x445>; /* PDC FS1 regs */ 252 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 253 #mbox-cells = <1>; 254 dma-coherent; 255 brcm,rx-status-len = <32>; 256 brcm,use-bcm-hdr; 257 }; 258 259 crypto1: crypto@612f0000 { 260 compatible = "brcm,spum-crypto"; 261 reg = <0x612f0000 0x900>; 262 mboxes = <&pdc1 0>; 263 }; 264 265 pdc2: iproc-pdc2@61300000 { 266 compatible = "brcm,iproc-pdc-mbox"; 267 reg = <0x61300000 0x445>; /* PDC FS2 regs */ 268 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 269 #mbox-cells = <1>; 270 dma-coherent; 271 brcm,rx-status-len = <32>; 272 brcm,use-bcm-hdr; 273 }; 274 275 crypto2: crypto@61310000 { 276 compatible = "brcm,spum-crypto"; 277 reg = <0x61310000 0x900>; 278 mboxes = <&pdc2 0>; 279 }; 280 281 pdc3: iproc-pdc3@61320000 { 282 compatible = "brcm,iproc-pdc-mbox"; 283 reg = <0x61320000 0x445>; /* PDC FS3 regs */ 284 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 285 #mbox-cells = <1>; 286 dma-coherent; 287 brcm,rx-status-len = <32>; 288 brcm,use-bcm-hdr; 289 }; 290 291 crypto3: crypto@61330000 { 292 compatible = "brcm,spum-crypto"; 293 reg = <0x61330000 0x900>; 294 mboxes = <&pdc3 0>; 295 }; 296 297 dma0: dma-controller@61360000 { 298 compatible = "arm,pl330", "arm,primecell"; 299 reg = <0x61360000 0x1000>; 300 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 309 #dma-cells = <1>; 310 clocks = <&iprocslow>; 311 clock-names = "apb_pclk"; 312 }; 313 314 smmu: iommu@64000000 { 315 compatible = "arm,mmu-500"; 316 reg = <0x64000000 0x40000>; 317 #global-interrupts = <2>; 318 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 352 #iommu-cells = <1>; 353 }; 354 355 lcpll_ddr: clock-controller@6501d058 { 356 #clock-cells = <1>; 357 compatible = "brcm,ns2-lcpll-ddr"; 358 reg = <0x6501d058 0x20>, 359 <0x6501c020 0x4>, 360 <0x6501d04c 0x4>; 361 clocks = <&osc>; 362 clock-output-names = "lcpll_ddr", "pcie_sata_usb", 363 "ddr", "ddr_ch2_unused", 364 "ddr_ch3_unused", "ddr_ch4_unused", 365 "ddr_ch5_unused"; 366 }; 367 368 lcpll_ports: clock-controller@6501d078 { 369 #clock-cells = <1>; 370 compatible = "brcm,ns2-lcpll-ports"; 371 reg = <0x6501d078 0x20>, 372 <0x6501c020 0x4>, 373 <0x6501d054 0x4>; 374 clocks = <&osc>; 375 clock-output-names = "lcpll_ports", "wan", "rgmii", 376 "ports_ch2_unused", 377 "ports_ch3_unused", 378 "ports_ch4_unused", 379 "ports_ch5_unused"; 380 }; 381 382 genpll_scr: clock-controller@6501d098 { 383 #clock-cells = <1>; 384 compatible = "brcm,ns2-genpll-scr"; 385 reg = <0x6501d098 0x32>, 386 <0x6501c020 0x4>, 387 <0x6501d044 0x4>; 388 clocks = <&osc>; 389 clock-output-names = "genpll_scr", "scr", "fs", 390 "audio_ref", "scr_ch3_unused", 391 "scr_ch4_unused", "scr_ch5_unused"; 392 }; 393 394 genpll_sw: clock-controller@6501d0c4 { 395 #clock-cells = <1>; 396 compatible = "brcm,ns2-genpll-sw"; 397 reg = <0x6501d0c4 0x32>, 398 <0x6501c020 0x4>, 399 <0x6501d044 0x4>; 400 clocks = <&osc>; 401 clock-output-names = "genpll_sw", "rpe", "250", "nic", 402 "chimp", "port", "sdio"; 403 }; 404 pinctrl: pinctrl@6501d130 { 405 compatible = "brcm,ns2-pinmux"; 406 reg = <0x6501d130 0x08>, 407 <0x660a0028 0x04>, 408 <0x660009b0 0x40>; 409 }; 410 411 gpio_aon: gpio@65024800 { 412 compatible = "brcm,iproc-gpio"; 413 reg = <0x65024800 0x50>, 414 <0x65024008 0x18>; 415 ngpios = <6>; 416 #gpio-cells = <2>; 417 gpio-controller; 418 }; 419 420 gic: interrupt-controller@65210000 { 421 compatible = "arm,gic-400"; 422 #interrupt-cells = <3>; 423 interrupt-controller; 424 reg = <0x65210000 0x1000>, 425 <0x65220000 0x1000>, 426 <0x65240000 0x2000>, 427 <0x65260000 0x1000>; 428 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 429 IRQ_TYPE_LEVEL_HIGH)>; 430 431 #address-cells = <1>; 432 #size-cells = <1>; 433 ranges = <0 0x652e0000 0x80000>; 434 435 v2m0: v2m@0 { 436 compatible = "arm,gic-v2m-frame"; 437 msi-controller; 438 reg = <0x00000 0x1000>; 439 arm,msi-base-spi = <72>; 440 arm,msi-num-spis = <16>; 441 }; 442 443 v2m1: v2m@10000 { 444 compatible = "arm,gic-v2m-frame"; 445 msi-controller; 446 reg = <0x10000 0x1000>; 447 arm,msi-base-spi = <88>; 448 arm,msi-num-spis = <16>; 449 }; 450 451 v2m2: v2m@20000 { 452 compatible = "arm,gic-v2m-frame"; 453 msi-controller; 454 reg = <0x20000 0x1000>; 455 arm,msi-base-spi = <104>; 456 arm,msi-num-spis = <16>; 457 }; 458 459 v2m3: v2m@30000 { 460 compatible = "arm,gic-v2m-frame"; 461 msi-controller; 462 reg = <0x30000 0x1000>; 463 arm,msi-base-spi = <120>; 464 arm,msi-num-spis = <16>; 465 }; 466 467 v2m4: v2m@40000 { 468 compatible = "arm,gic-v2m-frame"; 469 msi-controller; 470 reg = <0x40000 0x1000>; 471 arm,msi-base-spi = <136>; 472 arm,msi-num-spis = <16>; 473 }; 474 475 v2m5: v2m@50000 { 476 compatible = "arm,gic-v2m-frame"; 477 msi-controller; 478 reg = <0x50000 0x1000>; 479 arm,msi-base-spi = <152>; 480 arm,msi-num-spis = <16>; 481 }; 482 483 v2m6: v2m@60000 { 484 compatible = "arm,gic-v2m-frame"; 485 msi-controller; 486 reg = <0x60000 0x1000>; 487 arm,msi-base-spi = <168>; 488 arm,msi-num-spis = <16>; 489 }; 490 491 v2m7: v2m@70000 { 492 compatible = "arm,gic-v2m-frame"; 493 msi-controller; 494 reg = <0x70000 0x1000>; 495 arm,msi-base-spi = <184>; 496 arm,msi-num-spis = <16>; 497 }; 498 }; 499 500 cci@65590000 { 501 compatible = "arm,cci-400"; 502 #address-cells = <1>; 503 #size-cells = <1>; 504 reg = <0x65590000 0x1000>; 505 ranges = <0 0x65590000 0x10000>; 506 507 pmu@9000 { 508 compatible = "arm,cci-400-pmu,r1"; 509 reg = <0x9000 0x4000>; 510 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 516 }; 517 }; 518 519 usbdrd_phy: phy@66000960 { 520 #phy-cells = <0>; 521 compatible = "brcm,ns2-drd-phy"; 522 reg = <0x66000960 0x24>, 523 <0x67012800 0x4>, 524 <0x6501d148 0x4>, 525 <0x664d0700 0x4>; 526 reg-names = "icfg", "rst-ctrl", 527 "crmu-ctrl", "usb2-strap"; 528 id-gpios = <&gpio_g 30 0>; 529 vbus-gpios = <&gpio_g 31 0>; 530 status = "disabled"; 531 }; 532 533 pwm: pwm@66010000 { 534 compatible = "brcm,iproc-pwm"; 535 reg = <0x66010000 0x28>; 536 clocks = <&osc>; 537 #pwm-cells = <3>; 538 status = "disabled"; 539 }; 540 541 mdio_mux_iproc: mdio-mux@66020000 { 542 compatible = "brcm,mdio-mux-iproc"; 543 reg = <0x66020000 0x250>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 547 mdio@0 { 548 reg = <0x0>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 552 pci_phy0: pci-phy@0 { 553 compatible = "brcm,ns2-pcie-phy"; 554 reg = <0x0>; 555 #phy-cells = <0>; 556 status = "disabled"; 557 }; 558 }; 559 560 mdio@7 { 561 reg = <0x7>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 565 pci_phy1: pci-phy@0 { 566 compatible = "brcm,ns2-pcie-phy"; 567 reg = <0x0>; 568 #phy-cells = <0>; 569 status = "disabled"; 570 }; 571 }; 572 573 mdio@10 { 574 reg = <0x10>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 }; 578 }; 579 580 timer0: timer@66030000 { 581 compatible = "arm,sp804", "arm,primecell"; 582 reg = <0x66030000 0x1000>; 583 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&iprocslow>, 585 <&iprocslow>, 586 <&iprocslow>; 587 clock-names = "timer1", "timer2", "apb_pclk"; 588 }; 589 590 timer1: timer@66040000 { 591 compatible = "arm,sp804", "arm,primecell"; 592 reg = <0x66040000 0x1000>; 593 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&iprocslow>, 595 <&iprocslow>, 596 <&iprocslow>; 597 clock-names = "timer1", "timer2", "apb_pclk"; 598 }; 599 600 timer2: timer@66050000 { 601 compatible = "arm,sp804", "arm,primecell"; 602 reg = <0x66050000 0x1000>; 603 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&iprocslow>, 605 <&iprocslow>, 606 <&iprocslow>; 607 clock-names = "timer1", "timer2", "apb_pclk"; 608 }; 609 610 timer3: timer@66060000 { 611 compatible = "arm,sp804", "arm,primecell"; 612 reg = <0x66060000 0x1000>; 613 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&iprocslow>, 615 <&iprocslow>, 616 <&iprocslow>; 617 clock-names = "timer1", "timer2", "apb_pclk"; 618 }; 619 620 i2c0: i2c@66080000 { 621 compatible = "brcm,iproc-i2c"; 622 reg = <0x66080000 0x100>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 626 clock-frequency = <100000>; 627 status = "disabled"; 628 }; 629 630 wdt0: watchdog@66090000 { 631 compatible = "arm,sp805", "arm,primecell"; 632 reg = <0x66090000 0x1000>; 633 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&iprocslow>, <&iprocslow>; 635 clock-names = "wdog_clk", "apb_pclk"; 636 }; 637 638 gpio_g: gpio@660a0000 { 639 compatible = "brcm,iproc-gpio"; 640 reg = <0x660a0000 0x50>; 641 ngpios = <32>; 642 #gpio-cells = <2>; 643 gpio-controller; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 647 }; 648 649 i2c1: i2c@660b0000 { 650 compatible = "brcm,iproc-i2c"; 651 reg = <0x660b0000 0x100>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 655 clock-frequency = <100000>; 656 status = "disabled"; 657 }; 658 659 uart0: serial@66100000 { 660 compatible = "snps,dw-apb-uart"; 661 reg = <0x66100000 0x100>; 662 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&iprocslow>; 664 reg-shift = <2>; 665 reg-io-width = <4>; 666 status = "disabled"; 667 }; 668 669 uart1: serial@66110000 { 670 compatible = "snps,dw-apb-uart"; 671 reg = <0x66110000 0x100>; 672 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&iprocslow>; 674 reg-shift = <2>; 675 reg-io-width = <4>; 676 status = "disabled"; 677 }; 678 679 uart2: serial@66120000 { 680 compatible = "snps,dw-apb-uart"; 681 reg = <0x66120000 0x100>; 682 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&iprocslow>; 684 reg-shift = <2>; 685 reg-io-width = <4>; 686 status = "disabled"; 687 }; 688 689 uart3: serial@66130000 { 690 compatible = "snps,dw-apb-uart"; 691 reg = <0x66130000 0x100>; 692 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 693 reg-shift = <2>; 694 reg-io-width = <4>; 695 clocks = <&osc>; 696 status = "disabled"; 697 }; 698 699 ssp0: spi@66180000 { 700 compatible = "arm,pl022", "arm,primecell"; 701 reg = <0x66180000 0x1000>; 702 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&iprocslow>, <&iprocslow>; 704 clock-names = "sspclk", "apb_pclk"; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 status = "disabled"; 708 }; 709 710 ssp1: spi@66190000 { 711 compatible = "arm,pl022", "arm,primecell"; 712 reg = <0x66190000 0x1000>; 713 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&iprocslow>, <&iprocslow>; 715 clock-names = "sspclk", "apb_pclk"; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 hwrng: hwrng@66220000 { 722 compatible = "brcm,iproc-rng200"; 723 reg = <0x66220000 0x28>; 724 }; 725 726 sata_phy: sata-phy@663f0100 { 727 compatible = "brcm,iproc-ns2-sata-phy"; 728 reg = <0x663f0100 0x1f00>, 729 <0x663f004c 0x10>; 730 reg-names = "phy", "phy-ctrl"; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 734 sata_phy0: sata-phy@0 { 735 reg = <0>; 736 #phy-cells = <0>; 737 status = "disabled"; 738 }; 739 740 sata_phy1: sata-phy@1 { 741 reg = <1>; 742 #phy-cells = <0>; 743 status = "disabled"; 744 }; 745 }; 746 747 sata: sata@663f2000 { 748 compatible = "brcm,iproc-ahci", "generic-ahci"; 749 reg = <0x663f2000 0x1000>; 750 dma-coherent; 751 reg-names = "ahci"; 752 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 757 sata0: sata-port@0 { 758 reg = <0>; 759 phys = <&sata_phy0>; 760 phy-names = "sata-phy"; 761 }; 762 763 sata1: sata-port@1 { 764 reg = <1>; 765 phys = <&sata_phy1>; 766 phy-names = "sata-phy"; 767 }; 768 }; 769 770 sdio0: mmc@66420000 { 771 compatible = "brcm,sdhci-iproc-cygnus"; 772 reg = <0x66420000 0x100>; 773 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 774 dma-coherent; 775 bus-width = <8>; 776 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; 777 status = "disabled"; 778 }; 779 780 sdio1: mmc@66430000 { 781 compatible = "brcm,sdhci-iproc-cygnus"; 782 reg = <0x66430000 0x100>; 783 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 784 dma-coherent; 785 bus-width = <8>; 786 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>; 787 status = "disabled"; 788 }; 789 790 nand: nand-controller@66460000 { 791 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 792 reg = <0x66460000 0x600>, 793 <0x67015408 0x600>, 794 <0x66460f00 0x20>; 795 reg-names = "nand", "iproc-idm", "iproc-ext"; 796 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 797 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 brcm,nand-has-wp; 802 }; 803 804 qspi: spi@66470200 { 805 compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; 806 reg = <0x66470200 0x184>, 807 <0x66470000 0x124>, 808 <0x67017408 0x004>, 809 <0x664703a0 0x01c>; 810 reg-names = "mspi", "bspi", "intr_regs", 811 "intr_status_reg"; 812 interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; 813 interrupt-names = "spi_l1_intr"; 814 clocks = <&iprocmed>; 815 num-cs = <2>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 }; 819 820 }; 821}; 822