1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include <zlib.h>
24
25 #include "qapi/error.h"
26 #include "qemu/timer.h"
27 #include "qemu/queue.h"
28 #include "qemu/atomic.h"
29 #include "qemu/main-loop.h"
30 #include "qemu/module.h"
31 #include "hw/qdev-properties.h"
32 #include "system/runstate.h"
33 #include "migration/cpr.h"
34 #include "migration/vmstate.h"
35 #include "trace.h"
36
37 #include "qxl.h"
38
39 #undef SPICE_RING_CONS_ITEM
40 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
41 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
42 if (cons >= ARRAY_SIZE((r)->items)) { \
43 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
44 "%u >= %zu", cons, ARRAY_SIZE((r)->items)); \
45 ret = NULL; \
46 } else { \
47 ret = &(r)->items[cons].el; \
48 } \
49 }
50
51 #undef ALIGN
52 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
53
54 #define PIXEL_SIZE 0.2936875 /* 1280x1024 is 14.8" x 11.9" */
55
56 #define QXL_MODE(_x, _y, _b, _o) \
57 { .x_res = _x, \
58 .y_res = _y, \
59 .bits = _b, \
60 .stride = (_x) * (_b) / 8, \
61 .x_mili = PIXEL_SIZE * (_x), \
62 .y_mili = PIXEL_SIZE * (_y), \
63 .orientation = _o, \
64 }
65
66 #define QXL_MODE_16_32(x_res, y_res, orientation) \
67 QXL_MODE(x_res, y_res, 16, orientation), \
68 QXL_MODE(x_res, y_res, 32, orientation)
69
70 #define QXL_MODE_EX(x_res, y_res) \
71 QXL_MODE_16_32(x_res, y_res, 0), \
72 QXL_MODE_16_32(x_res, y_res, 1)
73
74 static QXLMode qxl_modes[] = {
75 QXL_MODE_EX(640, 480),
76 QXL_MODE_EX(800, 480),
77 QXL_MODE_EX(800, 600),
78 QXL_MODE_EX(832, 624),
79 QXL_MODE_EX(960, 640),
80 QXL_MODE_EX(1024, 600),
81 QXL_MODE_EX(1024, 768),
82 QXL_MODE_EX(1152, 864),
83 QXL_MODE_EX(1152, 870),
84 QXL_MODE_EX(1280, 720),
85 QXL_MODE_EX(1280, 760),
86 QXL_MODE_EX(1280, 768),
87 QXL_MODE_EX(1280, 800),
88 QXL_MODE_EX(1280, 960),
89 QXL_MODE_EX(1280, 1024),
90 QXL_MODE_EX(1360, 768),
91 QXL_MODE_EX(1366, 768),
92 QXL_MODE_EX(1400, 1050),
93 QXL_MODE_EX(1440, 900),
94 QXL_MODE_EX(1600, 900),
95 QXL_MODE_EX(1600, 1200),
96 QXL_MODE_EX(1680, 1050),
97 QXL_MODE_EX(1920, 1080),
98 /* these modes need more than 8 MB video memory */
99 QXL_MODE_EX(1920, 1200),
100 QXL_MODE_EX(1920, 1440),
101 QXL_MODE_EX(2000, 2000),
102 QXL_MODE_EX(2048, 1536),
103 QXL_MODE_EX(2048, 2048),
104 QXL_MODE_EX(2560, 1440),
105 QXL_MODE_EX(2560, 1600),
106 /* these modes need more than 16 MB video memory */
107 QXL_MODE_EX(2560, 2048),
108 QXL_MODE_EX(2800, 2100),
109 QXL_MODE_EX(3200, 2400),
110 /* these modes need more than 32 MB video memory */
111 QXL_MODE_EX(3840, 2160), /* 4k mainstream */
112 QXL_MODE_EX(4096, 2160), /* 4k */
113 /* these modes need more than 64 MB video memory */
114 QXL_MODE_EX(7680, 4320), /* 8k mainstream */
115 /* these modes need more than 128 MB video memory */
116 QXL_MODE_EX(8192, 4320), /* 8k */
117 };
118
119 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
120 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
121 static void qxl_reset_memslots(PCIQXLDevice *d);
122 static void qxl_reset_surfaces(PCIQXLDevice *d);
123 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
124
125 static void qxl_hw_update(void *opaque);
126
qxl_set_guest_bug(PCIQXLDevice * qxl,const char * msg,...)127 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
128 {
129 trace_qxl_set_guest_bug(qxl->id);
130 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
131 qxl->guest_bug = 1;
132 if (qxl->guestdebug) {
133 va_list ap;
134 va_start(ap, msg);
135 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
136 vfprintf(stderr, msg, ap);
137 fprintf(stderr, "\n");
138 va_end(ap);
139 }
140 }
141
qxl_clear_guest_bug(PCIQXLDevice * qxl)142 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
143 {
144 qxl->guest_bug = 0;
145 }
146
qxl_spice_update_area(PCIQXLDevice * qxl,uint32_t surface_id,struct QXLRect * area,struct QXLRect * dirty_rects,uint32_t num_dirty_rects,uint32_t clear_dirty_region,qxl_async_io async,struct QXLCookie * cookie)147 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
148 struct QXLRect *area, struct QXLRect *dirty_rects,
149 uint32_t num_dirty_rects,
150 uint32_t clear_dirty_region,
151 qxl_async_io async, struct QXLCookie *cookie)
152 {
153 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
154 area->top, area->bottom);
155 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
156 clear_dirty_region);
157 if (async == QXL_SYNC) {
158 spice_qxl_update_area(&qxl->ssd.qxl, surface_id, area,
159 dirty_rects, num_dirty_rects, clear_dirty_region);
160 } else {
161 assert(cookie != NULL);
162 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
163 clear_dirty_region, (uintptr_t)cookie);
164 }
165 }
166
qxl_spice_destroy_surface_wait_complete(PCIQXLDevice * qxl,uint32_t id)167 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
168 uint32_t id)
169 {
170 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
171 qemu_mutex_lock(&qxl->track_lock);
172 qxl->guest_surfaces.cmds[id] = 0;
173 qxl->guest_surfaces.count--;
174 qemu_mutex_unlock(&qxl->track_lock);
175 }
176
qxl_spice_destroy_surface_wait(PCIQXLDevice * qxl,uint32_t id,qxl_async_io async)177 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
178 qxl_async_io async)
179 {
180 QXLCookie *cookie;
181
182 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
183 if (async) {
184 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
185 QXL_IO_DESTROY_SURFACE_ASYNC);
186 cookie->u.surface_id = id;
187 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
188 } else {
189 spice_qxl_destroy_surface_wait(&qxl->ssd.qxl, id);
190 qxl_spice_destroy_surface_wait_complete(qxl, id);
191 }
192 }
193
qxl_spice_flush_surfaces_async(PCIQXLDevice * qxl)194 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
195 {
196 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
197 qxl->num_free_res);
198 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
199 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
200 QXL_IO_FLUSH_SURFACES_ASYNC));
201 }
202
qxl_spice_loadvm_commands(PCIQXLDevice * qxl,struct QXLCommandExt * ext,uint32_t count)203 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
204 uint32_t count)
205 {
206 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
207 spice_qxl_loadvm_commands(&qxl->ssd.qxl, ext, count);
208 }
209
qxl_spice_oom(PCIQXLDevice * qxl)210 void qxl_spice_oom(PCIQXLDevice *qxl)
211 {
212 trace_qxl_spice_oom(qxl->id);
213 spice_qxl_oom(&qxl->ssd.qxl);
214 }
215
qxl_spice_reset_memslots(PCIQXLDevice * qxl)216 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
217 {
218 trace_qxl_spice_reset_memslots(qxl->id);
219 spice_qxl_reset_memslots(&qxl->ssd.qxl);
220 }
221
qxl_spice_destroy_surfaces_complete(PCIQXLDevice * qxl)222 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
223 {
224 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
225 qemu_mutex_lock(&qxl->track_lock);
226 memset(qxl->guest_surfaces.cmds, 0,
227 sizeof(qxl->guest_surfaces.cmds[0]) * qxl->ssd.num_surfaces);
228 qxl->guest_surfaces.count = 0;
229 qemu_mutex_unlock(&qxl->track_lock);
230 }
231
qxl_spice_destroy_surfaces(PCIQXLDevice * qxl,qxl_async_io async)232 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
233 {
234 trace_qxl_spice_destroy_surfaces(qxl->id, async);
235 if (async) {
236 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
237 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
238 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
239 } else {
240 spice_qxl_destroy_surfaces(&qxl->ssd.qxl);
241 qxl_spice_destroy_surfaces_complete(qxl);
242 }
243 }
244
qxl_spice_monitors_config_async(PCIQXLDevice * qxl,int replay)245 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
246 {
247 QXLMonitorsConfig *cfg;
248
249 trace_qxl_spice_monitors_config(qxl->id);
250 if (replay) {
251 /*
252 * don't use QXL_COOKIE_TYPE_IO:
253 * - we are not running yet (post_load), we will assert
254 * in send_events
255 * - this is not a guest io, but a reply, so async_io isn't set.
256 */
257 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
258 qxl->guest_monitors_config,
259 MEMSLOT_GROUP_GUEST,
260 (uintptr_t)qxl_cookie_new(
261 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
262 0));
263 } else {
264 #if SPICE_SERVER_VERSION < 0x000e02 /* release 0.14.2 */
265 if (qxl->max_outputs) {
266 spice_qxl_set_max_monitors(&qxl->ssd.qxl, qxl->max_outputs);
267 }
268 #endif
269 qxl->guest_monitors_config = qxl->ram->monitors_config;
270 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
271 qxl->ram->monitors_config,
272 MEMSLOT_GROUP_GUEST,
273 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
274 QXL_IO_MONITORS_CONFIG_ASYNC));
275 }
276
277 cfg = qxl_phys2virt(qxl, qxl->guest_monitors_config, MEMSLOT_GROUP_GUEST,
278 sizeof(QXLMonitorsConfig));
279 if (cfg != NULL && cfg->count == 1) {
280 qxl->guest_primary.resized = 1;
281 qxl->guest_head0_width = cfg->heads[0].width;
282 qxl->guest_head0_height = cfg->heads[0].height;
283 } else {
284 qxl->guest_head0_width = 0;
285 qxl->guest_head0_height = 0;
286 }
287 }
288
qxl_spice_reset_image_cache(PCIQXLDevice * qxl)289 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
290 {
291 trace_qxl_spice_reset_image_cache(qxl->id);
292 spice_qxl_reset_image_cache(&qxl->ssd.qxl);
293 }
294
qxl_spice_reset_cursor(PCIQXLDevice * qxl)295 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
296 {
297 trace_qxl_spice_reset_cursor(qxl->id);
298 spice_qxl_reset_cursor(&qxl->ssd.qxl);
299 qemu_mutex_lock(&qxl->track_lock);
300 qxl->guest_cursor = 0;
301 qemu_mutex_unlock(&qxl->track_lock);
302 if (qxl->ssd.cursor) {
303 cursor_unref(qxl->ssd.cursor);
304 }
305 qxl->ssd.cursor = cursor_builtin_hidden();
306 }
307
qxl_crc32(const uint8_t * p,unsigned len)308 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
309 {
310 /*
311 * zlib xors the seed with 0xffffffff, and xors the result
312 * again with 0xffffffff; Both are not done with linux's crc32,
313 * which we want to be compatible with, so undo that.
314 */
315 return crc32(0xffffffff, p, len) ^ 0xffffffff;
316 }
317
qxl_rom_size(void)318 static ram_addr_t qxl_rom_size(void)
319 {
320 #define QXL_REQUIRED_SZ (sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes))
321 #define QXL_ROM_SZ 8192
322
323 QEMU_BUILD_BUG_ON(QXL_REQUIRED_SZ > QXL_ROM_SZ);
324 return QEMU_ALIGN_UP(QXL_REQUIRED_SZ, qemu_real_host_page_size());
325 }
326
init_qxl_rom(PCIQXLDevice * d)327 static void init_qxl_rom(PCIQXLDevice *d)
328 {
329 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
330 QXLModes *modes = (QXLModes *)(rom + 1);
331 uint32_t ram_header_size;
332 uint32_t surface0_area_size;
333 uint32_t num_pages;
334 uint32_t fb;
335 int i, n;
336
337 if (cpr_is_incoming()) {
338 goto skip_init;
339 }
340
341 memset(rom, 0, d->rom_size);
342
343 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
344 rom->id = cpu_to_le32(d->id);
345 rom->log_level = cpu_to_le32(d->guestdebug);
346 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
347
348 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
349 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
350 rom->slots_start = 1;
351 rom->slots_end = NUM_MEMSLOTS - 1;
352 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
353
354 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
355 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
356 if (fb > d->vgamem_size) {
357 continue;
358 }
359 modes->modes[n].id = cpu_to_le32(i);
360 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
361 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
362 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
363 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
364 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
365 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
366 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
367 n++;
368 }
369 modes->n_modes = cpu_to_le32(n);
370
371 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
372 surface0_area_size = ALIGN(d->vgamem_size, 4096);
373 num_pages = d->vga.vram_size;
374 num_pages -= ram_header_size;
375 num_pages -= surface0_area_size;
376 num_pages = num_pages / QXL_PAGE_SIZE;
377
378 assert(ram_header_size + surface0_area_size <= d->vga.vram_size);
379
380 rom->draw_area_offset = cpu_to_le32(0);
381 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
382 rom->pages_offset = cpu_to_le32(surface0_area_size);
383 rom->num_pages = cpu_to_le32(num_pages);
384 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
385
386 if (d->xres && d->yres) {
387 /* needs linux kernel 4.12+ to work */
388 rom->client_monitors_config.count = 1;
389 rom->client_monitors_config.heads[0].left = 0;
390 rom->client_monitors_config.heads[0].top = 0;
391 rom->client_monitors_config.heads[0].right = cpu_to_le32(d->xres);
392 rom->client_monitors_config.heads[0].bottom = cpu_to_le32(d->yres);
393 rom->client_monitors_config_crc = qxl_crc32(
394 (const uint8_t *)&rom->client_monitors_config,
395 sizeof(rom->client_monitors_config));
396 }
397
398 skip_init:
399 d->shadow_rom = *rom;
400 d->rom = rom;
401 d->modes = modes;
402 }
403
init_qxl_ram(PCIQXLDevice * d)404 static void init_qxl_ram(PCIQXLDevice *d)
405 {
406 uint8_t *buf;
407 uint32_t prod;
408 QXLReleaseRing *ring;
409
410 buf = d->vga.vram_ptr;
411 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
412 if (cpr_is_incoming()) {
413 return;
414 }
415 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
416 d->ram->int_pending = cpu_to_le32(0);
417 d->ram->int_mask = cpu_to_le32(0);
418 d->ram->update_surface = 0;
419 d->ram->monitors_config = 0;
420 SPICE_RING_INIT(&d->ram->cmd_ring);
421 SPICE_RING_INIT(&d->ram->cursor_ring);
422 SPICE_RING_INIT(&d->ram->release_ring);
423
424 ring = &d->ram->release_ring;
425 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
426 assert(prod < ARRAY_SIZE(ring->items));
427 ring->items[prod].el = 0;
428
429 qxl_ring_set_dirty(d);
430 }
431
432 /* can be called from spice server thread context */
qxl_set_dirty(MemoryRegion * mr,ram_addr_t addr,ram_addr_t end)433 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
434 {
435 memory_region_set_dirty(mr, addr, end - addr);
436 }
437
qxl_rom_set_dirty(PCIQXLDevice * qxl)438 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
439 {
440 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
441 }
442
443 /* called from spice server thread context only */
qxl_ram_set_dirty(PCIQXLDevice * qxl,void * ptr)444 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
445 {
446 void *base = qxl->vga.vram_ptr;
447 intptr_t offset;
448
449 offset = ptr - base;
450 assert(offset < qxl->vga.vram_size);
451 qxl_set_dirty(&qxl->vga.vram, offset, offset + 3);
452 }
453
454 /* can be called from spice server thread context */
qxl_ring_set_dirty(PCIQXLDevice * qxl)455 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
456 {
457 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
458 ram_addr_t end = qxl->vga.vram_size;
459 qxl_set_dirty(&qxl->vga.vram, addr, end);
460 }
461
462 /*
463 * keep track of some command state, for savevm/loadvm.
464 * called from spice server thread context only
465 */
qxl_track_command(PCIQXLDevice * qxl,struct QXLCommandExt * ext)466 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
467 {
468 switch (le32_to_cpu(ext->cmd.type)) {
469 case QXL_CMD_SURFACE:
470 {
471 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id,
472 sizeof(QXLSurfaceCmd));
473
474 if (!cmd) {
475 return 1;
476 }
477 uint32_t id = le32_to_cpu(cmd->surface_id);
478
479 if (id >= qxl->ssd.num_surfaces) {
480 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
481 qxl->ssd.num_surfaces);
482 return 1;
483 }
484 if (cmd->type == QXL_SURFACE_CMD_CREATE &&
485 (cmd->u.surface_create.stride & 0x03) != 0) {
486 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE stride = %d %% 4 != 0\n",
487 cmd->u.surface_create.stride);
488 return 1;
489 }
490 WITH_QEMU_LOCK_GUARD(&qxl->track_lock) {
491 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
492 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
493 qxl->guest_surfaces.count++;
494 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count) {
495 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
496 }
497 }
498 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
499 qxl->guest_surfaces.cmds[id] = 0;
500 qxl->guest_surfaces.count--;
501 }
502 }
503 break;
504 }
505 case QXL_CMD_CURSOR:
506 {
507 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id,
508 sizeof(QXLCursorCmd));
509
510 if (!cmd) {
511 return 1;
512 }
513 if (cmd->type == QXL_CURSOR_SET) {
514 qemu_mutex_lock(&qxl->track_lock);
515 qxl->guest_cursor = ext->cmd.data;
516 qemu_mutex_unlock(&qxl->track_lock);
517 }
518 if (cmd->type == QXL_CURSOR_HIDE) {
519 qemu_mutex_lock(&qxl->track_lock);
520 qxl->guest_cursor = 0;
521 qemu_mutex_unlock(&qxl->track_lock);
522 }
523 break;
524 }
525 }
526 return 0;
527 }
528
529 /* spice display interface callbacks */
530
interface_attached_worker(QXLInstance * sin)531 static void interface_attached_worker(QXLInstance *sin)
532 {
533 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
534
535 trace_qxl_interface_attach_worker(qxl->id);
536 }
537
538 #if !(SPICE_HAS_ATTACHED_WORKER)
interface_attach_worker(QXLInstance * sin,QXLWorker * qxl_worker)539 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
540 {
541 interface_attached_worker(sin);
542 }
543 #endif
544
interface_set_compression_level(QXLInstance * sin,int level)545 static void interface_set_compression_level(QXLInstance *sin, int level)
546 {
547 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
548
549 trace_qxl_interface_set_compression_level(qxl->id, level);
550 qxl->shadow_rom.compression_level = cpu_to_le32(level);
551 if (cpr_is_incoming()) {
552 assert(qxl->rom->compression_level == cpu_to_le32(level));
553 return;
554 }
555 qxl->rom->compression_level = cpu_to_le32(level);
556 qxl_rom_set_dirty(qxl);
557 }
558
interface_get_init_info(QXLInstance * sin,QXLDevInitInfo * info)559 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
560 {
561 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
562
563 trace_qxl_interface_get_init_info(qxl->id);
564 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
565 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
566 info->num_memslots = NUM_MEMSLOTS;
567 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
568 info->internal_groupslot_id = 0;
569 info->qxl_ram_size =
570 le32_to_cpu(qxl->shadow_rom.num_pages) << QXL_PAGE_BITS;
571 info->n_surfaces = qxl->ssd.num_surfaces;
572 }
573
qxl_mode_to_string(int mode)574 static const char *qxl_mode_to_string(int mode)
575 {
576 switch (mode) {
577 case QXL_MODE_COMPAT:
578 return "compat";
579 case QXL_MODE_NATIVE:
580 return "native";
581 case QXL_MODE_UNDEFINED:
582 return "undefined";
583 case QXL_MODE_VGA:
584 return "vga";
585 }
586 return "INVALID";
587 }
588
io_port_to_string(uint32_t io_port)589 static const char *io_port_to_string(uint32_t io_port)
590 {
591 if (io_port >= QXL_IO_RANGE_SIZE) {
592 return "out of range";
593 }
594 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
595 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
596 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
597 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
598 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
599 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
600 [QXL_IO_RESET] = "QXL_IO_RESET",
601 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
602 [QXL_IO_LOG] = "QXL_IO_LOG",
603 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
604 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
605 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
606 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
607 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
608 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
609 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
610 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
611 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
612 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
613 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
614 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
615 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
616 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
617 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
618 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
619 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
620 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
621 };
622 return io_port_to_string[io_port];
623 }
624
625 /* called from spice server thread context only */
interface_get_command(QXLInstance * sin,struct QXLCommandExt * ext)626 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
627 {
628 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
629 SimpleSpiceUpdate *update;
630 QXLCommandRing *ring;
631 QXLCommand *cmd;
632 int notify, ret;
633
634 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
635
636 switch (qxl->mode) {
637 case QXL_MODE_VGA:
638 ret = false;
639 qemu_mutex_lock(&qxl->ssd.lock);
640 update = QTAILQ_FIRST(&qxl->ssd.updates);
641 if (update != NULL) {
642 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
643 *ext = update->ext;
644 ret = true;
645 }
646 qemu_mutex_unlock(&qxl->ssd.lock);
647 if (ret) {
648 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
649 qxl_log_command(qxl, "vga", ext);
650 }
651 return ret;
652 case QXL_MODE_COMPAT:
653 case QXL_MODE_NATIVE:
654 case QXL_MODE_UNDEFINED:
655 ring = &qxl->ram->cmd_ring;
656 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
657 return false;
658 }
659 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
660 if (!cmd) {
661 return false;
662 }
663 ext->cmd = *cmd;
664 ext->group_id = MEMSLOT_GROUP_GUEST;
665 ext->flags = qxl->cmdflags;
666 SPICE_RING_POP(ring, notify);
667 qxl_ring_set_dirty(qxl);
668 if (notify) {
669 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
670 }
671 qxl->guest_primary.commands++;
672 qxl_track_command(qxl, ext);
673 qxl_log_command(qxl, "cmd", ext);
674 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
675 return true;
676 default:
677 return false;
678 }
679 }
680
681 /* called from spice server thread context only */
interface_req_cmd_notification(QXLInstance * sin)682 static int interface_req_cmd_notification(QXLInstance *sin)
683 {
684 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
685 int wait = 1;
686
687 trace_qxl_ring_command_req_notification(qxl->id);
688 switch (qxl->mode) {
689 case QXL_MODE_COMPAT:
690 case QXL_MODE_NATIVE:
691 case QXL_MODE_UNDEFINED:
692 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
693 qxl_ring_set_dirty(qxl);
694 break;
695 default:
696 /* nothing */
697 break;
698 }
699 return wait;
700 }
701
702 /* called from spice server thread context only */
qxl_push_free_res(PCIQXLDevice * d,int flush)703 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
704 {
705 QXLReleaseRing *ring = &d->ram->release_ring;
706 uint32_t prod;
707 int notify;
708
709 #define QXL_FREE_BUNCH_SIZE 32
710
711 if (ring->prod - ring->cons + 1 == ring->num_items) {
712 /* ring full -- can't push */
713 return;
714 }
715 if (!flush && d->oom_running) {
716 /* collect everything from oom handler before pushing */
717 return;
718 }
719 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
720 /* collect a bit more before pushing */
721 return;
722 }
723
724 SPICE_RING_PUSH(ring, notify);
725 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
726 d->guest_surfaces.count, d->num_free_res,
727 d->last_release, notify ? "yes" : "no");
728 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
729 ring->num_items, ring->prod, ring->cons);
730 if (notify) {
731 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
732 }
733
734 ring = &d->ram->release_ring;
735 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
736 if (prod >= ARRAY_SIZE(ring->items)) {
737 qxl_set_guest_bug(d, "SPICE_RING_PROD_ITEM indices mismatch "
738 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
739 return;
740 }
741 ring->items[prod].el = 0;
742 d->num_free_res = 0;
743 d->last_release = NULL;
744 qxl_ring_set_dirty(d);
745 }
746
747 /* called from spice server thread context only */
interface_release_resource(QXLInstance * sin,QXLReleaseInfoExt ext)748 static void interface_release_resource(QXLInstance *sin,
749 QXLReleaseInfoExt ext)
750 {
751 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
752 QXLReleaseRing *ring;
753 uint32_t prod;
754 uint64_t id;
755
756 if (!ext.info) {
757 return;
758 }
759 if (ext.group_id == MEMSLOT_GROUP_HOST) {
760 /* host group -> vga mode update request */
761 QXLCommandExt *cmdext = (void *)(intptr_t)(ext.info->id);
762 SimpleSpiceUpdate *update;
763 g_assert(cmdext->cmd.type == QXL_CMD_DRAW);
764 update = container_of(cmdext, SimpleSpiceUpdate, ext);
765 qemu_spice_destroy_update(&qxl->ssd, update);
766 return;
767 }
768
769 /*
770 * ext->info points into guest-visible memory
771 * pci bar 0, $command.release_info
772 */
773 ring = &qxl->ram->release_ring;
774 prod = ring->prod & SPICE_RING_INDEX_MASK(ring);
775 if (prod >= ARRAY_SIZE(ring->items)) {
776 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch "
777 "%u >= %zu", prod, ARRAY_SIZE(ring->items));
778 return;
779 }
780 if (ring->items[prod].el == 0) {
781 /* stick head into the ring */
782 id = ext.info->id;
783 ext.info->next = 0;
784 qxl_ram_set_dirty(qxl, &ext.info->next);
785 ring->items[prod].el = id;
786 qxl_ring_set_dirty(qxl);
787 } else {
788 /* append item to the list */
789 qxl->last_release->next = ext.info->id;
790 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
791 ext.info->next = 0;
792 qxl_ram_set_dirty(qxl, &ext.info->next);
793 }
794 qxl->last_release = ext.info;
795 qxl->num_free_res++;
796 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
797 qxl_push_free_res(qxl, 0);
798 }
799
800 /* called from spice server thread context only */
interface_get_cursor_command(QXLInstance * sin,struct QXLCommandExt * ext)801 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
802 {
803 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
804 QXLCursorRing *ring;
805 QXLCommand *cmd;
806 int notify;
807
808 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
809
810 switch (qxl->mode) {
811 case QXL_MODE_COMPAT:
812 case QXL_MODE_NATIVE:
813 case QXL_MODE_UNDEFINED:
814 ring = &qxl->ram->cursor_ring;
815 if (SPICE_RING_IS_EMPTY(ring)) {
816 return false;
817 }
818 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
819 if (!cmd) {
820 return false;
821 }
822 ext->cmd = *cmd;
823 ext->group_id = MEMSLOT_GROUP_GUEST;
824 ext->flags = qxl->cmdflags;
825 SPICE_RING_POP(ring, notify);
826 qxl_ring_set_dirty(qxl);
827 if (notify) {
828 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
829 }
830 qxl->guest_primary.commands++;
831 qxl_track_command(qxl, ext);
832 qxl_log_command(qxl, "csr", ext);
833 if (qxl->have_vga) {
834 qxl_render_cursor(qxl, ext);
835 }
836 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
837 return true;
838 default:
839 return false;
840 }
841 }
842
843 /* called from spice server thread context only */
interface_req_cursor_notification(QXLInstance * sin)844 static int interface_req_cursor_notification(QXLInstance *sin)
845 {
846 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
847 int wait = 1;
848
849 trace_qxl_ring_cursor_req_notification(qxl->id);
850 switch (qxl->mode) {
851 case QXL_MODE_COMPAT:
852 case QXL_MODE_NATIVE:
853 case QXL_MODE_UNDEFINED:
854 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
855 qxl_ring_set_dirty(qxl);
856 break;
857 default:
858 /* nothing */
859 break;
860 }
861 return wait;
862 }
863
864 /* called from spice server thread context */
interface_notify_update(QXLInstance * sin,uint32_t update_id)865 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
866 {
867 /*
868 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
869 * use by xf86-video-qxl and is defined out in the qxl windows driver.
870 * Probably was at some earlier version that is prior to git start (2009),
871 * and is still guest trigerrable.
872 */
873 fprintf(stderr, "%s: deprecated\n", __func__);
874 }
875
876 /* called from spice server thread context only */
interface_flush_resources(QXLInstance * sin)877 static int interface_flush_resources(QXLInstance *sin)
878 {
879 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
880 int ret;
881
882 ret = qxl->num_free_res;
883 if (ret) {
884 qxl_push_free_res(qxl, 1);
885 }
886 return ret;
887 }
888
889 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
890
891 /* called from spice server thread context only */
interface_async_complete_io(PCIQXLDevice * qxl,QXLCookie * cookie)892 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
893 {
894 uint32_t current_async;
895
896 qemu_mutex_lock(&qxl->async_lock);
897 current_async = qxl->current_async;
898 qxl->current_async = QXL_UNDEFINED_IO;
899 qemu_mutex_unlock(&qxl->async_lock);
900
901 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
902 if (!cookie) {
903 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
904 return;
905 }
906 if (cookie && current_async != cookie->io) {
907 fprintf(stderr,
908 "qxl: %s: error: current_async = %d != %"
909 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
910 }
911 switch (current_async) {
912 case QXL_IO_MEMSLOT_ADD_ASYNC:
913 case QXL_IO_DESTROY_PRIMARY_ASYNC:
914 case QXL_IO_UPDATE_AREA_ASYNC:
915 case QXL_IO_FLUSH_SURFACES_ASYNC:
916 case QXL_IO_MONITORS_CONFIG_ASYNC:
917 break;
918 case QXL_IO_CREATE_PRIMARY_ASYNC:
919 qxl_create_guest_primary_complete(qxl);
920 break;
921 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
922 qxl_spice_destroy_surfaces_complete(qxl);
923 break;
924 case QXL_IO_DESTROY_SURFACE_ASYNC:
925 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
926 break;
927 default:
928 fprintf(stderr, "qxl: %s: unexpected current_async %u\n", __func__,
929 current_async);
930 }
931 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
932 }
933
934 /* called from spice server thread context only */
interface_update_area_complete(QXLInstance * sin,uint32_t surface_id,QXLRect * dirty,uint32_t num_updated_rects)935 static void interface_update_area_complete(QXLInstance *sin,
936 uint32_t surface_id,
937 QXLRect *dirty, uint32_t num_updated_rects)
938 {
939 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
940 int i;
941 int qxl_i;
942
943 QEMU_LOCK_GUARD(&qxl->ssd.lock);
944 if (surface_id != 0 || !num_updated_rects ||
945 !qxl->render_update_cookie_num) {
946 return;
947 }
948 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
949 dirty->right, dirty->top, dirty->bottom);
950 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
951 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
952 /*
953 * overflow - treat this as a full update. Not expected to be common.
954 */
955 trace_qxl_interface_update_area_complete_overflow(qxl->id,
956 QXL_NUM_DIRTY_RECTS);
957 qxl->guest_primary.resized = 1;
958 }
959 if (qxl->guest_primary.resized) {
960 /*
961 * Don't bother copying or scheduling the bh since we will flip
962 * the whole area anyway on completion of the update_area async call
963 */
964 return;
965 }
966 qxl_i = qxl->num_dirty_rects;
967 for (i = 0; i < num_updated_rects; i++) {
968 qxl->dirty[qxl_i++] = dirty[i];
969 }
970 qxl->num_dirty_rects += num_updated_rects;
971 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
972 qxl->num_dirty_rects);
973 qemu_bh_schedule(qxl->update_area_bh);
974 }
975
976 /* called from spice server thread context only */
interface_async_complete(QXLInstance * sin,uint64_t cookie_token)977 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
978 {
979 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
980 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
981
982 switch (cookie->type) {
983 case QXL_COOKIE_TYPE_IO:
984 interface_async_complete_io(qxl, cookie);
985 g_free(cookie);
986 break;
987 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
988 qxl_render_update_area_done(qxl, cookie);
989 break;
990 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
991 break;
992 default:
993 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
994 __func__, cookie->type);
995 g_free(cookie);
996 }
997 }
998
999 /* called from spice server thread context only */
interface_set_client_capabilities(QXLInstance * sin,uint8_t client_present,uint8_t caps[58])1000 static void interface_set_client_capabilities(QXLInstance *sin,
1001 uint8_t client_present,
1002 uint8_t caps[58])
1003 {
1004 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1005
1006 if (qxl->revision < 4) {
1007 trace_qxl_set_client_capabilities_unsupported_by_revision(qxl->id,
1008 qxl->revision);
1009 return;
1010 }
1011
1012 if (runstate_check(RUN_STATE_INMIGRATE) ||
1013 runstate_check(RUN_STATE_POSTMIGRATE) ||
1014 cpr_is_incoming()) {
1015 return;
1016 }
1017
1018 qxl->shadow_rom.client_present = client_present;
1019 memcpy(qxl->shadow_rom.client_capabilities, caps,
1020 sizeof(qxl->shadow_rom.client_capabilities));
1021 qxl->rom->client_present = client_present;
1022 memcpy(qxl->rom->client_capabilities, caps,
1023 sizeof(qxl->rom->client_capabilities));
1024 qxl_rom_set_dirty(qxl);
1025
1026 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
1027 }
1028
qxl_rom_monitors_config_changed(QXLRom * rom,VDAgentMonitorsConfig * monitors_config,unsigned int max_outputs)1029 static bool qxl_rom_monitors_config_changed(QXLRom *rom,
1030 VDAgentMonitorsConfig *monitors_config,
1031 unsigned int max_outputs)
1032 {
1033 int i;
1034 unsigned int monitors_count;
1035
1036 monitors_count = MIN(monitors_config->num_of_monitors, max_outputs);
1037
1038 if (rom->client_monitors_config.count != monitors_count) {
1039 return true;
1040 }
1041
1042 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1043 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1044 QXLURect *rect = &rom->client_monitors_config.heads[i];
1045 /* monitor->depth ignored */
1046 if ((rect->left != monitor->x) ||
1047 (rect->top != monitor->y) ||
1048 (rect->right != monitor->x + monitor->width) ||
1049 (rect->bottom != monitor->y + monitor->height)) {
1050 return true;
1051 }
1052 }
1053
1054 return false;
1055 }
1056
1057 /* called from main context only */
interface_client_monitors_config(QXLInstance * sin,VDAgentMonitorsConfig * monitors_config)1058 static int interface_client_monitors_config(QXLInstance *sin,
1059 VDAgentMonitorsConfig *monitors_config)
1060 {
1061 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
1062 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
1063 int i;
1064 unsigned max_outputs = ARRAY_SIZE(rom->client_monitors_config.heads);
1065 bool config_changed = false;
1066
1067 if (qxl->revision < 4) {
1068 trace_qxl_client_monitors_config_unsupported_by_device(qxl->id,
1069 qxl->revision);
1070 return 0;
1071 }
1072 /*
1073 * Older windows drivers set int_mask to 0 when their ISR is called,
1074 * then later set it to ~0. So it doesn't relate to the actual interrupts
1075 * handled. However, they are old, so clearly they don't support this
1076 * interrupt
1077 */
1078 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1079 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1080 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1081 qxl->ram->int_mask,
1082 monitors_config);
1083 return 0;
1084 }
1085 if (!monitors_config) {
1086 return 1;
1087 }
1088
1089 /* limit number of outputs based on setting limit */
1090 if (qxl->max_outputs && qxl->max_outputs <= max_outputs) {
1091 max_outputs = qxl->max_outputs;
1092 }
1093
1094 config_changed = qxl_rom_monitors_config_changed(rom,
1095 monitors_config,
1096 max_outputs);
1097
1098 memset(&rom->client_monitors_config, 0,
1099 sizeof(rom->client_monitors_config));
1100 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1101 /* monitors_config->flags ignored */
1102 if (rom->client_monitors_config.count >= max_outputs) {
1103 trace_qxl_client_monitors_config_capped(qxl->id,
1104 monitors_config->num_of_monitors,
1105 max_outputs);
1106 rom->client_monitors_config.count = max_outputs;
1107 }
1108 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1109 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1110 QXLURect *rect = &rom->client_monitors_config.heads[i];
1111 /* monitor->depth ignored */
1112 rect->left = monitor->x;
1113 rect->top = monitor->y;
1114 rect->right = monitor->x + monitor->width;
1115 rect->bottom = monitor->y + monitor->height;
1116 }
1117 rom->client_monitors_config_crc = qxl_crc32(
1118 (const uint8_t *)&rom->client_monitors_config,
1119 sizeof(rom->client_monitors_config));
1120 trace_qxl_client_monitors_config_crc(qxl->id,
1121 sizeof(rom->client_monitors_config),
1122 rom->client_monitors_config_crc);
1123
1124 trace_qxl_interrupt_client_monitors_config(qxl->id,
1125 rom->client_monitors_config.count,
1126 rom->client_monitors_config.heads);
1127 if (config_changed) {
1128 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1129 }
1130 return 1;
1131 }
1132
1133 static const QXLInterface qxl_interface = {
1134 .base.type = SPICE_INTERFACE_QXL,
1135 .base.description = "qxl gpu",
1136 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1137 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1138
1139 #if SPICE_HAS_ATTACHED_WORKER
1140 .attached_worker = interface_attached_worker,
1141 #else
1142 .attache_worker = interface_attach_worker,
1143 #endif
1144
1145 .set_compression_level = interface_set_compression_level,
1146 .get_init_info = interface_get_init_info,
1147
1148 /* the callbacks below are called from spice server thread context */
1149 .get_command = interface_get_command,
1150 .req_cmd_notification = interface_req_cmd_notification,
1151 .release_resource = interface_release_resource,
1152 .get_cursor_command = interface_get_cursor_command,
1153 .req_cursor_notification = interface_req_cursor_notification,
1154 .notify_update = interface_notify_update,
1155 .flush_resources = interface_flush_resources,
1156 .async_complete = interface_async_complete,
1157 .update_area_complete = interface_update_area_complete,
1158 .set_client_capabilities = interface_set_client_capabilities,
1159 .client_monitors_config = interface_client_monitors_config,
1160 };
1161
1162 static const GraphicHwOps qxl_ops = {
1163 .gfx_update = qxl_hw_update,
1164 .gfx_update_async = true,
1165 };
1166
qxl_enter_vga_mode(PCIQXLDevice * d)1167 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1168 {
1169 if (d->mode == QXL_MODE_VGA) {
1170 return;
1171 }
1172 trace_qxl_enter_vga_mode(d->id);
1173 spice_qxl_driver_unload(&d->ssd.qxl);
1174 graphic_console_set_hwops(d->ssd.dcl.con, d->vga.hw_ops, &d->vga);
1175 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_DEFAULT);
1176 qemu_spice_create_host_primary(&d->ssd);
1177 d->mode = QXL_MODE_VGA;
1178 qemu_spice_display_switch(&d->ssd, d->ssd.ds);
1179 vga_dirty_log_start(&d->vga);
1180 graphic_hw_update(d->vga.con);
1181 }
1182
qxl_exit_vga_mode(PCIQXLDevice * d)1183 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1184 {
1185 if (d->mode != QXL_MODE_VGA) {
1186 return;
1187 }
1188 trace_qxl_exit_vga_mode(d->id);
1189 graphic_console_set_hwops(d->ssd.dcl.con, &qxl_ops, d);
1190 update_displaychangelistener(&d->ssd.dcl, GUI_REFRESH_INTERVAL_IDLE);
1191 vga_dirty_log_stop(&d->vga);
1192 qxl_destroy_primary(d, QXL_SYNC);
1193 }
1194
qxl_update_irq(PCIQXLDevice * d)1195 static void qxl_update_irq(PCIQXLDevice *d)
1196 {
1197 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1198 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1199 int level = !!(pending & mask);
1200 pci_set_irq(&d->pci, level);
1201 qxl_ring_set_dirty(d);
1202 }
1203
qxl_check_state(PCIQXLDevice * d)1204 static void qxl_check_state(PCIQXLDevice *d)
1205 {
1206 QXLRam *ram = d->ram;
1207 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1208
1209 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1210 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1211 }
1212
qxl_reset_state(PCIQXLDevice * d)1213 static void qxl_reset_state(PCIQXLDevice *d)
1214 {
1215 QXLRom *rom = d->rom;
1216
1217 if (cpr_is_incoming()) {
1218 return;
1219 }
1220
1221 qxl_check_state(d);
1222 d->shadow_rom.update_id = cpu_to_le32(0);
1223 *rom = d->shadow_rom;
1224 qxl_rom_set_dirty(d);
1225 init_qxl_ram(d);
1226 d->num_free_res = 0;
1227 d->last_release = NULL;
1228 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1229 qxl_update_irq(d);
1230 }
1231
qxl_soft_reset(PCIQXLDevice * d)1232 static void qxl_soft_reset(PCIQXLDevice *d)
1233 {
1234 trace_qxl_soft_reset(d->id);
1235 qxl_check_state(d);
1236 qxl_clear_guest_bug(d);
1237 qemu_mutex_lock(&d->async_lock);
1238 d->current_async = QXL_UNDEFINED_IO;
1239 qemu_mutex_unlock(&d->async_lock);
1240
1241 if (d->have_vga) {
1242 qxl_enter_vga_mode(d);
1243 } else {
1244 d->mode = QXL_MODE_UNDEFINED;
1245 }
1246 }
1247
qxl_hard_reset(PCIQXLDevice * d,int loadvm)1248 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1249 {
1250 bool startstop = qemu_spice_display_is_running(&d->ssd);
1251
1252 trace_qxl_hard_reset(d->id, loadvm);
1253
1254 if (startstop) {
1255 qemu_spice_display_stop();
1256 }
1257
1258 qxl_spice_reset_cursor(d);
1259 qxl_spice_reset_image_cache(d);
1260 qxl_reset_surfaces(d);
1261 qxl_reset_memslots(d);
1262
1263 /* pre loadvm reset must not touch QXLRam. This lives in
1264 * device memory, is migrated together with RAM and thus
1265 * already loaded at this point */
1266 if (!loadvm) {
1267 qxl_reset_state(d);
1268 }
1269 qemu_spice_create_host_memslot(&d->ssd);
1270 qxl_soft_reset(d);
1271
1272 if (startstop) {
1273 qemu_spice_display_start();
1274 }
1275 }
1276
qxl_reset_handler(DeviceState * dev)1277 static void qxl_reset_handler(DeviceState *dev)
1278 {
1279 PCIQXLDevice *d = PCI_QXL(PCI_DEVICE(dev));
1280
1281 qxl_hard_reset(d, 0);
1282 }
1283
qxl_vga_ioport_write(void * opaque,uint32_t addr,uint32_t val)1284 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1285 {
1286 VGACommonState *vga = opaque;
1287 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1288
1289 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1290 if (qxl->mode != QXL_MODE_VGA &&
1291 qxl->revision <= QXL_REVISION_STABLE_V12) {
1292 qxl_destroy_primary(qxl, QXL_SYNC);
1293 qxl_soft_reset(qxl);
1294 }
1295 vga_ioport_write(opaque, addr, val);
1296 }
1297
1298 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1299 { 0x04, 2, 1, .read = vga_ioport_read,
1300 .write = qxl_vga_ioport_write }, /* 3b4 */
1301 { 0x0a, 1, 1, .read = vga_ioport_read,
1302 .write = qxl_vga_ioport_write }, /* 3ba */
1303 { 0x10, 16, 1, .read = vga_ioport_read,
1304 .write = qxl_vga_ioport_write }, /* 3c0 */
1305 { 0x24, 2, 1, .read = vga_ioport_read,
1306 .write = qxl_vga_ioport_write }, /* 3d4 */
1307 { 0x2a, 1, 1, .read = vga_ioport_read,
1308 .write = qxl_vga_ioport_write }, /* 3da */
1309 PORTIO_END_OF_LIST(),
1310 };
1311
qxl_add_memslot(PCIQXLDevice * d,uint32_t slot_id,uint64_t delta,qxl_async_io async)1312 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1313 qxl_async_io async)
1314 {
1315 static const int regions[] = {
1316 QXL_RAM_RANGE_INDEX,
1317 QXL_VRAM_RANGE_INDEX,
1318 QXL_VRAM64_RANGE_INDEX,
1319 };
1320 uint64_t guest_start;
1321 uint64_t guest_end;
1322 int pci_region = -1;
1323 pcibus_t pci_start = PCI_BAR_UNMAPPED;
1324 pcibus_t pci_end;
1325 MemoryRegion *mr;
1326 intptr_t virt_start;
1327 QXLDevMemSlot memslot;
1328 int i;
1329
1330 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1331 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1332
1333 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1334
1335 if (slot_id >= NUM_MEMSLOTS) {
1336 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1337 slot_id, NUM_MEMSLOTS);
1338 return 1;
1339 }
1340 if (guest_start > guest_end) {
1341 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1342 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1343 return 1;
1344 }
1345
1346 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1347 pci_region = regions[i];
1348 pci_start = d->pci.io_regions[pci_region].addr;
1349 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1350 /* mapped? */
1351 if (pci_start == -1) {
1352 continue;
1353 }
1354 /* start address in range ? */
1355 if (guest_start < pci_start || guest_start > pci_end) {
1356 continue;
1357 }
1358 /* end address in range ? */
1359 if (guest_end > pci_end) {
1360 continue;
1361 }
1362 /* passed */
1363 break;
1364 }
1365 if (i == ARRAY_SIZE(regions)) {
1366 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1367 return 1;
1368 }
1369
1370 switch (pci_region) {
1371 case QXL_RAM_RANGE_INDEX:
1372 mr = &d->vga.vram;
1373 break;
1374 case QXL_VRAM_RANGE_INDEX:
1375 case 4 /* vram 64bit */:
1376 mr = &d->vram_bar;
1377 break;
1378 default:
1379 /* should not happen */
1380 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1381 return 1;
1382 }
1383 assert(guest_end - pci_start <= memory_region_size(mr));
1384
1385 virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
1386 memslot.slot_id = slot_id;
1387 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1388 memslot.virt_start = virt_start + (guest_start - pci_start);
1389 memslot.virt_end = virt_start + (guest_end - pci_start);
1390 memslot.addr_delta = memslot.virt_start - delta;
1391 if (!cpr_is_incoming()) {
1392 d->rom->slot_generation = 0;
1393 qxl_rom_set_dirty(d);
1394 }
1395 memslot.generation = d->rom->slot_generation;
1396
1397 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1398 d->guest_slots[slot_id].mr = mr;
1399 d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
1400 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1401 d->guest_slots[slot_id].delta = delta;
1402 d->guest_slots[slot_id].active = 1;
1403 return 0;
1404 }
1405
qxl_del_memslot(PCIQXLDevice * d,uint32_t slot_id)1406 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1407 {
1408 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1409 d->guest_slots[slot_id].active = 0;
1410 }
1411
qxl_reset_memslots(PCIQXLDevice * d)1412 static void qxl_reset_memslots(PCIQXLDevice *d)
1413 {
1414 qxl_spice_reset_memslots(d);
1415 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1416 }
1417
qxl_reset_surfaces(PCIQXLDevice * d)1418 static void qxl_reset_surfaces(PCIQXLDevice *d)
1419 {
1420 trace_qxl_reset_surfaces(d->id);
1421 d->mode = QXL_MODE_UNDEFINED;
1422 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1423 }
1424
1425 /* can be also called from spice server thread context */
qxl_get_check_slot_offset(PCIQXLDevice * qxl,QXLPHYSICAL pqxl,uint32_t * s,uint64_t * o,size_t size_requested)1426 static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1427 uint32_t *s, uint64_t *o,
1428 size_t size_requested)
1429 {
1430 uint64_t phys = le64_to_cpu(pqxl);
1431 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1432 uint64_t offset = phys & 0xffffffffffff;
1433 uint64_t size_available;
1434
1435 if (slot >= NUM_MEMSLOTS) {
1436 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1437 NUM_MEMSLOTS);
1438 return false;
1439 }
1440 if (!qxl->guest_slots[slot].active) {
1441 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1442 return false;
1443 }
1444 if (offset < qxl->guest_slots[slot].delta) {
1445 qxl_set_guest_bug(qxl,
1446 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1447 slot, offset, qxl->guest_slots[slot].delta);
1448 return false;
1449 }
1450 offset -= qxl->guest_slots[slot].delta;
1451 if (offset > qxl->guest_slots[slot].size) {
1452 qxl_set_guest_bug(qxl,
1453 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1454 slot, offset, qxl->guest_slots[slot].size);
1455 return false;
1456 }
1457 size_available = memory_region_size(qxl->guest_slots[slot].mr);
1458 if (qxl->guest_slots[slot].offset + offset >= size_available) {
1459 qxl_set_guest_bug(qxl,
1460 "slot %d offset %"PRIu64" > region size %"PRIu64"\n",
1461 slot, qxl->guest_slots[slot].offset + offset,
1462 size_available);
1463 return false;
1464 }
1465 size_available -= qxl->guest_slots[slot].offset + offset;
1466 if (size_requested > size_available) {
1467 qxl_set_guest_bug(qxl,
1468 "slot %d offset %"PRIu64" size %zu: "
1469 "overrun by %"PRIu64" bytes\n",
1470 slot, offset, size_requested,
1471 size_requested - size_available);
1472 return false;
1473 }
1474
1475 *s = slot;
1476 *o = offset;
1477 return true;
1478 }
1479
1480 /* can be also called from spice server thread context */
qxl_phys2virt(PCIQXLDevice * qxl,QXLPHYSICAL pqxl,int group_id,size_t size)1481 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id,
1482 size_t size)
1483 {
1484 uint64_t offset;
1485 uint32_t slot;
1486 void *ptr;
1487
1488 switch (group_id) {
1489 case MEMSLOT_GROUP_HOST:
1490 offset = le64_to_cpu(pqxl) & 0xffffffffffff;
1491 return (void *)(intptr_t)offset;
1492 case MEMSLOT_GROUP_GUEST:
1493 if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset, size)) {
1494 return NULL;
1495 }
1496 ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
1497 ptr += qxl->guest_slots[slot].offset;
1498 ptr += offset;
1499 return ptr;
1500 }
1501 return NULL;
1502 }
1503
qxl_create_guest_primary_complete(PCIQXLDevice * qxl)1504 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1505 {
1506 /* for local rendering */
1507 qxl_render_resize(qxl);
1508 }
1509
qxl_create_guest_primary(PCIQXLDevice * qxl,int loadvm,qxl_async_io async)1510 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1511 qxl_async_io async)
1512 {
1513 QXLDevSurfaceCreate surface;
1514 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1515 uint32_t requested_height = le32_to_cpu(sc->height);
1516 int requested_stride = le32_to_cpu(sc->stride);
1517
1518 if (requested_stride == INT32_MIN ||
1519 abs(requested_stride) * (uint64_t)requested_height
1520 > qxl->vgamem_size) {
1521 qxl_set_guest_bug(qxl, "%s: requested primary larger than framebuffer"
1522 " stride %d x height %" PRIu32 " > %" PRIu32,
1523 __func__, requested_stride, requested_height,
1524 qxl->vgamem_size);
1525 return;
1526 }
1527
1528 if (qxl->mode == QXL_MODE_NATIVE) {
1529 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1530 __func__);
1531 }
1532 qxl_exit_vga_mode(qxl);
1533
1534 surface.format = le32_to_cpu(sc->format);
1535 surface.height = le32_to_cpu(sc->height);
1536 surface.mem = le64_to_cpu(sc->mem);
1537 surface.position = le32_to_cpu(sc->position);
1538 surface.stride = le32_to_cpu(sc->stride);
1539 surface.width = le32_to_cpu(sc->width);
1540 surface.type = le32_to_cpu(sc->type);
1541 surface.flags = le32_to_cpu(sc->flags);
1542 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1543 sc->format, sc->position);
1544 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1545 sc->flags);
1546
1547 if ((surface.stride & 0x3) != 0) {
1548 qxl_set_guest_bug(qxl, "primary surface stride = %d %% 4 != 0",
1549 surface.stride);
1550 return;
1551 }
1552
1553 surface.mouse_mode = true;
1554 surface.group_id = MEMSLOT_GROUP_GUEST;
1555 if (loadvm) {
1556 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1557 }
1558
1559 qxl->mode = QXL_MODE_NATIVE;
1560 qxl->cmdflags = 0;
1561 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1562
1563 if (async == QXL_SYNC) {
1564 qxl_create_guest_primary_complete(qxl);
1565 }
1566 }
1567
1568 /* return 1 if surface destroy was initiated (in QXL_ASYNC case) or
1569 * done (in QXL_SYNC case), 0 otherwise. */
qxl_destroy_primary(PCIQXLDevice * d,qxl_async_io async)1570 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1571 {
1572 if (d->mode == QXL_MODE_UNDEFINED) {
1573 return 0;
1574 }
1575 trace_qxl_destroy_primary(d->id);
1576 d->mode = QXL_MODE_UNDEFINED;
1577 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1578 qxl_spice_reset_cursor(d);
1579 return 1;
1580 }
1581
qxl_set_mode(PCIQXLDevice * d,unsigned int modenr,int loadvm)1582 static void qxl_set_mode(PCIQXLDevice *d, unsigned int modenr, int loadvm)
1583 {
1584 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1585 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1586 QXLMode *mode = d->modes->modes + modenr;
1587 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1588 QXLMemSlot slot = {
1589 .mem_start = start,
1590 .mem_end = end
1591 };
1592
1593 if (modenr >= d->modes->n_modes) {
1594 qxl_set_guest_bug(d, "mode number out of range");
1595 return;
1596 }
1597
1598 QXLSurfaceCreate surface = {
1599 .width = mode->x_res,
1600 .height = mode->y_res,
1601 .stride = -mode->x_res * 4,
1602 .format = SPICE_SURFACE_FMT_32_xRGB,
1603 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1604 .mouse_mode = true,
1605 .mem = devmem + d->shadow_rom.draw_area_offset,
1606 };
1607
1608 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1609 devmem);
1610 if (!loadvm) {
1611 qxl_hard_reset(d, 0);
1612 }
1613
1614 d->guest_slots[0].slot = slot;
1615 if (qxl_add_memslot(d, 0, devmem, QXL_SYNC) != 0) {
1616 qxl_set_guest_bug(d, "device isn't initialized yet");
1617 return;
1618 }
1619
1620 d->guest_primary.surface = surface;
1621 qxl_create_guest_primary(d, 0, QXL_SYNC);
1622
1623 d->mode = QXL_MODE_COMPAT;
1624 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1625 if (mode->bits == 16) {
1626 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1627 }
1628 d->shadow_rom.mode = cpu_to_le32(modenr);
1629 d->rom->mode = cpu_to_le32(modenr);
1630 qxl_rom_set_dirty(d);
1631 }
1632
ioport_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)1633 static void ioport_write(void *opaque, hwaddr addr,
1634 uint64_t val, unsigned size)
1635 {
1636 PCIQXLDevice *d = opaque;
1637 uint32_t io_port = addr;
1638 qxl_async_io async = QXL_SYNC;
1639 uint32_t orig_io_port;
1640
1641 if (d->guest_bug && io_port != QXL_IO_RESET) {
1642 return;
1643 }
1644
1645 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1646 io_port > QXL_IO_FLUSH_RELEASE) {
1647 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1648 io_port, d->revision);
1649 return;
1650 }
1651
1652 switch (io_port) {
1653 case QXL_IO_RESET:
1654 case QXL_IO_SET_MODE:
1655 case QXL_IO_MEMSLOT_ADD:
1656 case QXL_IO_MEMSLOT_DEL:
1657 case QXL_IO_CREATE_PRIMARY:
1658 case QXL_IO_UPDATE_IRQ:
1659 case QXL_IO_LOG:
1660 case QXL_IO_MEMSLOT_ADD_ASYNC:
1661 case QXL_IO_CREATE_PRIMARY_ASYNC:
1662 break;
1663 default:
1664 if (d->mode != QXL_MODE_VGA) {
1665 break;
1666 }
1667 trace_qxl_io_unexpected_vga_mode(d->id,
1668 addr, val, io_port_to_string(io_port));
1669 /* be nice to buggy guest drivers */
1670 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1671 io_port < QXL_IO_RANGE_SIZE) {
1672 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1673 }
1674 return;
1675 }
1676
1677 /* we change the io_port to avoid ifdeffery in the main switch */
1678 orig_io_port = io_port;
1679 switch (io_port) {
1680 case QXL_IO_UPDATE_AREA_ASYNC:
1681 io_port = QXL_IO_UPDATE_AREA;
1682 goto async_common;
1683 case QXL_IO_MEMSLOT_ADD_ASYNC:
1684 io_port = QXL_IO_MEMSLOT_ADD;
1685 goto async_common;
1686 case QXL_IO_CREATE_PRIMARY_ASYNC:
1687 io_port = QXL_IO_CREATE_PRIMARY;
1688 goto async_common;
1689 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1690 io_port = QXL_IO_DESTROY_PRIMARY;
1691 goto async_common;
1692 case QXL_IO_DESTROY_SURFACE_ASYNC:
1693 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1694 goto async_common;
1695 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1696 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1697 goto async_common;
1698 case QXL_IO_FLUSH_SURFACES_ASYNC:
1699 case QXL_IO_MONITORS_CONFIG_ASYNC:
1700 async_common:
1701 async = QXL_ASYNC;
1702 WITH_QEMU_LOCK_GUARD(&d->async_lock) {
1703 if (d->current_async != QXL_UNDEFINED_IO) {
1704 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1705 io_port, d->current_async);
1706 return;
1707 }
1708 d->current_async = orig_io_port;
1709 }
1710 break;
1711 default:
1712 break;
1713 }
1714 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode),
1715 addr, io_port_to_string(addr),
1716 val, size, async);
1717
1718 switch (io_port) {
1719 case QXL_IO_UPDATE_AREA:
1720 {
1721 QXLCookie *cookie = NULL;
1722 QXLRect update = d->ram->update_area;
1723
1724 if (d->ram->update_surface > d->ssd.num_surfaces) {
1725 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1726 d->ram->update_surface);
1727 break;
1728 }
1729 if (update.left >= update.right || update.top >= update.bottom ||
1730 update.left < 0 || update.top < 0) {
1731 qxl_set_guest_bug(d,
1732 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1733 update.left, update.top, update.right, update.bottom);
1734 if (update.left == update.right || update.top == update.bottom) {
1735 /* old drivers may provide empty area, keep going */
1736 qxl_clear_guest_bug(d);
1737 goto cancel_async;
1738 }
1739 break;
1740 }
1741 if (async == QXL_ASYNC) {
1742 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1743 QXL_IO_UPDATE_AREA_ASYNC);
1744 cookie->u.area = update;
1745 }
1746 qxl_spice_update_area(d, d->ram->update_surface,
1747 cookie ? &cookie->u.area : &update,
1748 NULL, 0, 0, async, cookie);
1749 break;
1750 }
1751 case QXL_IO_NOTIFY_CMD:
1752 qemu_spice_wakeup(&d->ssd);
1753 break;
1754 case QXL_IO_NOTIFY_CURSOR:
1755 qemu_spice_wakeup(&d->ssd);
1756 break;
1757 case QXL_IO_UPDATE_IRQ:
1758 qxl_update_irq(d);
1759 break;
1760 case QXL_IO_NOTIFY_OOM:
1761 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1762 break;
1763 }
1764 d->oom_running = 1;
1765 qxl_spice_oom(d);
1766 d->oom_running = 0;
1767 break;
1768 case QXL_IO_SET_MODE:
1769 qxl_set_mode(d, val, 0);
1770 break;
1771 case QXL_IO_LOG:
1772 #ifdef CONFIG_MODULES
1773 /*
1774 * FIXME
1775 * trace_event_get_state_backends() does not work for modules,
1776 * it leads to "undefined symbol: qemu_qxl_io_log_semaphore"
1777 */
1778 if (true) {
1779 #else
1780 if (trace_event_get_state_backends(TRACE_QXL_IO_LOG) || d->guestdebug) {
1781 #endif
1782 /* We cannot trust the guest to NUL terminate d->ram->log_buf */
1783 char *log_buf = g_strndup((const char *)d->ram->log_buf,
1784 sizeof(d->ram->log_buf));
1785 trace_qxl_io_log(d->id, log_buf);
1786 if (d->guestdebug) {
1787 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1788 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), log_buf);
1789 }
1790 g_free(log_buf);
1791 }
1792 break;
1793 case QXL_IO_RESET:
1794 qxl_hard_reset(d, 0);
1795 break;
1796 case QXL_IO_MEMSLOT_ADD:
1797 if (val >= NUM_MEMSLOTS) {
1798 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1799 break;
1800 }
1801 if (d->guest_slots[val].active) {
1802 qxl_set_guest_bug(d,
1803 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1804 break;
1805 }
1806 d->guest_slots[val].slot = d->ram->mem_slot;
1807 qxl_add_memslot(d, val, 0, async);
1808 break;
1809 case QXL_IO_MEMSLOT_DEL:
1810 if (val >= NUM_MEMSLOTS) {
1811 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1812 break;
1813 }
1814 qxl_del_memslot(d, val);
1815 break;
1816 case QXL_IO_CREATE_PRIMARY:
1817 if (val != 0) {
1818 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1819 async);
1820 goto cancel_async;
1821 }
1822 d->guest_primary.surface = d->ram->create_surface;
1823 qxl_create_guest_primary(d, 0, async);
1824 break;
1825 case QXL_IO_DESTROY_PRIMARY:
1826 if (val != 0) {
1827 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1828 async);
1829 goto cancel_async;
1830 }
1831 if (!qxl_destroy_primary(d, async)) {
1832 trace_qxl_io_destroy_primary_ignored(d->id,
1833 qxl_mode_to_string(d->mode));
1834 goto cancel_async;
1835 }
1836 break;
1837 case QXL_IO_DESTROY_SURFACE_WAIT:
1838 if (val >= d->ssd.num_surfaces) {
1839 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1840 "%" PRIu64 " >= NUM_SURFACES", async, val);
1841 goto cancel_async;
1842 }
1843 qxl_spice_destroy_surface_wait(d, val, async);
1844 break;
1845 case QXL_IO_FLUSH_RELEASE: {
1846 QXLReleaseRing *ring = &d->ram->release_ring;
1847 if (ring->prod - ring->cons + 1 == ring->num_items) {
1848 fprintf(stderr,
1849 "ERROR: no flush, full release ring [p%d,%dc]\n",
1850 ring->prod, ring->cons);
1851 }
1852 qxl_push_free_res(d, 1 /* flush */);
1853 break;
1854 }
1855 case QXL_IO_FLUSH_SURFACES_ASYNC:
1856 qxl_spice_flush_surfaces_async(d);
1857 break;
1858 case QXL_IO_DESTROY_ALL_SURFACES:
1859 d->mode = QXL_MODE_UNDEFINED;
1860 qxl_spice_destroy_surfaces(d, async);
1861 break;
1862 case QXL_IO_MONITORS_CONFIG_ASYNC:
1863 qxl_spice_monitors_config_async(d, 0);
1864 break;
1865 default:
1866 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1867 }
1868 return;
1869 cancel_async:
1870 if (async) {
1871 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1872 qemu_mutex_lock(&d->async_lock);
1873 d->current_async = QXL_UNDEFINED_IO;
1874 qemu_mutex_unlock(&d->async_lock);
1875 }
1876 }
1877
1878 static uint64_t ioport_read(void *opaque, hwaddr addr,
1879 unsigned size)
1880 {
1881 PCIQXLDevice *qxl = opaque;
1882
1883 trace_qxl_io_read_unexpected(qxl->id);
1884 return 0xff;
1885 }
1886
1887 static const MemoryRegionOps qxl_io_ops = {
1888 .read = ioport_read,
1889 .write = ioport_write,
1890 .valid = {
1891 .min_access_size = 1,
1892 .max_access_size = 1,
1893 },
1894 };
1895
1896 static void qxl_update_irq_bh(void *opaque)
1897 {
1898 PCIQXLDevice *d = opaque;
1899 qxl_update_irq(d);
1900 }
1901
1902 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1903 {
1904 uint32_t old_pending;
1905 uint32_t le_events = cpu_to_le32(events);
1906
1907 trace_qxl_send_events(d->id, events);
1908 if (!qemu_spice_display_is_running(&d->ssd)) {
1909 /* spice-server tracks guest running state and should not do this */
1910 fprintf(stderr, "%s: spice-server bug: guest stopped, ignoring\n",
1911 __func__);
1912 trace_qxl_send_events_vm_stopped(d->id, events);
1913 return;
1914 }
1915 /*
1916 * Older versions of Spice forgot to define the QXLRam struct
1917 * with the '__aligned__(4)' attribute. clang 7 and newer will
1918 * thus warn that qatomic_fetch_or(&d->ram->int_pending, ...)
1919 * might be a misaligned atomic access, and will generate an
1920 * out-of-line call for it, which results in a link error since
1921 * we don't currently link against libatomic.
1922 *
1923 * In fact we set up d->ram in init_qxl_ram() so it always starts
1924 * at a 4K boundary, so we know that &d->ram->int_pending is
1925 * naturally aligned for a uint32_t. Newer Spice versions
1926 * (with Spice commit beda5ec7a6848be20c0cac2a9a8ef2a41e8069c1)
1927 * will fix the bug directly. To deal with older versions,
1928 * we tell the compiler to assume the address really is aligned.
1929 * Any compiler which cares about the misalignment will have
1930 * __builtin_assume_aligned.
1931 */
1932 #ifdef HAS_ASSUME_ALIGNED
1933 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)__builtin_assume_aligned(P, 4))
1934 #else
1935 #define ALIGNED_UINT32_PTR(P) ((uint32_t *)P)
1936 #endif
1937
1938 old_pending = qatomic_fetch_or(ALIGNED_UINT32_PTR(&d->ram->int_pending),
1939 le_events);
1940 if ((old_pending & le_events) == le_events) {
1941 return;
1942 }
1943 qemu_bh_schedule(d->update_irq);
1944 }
1945
1946 /* graphics console */
1947
1948 static void qxl_hw_update(void *opaque)
1949 {
1950 PCIQXLDevice *qxl = opaque;
1951
1952 qxl_render_update(qxl);
1953 }
1954
1955 static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
1956 uint32_t height, int32_t stride)
1957 {
1958 uint64_t offset, size;
1959 uint32_t slot;
1960 bool rc;
1961
1962 size = (uint64_t)height * abs(stride);
1963 rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset, size);
1964 assert(rc == true);
1965 trace_qxl_surfaces_dirty(qxl->id, offset, size);
1966 qxl_set_dirty(qxl->guest_slots[slot].mr,
1967 qxl->guest_slots[slot].offset + offset,
1968 qxl->guest_slots[slot].offset + offset + size);
1969 }
1970
1971 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1972 {
1973 int i;
1974
1975 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1976 return;
1977 }
1978
1979 /* dirty the primary surface */
1980 qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
1981 qxl->guest_primary.surface.height,
1982 qxl->guest_primary.surface.stride);
1983
1984 /* dirty the off-screen surfaces */
1985 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1986 QXLSurfaceCmd *cmd;
1987
1988 if (qxl->guest_surfaces.cmds[i] == 0) {
1989 continue;
1990 }
1991
1992 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1993 MEMSLOT_GROUP_GUEST, sizeof(QXLSurfaceCmd));
1994 assert(cmd);
1995 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1996 qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
1997 cmd->u.surface_create.height,
1998 cmd->u.surface_create.stride);
1999 }
2000 }
2001
2002 static void qxl_vm_change_state_handler(void *opaque, bool running,
2003 RunState state)
2004 {
2005 PCIQXLDevice *qxl = opaque;
2006
2007 if (running) {
2008 /*
2009 * if qxl_send_events was called from spice server context before
2010 * migration ended, qxl_update_irq for these events might not have been
2011 * called
2012 */
2013 qxl_update_irq(qxl);
2014 } else {
2015 /* make sure surfaces are saved before migration */
2016 qxl_dirty_surfaces(qxl);
2017 }
2018 }
2019
2020 /* display change listener */
2021
2022 static void display_update(DisplayChangeListener *dcl,
2023 int x, int y, int w, int h)
2024 {
2025 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2026
2027 if (qxl->mode == QXL_MODE_VGA) {
2028 qemu_spice_display_update(&qxl->ssd, x, y, w, h);
2029 }
2030 }
2031
2032 static void display_switch(DisplayChangeListener *dcl,
2033 struct DisplaySurface *surface)
2034 {
2035 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2036
2037 qxl->ssd.ds = surface;
2038 if (qxl->mode == QXL_MODE_VGA) {
2039 qemu_spice_display_switch(&qxl->ssd, surface);
2040 }
2041 }
2042
2043 static void display_refresh(DisplayChangeListener *dcl)
2044 {
2045 PCIQXLDevice *qxl = container_of(dcl, PCIQXLDevice, ssd.dcl);
2046
2047 if (qxl->mode == QXL_MODE_VGA) {
2048 qemu_spice_display_refresh(&qxl->ssd);
2049 }
2050 }
2051
2052 static DisplayChangeListenerOps display_listener_ops = {
2053 .dpy_name = "spice/qxl",
2054 .dpy_gfx_update = display_update,
2055 .dpy_gfx_switch = display_switch,
2056 .dpy_refresh = display_refresh,
2057 };
2058
2059 static void qxl_init_ramsize(PCIQXLDevice *qxl)
2060 {
2061 /* vga mode framebuffer / primary surface (bar 0, first part) */
2062 if (qxl->vgamem_size_mb < 8) {
2063 qxl->vgamem_size_mb = 8;
2064 }
2065 /* XXX: we round vgamem_size_mb up to a nearest power of two and it must be
2066 * less than vga_common_init()'s maximum on qxl->vga.vram_size (512 now).
2067 */
2068 if (qxl->vgamem_size_mb > 256) {
2069 qxl->vgamem_size_mb = 256;
2070 }
2071 qxl->vgamem_size = qxl->vgamem_size_mb * MiB;
2072
2073 /* vga ram (bar 0, total) */
2074 if (qxl->ram_size_mb != -1) {
2075 qxl->vga.vram_size = qxl->ram_size_mb * MiB;
2076 }
2077 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
2078 qxl->vga.vram_size = qxl->vgamem_size * 2;
2079 }
2080
2081 /* vram32 (surfaces, 32bit, bar 1) */
2082 if (qxl->vram32_size_mb != -1) {
2083 qxl->vram32_size = qxl->vram32_size_mb * MiB;
2084 }
2085 if (qxl->vram32_size < 4096) {
2086 qxl->vram32_size = 4096;
2087 }
2088
2089 /* vram (surfaces, 64bit, bar 4+5) */
2090 if (qxl->vram_size_mb != -1) {
2091 qxl->vram_size = (uint64_t)qxl->vram_size_mb * MiB;
2092 }
2093 if (qxl->vram_size < qxl->vram32_size) {
2094 qxl->vram_size = qxl->vram32_size;
2095 }
2096
2097 if (qxl->revision == 1) {
2098 qxl->vram32_size = 4096;
2099 qxl->vram_size = 4096;
2100 }
2101 qxl->vgamem_size = pow2ceil(qxl->vgamem_size);
2102 qxl->vga.vram_size = pow2ceil(qxl->vga.vram_size);
2103 qxl->vram32_size = pow2ceil(qxl->vram32_size);
2104 qxl->vram_size = pow2ceil(qxl->vram_size);
2105 }
2106
2107 static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
2108 {
2109 uint8_t* config = qxl->pci.config;
2110 uint32_t pci_device_rev;
2111 uint32_t io_size;
2112
2113 qemu_spice_display_init_common(&qxl->ssd);
2114 qxl->mode = QXL_MODE_UNDEFINED;
2115 qxl->num_memslots = NUM_MEMSLOTS;
2116 qemu_mutex_init(&qxl->track_lock);
2117 qemu_mutex_init(&qxl->async_lock);
2118 qxl->current_async = QXL_UNDEFINED_IO;
2119 qxl->guest_bug = 0;
2120
2121 switch (qxl->revision) {
2122 case 1: /* spice 0.4 -- qxl-1 */
2123 pci_device_rev = QXL_REVISION_STABLE_V04;
2124 io_size = 8;
2125 break;
2126 case 2: /* spice 0.6 -- qxl-2 */
2127 pci_device_rev = QXL_REVISION_STABLE_V06;
2128 io_size = 16;
2129 break;
2130 case 3: /* qxl-3 */
2131 pci_device_rev = QXL_REVISION_STABLE_V10;
2132 io_size = 32; /* PCI region size must be pow2 */
2133 break;
2134 case 4: /* qxl-4 */
2135 pci_device_rev = QXL_REVISION_STABLE_V12;
2136 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2137 break;
2138 case 5: /* qxl-5 */
2139 pci_device_rev = QXL_REVISION_STABLE_V12 + 1;
2140 io_size = pow2ceil(QXL_IO_RANGE_SIZE);
2141 break;
2142 default:
2143 error_setg(errp, "Invalid revision %d for qxl device (max %d)",
2144 qxl->revision, QXL_DEFAULT_REVISION);
2145 return;
2146 }
2147
2148 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
2149 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
2150
2151 qxl->rom_size = qxl_rom_size();
2152 memory_region_init_rom(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom",
2153 qxl->rom_size, &error_fatal);
2154 init_qxl_rom(qxl);
2155 init_qxl_ram(qxl);
2156
2157 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
2158 memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram",
2159 qxl->vram_size, &error_fatal);
2160 memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32",
2161 &qxl->vram_bar, 0, qxl->vram32_size);
2162
2163 memory_region_init_io(&qxl->io_bar, OBJECT(qxl), &qxl_io_ops, qxl,
2164 "qxl-ioports", io_size);
2165 if (qxl->have_vga) {
2166 vga_dirty_log_start(&qxl->vga);
2167 }
2168 memory_region_set_flush_coalesced(&qxl->io_bar);
2169
2170
2171 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2172 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2173
2174 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2175 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2176
2177 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2178 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2179
2180 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2181 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2182
2183 if (qxl->vram32_size < qxl->vram_size) {
2184 /*
2185 * Make the 64bit vram bar show up only in case it is
2186 * configured to be larger than the 32bit vram bar.
2187 */
2188 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2189 PCI_BASE_ADDRESS_SPACE_MEMORY |
2190 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2191 PCI_BASE_ADDRESS_MEM_PREFETCH,
2192 &qxl->vram_bar);
2193 }
2194
2195 /* print pci bar details */
2196 dprint(qxl, 1, "ram/%s: %" PRId64 " MB [region 0]\n",
2197 qxl->have_vga ? "pri" : "sec", qxl->vga.vram_size / MiB);
2198 dprint(qxl, 1, "vram/32: %" PRIx64 " MB [region 1]\n",
2199 qxl->vram32_size / MiB);
2200 dprint(qxl, 1, "vram/64: %" PRIx64 " MB %s\n",
2201 qxl->vram_size / MiB,
2202 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2203
2204 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2205 if (qemu_spice_add_display_interface(&qxl->ssd.qxl, qxl->vga.con) != 0) {
2206 error_setg(errp, "qxl interface %d.%d not supported by spice-server",
2207 SPICE_INTERFACE_QXL_MAJOR, SPICE_INTERFACE_QXL_MINOR);
2208 return;
2209 }
2210
2211 #if SPICE_SERVER_VERSION >= 0x000e02 /* release 0.14.2 */
2212 Error *err = NULL;
2213 char device_address[256] = "";
2214 if (qemu_console_fill_device_address(qxl->vga.con,
2215 device_address, sizeof(device_address),
2216 &err)) {
2217 spice_qxl_set_device_info(&qxl->ssd.qxl,
2218 device_address,
2219 0,
2220 qxl->max_outputs);
2221 } else {
2222 error_report_err(err);
2223 }
2224 #endif
2225
2226 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2227
2228 qxl->update_irq = qemu_bh_new_guarded(qxl_update_irq_bh, qxl,
2229 &DEVICE(qxl)->mem_reentrancy_guard);
2230 qxl_reset_state(qxl);
2231
2232 qxl->update_area_bh = qemu_bh_new_guarded(qxl_render_update_area_bh, qxl,
2233 &DEVICE(qxl)->mem_reentrancy_guard);
2234 qxl->ssd.cursor_bh = qemu_bh_new_guarded(qemu_spice_cursor_refresh_bh, &qxl->ssd,
2235 &DEVICE(qxl)->mem_reentrancy_guard);
2236 }
2237
2238 static void qxl_realize_primary(PCIDevice *dev, Error **errp)
2239 {
2240 PCIQXLDevice *qxl = PCI_QXL(dev);
2241 VGACommonState *vga = &qxl->vga;
2242 Error *local_err = NULL;
2243
2244 qxl_init_ramsize(qxl);
2245 vga->vbe_size = qxl->vgamem_size;
2246 vga->vram_size_mb = qxl->vga.vram_size / MiB;
2247 vga_common_init(vga, OBJECT(dev), &local_err);
2248 if (local_err) {
2249 error_propagate(errp, local_err);
2250 return;
2251 }
2252 vga_init(vga, OBJECT(dev),
2253 pci_address_space(dev), pci_address_space_io(dev), false);
2254 portio_list_init(&qxl->vga_port_list, OBJECT(dev), qxl_vga_portio_list,
2255 vga, "vga");
2256 portio_list_set_flush_coalesced(&qxl->vga_port_list);
2257 portio_list_add(&qxl->vga_port_list, pci_address_space_io(dev), 0x3b0);
2258 qxl->have_vga = true;
2259
2260 vga->con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2261 qxl->id = qemu_console_get_index(vga->con); /* == channel_id */
2262 if (qxl->id != 0) {
2263 error_setg(errp, "primary qxl-vga device must be console 0 "
2264 "(first display device on the command line)");
2265 return;
2266 }
2267
2268 qxl_realize_common(qxl, &local_err);
2269 if (local_err) {
2270 error_propagate(errp, local_err);
2271 return;
2272 }
2273
2274 qxl->ssd.dcl.ops = &display_listener_ops;
2275 qxl->ssd.dcl.con = vga->con;
2276 register_displaychangelistener(&qxl->ssd.dcl);
2277 }
2278
2279 static void qxl_realize_secondary(PCIDevice *dev, Error **errp)
2280 {
2281 PCIQXLDevice *qxl = PCI_QXL(dev);
2282
2283 qxl_init_ramsize(qxl);
2284 memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram",
2285 qxl->vga.vram_size, &error_fatal);
2286 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2287 qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl);
2288 qxl->ssd.dcl.con = qxl->vga.con;
2289 qxl->id = qemu_console_get_index(qxl->vga.con); /* == channel_id */
2290
2291 qxl_realize_common(qxl, errp);
2292 }
2293
2294 static int qxl_pre_save(void *opaque)
2295 {
2296 PCIQXLDevice* d = opaque;
2297 uint8_t *ram_start = d->vga.vram_ptr;
2298
2299 trace_qxl_pre_save(d->id);
2300 if (d->last_release == NULL) {
2301 d->last_release_offset = 0;
2302 } else {
2303 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2304 }
2305 if (d->last_release_offset >= d->vga.vram_size) {
2306 return 1;
2307 }
2308
2309 return 0;
2310 }
2311
2312 static int qxl_pre_load(void *opaque)
2313 {
2314 PCIQXLDevice* d = opaque;
2315
2316 trace_qxl_pre_load(d->id);
2317 qxl_hard_reset(d, 1);
2318 qxl_exit_vga_mode(d);
2319 return 0;
2320 }
2321
2322 static void qxl_create_memslots(PCIQXLDevice *d)
2323 {
2324 int i;
2325
2326 for (i = 0; i < NUM_MEMSLOTS; i++) {
2327 if (!d->guest_slots[i].active) {
2328 continue;
2329 }
2330 qxl_add_memslot(d, i, 0, QXL_SYNC);
2331 }
2332 }
2333
2334 static int qxl_post_load(void *opaque, int version)
2335 {
2336 PCIQXLDevice* d = opaque;
2337 uint8_t *ram_start = d->vga.vram_ptr;
2338 QXLCommandExt *cmds;
2339 int in, out, newmode;
2340
2341 assert(d->last_release_offset < d->vga.vram_size);
2342 if (d->last_release_offset == 0) {
2343 d->last_release = NULL;
2344 } else {
2345 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2346 }
2347
2348 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2349
2350 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2351 newmode = d->mode;
2352 d->mode = QXL_MODE_UNDEFINED;
2353
2354 switch (newmode) {
2355 case QXL_MODE_UNDEFINED:
2356 qxl_create_memslots(d);
2357 break;
2358 case QXL_MODE_VGA:
2359 qxl_create_memslots(d);
2360 qxl_enter_vga_mode(d);
2361 break;
2362 case QXL_MODE_NATIVE:
2363 qxl_create_memslots(d);
2364 qxl_create_guest_primary(d, 1, QXL_SYNC);
2365
2366 /* replay surface-create and cursor-set commands */
2367 cmds = g_new0(QXLCommandExt, d->ssd.num_surfaces + 1);
2368 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2369 if (d->guest_surfaces.cmds[in] == 0) {
2370 continue;
2371 }
2372 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2373 cmds[out].cmd.type = QXL_CMD_SURFACE;
2374 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2375 out++;
2376 }
2377 if (d->guest_cursor) {
2378 cmds[out].cmd.data = d->guest_cursor;
2379 cmds[out].cmd.type = QXL_CMD_CURSOR;
2380 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2381 out++;
2382 }
2383 qxl_spice_loadvm_commands(d, cmds, out);
2384 g_free(cmds);
2385 if (d->guest_monitors_config) {
2386 qxl_spice_monitors_config_async(d, 1);
2387 }
2388 break;
2389 case QXL_MODE_COMPAT:
2390 /* note: no need to call qxl_create_memslots, qxl_set_mode
2391 * creates the mem slot. */
2392 qxl_set_mode(d, d->shadow_rom.mode, 1);
2393 break;
2394 }
2395 return 0;
2396 }
2397
2398 #define QXL_SAVE_VERSION 21
2399
2400 static bool qxl_monitors_config_needed(void *opaque)
2401 {
2402 PCIQXLDevice *qxl = opaque;
2403
2404 return qxl->guest_monitors_config != 0;
2405 }
2406
2407
2408 static const VMStateDescription qxl_memslot = {
2409 .name = "qxl-memslot",
2410 .version_id = QXL_SAVE_VERSION,
2411 .minimum_version_id = QXL_SAVE_VERSION,
2412 .fields = (const VMStateField[]) {
2413 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2414 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2415 VMSTATE_UINT32(active, struct guest_slots),
2416 VMSTATE_END_OF_LIST()
2417 }
2418 };
2419
2420 static const VMStateDescription qxl_surface = {
2421 .name = "qxl-surface",
2422 .version_id = QXL_SAVE_VERSION,
2423 .minimum_version_id = QXL_SAVE_VERSION,
2424 .fields = (const VMStateField[]) {
2425 VMSTATE_UINT32(width, QXLSurfaceCreate),
2426 VMSTATE_UINT32(height, QXLSurfaceCreate),
2427 VMSTATE_INT32(stride, QXLSurfaceCreate),
2428 VMSTATE_UINT32(format, QXLSurfaceCreate),
2429 VMSTATE_UINT32(position, QXLSurfaceCreate),
2430 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2431 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2432 VMSTATE_UINT32(type, QXLSurfaceCreate),
2433 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2434 VMSTATE_END_OF_LIST()
2435 }
2436 };
2437
2438 static const VMStateDescription qxl_vmstate_monitors_config = {
2439 .name = "qxl/monitors-config",
2440 .version_id = 1,
2441 .minimum_version_id = 1,
2442 .needed = qxl_monitors_config_needed,
2443 .fields = (const VMStateField[]) {
2444 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2445 VMSTATE_END_OF_LIST()
2446 },
2447 };
2448
2449 static const VMStateDescription qxl_vmstate = {
2450 .name = "qxl",
2451 .version_id = QXL_SAVE_VERSION,
2452 .minimum_version_id = QXL_SAVE_VERSION,
2453 .pre_save = qxl_pre_save,
2454 .pre_load = qxl_pre_load,
2455 .post_load = qxl_post_load,
2456 .fields = (const VMStateField[]) {
2457 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2458 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2459 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2460 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2461 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2462 VMSTATE_UINT32(mode, PCIQXLDevice),
2463 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2464 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice, NULL),
2465 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2466 qxl_memslot, struct guest_slots),
2467 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2468 qxl_surface, QXLSurfaceCreate),
2469 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice, NULL),
2470 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2471 ssd.num_surfaces, 0,
2472 vmstate_info_uint64, uint64_t),
2473 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2474 VMSTATE_END_OF_LIST()
2475 },
2476 .subsections = (const VMStateDescription * const []) {
2477 &qxl_vmstate_monitors_config,
2478 NULL
2479 }
2480 };
2481
2482 static const Property qxl_properties[] = {
2483 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * MiB),
2484 DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * MiB),
2485 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2486 QXL_DEFAULT_REVISION),
2487 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2488 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2489 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2490 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2491 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2492 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2493 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2494 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2495 DEFINE_PROP_UINT16("max_outputs", PCIQXLDevice, max_outputs, 0),
2496 DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0),
2497 DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0),
2498 DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false),
2499 };
2500
2501 static void qxl_pci_class_init(ObjectClass *klass, const void *data)
2502 {
2503 DeviceClass *dc = DEVICE_CLASS(klass);
2504 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2505
2506 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2507 k->device_id = QXL_DEVICE_ID_STABLE;
2508 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
2509 device_class_set_legacy_reset(dc, qxl_reset_handler);
2510 dc->vmsd = &qxl_vmstate;
2511 device_class_set_props(dc, qxl_properties);
2512 }
2513
2514 static const TypeInfo qxl_pci_type_info = {
2515 .name = TYPE_PCI_QXL,
2516 .parent = TYPE_PCI_DEVICE,
2517 .instance_size = sizeof(PCIQXLDevice),
2518 .abstract = true,
2519 .class_init = qxl_pci_class_init,
2520 .interfaces = (const InterfaceInfo[]) {
2521 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2522 { },
2523 },
2524 };
2525
2526 static void qxl_primary_class_init(ObjectClass *klass, const void *data)
2527 {
2528 DeviceClass *dc = DEVICE_CLASS(klass);
2529 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2530
2531 k->realize = qxl_realize_primary;
2532 k->romfile = "vgabios-qxl.bin";
2533 k->class_id = PCI_CLASS_DISPLAY_VGA;
2534 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2535 dc->hotpluggable = false;
2536 }
2537
2538 static const TypeInfo qxl_primary_info = {
2539 .name = "qxl-vga",
2540 .parent = TYPE_PCI_QXL,
2541 .class_init = qxl_primary_class_init,
2542 };
2543 module_obj("qxl-vga");
2544 module_kconfig(QXL);
2545
2546 static void qxl_secondary_class_init(ObjectClass *klass, const void *data)
2547 {
2548 DeviceClass *dc = DEVICE_CLASS(klass);
2549 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2550
2551 k->realize = qxl_realize_secondary;
2552 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2553 dc->desc = "Spice QXL GPU (secondary)";
2554 }
2555
2556 static const TypeInfo qxl_secondary_info = {
2557 .name = "qxl",
2558 .parent = TYPE_PCI_QXL,
2559 .class_init = qxl_secondary_class_init,
2560 };
2561 module_obj("qxl");
2562
2563 static void qxl_register_types(void)
2564 {
2565 type_register_static(&qxl_pci_type_info);
2566 type_register_static(&qxl_primary_info);
2567 type_register_static(&qxl_secondary_info);
2568 }
2569
2570 type_init(qxl_register_types)
2571
2572 module_dep("ui-spice-core");
2573