1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7 #include <linux/component.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_platform.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/dma-mapping.h>
14
15 #include <drm/clients/drm_client_setup.h>
16 #include <drm/drm_atomic.h>
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_drv.h>
19 #include <drm/drm_fbdev_dma.h>
20 #include <drm/drm_fourcc.h>
21 #include <drm/drm_gem.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_ioctl.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_probe_helper.h>
26 #include <drm/drm_vblank.h>
27
28 #include "mtk_crtc.h"
29 #include "mtk_ddp_comp.h"
30 #include "mtk_disp_drv.h"
31 #include "mtk_drm_drv.h"
32 #include "mtk_gem.h"
33
34 #define DRIVER_NAME "mediatek"
35 #define DRIVER_DESC "Mediatek SoC DRM"
36 #define DRIVER_MAJOR 1
37 #define DRIVER_MINOR 0
38
39 static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
40 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
41 };
42
43 static struct drm_framebuffer *
mtk_drm_mode_fb_create(struct drm_device * dev,struct drm_file * file,const struct drm_format_info * info,const struct drm_mode_fb_cmd2 * cmd)44 mtk_drm_mode_fb_create(struct drm_device *dev,
45 struct drm_file *file,
46 const struct drm_format_info *info,
47 const struct drm_mode_fb_cmd2 *cmd)
48 {
49 if (info->num_planes != 1)
50 return ERR_PTR(-EINVAL);
51
52 return drm_gem_fb_create(dev, file, info, cmd);
53 }
54
55 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
56 .fb_create = mtk_drm_mode_fb_create,
57 .atomic_check = drm_atomic_helper_check,
58 .atomic_commit = drm_atomic_helper_commit,
59 };
60
61 static const unsigned int mt2701_mtk_ddp_main[] = {
62 DDP_COMPONENT_OVL0,
63 DDP_COMPONENT_RDMA0,
64 DDP_COMPONENT_COLOR0,
65 DDP_COMPONENT_BLS,
66 DDP_COMPONENT_DSI0,
67 };
68
69 static const unsigned int mt2701_mtk_ddp_ext[] = {
70 DDP_COMPONENT_RDMA1,
71 DDP_COMPONENT_DPI0,
72 };
73
74 static const unsigned int mt7623_mtk_ddp_main[] = {
75 DDP_COMPONENT_OVL0,
76 DDP_COMPONENT_RDMA0,
77 DDP_COMPONENT_COLOR0,
78 DDP_COMPONENT_BLS,
79 DDP_COMPONENT_DPI0,
80 };
81
82 static const unsigned int mt7623_mtk_ddp_ext[] = {
83 DDP_COMPONENT_RDMA1,
84 DDP_COMPONENT_DSI0,
85 };
86
87 static const unsigned int mt2712_mtk_ddp_main[] = {
88 DDP_COMPONENT_OVL0,
89 DDP_COMPONENT_COLOR0,
90 DDP_COMPONENT_AAL0,
91 DDP_COMPONENT_OD0,
92 DDP_COMPONENT_RDMA0,
93 DDP_COMPONENT_DPI0,
94 DDP_COMPONENT_PWM0,
95 };
96
97 static const unsigned int mt2712_mtk_ddp_ext[] = {
98 DDP_COMPONENT_OVL1,
99 DDP_COMPONENT_COLOR1,
100 DDP_COMPONENT_AAL1,
101 DDP_COMPONENT_OD1,
102 DDP_COMPONENT_RDMA1,
103 DDP_COMPONENT_DPI1,
104 DDP_COMPONENT_PWM1,
105 };
106
107 static const unsigned int mt2712_mtk_ddp_third[] = {
108 DDP_COMPONENT_RDMA2,
109 DDP_COMPONENT_DSI3,
110 DDP_COMPONENT_PWM2,
111 };
112
113 static unsigned int mt8167_mtk_ddp_main[] = {
114 DDP_COMPONENT_OVL0,
115 DDP_COMPONENT_COLOR0,
116 DDP_COMPONENT_CCORR,
117 DDP_COMPONENT_AAL0,
118 DDP_COMPONENT_GAMMA,
119 DDP_COMPONENT_DITHER0,
120 DDP_COMPONENT_RDMA0,
121 DDP_COMPONENT_DSI0,
122 };
123
124 static const unsigned int mt8173_mtk_ddp_main[] = {
125 DDP_COMPONENT_OVL0,
126 DDP_COMPONENT_COLOR0,
127 DDP_COMPONENT_AAL0,
128 DDP_COMPONENT_OD0,
129 DDP_COMPONENT_RDMA0,
130 DDP_COMPONENT_UFOE,
131 DDP_COMPONENT_DSI0,
132 DDP_COMPONENT_PWM0,
133 };
134
135 static const unsigned int mt8173_mtk_ddp_ext[] = {
136 DDP_COMPONENT_OVL1,
137 DDP_COMPONENT_COLOR1,
138 DDP_COMPONENT_GAMMA,
139 DDP_COMPONENT_RDMA1,
140 DDP_COMPONENT_DPI0,
141 };
142
143 static const unsigned int mt8183_mtk_ddp_main[] = {
144 DDP_COMPONENT_OVL0,
145 DDP_COMPONENT_OVL_2L0,
146 DDP_COMPONENT_RDMA0,
147 DDP_COMPONENT_COLOR0,
148 DDP_COMPONENT_CCORR,
149 DDP_COMPONENT_AAL0,
150 DDP_COMPONENT_GAMMA,
151 DDP_COMPONENT_DITHER0,
152 DDP_COMPONENT_DSI0,
153 };
154
155 static const unsigned int mt8183_mtk_ddp_ext[] = {
156 DDP_COMPONENT_OVL_2L1,
157 DDP_COMPONENT_RDMA1,
158 DDP_COMPONENT_DPI0,
159 };
160
161 static const unsigned int mt8186_mtk_ddp_main[] = {
162 DDP_COMPONENT_OVL0,
163 DDP_COMPONENT_RDMA0,
164 DDP_COMPONENT_COLOR0,
165 DDP_COMPONENT_CCORR,
166 DDP_COMPONENT_AAL0,
167 DDP_COMPONENT_GAMMA,
168 DDP_COMPONENT_POSTMASK0,
169 DDP_COMPONENT_DITHER0,
170 DDP_COMPONENT_DSI0,
171 };
172
173 static const unsigned int mt8186_mtk_ddp_ext[] = {
174 DDP_COMPONENT_OVL_2L0,
175 DDP_COMPONENT_RDMA1,
176 DDP_COMPONENT_DPI0,
177 };
178
179 static const unsigned int mt8188_mtk_ddp_main[] = {
180 DDP_COMPONENT_OVL0,
181 DDP_COMPONENT_RDMA0,
182 DDP_COMPONENT_COLOR0,
183 DDP_COMPONENT_CCORR,
184 DDP_COMPONENT_AAL0,
185 DDP_COMPONENT_GAMMA,
186 DDP_COMPONENT_POSTMASK0,
187 DDP_COMPONENT_DITHER0,
188 };
189
190 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
191 {0, DDP_COMPONENT_DP_INTF0},
192 {0, DDP_COMPONENT_DSI0},
193 };
194
195 static const unsigned int mt8192_mtk_ddp_main[] = {
196 DDP_COMPONENT_OVL0,
197 DDP_COMPONENT_OVL_2L0,
198 DDP_COMPONENT_RDMA0,
199 DDP_COMPONENT_COLOR0,
200 DDP_COMPONENT_CCORR,
201 DDP_COMPONENT_AAL0,
202 DDP_COMPONENT_GAMMA,
203 DDP_COMPONENT_POSTMASK0,
204 DDP_COMPONENT_DITHER0,
205 DDP_COMPONENT_DSI0,
206 };
207
208 static const unsigned int mt8192_mtk_ddp_ext[] = {
209 DDP_COMPONENT_OVL_2L2,
210 DDP_COMPONENT_RDMA4,
211 DDP_COMPONENT_DPI0,
212 };
213
214 static const unsigned int mt8195_mtk_ddp_main[] = {
215 DDP_COMPONENT_OVL0,
216 DDP_COMPONENT_RDMA0,
217 DDP_COMPONENT_COLOR0,
218 DDP_COMPONENT_CCORR,
219 DDP_COMPONENT_AAL0,
220 DDP_COMPONENT_GAMMA,
221 DDP_COMPONENT_DITHER0,
222 DDP_COMPONENT_DSC0,
223 DDP_COMPONENT_MERGE0,
224 DDP_COMPONENT_DP_INTF0,
225 };
226
227 static const unsigned int mt8195_mtk_ddp_ext[] = {
228 DDP_COMPONENT_DRM_OVL_ADAPTOR,
229 DDP_COMPONENT_MERGE5,
230 DDP_COMPONENT_DP_INTF1,
231 };
232
233 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
234 .main_path = mt2701_mtk_ddp_main,
235 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
236 .ext_path = mt2701_mtk_ddp_ext,
237 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
238 .shadow_register = true,
239 .mmsys_dev_num = 1,
240 };
241
242 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
243 .main_path = mt7623_mtk_ddp_main,
244 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
245 .ext_path = mt7623_mtk_ddp_ext,
246 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
247 .shadow_register = true,
248 .mmsys_dev_num = 1,
249 };
250
251 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
252 .main_path = mt2712_mtk_ddp_main,
253 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
254 .ext_path = mt2712_mtk_ddp_ext,
255 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
256 .third_path = mt2712_mtk_ddp_third,
257 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
258 .mmsys_dev_num = 1,
259 };
260
261 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
262 .main_path = mt8167_mtk_ddp_main,
263 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
264 .mmsys_dev_num = 1,
265 };
266
267 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
268 .main_path = mt8173_mtk_ddp_main,
269 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
270 .ext_path = mt8173_mtk_ddp_ext,
271 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
272 .mmsys_dev_num = 1,
273 };
274
275 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
276 .main_path = mt8183_mtk_ddp_main,
277 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
278 .ext_path = mt8183_mtk_ddp_ext,
279 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
280 .mmsys_dev_num = 1,
281 };
282
283 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
284 .main_path = mt8186_mtk_ddp_main,
285 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
286 .ext_path = mt8186_mtk_ddp_ext,
287 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
288 .mmsys_dev_num = 1,
289 };
290
291 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
292 .main_path = mt8188_mtk_ddp_main,
293 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
294 .conn_routes = mt8188_mtk_ddp_main_routes,
295 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
296 .mmsys_dev_num = 2,
297 .max_width = 8191,
298 .min_width = 1,
299 .min_height = 1,
300 };
301
302 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
303 .main_path = mt8192_mtk_ddp_main,
304 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
305 .ext_path = mt8192_mtk_ddp_ext,
306 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
307 .mmsys_dev_num = 1,
308 };
309
310 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
311 .main_path = mt8195_mtk_ddp_main,
312 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
313 .mmsys_dev_num = 2,
314 .max_width = 8191,
315 .min_width = 1,
316 .min_height = 1,
317 };
318
319 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
320 .ext_path = mt8195_mtk_ddp_ext,
321 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
322 .mmsys_id = 1,
323 .mmsys_dev_num = 2,
324 .max_width = 8191,
325 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
326 .min_height = 1,
327 };
328
329 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
330 .mmsys_dev_num = 1,
331 };
332
333 static const struct of_device_id mtk_drm_of_ids[] = {
334 { .compatible = "mediatek,mt2701-mmsys",
335 .data = &mt2701_mmsys_driver_data},
336 { .compatible = "mediatek,mt7623-mmsys",
337 .data = &mt7623_mmsys_driver_data},
338 { .compatible = "mediatek,mt2712-mmsys",
339 .data = &mt2712_mmsys_driver_data},
340 { .compatible = "mediatek,mt8167-mmsys",
341 .data = &mt8167_mmsys_driver_data},
342 { .compatible = "mediatek,mt8173-mmsys",
343 .data = &mt8173_mmsys_driver_data},
344 { .compatible = "mediatek,mt8183-mmsys",
345 .data = &mt8183_mmsys_driver_data},
346 { .compatible = "mediatek,mt8186-mmsys",
347 .data = &mt8186_mmsys_driver_data},
348 { .compatible = "mediatek,mt8188-vdosys0",
349 .data = &mt8188_vdosys0_driver_data},
350 { .compatible = "mediatek,mt8188-vdosys1",
351 .data = &mt8195_vdosys1_driver_data},
352 { .compatible = "mediatek,mt8192-mmsys",
353 .data = &mt8192_mmsys_driver_data},
354 { .compatible = "mediatek,mt8195-mmsys",
355 .data = &mt8195_vdosys0_driver_data},
356 { .compatible = "mediatek,mt8195-vdosys0",
357 .data = &mt8195_vdosys0_driver_data},
358 { .compatible = "mediatek,mt8195-vdosys1",
359 .data = &mt8195_vdosys1_driver_data},
360 { .compatible = "mediatek,mt8365-mmsys",
361 .data = &mt8365_mmsys_driver_data},
362 { }
363 };
364 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
365
mtk_drm_match(struct device * dev,const void * data)366 static int mtk_drm_match(struct device *dev, const void *data)
367 {
368 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
369 return true;
370 return false;
371 }
372
mtk_drm_get_all_drm_priv(struct device * dev)373 static bool mtk_drm_get_all_drm_priv(struct device *dev)
374 {
375 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
376 struct mtk_drm_private *all_drm_priv[MAX_CRTC];
377 struct mtk_drm_private *temp_drm_priv;
378 struct device_node *phandle = dev->parent->of_node;
379 const struct of_device_id *of_id;
380 struct device_node *node;
381 struct device *drm_dev;
382 unsigned int cnt = 0;
383 int i, j;
384
385 for_each_child_of_node(phandle->parent, node) {
386 struct platform_device *pdev;
387
388 of_id = of_match_node(mtk_drm_of_ids, node);
389 if (!of_id)
390 continue;
391
392 pdev = of_find_device_by_node(node);
393 if (!pdev)
394 continue;
395
396 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
397 if (!drm_dev)
398 continue;
399
400 temp_drm_priv = dev_get_drvdata(drm_dev);
401 if (!temp_drm_priv)
402 continue;
403
404 if (temp_drm_priv->data->main_len)
405 all_drm_priv[CRTC_MAIN] = temp_drm_priv;
406 else if (temp_drm_priv->data->ext_len)
407 all_drm_priv[CRTC_EXT] = temp_drm_priv;
408 else if (temp_drm_priv->data->third_len)
409 all_drm_priv[CRTC_THIRD] = temp_drm_priv;
410
411 if (temp_drm_priv->mtk_drm_bound)
412 cnt++;
413
414 if (cnt == MAX_CRTC) {
415 of_node_put(node);
416 break;
417 }
418 }
419
420 if (drm_priv->data->mmsys_dev_num == cnt) {
421 for (i = 0; i < cnt; i++)
422 for (j = 0; j < cnt; j++)
423 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
424
425 return true;
426 }
427
428 return false;
429 }
430
mtk_drm_find_mmsys_comp(struct mtk_drm_private * private,int comp_id)431 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
432 {
433 const struct mtk_mmsys_driver_data *drv_data = private->data;
434 int i;
435
436 if (drv_data->main_path)
437 for (i = 0; i < drv_data->main_len; i++)
438 if (drv_data->main_path[i] == comp_id)
439 return true;
440
441 if (drv_data->ext_path)
442 for (i = 0; i < drv_data->ext_len; i++)
443 if (drv_data->ext_path[i] == comp_id)
444 return true;
445
446 if (drv_data->third_path)
447 for (i = 0; i < drv_data->third_len; i++)
448 if (drv_data->third_path[i] == comp_id)
449 return true;
450
451 if (drv_data->num_conn_routes)
452 for (i = 0; i < drv_data->num_conn_routes; i++)
453 if (drv_data->conn_routes[i].route_ddp == comp_id)
454 return true;
455
456 return false;
457 }
458
mtk_drm_kms_init(struct drm_device * drm)459 static int mtk_drm_kms_init(struct drm_device *drm)
460 {
461 struct mtk_drm_private *private = drm->dev_private;
462 struct mtk_drm_private *priv_n;
463 struct device *dma_dev = NULL;
464 struct drm_crtc *crtc;
465 int ret, i, j;
466
467 if (drm_firmware_drivers_only())
468 return -ENODEV;
469
470 ret = drmm_mode_config_init(drm);
471 if (ret)
472 return ret;
473
474 drm->mode_config.min_width = 64;
475 drm->mode_config.min_height = 64;
476
477 /*
478 * set max width and height as default value(4096x4096).
479 * this value would be used to check framebuffer size limitation
480 * at drm_mode_addfb().
481 */
482 drm->mode_config.max_width = 4096;
483 drm->mode_config.max_height = 4096;
484 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
485 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
486
487 for (i = 0; i < private->data->mmsys_dev_num; i++) {
488 drm->dev_private = private->all_drm_private[i];
489 ret = component_bind_all(private->all_drm_private[i]->dev, drm);
490 if (ret) {
491 while (--i >= 0)
492 component_unbind_all(private->all_drm_private[i]->dev, drm);
493 return ret;
494 }
495 }
496
497 /*
498 * Ensure internal panels are at the top of the connector list before
499 * crtc creation.
500 */
501 drm_helper_move_panel_connectors_to_head(drm);
502
503 /*
504 * 1. We currently support two fixed data streams, each optional,
505 * and each statically assigned to a crtc:
506 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
507 * 2. For multi mmsys architecture, crtc path data are located in
508 * different drm private data structures. Loop through crtc index to
509 * create crtc from the main path and then ext_path and finally the
510 * third path.
511 */
512 for (i = 0; i < MAX_CRTC; i++) {
513 for (j = 0; j < private->data->mmsys_dev_num; j++) {
514 priv_n = private->all_drm_private[j];
515
516 if (priv_n->data->max_width)
517 drm->mode_config.max_width = priv_n->data->max_width;
518
519 if (priv_n->data->min_width)
520 drm->mode_config.min_width = priv_n->data->min_width;
521
522 if (priv_n->data->min_height)
523 drm->mode_config.min_height = priv_n->data->min_height;
524
525 if (i == CRTC_MAIN && priv_n->data->main_len) {
526 ret = mtk_crtc_create(drm, priv_n->data->main_path,
527 priv_n->data->main_len, j,
528 priv_n->data->conn_routes,
529 priv_n->data->num_conn_routes);
530 if (ret)
531 goto err_component_unbind;
532
533 continue;
534 } else if (i == CRTC_EXT && priv_n->data->ext_len) {
535 ret = mtk_crtc_create(drm, priv_n->data->ext_path,
536 priv_n->data->ext_len, j, NULL, 0);
537 if (ret)
538 goto err_component_unbind;
539
540 continue;
541 } else if (i == CRTC_THIRD && priv_n->data->third_len) {
542 ret = mtk_crtc_create(drm, priv_n->data->third_path,
543 priv_n->data->third_len, j, NULL, 0);
544 if (ret)
545 goto err_component_unbind;
546
547 continue;
548 }
549 }
550 }
551
552 /* IGT will check if the cursor size is configured */
553 drm->mode_config.cursor_width = 512;
554 drm->mode_config.cursor_height = 512;
555
556 /* Use OVL device for all DMA memory allocations */
557 crtc = drm_crtc_from_index(drm, 0);
558 if (crtc)
559 dma_dev = mtk_crtc_dma_dev_get(crtc);
560 if (!dma_dev) {
561 ret = -ENODEV;
562 dev_err(drm->dev, "Need at least one OVL device\n");
563 goto err_component_unbind;
564 }
565
566 for (i = 0; i < private->data->mmsys_dev_num; i++)
567 private->all_drm_private[i]->dma_dev = dma_dev;
568
569 /*
570 * Configure the DMA segment size to make sure we get contiguous IOVA
571 * when importing PRIME buffers.
572 */
573 dma_set_max_seg_size(dma_dev, UINT_MAX);
574
575 ret = drm_vblank_init(drm, MAX_CRTC);
576 if (ret < 0)
577 goto err_component_unbind;
578
579 drm_kms_helper_poll_init(drm);
580 drm_mode_config_reset(drm);
581
582 return 0;
583
584 err_component_unbind:
585 for (i = 0; i < private->data->mmsys_dev_num; i++)
586 component_unbind_all(private->all_drm_private[i]->dev, drm);
587
588 return ret;
589 }
590
mtk_drm_kms_deinit(struct drm_device * drm)591 static void mtk_drm_kms_deinit(struct drm_device *drm)
592 {
593 drm_kms_helper_poll_fini(drm);
594 drm_atomic_helper_shutdown(drm);
595
596 component_unbind_all(drm->dev, drm);
597 }
598
599 DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
600
601 /*
602 * We need to override this because the device used to import the memory is
603 * not dev->dev, as drm_gem_prime_import() expects.
604 */
mtk_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)605 static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev,
606 struct dma_buf *dma_buf)
607 {
608 struct mtk_drm_private *private = dev->dev_private;
609
610 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
611 }
612
613 static const struct drm_driver mtk_drm_driver = {
614 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
615
616 .dumb_create = mtk_gem_dumb_create,
617 DRM_FBDEV_DMA_DRIVER_OPS,
618
619 .gem_prime_import = mtk_gem_prime_import,
620 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
621 .fops = &mtk_drm_fops,
622
623 .name = DRIVER_NAME,
624 .desc = DRIVER_DESC,
625 .major = DRIVER_MAJOR,
626 .minor = DRIVER_MINOR,
627 };
628
compare_dev(struct device * dev,void * data)629 static int compare_dev(struct device *dev, void *data)
630 {
631 return dev == (struct device *)data;
632 }
633
mtk_drm_bind(struct device * dev)634 static int mtk_drm_bind(struct device *dev)
635 {
636 struct mtk_drm_private *private = dev_get_drvdata(dev);
637 struct platform_device *pdev;
638 struct drm_device *drm;
639 int ret, i;
640
641 pdev = of_find_device_by_node(private->mutex_node);
642 if (!pdev) {
643 dev_err(dev, "Waiting for disp-mutex device %pOF\n",
644 private->mutex_node);
645 of_node_put(private->mutex_node);
646 return -EPROBE_DEFER;
647 }
648
649 private->mutex_dev = &pdev->dev;
650 private->mtk_drm_bound = true;
651 private->dev = dev;
652
653 if (!mtk_drm_get_all_drm_priv(dev))
654 return 0;
655
656 drm = drm_dev_alloc(&mtk_drm_driver, dev);
657 if (IS_ERR(drm)) {
658 ret = PTR_ERR(drm);
659 goto err_put_dev;
660 }
661
662 private->drm_master = true;
663 drm->dev_private = private;
664 for (i = 0; i < private->data->mmsys_dev_num; i++)
665 private->all_drm_private[i]->drm = drm;
666
667 ret = mtk_drm_kms_init(drm);
668 if (ret < 0)
669 goto err_free;
670
671 ret = drm_dev_register(drm, 0);
672 if (ret < 0)
673 goto err_deinit;
674
675 drm_client_setup(drm, NULL);
676
677 return 0;
678
679 err_deinit:
680 mtk_drm_kms_deinit(drm);
681 err_free:
682 private->drm = NULL;
683 drm_dev_put(drm);
684 for (i = 0; i < private->data->mmsys_dev_num; i++)
685 private->all_drm_private[i]->drm = NULL;
686 err_put_dev:
687 for (i = 0; i < private->data->mmsys_dev_num; i++) {
688 /* For device_find_child in mtk_drm_get_all_priv() */
689 put_device(private->all_drm_private[i]->dev);
690 }
691 put_device(private->mutex_dev);
692 return ret;
693 }
694
mtk_drm_unbind(struct device * dev)695 static void mtk_drm_unbind(struct device *dev)
696 {
697 struct mtk_drm_private *private = dev_get_drvdata(dev);
698 int i;
699
700 /* for multi mmsys dev, unregister drm dev in mmsys master */
701 if (private->drm_master) {
702 drm_dev_unregister(private->drm);
703 mtk_drm_kms_deinit(private->drm);
704 drm_dev_put(private->drm);
705
706 for (i = 0; i < private->data->mmsys_dev_num; i++) {
707 /* For device_find_child in mtk_drm_get_all_priv() */
708 put_device(private->all_drm_private[i]->dev);
709 }
710 put_device(private->mutex_dev);
711 }
712 private->mtk_drm_bound = false;
713 private->drm_master = false;
714 private->drm = NULL;
715 }
716
717 static const struct component_master_ops mtk_drm_ops = {
718 .bind = mtk_drm_bind,
719 .unbind = mtk_drm_unbind,
720 };
721
722 static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
723 { .compatible = "mediatek,mt8167-disp-aal",
724 .data = (void *)MTK_DISP_AAL},
725 { .compatible = "mediatek,mt8173-disp-aal",
726 .data = (void *)MTK_DISP_AAL},
727 { .compatible = "mediatek,mt8183-disp-aal",
728 .data = (void *)MTK_DISP_AAL},
729 { .compatible = "mediatek,mt8192-disp-aal",
730 .data = (void *)MTK_DISP_AAL},
731 { .compatible = "mediatek,mt8167-disp-ccorr",
732 .data = (void *)MTK_DISP_CCORR },
733 { .compatible = "mediatek,mt8183-disp-ccorr",
734 .data = (void *)MTK_DISP_CCORR },
735 { .compatible = "mediatek,mt8192-disp-ccorr",
736 .data = (void *)MTK_DISP_CCORR },
737 { .compatible = "mediatek,mt2701-disp-color",
738 .data = (void *)MTK_DISP_COLOR },
739 { .compatible = "mediatek,mt8167-disp-color",
740 .data = (void *)MTK_DISP_COLOR },
741 { .compatible = "mediatek,mt8173-disp-color",
742 .data = (void *)MTK_DISP_COLOR },
743 { .compatible = "mediatek,mt8167-disp-dither",
744 .data = (void *)MTK_DISP_DITHER },
745 { .compatible = "mediatek,mt8183-disp-dither",
746 .data = (void *)MTK_DISP_DITHER },
747 { .compatible = "mediatek,mt8195-disp-dsc",
748 .data = (void *)MTK_DISP_DSC },
749 { .compatible = "mediatek,mt8167-disp-gamma",
750 .data = (void *)MTK_DISP_GAMMA, },
751 { .compatible = "mediatek,mt8173-disp-gamma",
752 .data = (void *)MTK_DISP_GAMMA, },
753 { .compatible = "mediatek,mt8183-disp-gamma",
754 .data = (void *)MTK_DISP_GAMMA, },
755 { .compatible = "mediatek,mt8195-disp-gamma",
756 .data = (void *)MTK_DISP_GAMMA, },
757 { .compatible = "mediatek,mt8195-disp-merge",
758 .data = (void *)MTK_DISP_MERGE },
759 { .compatible = "mediatek,mt2701-disp-mutex",
760 .data = (void *)MTK_DISP_MUTEX },
761 { .compatible = "mediatek,mt2712-disp-mutex",
762 .data = (void *)MTK_DISP_MUTEX },
763 { .compatible = "mediatek,mt8167-disp-mutex",
764 .data = (void *)MTK_DISP_MUTEX },
765 { .compatible = "mediatek,mt8173-disp-mutex",
766 .data = (void *)MTK_DISP_MUTEX },
767 { .compatible = "mediatek,mt8183-disp-mutex",
768 .data = (void *)MTK_DISP_MUTEX },
769 { .compatible = "mediatek,mt8186-disp-mutex",
770 .data = (void *)MTK_DISP_MUTEX },
771 { .compatible = "mediatek,mt8188-disp-mutex",
772 .data = (void *)MTK_DISP_MUTEX },
773 { .compatible = "mediatek,mt8192-disp-mutex",
774 .data = (void *)MTK_DISP_MUTEX },
775 { .compatible = "mediatek,mt8195-disp-mutex",
776 .data = (void *)MTK_DISP_MUTEX },
777 { .compatible = "mediatek,mt8365-disp-mutex",
778 .data = (void *)MTK_DISP_MUTEX },
779 { .compatible = "mediatek,mt8173-disp-od",
780 .data = (void *)MTK_DISP_OD },
781 { .compatible = "mediatek,mt2701-disp-ovl",
782 .data = (void *)MTK_DISP_OVL },
783 { .compatible = "mediatek,mt8167-disp-ovl",
784 .data = (void *)MTK_DISP_OVL },
785 { .compatible = "mediatek,mt8173-disp-ovl",
786 .data = (void *)MTK_DISP_OVL },
787 { .compatible = "mediatek,mt8183-disp-ovl",
788 .data = (void *)MTK_DISP_OVL },
789 { .compatible = "mediatek,mt8192-disp-ovl",
790 .data = (void *)MTK_DISP_OVL },
791 { .compatible = "mediatek,mt8195-disp-ovl",
792 .data = (void *)MTK_DISP_OVL },
793 { .compatible = "mediatek,mt8183-disp-ovl-2l",
794 .data = (void *)MTK_DISP_OVL_2L },
795 { .compatible = "mediatek,mt8192-disp-ovl-2l",
796 .data = (void *)MTK_DISP_OVL_2L },
797 { .compatible = "mediatek,mt8192-disp-postmask",
798 .data = (void *)MTK_DISP_POSTMASK },
799 { .compatible = "mediatek,mt2701-disp-pwm",
800 .data = (void *)MTK_DISP_BLS },
801 { .compatible = "mediatek,mt8167-disp-pwm",
802 .data = (void *)MTK_DISP_PWM },
803 { .compatible = "mediatek,mt8173-disp-pwm",
804 .data = (void *)MTK_DISP_PWM },
805 { .compatible = "mediatek,mt2701-disp-rdma",
806 .data = (void *)MTK_DISP_RDMA },
807 { .compatible = "mediatek,mt8167-disp-rdma",
808 .data = (void *)MTK_DISP_RDMA },
809 { .compatible = "mediatek,mt8173-disp-rdma",
810 .data = (void *)MTK_DISP_RDMA },
811 { .compatible = "mediatek,mt8183-disp-rdma",
812 .data = (void *)MTK_DISP_RDMA },
813 { .compatible = "mediatek,mt8195-disp-rdma",
814 .data = (void *)MTK_DISP_RDMA },
815 { .compatible = "mediatek,mt8173-disp-ufoe",
816 .data = (void *)MTK_DISP_UFOE },
817 { .compatible = "mediatek,mt8173-disp-wdma",
818 .data = (void *)MTK_DISP_WDMA },
819 { .compatible = "mediatek,mt2701-dpi",
820 .data = (void *)MTK_DPI },
821 { .compatible = "mediatek,mt8167-dsi",
822 .data = (void *)MTK_DSI },
823 { .compatible = "mediatek,mt8173-dpi",
824 .data = (void *)MTK_DPI },
825 { .compatible = "mediatek,mt8183-dpi",
826 .data = (void *)MTK_DPI },
827 { .compatible = "mediatek,mt8186-dpi",
828 .data = (void *)MTK_DPI },
829 { .compatible = "mediatek,mt8188-dp-intf",
830 .data = (void *)MTK_DP_INTF },
831 { .compatible = "mediatek,mt8192-dpi",
832 .data = (void *)MTK_DPI },
833 { .compatible = "mediatek,mt8195-dp-intf",
834 .data = (void *)MTK_DP_INTF },
835 { .compatible = "mediatek,mt8195-dpi",
836 .data = (void *)MTK_DPI },
837 { .compatible = "mediatek,mt2701-dsi",
838 .data = (void *)MTK_DSI },
839 { .compatible = "mediatek,mt8173-dsi",
840 .data = (void *)MTK_DSI },
841 { .compatible = "mediatek,mt8183-dsi",
842 .data = (void *)MTK_DSI },
843 { .compatible = "mediatek,mt8186-dsi",
844 .data = (void *)MTK_DSI },
845 { .compatible = "mediatek,mt8188-dsi",
846 .data = (void *)MTK_DSI },
847 { }
848 };
849
mtk_drm_of_get_ddp_comp_type(struct device_node * node,enum mtk_ddp_comp_type * ctype)850 static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype)
851 {
852 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
853
854 if (!of_id)
855 return -EINVAL;
856
857 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data);
858
859 return 0;
860 }
861
mtk_drm_of_get_ddp_ep_cid(struct device_node * node,int output_port,enum mtk_crtc_path crtc_path,struct device_node ** next,unsigned int * cid)862 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
863 int output_port, enum mtk_crtc_path crtc_path,
864 struct device_node **next, unsigned int *cid)
865 {
866 struct device_node *ep_dev_node, *ep_out;
867 enum mtk_ddp_comp_type comp_type;
868 int ret;
869
870 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path);
871 if (!ep_out)
872 return -ENOENT;
873
874 ep_dev_node = of_graph_get_remote_port_parent(ep_out);
875 of_node_put(ep_out);
876 if (!ep_dev_node)
877 return -EINVAL;
878
879 /*
880 * Pass the next node pointer regardless of failures in the later code
881 * so that if this function is called in a loop it will walk through all
882 * of the subsequent endpoints anyway.
883 */
884 *next = ep_dev_node;
885
886 if (!of_device_is_available(ep_dev_node))
887 return -ENODEV;
888
889 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type);
890 if (ret) {
891 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) {
892 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR;
893 return 0;
894 }
895 return ret;
896 }
897
898 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type);
899 if (ret < 0)
900 return ret;
901
902 /* All ok! Pass the Component ID to the caller. */
903 *cid = (unsigned int)ret;
904
905 return 0;
906 }
907
908 /**
909 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path
910 * @dev: The mediatek-drm device
911 * @cpath: CRTC Path relative to a VDO or MMSYS
912 * @out_path: Pointer to an array that will contain the new pipeline
913 * @out_path_len: Number of entries in the pipeline array
914 *
915 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending
916 * on the board-specific desired display configuration; this function walks
917 * through all of the output endpoints starting from a VDO or MMSYS hardware
918 * instance and builds the right pipeline as specified in device trees.
919 *
920 * Return:
921 * * %0 - Display HW Pipeline successfully built and validated
922 * * %-ENOENT - Display pipeline was not specified in device tree
923 * * %-EINVAL - Display pipeline built but validation failed
924 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller
925 */
mtk_drm_of_ddp_path_build_one(struct device * dev,enum mtk_crtc_path cpath,const unsigned int ** out_path,unsigned int * out_path_len)926 static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath,
927 const unsigned int **out_path,
928 unsigned int *out_path_len)
929 {
930 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node;
931 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 };
932 unsigned int *final_ddp_path;
933 unsigned short int idx = 0;
934 bool ovl_adaptor_comp_added = false;
935 int ret;
936
937 /* Get the first entry for the temp_path array */
938 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]);
939 if (ret) {
940 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
941 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next);
942 ovl_adaptor_comp_added = true;
943 } else {
944 if (next)
945 dev_err(dev, "Invalid component %pOF\n", next);
946 else
947 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath);
948
949 return ret;
950 }
951 }
952 idx++;
953
954 /*
955 * Walk through port outputs until we reach the last valid mediatek-drm component.
956 * To be valid, this must end with an "invalid" component that is a display node.
957 */
958 do {
959 prev = next;
960 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]);
961 of_node_put(prev);
962 if (ret) {
963 of_node_put(next);
964 break;
965 }
966
967 /*
968 * If this is an OVL adaptor exclusive component and one of those
969 * was already added, don't add another instance of the generic
970 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether
971 * to probe that component master driver of which only one instance
972 * is needed and possible.
973 */
974 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
975 if (!ovl_adaptor_comp_added)
976 ovl_adaptor_comp_added = true;
977 else
978 idx--;
979 }
980 } while (++idx < DDP_COMPONENT_DRM_ID_MAX);
981
982 /*
983 * The device component might not be enabled: in that case, don't
984 * check the last entry and just report that the device is missing.
985 */
986 if (ret == -ENODEV)
987 return ret;
988
989 /* If the last entry is not a final display output, the configuration is wrong */
990 switch (temp_path[idx - 1]) {
991 case DDP_COMPONENT_DP_INTF0:
992 case DDP_COMPONENT_DP_INTF1:
993 case DDP_COMPONENT_DPI0:
994 case DDP_COMPONENT_DPI1:
995 case DDP_COMPONENT_DSI0:
996 case DDP_COMPONENT_DSI1:
997 case DDP_COMPONENT_DSI2:
998 case DDP_COMPONENT_DSI3:
999 break;
1000 default:
1001 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n",
1002 temp_path[idx - 1], ret);
1003 return -EINVAL;
1004 }
1005
1006 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL);
1007 if (!final_ddp_path)
1008 return -ENOMEM;
1009
1010 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx);
1011
1012 /* Pipeline built! */
1013 *out_path = final_ddp_path;
1014 *out_path_len = idx;
1015
1016 return 0;
1017 }
1018
mtk_drm_of_ddp_path_build(struct device * dev,struct device_node * node,struct mtk_mmsys_driver_data * data)1019 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node,
1020 struct mtk_mmsys_driver_data *data)
1021 {
1022 struct device_node *ep_node;
1023 struct of_endpoint of_ep;
1024 bool output_present[MAX_CRTC] = { false };
1025 int ret;
1026
1027 for_each_endpoint_of_node(node, ep_node) {
1028 ret = of_graph_parse_endpoint(ep_node, &of_ep);
1029 if (ret) {
1030 dev_err_probe(dev, ret, "Cannot parse endpoint\n");
1031 break;
1032 }
1033
1034 if (of_ep.id >= MAX_CRTC) {
1035 ret = dev_err_probe(dev, -EINVAL,
1036 "Invalid endpoint%u number\n", of_ep.port);
1037 break;
1038 }
1039
1040 output_present[of_ep.id] = true;
1041 }
1042
1043 if (ret) {
1044 of_node_put(ep_node);
1045 return ret;
1046 }
1047
1048 if (output_present[CRTC_MAIN]) {
1049 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN,
1050 &data->main_path, &data->main_len);
1051 if (ret && ret != -ENODEV)
1052 return ret;
1053 }
1054
1055 if (output_present[CRTC_EXT]) {
1056 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT,
1057 &data->ext_path, &data->ext_len);
1058 if (ret && ret != -ENODEV)
1059 return ret;
1060 }
1061
1062 if (output_present[CRTC_THIRD]) {
1063 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD,
1064 &data->third_path, &data->third_len);
1065 if (ret && ret != -ENODEV)
1066 return ret;
1067 }
1068
1069 return 0;
1070 }
1071
mtk_drm_probe(struct platform_device * pdev)1072 static int mtk_drm_probe(struct platform_device *pdev)
1073 {
1074 struct device *dev = &pdev->dev;
1075 struct device_node *phandle = dev->parent->of_node;
1076 const struct of_device_id *of_id;
1077 struct mtk_drm_private *private;
1078 struct mtk_mmsys_driver_data *mtk_drm_data;
1079 struct device_node *node;
1080 struct component_match *match = NULL;
1081 struct platform_device *ovl_adaptor;
1082 int ret;
1083 int i;
1084
1085 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
1086 if (!private)
1087 return -ENOMEM;
1088
1089 private->mmsys_dev = dev->parent;
1090 if (!private->mmsys_dev) {
1091 dev_err(dev, "Failed to get MMSYS device\n");
1092 return -ENODEV;
1093 }
1094
1095 of_id = of_match_node(mtk_drm_of_ids, phandle);
1096 if (!of_id)
1097 return -ENODEV;
1098
1099 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data;
1100 if (!mtk_drm_data)
1101 return -EINVAL;
1102
1103 /* Try to build the display pipeline from devicetree graphs */
1104 if (of_graph_is_present(phandle)) {
1105 dev_dbg(dev, "Building display pipeline for MMSYS %u\n",
1106 mtk_drm_data->mmsys_id);
1107 private->data = devm_kmemdup(dev, mtk_drm_data,
1108 sizeof(*mtk_drm_data), GFP_KERNEL);
1109 if (!private->data)
1110 return -ENOMEM;
1111
1112 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data);
1113 if (ret)
1114 return ret;
1115 } else {
1116 /* No devicetree graphs support: go with hardcoded paths if present */
1117 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id);
1118 private->data = mtk_drm_data;
1119 }
1120
1121 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
1122 sizeof(*private->all_drm_private),
1123 GFP_KERNEL);
1124 if (!private->all_drm_private)
1125 return -ENOMEM;
1126
1127 /* Bringup ovl_adaptor */
1128 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
1129 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
1130 PLATFORM_DEVID_AUTO,
1131 (void *)private->mmsys_dev,
1132 sizeof(*private->mmsys_dev));
1133 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
1134 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
1135 DDP_COMPONENT_DRM_OVL_ADAPTOR);
1136 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
1137 }
1138
1139 /* Iterate over sibling DISP function blocks */
1140 for_each_child_of_node(phandle->parent, node) {
1141 enum mtk_ddp_comp_type comp_type;
1142 int comp_id;
1143
1144 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type);
1145 if (ret)
1146 continue;
1147
1148 if (!of_device_is_available(node)) {
1149 dev_dbg(dev, "Skipping disabled component %pOF\n",
1150 node);
1151 continue;
1152 }
1153
1154 if (comp_type == MTK_DISP_MUTEX) {
1155 int id;
1156
1157 id = of_alias_get_id(node, "mutex");
1158 if (id < 0 || id == private->data->mmsys_id) {
1159 private->mutex_node = of_node_get(node);
1160 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
1161 }
1162 continue;
1163 }
1164
1165 comp_id = mtk_ddp_comp_get_id(node, comp_type);
1166 if (comp_id < 0) {
1167 dev_warn(dev, "Skipping unknown component %pOF\n",
1168 node);
1169 continue;
1170 }
1171
1172 if (!mtk_drm_find_mmsys_comp(private, comp_id))
1173 continue;
1174
1175 private->comp_node[comp_id] = of_node_get(node);
1176
1177 /*
1178 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
1179 * blocks have separate component platform drivers and initialize their own
1180 * DDP component structure. The others are initialized here.
1181 */
1182 if (comp_type == MTK_DISP_AAL ||
1183 comp_type == MTK_DISP_CCORR ||
1184 comp_type == MTK_DISP_COLOR ||
1185 comp_type == MTK_DISP_GAMMA ||
1186 comp_type == MTK_DISP_MERGE ||
1187 comp_type == MTK_DISP_OVL ||
1188 comp_type == MTK_DISP_OVL_2L ||
1189 comp_type == MTK_DISP_OVL_ADAPTOR ||
1190 comp_type == MTK_DISP_RDMA ||
1191 comp_type == MTK_DP_INTF ||
1192 comp_type == MTK_DPI ||
1193 comp_type == MTK_DSI) {
1194 dev_info(dev, "Adding component match for %pOF\n",
1195 node);
1196 drm_of_component_match_add(dev, &match, component_compare_of,
1197 node);
1198 }
1199
1200 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
1201 if (ret) {
1202 of_node_put(node);
1203 goto err_node;
1204 }
1205 }
1206
1207 if (!private->mutex_node) {
1208 dev_err(dev, "Failed to find disp-mutex node\n");
1209 ret = -ENODEV;
1210 goto err_node;
1211 }
1212
1213 pm_runtime_enable(dev);
1214
1215 platform_set_drvdata(pdev, private);
1216
1217 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
1218 if (ret)
1219 goto err_pm;
1220
1221 return 0;
1222
1223 err_pm:
1224 pm_runtime_disable(dev);
1225 err_node:
1226 of_node_put(private->mutex_node);
1227 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1228 of_node_put(private->comp_node[i]);
1229 return ret;
1230 }
1231
mtk_drm_remove(struct platform_device * pdev)1232 static void mtk_drm_remove(struct platform_device *pdev)
1233 {
1234 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1235 int i;
1236
1237 component_master_del(&pdev->dev, &mtk_drm_ops);
1238 pm_runtime_disable(&pdev->dev);
1239 of_node_put(private->mutex_node);
1240 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1241 of_node_put(private->comp_node[i]);
1242 }
1243
mtk_drm_shutdown(struct platform_device * pdev)1244 static void mtk_drm_shutdown(struct platform_device *pdev)
1245 {
1246 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1247
1248 drm_atomic_helper_shutdown(private->drm);
1249 }
1250
mtk_drm_sys_prepare(struct device * dev)1251 static int mtk_drm_sys_prepare(struct device *dev)
1252 {
1253 struct mtk_drm_private *private = dev_get_drvdata(dev);
1254 struct drm_device *drm = private->drm;
1255
1256 if (private->drm_master)
1257 return drm_mode_config_helper_suspend(drm);
1258 else
1259 return 0;
1260 }
1261
mtk_drm_sys_complete(struct device * dev)1262 static void mtk_drm_sys_complete(struct device *dev)
1263 {
1264 struct mtk_drm_private *private = dev_get_drvdata(dev);
1265 struct drm_device *drm = private->drm;
1266 int ret = 0;
1267
1268 if (private->drm_master)
1269 ret = drm_mode_config_helper_resume(drm);
1270 if (ret)
1271 dev_err(dev, "Failed to resume\n");
1272 }
1273
1274 static const struct dev_pm_ops mtk_drm_pm_ops = {
1275 .prepare = mtk_drm_sys_prepare,
1276 .complete = mtk_drm_sys_complete,
1277 };
1278
1279 static struct platform_driver mtk_drm_platform_driver = {
1280 .probe = mtk_drm_probe,
1281 .remove = mtk_drm_remove,
1282 .shutdown = mtk_drm_shutdown,
1283 .driver = {
1284 .name = "mediatek-drm",
1285 .pm = &mtk_drm_pm_ops,
1286 },
1287 };
1288
1289 static struct platform_driver * const mtk_drm_drivers[] = {
1290 &mtk_disp_aal_driver,
1291 &mtk_disp_ccorr_driver,
1292 &mtk_disp_color_driver,
1293 &mtk_disp_gamma_driver,
1294 &mtk_disp_merge_driver,
1295 &mtk_disp_ovl_adaptor_driver,
1296 &mtk_disp_ovl_driver,
1297 &mtk_disp_rdma_driver,
1298 &mtk_dpi_driver,
1299 &mtk_drm_platform_driver,
1300 &mtk_dsi_driver,
1301 &mtk_ethdr_driver,
1302 &mtk_mdp_rdma_driver,
1303 &mtk_padding_driver,
1304 };
1305
mtk_drm_init(void)1306 static int __init mtk_drm_init(void)
1307 {
1308 return platform_register_drivers(mtk_drm_drivers,
1309 ARRAY_SIZE(mtk_drm_drivers));
1310 }
1311
mtk_drm_exit(void)1312 static void __exit mtk_drm_exit(void)
1313 {
1314 platform_unregister_drivers(mtk_drm_drivers,
1315 ARRAY_SIZE(mtk_drm_drivers));
1316 }
1317
1318 module_init(mtk_drm_init);
1319 module_exit(mtk_drm_exit);
1320
1321 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
1322 MODULE_DESCRIPTION("Mediatek SoC DRM driver");
1323 MODULE_LICENSE("GPL v2");
1324