1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/clock/nxp,imx95-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13#include "imx95-clock.h" 14#include "imx95-pinfunc.h" 15#include "imx95-power.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 idle-states { 27 entry-method = "psci"; 28 29 cpu_pd_wait: cpu-pd-wait { 30 compatible = "arm,idle-state"; 31 arm,psci-suspend-param = <0x0010033>; 32 local-timer-stop; 33 entry-latency-us = <10000>; 34 exit-latency-us = <7000>; 35 min-residency-us = <27000>; 36 wakeup-latency-us = <15000>; 37 }; 38 }; 39 40 A55_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x0>; 44 enable-method = "psci"; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&cpu_pd_wait>; 47 power-domains = <&scmi_perf IMX95_PERF_A55>; 48 power-domain-names = "perf"; 49 i-cache-size = <32768>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <128>; 52 d-cache-size = <32768>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 next-level-cache = <&l2_cache_l0>; 56 }; 57 58 A55_1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x100>; 62 enable-method = "psci"; 63 #cooling-cells = <2>; 64 cpu-idle-states = <&cpu_pd_wait>; 65 power-domains = <&scmi_perf IMX95_PERF_A55>; 66 power-domain-names = "perf"; 67 i-cache-size = <32768>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <128>; 70 d-cache-size = <32768>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&l2_cache_l1>; 74 }; 75 76 A55_2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x200>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 power-domains = <&scmi_perf IMX95_PERF_A55>; 84 power-domain-names = "perf"; 85 i-cache-size = <32768>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <128>; 88 d-cache-size = <32768>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&l2_cache_l2>; 92 }; 93 94 A55_3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x300>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; 100 cpu-idle-states = <&cpu_pd_wait>; 101 power-domains = <&scmi_perf IMX95_PERF_A55>; 102 power-domain-names = "perf"; 103 i-cache-size = <32768>; 104 i-cache-line-size = <64>; 105 i-cache-sets = <128>; 106 d-cache-size = <32768>; 107 d-cache-line-size = <64>; 108 d-cache-sets = <128>; 109 next-level-cache = <&l2_cache_l3>; 110 }; 111 112 A55_4: cpu@400 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x400>; 116 power-domains = <&scmi_perf IMX95_PERF_A55>; 117 power-domain-names = "perf"; 118 enable-method = "psci"; 119 #cooling-cells = <2>; 120 cpu-idle-states = <&cpu_pd_wait>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <128>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_cache_l4>; 128 }; 129 130 A55_5: cpu@500 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x500>; 134 power-domains = <&scmi_perf IMX95_PERF_A55>; 135 power-domain-names = "perf"; 136 enable-method = "psci"; 137 #cooling-cells = <2>; 138 cpu-idle-states = <&cpu_pd_wait>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l5>; 146 }; 147 148 l2_cache_l0: l2-cache-l0 { 149 compatible = "cache"; 150 cache-size = <65536>; 151 cache-line-size = <64>; 152 cache-sets = <256>; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&l3_cache>; 156 }; 157 158 l2_cache_l1: l2-cache-l1 { 159 compatible = "cache"; 160 cache-size = <65536>; 161 cache-line-size = <64>; 162 cache-sets = <256>; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&l3_cache>; 166 }; 167 168 l2_cache_l2: l2-cache-l2 { 169 compatible = "cache"; 170 cache-size = <65536>; 171 cache-line-size = <64>; 172 cache-sets = <256>; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_cache>; 176 }; 177 178 l2_cache_l3: l2-cache-l3 { 179 compatible = "cache"; 180 cache-size = <65536>; 181 cache-line-size = <64>; 182 cache-sets = <256>; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_cache>; 186 }; 187 188 l2_cache_l4: l2-cache-l4 { 189 compatible = "cache"; 190 cache-size = <65536>; 191 cache-line-size = <64>; 192 cache-sets = <256>; 193 cache-level = <2>; 194 cache-unified; 195 next-level-cache = <&l3_cache>; 196 }; 197 198 l2_cache_l5: l2-cache-l5 { 199 compatible = "cache"; 200 cache-size = <65536>; 201 cache-line-size = <64>; 202 cache-sets = <256>; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_cache>; 206 }; 207 208 l3_cache: l3-cache { 209 compatible = "cache"; 210 cache-size = <524288>; 211 cache-line-size = <64>; 212 cache-sets = <512>; 213 cache-level = <3>; 214 cache-unified; 215 }; 216 217 cpu-map { 218 cluster0 { 219 core0 { 220 cpu = <&A55_0>; 221 }; 222 223 core1 { 224 cpu = <&A55_1>; 225 }; 226 227 core2 { 228 cpu = <&A55_2>; 229 }; 230 231 core3 { 232 cpu = <&A55_3>; 233 }; 234 235 core4 { 236 cpu = <&A55_4>; 237 }; 238 239 core5 { 240 cpu = <&A55_5>; 241 }; 242 }; 243 }; 244 }; 245 246 dummy: clock-dummy { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency = <0>; 250 clock-output-names = "dummy"; 251 }; 252 253 clk_ext1: clock-ext1 { 254 compatible = "fixed-clock"; 255 #clock-cells = <0>; 256 clock-frequency = <133000000>; 257 clock-output-names = "clk_ext1"; 258 }; 259 260 sai1_mclk: clock-sai-mclk1 { 261 compatible = "fixed-clock"; 262 #clock-cells = <0>; 263 clock-frequency= <0>; 264 clock-output-names = "sai1_mclk"; 265 }; 266 267 sai2_mclk: clock-sai-mclk2 { 268 compatible = "fixed-clock"; 269 #clock-cells = <0>; 270 clock-frequency= <0>; 271 clock-output-names = "sai2_mclk"; 272 }; 273 274 sai3_mclk: clock-sai-mclk3 { 275 compatible = "fixed-clock"; 276 #clock-cells = <0>; 277 clock-frequency= <0>; 278 clock-output-names = "sai3_mclk"; 279 }; 280 281 sai4_mclk: clock-sai-mclk4 { 282 compatible = "fixed-clock"; 283 #clock-cells = <0>; 284 clock-frequency= <0>; 285 clock-output-names = "sai4_mclk"; 286 }; 287 288 sai5_mclk: clock-sai-mclk5 { 289 compatible = "fixed-clock"; 290 #clock-cells = <0>; 291 clock-frequency= <0>; 292 clock-output-names = "sai5_mclk"; 293 }; 294 295 clk_sys100m: clock-sys100m { 296 compatible = "fixed-clock"; 297 #clock-cells = <0>; 298 clock-frequency = <100000000>; 299 clock-output-names = "clk_sys100m"; 300 }; 301 302 osc_24m: clock-24m { 303 compatible = "fixed-clock"; 304 #clock-cells = <0>; 305 clock-frequency = <24000000>; 306 clock-output-names = "osc_24m"; 307 }; 308 309 sram1: sram@204c0000 { 310 compatible = "mmio-sram"; 311 reg = <0x0 0x204c0000 0x0 0x18000>; 312 ranges = <0x0 0x0 0x204c0000 0x18000>; 313 #address-cells = <1>; 314 #size-cells = <1>; 315 }; 316 317 firmware { 318 scmi { 319 compatible = "arm,scmi"; 320 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 321 shmem = <&scmi_buf0>, <&scmi_buf1>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 arm,max-rx-timeout-ms = <5000>; 325 326 scmi_devpd: protocol@11 { 327 reg = <0x11>; 328 #power-domain-cells = <1>; 329 }; 330 331 scmi_sys_power: protocol@12 { 332 reg = <0x12>; 333 }; 334 335 scmi_perf: protocol@13 { 336 reg = <0x13>; 337 #power-domain-cells = <1>; 338 }; 339 340 scmi_clk: protocol@14 { 341 reg = <0x14>; 342 #clock-cells = <1>; 343 }; 344 345 scmi_sensor: protocol@15 { 346 reg = <0x15>; 347 #thermal-sensor-cells = <1>; 348 }; 349 350 scmi_iomuxc: protocol@19 { 351 reg = <0x19>; 352 }; 353 354 scmi_bbm: protocol@81 { 355 reg = <0x81>; 356 }; 357 358 scmi_misc: protocol@84 { 359 reg = <0x84>; 360 }; 361 }; 362 }; 363 364 pmu { 365 compatible = "arm,cortex-a55-pmu"; 366 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 367 }; 368 369 thermal_zones: thermal-zones { 370 a55-thermal { 371 polling-delay-passive = <250>; 372 polling-delay = <2000>; 373 thermal-sensors = <&scmi_sensor 1>; 374 375 trips { 376 cpu_alert0: trip0 { 377 temperature = <105000>; 378 hysteresis = <2000>; 379 type = "passive"; 380 }; 381 382 cpu_crit0: trip1 { 383 temperature = <125000>; 384 hysteresis = <2000>; 385 type = "critical"; 386 }; 387 }; 388 389 cooling-maps { 390 map0 { 391 trip = <&cpu_alert0>; 392 cooling-device = 393 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 394 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 395 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 396 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 397 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 398 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 399 }; 400 }; 401 }; 402 403 ana-thermal { 404 polling-delay-passive = <250>; 405 polling-delay = <2000>; 406 thermal-sensors = <&scmi_sensor 0>; 407 trips { 408 ana_alert: trip0 { 409 temperature = <105000>; 410 hysteresis = <2000>; 411 type = "passive"; 412 }; 413 414 ana_crit0: trip1 { 415 temperature = <125000>; 416 hysteresis = <2000>; 417 type = "critical"; 418 }; 419 }; 420 421 cooling-maps { 422 map0 { 423 trip = <&ana_alert>; 424 cooling-device = 425 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 426 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 427 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 428 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 429 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 430 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 431 }; 432 }; 433 }; 434 }; 435 436 psci { 437 compatible = "arm,psci-1.0"; 438 method = "smc"; 439 }; 440 441 timer { 442 compatible = "arm,armv8-timer"; 443 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 444 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 445 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 446 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 447 clock-frequency = <24000000>; 448 arm,no-tick-in-suspend; 449 interrupt-parent = <&gic>; 450 }; 451 452 gic: interrupt-controller@48000000 { 453 compatible = "arm,gic-v3"; 454 reg = <0 0x48000000 0 0x10000>, 455 <0 0x48060000 0 0xc0000>; 456 #address-cells = <2>; 457 #size-cells = <2>; 458 #interrupt-cells = <3>; 459 interrupt-controller; 460 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-parent = <&gic>; 462 dma-noncoherent; 463 ranges; 464 465 its: msi-controller@48040000 { 466 compatible = "arm,gic-v3-its"; 467 reg = <0 0x48040000 0 0x20000>; 468 msi-controller; 469 #msi-cells = <1>; 470 dma-noncoherent; 471 }; 472 }; 473 474 usbphynop: usbphynop { 475 compatible = "usb-nop-xceiv"; 476 clocks = <&scmi_clk IMX95_CLK_HSIO>; 477 clock-names = "main_clk"; 478 #phy-cells = <0>; 479 }; 480 481 soc { 482 compatible = "simple-bus"; 483 #address-cells = <2>; 484 #size-cells = <2>; 485 ranges; 486 487 aips2: bus@42000000 { 488 compatible = "fsl,aips-bus", "simple-bus"; 489 reg = <0x0 0x42000000 0x0 0x800000>; 490 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 491 <0x28000000 0x0 0x28000000 0x10000000>; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 495 edma2: dma-controller@42000000 { 496 compatible = "fsl,imx95-edma5"; 497 reg = <0x42000000 0x210000>; 498 #dma-cells = <3>; 499 dma-channels = <64>; 500 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 565 clock-names = "dma"; 566 }; 567 568 edma3: dma-controller@42210000 { 569 compatible = "fsl,imx95-edma5"; 570 reg = <0x42210000 0x210000>; 571 #dma-cells = <3>; 572 dma-channels = <64>; 573 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 638 clock-names = "dma"; 639 }; 640 641 mu7: mailbox@42430000 { 642 compatible = "fsl,imx95-mu"; 643 reg = <0x42430000 0x10000>; 644 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 646 #mbox-cells = <2>; 647 status = "disabled"; 648 }; 649 650 wdog3: watchdog@42490000 { 651 compatible = "fsl,imx93-wdt"; 652 reg = <0x42490000 0x10000>; 653 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 655 timeout-sec = <40>; 656 status = "disabled"; 657 }; 658 659 tpm3: pwm@424e0000 { 660 compatible = "fsl,imx7ulp-pwm"; 661 reg = <0x424e0000 0x1000>; 662 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 663 #pwm-cells = <3>; 664 status = "disabled"; 665 }; 666 667 tpm4: pwm@424f0000 { 668 compatible = "fsl,imx7ulp-pwm"; 669 reg = <0x424f0000 0x1000>; 670 clocks = <&scmi_clk IMX95_CLK_TPM4>; 671 #pwm-cells = <3>; 672 status = "disabled"; 673 }; 674 675 tpm5: pwm@42500000 { 676 compatible = "fsl,imx7ulp-pwm"; 677 reg = <0x42500000 0x1000>; 678 clocks = <&scmi_clk IMX95_CLK_TPM5>; 679 #pwm-cells = <3>; 680 status = "disabled"; 681 }; 682 683 tpm6: pwm@42510000 { 684 compatible = "fsl,imx7ulp-pwm"; 685 reg = <0x42510000 0x1000>; 686 clocks = <&scmi_clk IMX95_CLK_TPM6>; 687 #pwm-cells = <3>; 688 status = "disabled"; 689 }; 690 691 i3c2: i3c@42520000 { 692 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 693 reg = <0x42520000 0x10000>; 694 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 695 #address-cells = <3>; 696 #size-cells = <0>; 697 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 698 <&scmi_clk IMX95_CLK_I3C2SLOW>; 699 clock-names = "pclk", "fast_clk"; 700 status = "disabled"; 701 }; 702 703 lpi2c3: i2c@42530000 { 704 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 705 reg = <0x42530000 0x10000>; 706 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 708 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 709 clock-names = "per", "ipg"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 713 dma-names = "tx", "rx"; 714 status = "disabled"; 715 }; 716 717 lpi2c4: i2c@42540000 { 718 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 719 reg = <0x42540000 0x10000>; 720 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 722 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 723 clock-names = "per", "ipg"; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 727 dma-names = "tx", "rx"; 728 status = "disabled"; 729 }; 730 731 lpspi3: spi@42550000 { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 735 reg = <0x42550000 0x10000>; 736 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 738 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 739 clock-names = "per", "ipg"; 740 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 741 dma-names = "tx", "rx"; 742 status = "disabled"; 743 }; 744 745 lpspi4: spi@42560000 { 746 #address-cells = <1>; 747 #size-cells = <0>; 748 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 749 reg = <0x42560000 0x10000>; 750 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 752 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 753 clock-names = "per", "ipg"; 754 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 755 dma-names = "tx", "rx"; 756 status = "disabled"; 757 }; 758 759 lpuart3: serial@42570000 { 760 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 761 "fsl,imx7ulp-lpuart"; 762 reg = <0x42570000 0x1000>; 763 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 765 clock-names = "ipg"; 766 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 767 dma-names = "rx", "tx"; 768 status = "disabled"; 769 }; 770 771 lpuart4: serial@42580000 { 772 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 773 "fsl,imx7ulp-lpuart"; 774 reg = <0x42580000 0x1000>; 775 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 776 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 777 clock-names = "ipg"; 778 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 779 dma-names = "rx", "tx"; 780 status = "disabled"; 781 }; 782 783 lpuart5: serial@42590000 { 784 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 785 "fsl,imx7ulp-lpuart"; 786 reg = <0x42590000 0x1000>; 787 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 789 clock-names = "ipg"; 790 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 791 dma-names = "rx", "tx"; 792 status = "disabled"; 793 }; 794 795 lpuart6: serial@425a0000 { 796 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 797 "fsl,imx7ulp-lpuart"; 798 reg = <0x425a0000 0x1000>; 799 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 801 clock-names = "ipg"; 802 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 803 dma-names = "rx", "tx"; 804 status = "disabled"; 805 }; 806 807 flexcan2: can@425b0000 { 808 compatible = "fsl,imx95-flexcan"; 809 reg = <0x425b0000 0x10000>; 810 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 812 <&scmi_clk IMX95_CLK_CAN2>; 813 clock-names = "ipg", "per"; 814 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 815 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 816 assigned-clock-rates = <40000000>; 817 fsl,clk-source = /bits/ 8 <0>; 818 status = "disabled"; 819 }; 820 821 flexcan3: can@42600000 { 822 compatible = "fsl,imx95-flexcan"; 823 reg = <0x42600000 0x10000>; 824 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 826 <&scmi_clk IMX95_CLK_CAN3>; 827 clock-names = "ipg", "per"; 828 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 829 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 830 assigned-clock-rates = <40000000>; 831 fsl,clk-source = /bits/ 8 <0>; 832 status = "disabled"; 833 }; 834 835 flexspi1: spi@425e0000 { 836 compatible = "nxp,imx8mm-fspi"; 837 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 838 reg-names = "fspi_base", "fspi_mmap"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 842 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 843 <&scmi_clk IMX95_CLK_FLEXSPI1>; 844 clock-names = "fspi_en", "fspi"; 845 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 846 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 847 assigned-clock-rates = <200000000>; 848 status = "disabled"; 849 }; 850 851 sai3: sai@42650000 { 852 compatible = "fsl,imx95-sai"; 853 reg = <0x42650000 0x10000>; 854 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 856 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 857 <&dummy>; 858 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 859 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 860 dma-names = "rx", "tx"; 861 status = "disabled"; 862 }; 863 864 sai4: sai@42660000 { 865 compatible = "fsl,imx95-sai"; 866 reg = <0x42660000 0x10000>; 867 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 869 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 870 <&dummy>; 871 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 872 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 873 dma-names = "rx", "tx"; 874 status = "disabled"; 875 }; 876 877 sai5: sai@42670000 { 878 compatible = "fsl,imx95-sai"; 879 reg = <0x42670000 0x10000>; 880 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 882 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 883 <&dummy>; 884 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 885 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 886 dma-names = "rx", "tx"; 887 status = "disabled"; 888 }; 889 890 xcvr: xcvr@42680000 { 891 compatible = "fsl,imx95-xcvr"; 892 reg = <0x42680000 0x800>, <0x42680800 0x400>, 893 <0x42680c00 0x080>, <0x42680e00 0x080>; 894 reg-names = "ram", "regs", "rxfifo", "txfifo"; 895 interrupts = /* XCVR IRQ 0 */ 896 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 897 /* XCVR IRQ 1 */ 898 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 900 <&scmi_clk IMX95_CLK_SPDIF>, 901 <&dummy>, 902 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 903 clock-names = "ipg", "phy", "spba", "pll_ipg"; 904 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 905 dma-names = "rx", "tx"; 906 status = "disabled"; 907 }; 908 909 lpuart7: serial@42690000 { 910 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 911 "fsl,imx7ulp-lpuart"; 912 reg = <0x42690000 0x1000>; 913 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 915 clock-names = "ipg"; 916 dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>; 917 dma-names = "rx", "tx"; 918 status = "disabled"; 919 }; 920 921 lpuart8: serial@426a0000 { 922 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 923 "fsl,imx7ulp-lpuart"; 924 reg = <0x426a0000 0x1000>; 925 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 927 clock-names = "ipg"; 928 dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>; 929 dma-names = "rx", "tx"; 930 status = "disabled"; 931 }; 932 933 lpi2c5: i2c@426b0000 { 934 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 935 reg = <0x426b0000 0x10000>; 936 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 938 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 939 clock-names = "per", "ipg"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 943 dma-names = "tx", "rx"; 944 status = "disabled"; 945 }; 946 947 lpi2c6: i2c@426c0000 { 948 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 949 reg = <0x426c0000 0x10000>; 950 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 952 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 953 clock-names = "per", "ipg"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 957 dma-names = "tx", "rx"; 958 status = "disabled"; 959 }; 960 961 lpi2c7: i2c@426d0000 { 962 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 963 reg = <0x426d0000 0x10000>; 964 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 966 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 967 clock-names = "per", "ipg"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 971 dma-names = "tx", "rx"; 972 status = "disabled"; 973 }; 974 975 lpi2c8: i2c@426e0000 { 976 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 977 reg = <0x426e0000 0x10000>; 978 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 980 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 981 clock-names = "per", "ipg"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 985 dma-names = "tx", "rx"; 986 status = "disabled"; 987 }; 988 989 lpspi5: spi@426f0000 { 990 #address-cells = <1>; 991 #size-cells = <0>; 992 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 993 reg = <0x426f0000 0x10000>; 994 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 996 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 997 clock-names = "per", "ipg"; 998 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 999 dma-names = "tx", "rx"; 1000 status = "disabled"; 1001 }; 1002 1003 lpspi6: spi@42700000 { 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1007 reg = <0x42700000 0x10000>; 1008 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 1010 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1011 clock-names = "per", "ipg"; 1012 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1013 dma-names = "tx", "rx"; 1014 status = "disabled"; 1015 }; 1016 1017 lpspi7: spi@42710000 { 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1021 reg = <0x42710000 0x10000>; 1022 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 1024 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1025 clock-names = "per", "ipg"; 1026 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1027 dma-names = "tx", "rx"; 1028 status = "disabled"; 1029 }; 1030 1031 lpspi8: spi@42720000 { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1035 reg = <0x42720000 0x10000>; 1036 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 1038 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1039 clock-names = "per", "ipg"; 1040 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1041 dma-names = "tx", "rx"; 1042 status = "disabled"; 1043 }; 1044 1045 mu8: mailbox@42730000 { 1046 compatible = "fsl,imx95-mu"; 1047 reg = <0x42730000 0x10000>; 1048 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1050 #mbox-cells = <2>; 1051 status = "disabled"; 1052 }; 1053 1054 flexcan4: can@427c0000 { 1055 compatible = "fsl,imx95-flexcan"; 1056 reg = <0x427c0000 0x10000>; 1057 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1058 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1059 <&scmi_clk IMX95_CLK_CAN4>; 1060 clock-names = "ipg", "per"; 1061 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 1062 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1063 assigned-clock-rates = <40000000>; 1064 fsl,clk-source = /bits/ 8 <0>; 1065 status = "disabled"; 1066 }; 1067 1068 flexcan5: can@427d0000 { 1069 compatible = "fsl,imx95-flexcan"; 1070 reg = <0x427d0000 0x10000>; 1071 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1073 <&scmi_clk IMX95_CLK_CAN5>; 1074 clock-names = "ipg", "per"; 1075 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 1076 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1077 assigned-clock-rates = <40000000>; 1078 fsl,clk-source = /bits/ 8 <0>; 1079 status = "disabled"; 1080 }; 1081 }; 1082 1083 aips3: bus@42800000 { 1084 compatible = "fsl,aips-bus", "simple-bus"; 1085 reg = <0 0x42800000 0 0x800000>; 1086 #address-cells = <1>; 1087 #size-cells = <1>; 1088 ranges = <0x42800000 0x0 0x42800000 0x800000>; 1089 1090 usdhc1: mmc@42850000 { 1091 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1092 reg = <0x42850000 0x10000>; 1093 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1095 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1096 <&scmi_clk IMX95_CLK_USDHC1>; 1097 clock-names = "ipg", "ahb", "per"; 1098 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1099 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1100 assigned-clock-rates = <400000000>; 1101 bus-width = <8>; 1102 fsl,tuning-start-tap = <1>; 1103 fsl,tuning-step= <2>; 1104 status = "disabled"; 1105 }; 1106 1107 usdhc2: mmc@42860000 { 1108 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1109 reg = <0x42860000 0x10000>; 1110 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1112 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1113 <&scmi_clk IMX95_CLK_USDHC2>; 1114 clock-names = "ipg", "ahb", "per"; 1115 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1116 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1117 assigned-clock-rates = <400000000>; 1118 bus-width = <4>; 1119 fsl,tuning-start-tap = <1>; 1120 fsl,tuning-step= <2>; 1121 status = "disabled"; 1122 }; 1123 1124 usdhc3: mmc@428b0000 { 1125 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1126 reg = <0x428b0000 0x10000>; 1127 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1129 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1130 <&scmi_clk IMX95_CLK_USDHC3>; 1131 clock-names = "ipg", "ahb", "per"; 1132 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1133 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1134 assigned-clock-rates = <400000000>; 1135 bus-width = <4>; 1136 fsl,tuning-start-tap = <1>; 1137 fsl,tuning-step= <2>; 1138 status = "disabled"; 1139 }; 1140 }; 1141 1142 gpio2: gpio@43810000 { 1143 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1144 reg = <0x0 0x43810000 0x0 0x1000>; 1145 gpio-controller; 1146 #gpio-cells = <2>; 1147 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1149 interrupt-controller; 1150 #interrupt-cells = <2>; 1151 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1152 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1153 clock-names = "gpio", "port"; 1154 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1155 ngpios = <32>; 1156 }; 1157 1158 gpio3: gpio@43820000 { 1159 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1160 reg = <0x0 0x43820000 0x0 0x1000>; 1161 gpio-controller; 1162 #gpio-cells = <2>; 1163 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-controller; 1166 #interrupt-cells = <2>; 1167 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1168 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1169 clock-names = "gpio", "port"; 1170 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1171 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1172 ngpios = <32>; 1173 }; 1174 1175 gpio4: gpio@43840000 { 1176 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1177 reg = <0x0 0x43840000 0x0 0x1000>; 1178 gpio-controller; 1179 #gpio-cells = <2>; 1180 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1182 interrupt-controller; 1183 #interrupt-cells = <2>; 1184 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1185 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1186 clock-names = "gpio", "port"; 1187 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1188 ngpios = <30>; 1189 }; 1190 1191 gpio5: gpio@43850000 { 1192 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1193 reg = <0x0 0x43850000 0x0 0x1000>; 1194 gpio-controller; 1195 #gpio-cells = <2>; 1196 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupt-controller; 1199 #interrupt-cells = <2>; 1200 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1201 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1202 clock-names = "gpio", "port"; 1203 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1204 ngpios = <18>; 1205 }; 1206 1207 aips1: bus@44000000 { 1208 compatible = "fsl,aips-bus", "simple-bus"; 1209 reg = <0x0 0x44000000 0x0 0x800000>; 1210 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1211 #address-cells = <1>; 1212 #size-cells = <1>; 1213 1214 edma1: dma-controller@44000000 { 1215 compatible = "fsl,imx93-edma3"; 1216 reg = <0x44000000 0x200000>; 1217 #dma-cells = <3>; 1218 dma-channels = <31>; 1219 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1250 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1251 clock-names = "dma"; 1252 }; 1253 1254 mu1: mailbox@44220000 { 1255 compatible = "fsl,imx95-mu"; 1256 reg = <0x44220000 0x10000>; 1257 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1259 #mbox-cells = <2>; 1260 status = "disabled"; 1261 }; 1262 1263 tpm1: pwm@44310000 { 1264 compatible = "fsl,imx7ulp-pwm"; 1265 reg = <0x44310000 0x1000>; 1266 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1267 #pwm-cells = <3>; 1268 status = "disabled"; 1269 }; 1270 1271 tpm2: pwm@44320000 { 1272 compatible = "fsl,imx7ulp-pwm"; 1273 reg = <0x44320000 0x1000>; 1274 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1275 #pwm-cells = <3>; 1276 status = "disabled"; 1277 }; 1278 1279 i3c1: i3c@44330000 { 1280 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 1281 reg = <0x44330000 0x10000>; 1282 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1283 #address-cells = <3>; 1284 #size-cells = <0>; 1285 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1286 <&scmi_clk IMX95_CLK_I3C1SLOW>; 1287 clock-names = "pclk", "fast_clk"; 1288 status = "disabled"; 1289 }; 1290 1291 lpi2c1: i2c@44340000 { 1292 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1293 reg = <0x44340000 0x10000>; 1294 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1296 <&scmi_clk IMX95_CLK_BUSAON>; 1297 clock-names = "per", "ipg"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1301 dma-names = "tx", "rx"; 1302 status = "disabled"; 1303 }; 1304 1305 lpi2c2: i2c@44350000 { 1306 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1307 reg = <0x44350000 0x10000>; 1308 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1310 <&scmi_clk IMX95_CLK_BUSAON>; 1311 clock-names = "per", "ipg"; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1315 dma-names = "tx", "rx"; 1316 status = "disabled"; 1317 }; 1318 1319 lpspi1: spi@44360000 { 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1323 reg = <0x44360000 0x10000>; 1324 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1326 <&scmi_clk IMX95_CLK_BUSAON>; 1327 clock-names = "per", "ipg"; 1328 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1329 dma-names = "tx", "rx"; 1330 status = "disabled"; 1331 }; 1332 1333 lpspi2: spi@44370000 { 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1337 reg = <0x44370000 0x10000>; 1338 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1339 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1340 <&scmi_clk IMX95_CLK_BUSAON>; 1341 clock-names = "per", "ipg"; 1342 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1343 dma-names = "tx", "rx"; 1344 status = "disabled"; 1345 }; 1346 1347 lpuart1: serial@44380000 { 1348 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1349 "fsl,imx7ulp-lpuart"; 1350 reg = <0x44380000 0x1000>; 1351 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1353 clock-names = "ipg"; 1354 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1355 dma-names = "rx", "tx"; 1356 status = "disabled"; 1357 }; 1358 1359 lpuart2: serial@44390000 { 1360 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1361 "fsl,imx7ulp-lpuart"; 1362 reg = <0x44390000 0x1000>; 1363 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1365 clock-names = "ipg"; 1366 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1367 dma-names = "rx", "tx"; 1368 status = "disabled"; 1369 }; 1370 1371 flexcan1: can@443a0000 { 1372 compatible = "fsl,imx95-flexcan"; 1373 reg = <0x443a0000 0x10000>; 1374 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1375 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1376 <&scmi_clk IMX95_CLK_CAN1>; 1377 clock-names = "ipg", "per"; 1378 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1379 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1380 assigned-clock-rates = <40000000>; 1381 fsl,clk-source = /bits/ 8 <0>; 1382 status = "disabled"; 1383 }; 1384 1385 sai1: sai@443b0000 { 1386 compatible = "fsl,imx95-sai"; 1387 reg = <0x443b0000 0x10000>; 1388 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1389 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1390 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1391 <&dummy>; 1392 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1393 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1394 dma-names = "rx", "tx"; 1395 status = "disabled"; 1396 }; 1397 1398 micfil: micfil@44520000 { 1399 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1400 reg = <0x44520000 0x10000>; 1401 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1405 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1406 <&scmi_clk IMX95_CLK_PDM>, 1407 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1408 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1409 <&dummy>; 1410 clock-names = "ipg_clk", "ipg_clk_app", 1411 "pll8k", "pll11k", "clkext3"; 1412 dmas = <&edma1 6 0 5>; 1413 dma-names = "rx"; 1414 status = "disabled"; 1415 }; 1416 1417 adc1: adc@44530000 { 1418 compatible = "nxp,imx93-adc"; 1419 reg = <0x44530000 0x10000>; 1420 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&scmi_clk IMX95_CLK_ADC>; 1424 clock-names = "ipg"; 1425 #io-channel-cells = <1>; 1426 status = "disabled"; 1427 }; 1428 1429 mu2: mailbox@445b0000 { 1430 compatible = "fsl,imx95-mu"; 1431 reg = <0x445b0000 0x1000>; 1432 ranges; 1433 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1434 #address-cells = <1>; 1435 #size-cells = <1>; 1436 #mbox-cells = <2>; 1437 1438 sram0: sram@445b1000 { 1439 compatible = "mmio-sram"; 1440 reg = <0x445b1000 0x400>; 1441 ranges = <0x0 0x445b1000 0x400>; 1442 #address-cells = <1>; 1443 #size-cells = <1>; 1444 1445 scmi_buf0: scmi-sram-section@0 { 1446 compatible = "arm,scmi-shmem"; 1447 reg = <0x0 0x80>; 1448 }; 1449 1450 scmi_buf1: scmi-sram-section@80 { 1451 compatible = "arm,scmi-shmem"; 1452 reg = <0x80 0x80>; 1453 }; 1454 }; 1455 1456 }; 1457 1458 mu3: mailbox@445d0000 { 1459 compatible = "fsl,imx95-mu"; 1460 reg = <0x445d0000 0x10000>; 1461 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1462 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1463 #mbox-cells = <2>; 1464 status = "disabled"; 1465 }; 1466 1467 mu4: mailbox@445f0000 { 1468 compatible = "fsl,imx95-mu"; 1469 reg = <0x445f0000 0x10000>; 1470 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1472 #mbox-cells = <2>; 1473 status = "disabled"; 1474 }; 1475 1476 mu6: mailbox@44630000 { 1477 compatible = "fsl,imx95-mu"; 1478 reg = <0x44630000 0x10000>; 1479 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1480 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1481 #mbox-cells = <2>; 1482 status = "disabled"; 1483 }; 1484 }; 1485 1486 mailbox@47320000 { 1487 compatible = "fsl,imx95-mu-v2x"; 1488 reg = <0x0 0x47320000 0x0 0x10000>; 1489 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1490 #mbox-cells = <2>; 1491 }; 1492 1493 mailbox@47350000 { 1494 compatible = "fsl,imx95-mu-v2x"; 1495 reg = <0x0 0x47350000 0x0 0x10000>; 1496 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1497 #mbox-cells = <2>; 1498 }; 1499 1500 /* GPIO1 is under exclusive control of System Manager */ 1501 gpio1: gpio@47400000 { 1502 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1503 reg = <0x0 0x47400000 0x0 0x1000>; 1504 gpio-controller; 1505 #gpio-cells = <2>; 1506 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1508 interrupt-controller; 1509 #interrupt-cells = <2>; 1510 clocks = <&scmi_clk IMX95_CLK_M33>, 1511 <&scmi_clk IMX95_CLK_M33>; 1512 clock-names = "gpio", "port"; 1513 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1514 ngpios = <16>; 1515 status = "disabled"; 1516 }; 1517 1518 elemu0: mailbox@47520000 { 1519 compatible = "fsl,imx95-mu-ele"; 1520 reg = <0x0 0x47520000 0x0 0x10000>; 1521 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1522 #mbox-cells = <2>; 1523 status = "disabled"; 1524 }; 1525 1526 elemu1: mailbox@47530000 { 1527 compatible = "fsl,imx95-mu-ele"; 1528 reg = <0x0 0x47530000 0x0 0x10000>; 1529 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1530 #mbox-cells = <2>; 1531 status = "disabled"; 1532 }; 1533 1534 elemu2: mailbox@47540000 { 1535 compatible = "fsl,imx95-mu-ele"; 1536 reg = <0x0 0x47540000 0x0 0x10000>; 1537 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1538 #mbox-cells = <2>; 1539 status = "disabled"; 1540 }; 1541 1542 elemu3: mailbox@47550000 { 1543 compatible = "fsl,imx95-mu-ele"; 1544 reg = <0x0 0x47550000 0x0 0x10000>; 1545 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1546 #mbox-cells = <2>; 1547 }; 1548 1549 elemu4: mailbox@47560000 { 1550 compatible = "fsl,imx95-mu-ele"; 1551 reg = <0x0 0x47560000 0x0 0x10000>; 1552 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1553 #mbox-cells = <2>; 1554 status = "disabled"; 1555 }; 1556 1557 elemu5: mailbox@47570000 { 1558 compatible = "fsl,imx95-mu-ele"; 1559 reg = <0x0 0x47570000 0x0 0x10000>; 1560 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1561 #mbox-cells = <2>; 1562 status = "disabled"; 1563 }; 1564 1565 aips4: bus@49000000 { 1566 compatible = "fsl,aips-bus", "simple-bus"; 1567 reg = <0x0 0x49000000 0x0 0x800000>; 1568 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1569 #address-cells = <1>; 1570 #size-cells = <1>; 1571 1572 smmu: iommu@490d0000 { 1573 compatible = "arm,smmu-v3"; 1574 reg = <0x490d0000 0x100000>; 1575 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1576 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1577 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1578 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1579 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1580 #iommu-cells = <1>; 1581 status = "disabled"; 1582 }; 1583 }; 1584 1585 usb3: usb@4c010010 { 1586 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; 1587 reg = <0x0 0x4c010010 0x0 0x04>, 1588 <0x0 0x4c1f0000 0x0 0x20>; 1589 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1590 <&scmi_clk IMX95_CLK_32K>; 1591 clock-names = "hsio", "suspend"; 1592 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1593 #address-cells = <2>; 1594 #size-cells = <2>; 1595 ranges; 1596 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1597 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 1598 status = "disabled"; 1599 1600 usb3_dwc3: usb@4c100000 { 1601 compatible = "snps,dwc3"; 1602 reg = <0x0 0x4c100000 0x0 0x10000>; 1603 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1604 <&scmi_clk IMX95_CLK_24M>, 1605 <&scmi_clk IMX95_CLK_32K>; 1606 clock-names = "bus_early", "ref", "suspend"; 1607 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1608 phys = <&usb3_phy>, <&usb3_phy>; 1609 phy-names = "usb2-phy", "usb3-phy"; 1610 snps,gfladj-refclk-lpm-sel-quirk; 1611 snps,parkmode-disable-ss-quirk; 1612 iommus = <&smmu 0xe>; 1613 }; 1614 }; 1615 1616 hsio_blk_ctl: syscon@4c0100c0 { 1617 compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; 1618 reg = <0x0 0x4c0100c0 0x0 0x1>; 1619 #clock-cells = <1>; 1620 clocks = <&clk_sys100m>; 1621 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1622 }; 1623 1624 usb3_phy: phy@4c1f0040 { 1625 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; 1626 reg = <0x0 0x4c1f0040 0x0 0x40>, 1627 <0x0 0x4c1fc000 0x0 0x100>; 1628 clocks = <&scmi_clk IMX95_CLK_HSIO>; 1629 clock-names = "phy"; 1630 #phy-cells = <0>; 1631 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1632 status = "disabled"; 1633 }; 1634 1635 usb2: usb@4c200000 { 1636 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1637 reg = <0x0 0x4c200000 0x0 0x200>; 1638 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1640 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1641 <&scmi_clk IMX95_CLK_32K>; 1642 clock-names = "usb_ctrl_root", "usb_wakeup"; 1643 iommus = <&smmu 0xf>; 1644 phys = <&usbphynop>; 1645 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1646 fsl,usbmisc = <&usbmisc 0>; 1647 status = "disabled"; 1648 }; 1649 1650 usbmisc: usbmisc@4c200200 { 1651 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", 1652 "fsl,imx6q-usbmisc"; 1653 reg = <0x0 0x4c200200 0x0 0x200>, 1654 <0x0 0x4c010014 0x0 0x04>; 1655 #index-cells = <1>; 1656 }; 1657 1658 pcie0: pcie@4c300000 { 1659 compatible = "fsl,imx95-pcie"; 1660 reg = <0 0x4c300000 0 0x10000>, 1661 <0 0x60100000 0 0xfe00000>, 1662 <0 0x4c360000 0 0x10000>, 1663 <0 0x4c340000 0 0x4000>; 1664 reg-names = "dbi", "config", "atu", "app"; 1665 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1666 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1667 #address-cells = <3>; 1668 #size-cells = <2>; 1669 device_type = "pci"; 1670 linux,pci-domain = <0>; 1671 bus-range = <0x00 0xff>; 1672 num-lanes = <1>; 1673 num-viewport = <8>; 1674 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1675 interrupt-names = "msi"; 1676 #interrupt-cells = <1>; 1677 interrupt-map-mask = <0 0 0 0x7>; 1678 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1679 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1680 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1681 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1682 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1683 <&scmi_clk IMX95_CLK_HSIOPLL>, 1684 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1685 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1686 <&hsio_blk_ctl 0>; 1687 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1688 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1689 <&scmi_clk IMX95_CLK_HSIOPLL>, 1690 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1691 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1692 assigned-clock-parents = <0>, <0>, 1693 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1694 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1695 /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ 1696 msi-map = <0x0 &its 0x10 0x1>, 1697 <0x100 &its 0x11 0x7>; 1698 iommu-map = <0x000 &smmu 0x10 0x1>, 1699 <0x100 &smmu 0x11 0x7>; 1700 iommu-map-mask = <0x1ff>; 1701 fsl,max-link-speed = <3>; 1702 status = "disabled"; 1703 }; 1704 1705 pcie0_ep: pcie-ep@4c300000 { 1706 compatible = "fsl,imx95-pcie-ep"; 1707 reg = <0 0x4c300000 0 0x10000>, 1708 <0 0x4c360000 0 0x1000>, 1709 <0 0x4c320000 0 0x1000>, 1710 <0 0x4c340000 0 0x4000>, 1711 <0 0x4c370000 0 0x10000>, 1712 <0x9 0 1 0>; 1713 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1714 num-lanes = <1>; 1715 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1716 interrupt-names = "dma"; 1717 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1718 <&scmi_clk IMX95_CLK_HSIOPLL>, 1719 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1720 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1721 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1722 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1723 <&scmi_clk IMX95_CLK_HSIOPLL>, 1724 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1725 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1726 assigned-clock-parents = <0>, <0>, 1727 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1728 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1729 status = "disabled"; 1730 }; 1731 1732 pcie1: pcie@4c380000 { 1733 compatible = "fsl,imx95-pcie"; 1734 reg = <0 0x4c380000 0 0x10000>, 1735 <8 0x80100000 0 0xfe00000>, 1736 <0 0x4c3e0000 0 0x10000>, 1737 <0 0x4c3c0000 0 0x4000>; 1738 reg-names = "dbi", "config", "atu", "app"; 1739 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1740 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1741 #address-cells = <3>; 1742 #size-cells = <2>; 1743 device_type = "pci"; 1744 linux,pci-domain = <1>; 1745 bus-range = <0x00 0xff>; 1746 num-lanes = <1>; 1747 num-viewport = <8>; 1748 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1749 interrupt-names = "msi"; 1750 #interrupt-cells = <1>; 1751 interrupt-map-mask = <0 0 0 0x7>; 1752 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1753 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1754 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1755 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1756 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1757 <&scmi_clk IMX95_CLK_HSIOPLL>, 1758 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1759 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1760 <&hsio_blk_ctl 0>; 1761 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1762 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1763 <&scmi_clk IMX95_CLK_HSIOPLL>, 1764 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1765 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1766 assigned-clock-parents = <0>, <0>, 1767 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1768 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1769 /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ 1770 msi-map = <0x0 &its 0x98 0x1>, 1771 <0x100 &its 0x99 0x7>; 1772 msi-map-mask = <0x1ff>; 1773 /* smmu have not Devid(BIT[7:6]) */ 1774 iommu-map = <0x000 &smmu 0x18 0x1>, 1775 <0x100 &smmu 0x19 0x7>; 1776 iommu-map-mask = <0x1ff>; 1777 fsl,max-link-speed = <3>; 1778 status = "disabled"; 1779 }; 1780 1781 pcie1_ep: pcie-ep@4c380000 { 1782 compatible = "fsl,imx95-pcie-ep"; 1783 reg = <0 0x4c380000 0 0x10000>, 1784 <0 0x4c3e0000 0 0x1000>, 1785 <0 0x4c3a0000 0 0x1000>, 1786 <0 0x4c3c0000 0 0x4000>, 1787 <0 0x4c3f0000 0 0x10000>, 1788 <0xa 0 1 0>; 1789 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1790 num-lanes = <1>; 1791 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1792 interrupt-names = "dma"; 1793 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1794 <&scmi_clk IMX95_CLK_HSIOPLL>, 1795 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1796 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1797 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1798 assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1799 <&scmi_clk IMX95_CLK_HSIOPLL>, 1800 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1801 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1802 assigned-clock-parents = <0>, <0>, 1803 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1804 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1805 status = "disabled"; 1806 }; 1807 1808 vpu_blk_ctrl: clock-controller@4c410000 { 1809 compatible = "nxp,imx95-vpu-csr", "syscon"; 1810 reg = <0x0 0x4c410000 0x0 0x10000>; 1811 #clock-cells = <1>; 1812 clocks = <&scmi_clk IMX95_CLK_VPUAPB>; 1813 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1814 assigned-clocks = <&scmi_clk IMX95_CLK_VPUAPB>, 1815 <&scmi_clk IMX95_CLK_VPU>, 1816 <&scmi_clk IMX95_CLK_VPUJPEG>; 1817 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>, 1818 <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 1819 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 1820 assigned-clock-rates = <133333333>, <667000000>, <500000000>; 1821 }; 1822 1823 jpegdec: jpegdec@4c500000 { 1824 compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec"; 1825 reg = <0x0 0x4C500000 0x0 0x00050000>; 1826 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1830 clocks = <&scmi_clk IMX95_CLK_VPU>, 1831 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 1832 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 1833 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 1834 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1835 }; 1836 1837 jpegenc: jpegenc@4c550000 { 1838 compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc"; 1839 reg = <0x0 0x4C550000 0x0 0x00050000>; 1840 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 1844 clocks = <&scmi_clk IMX95_CLK_VPU>, 1845 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 1846 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 1847 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 1848 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1849 }; 1850 1851 netcmix_blk_ctrl: syscon@4c810000 { 1852 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 1853 reg = <0x0 0x4c810000 0x0 0x8>; 1854 #clock-cells = <1>; 1855 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1856 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 1857 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1858 assigned-clock-rates = <133333333>; 1859 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1860 status = "disabled"; 1861 }; 1862 1863 sai2: sai@4c880000 { 1864 compatible = "fsl,imx95-sai"; 1865 reg = <0x0 0x4c880000 0x0 0x10000>; 1866 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1867 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 1868 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 1869 <&dummy>; 1870 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1871 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1872 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 1873 dma-names = "rx", "tx"; 1874 status = "disabled"; 1875 }; 1876 1877 netc_blk_ctrl: system-controller@4cde0000 { 1878 compatible = "nxp,imx95-netc-blk-ctrl"; 1879 reg = <0x0 0x4cde0000 0x0 0x10000>, 1880 <0x0 0x4cdf0000 0x0 0x10000>, 1881 <0x0 0x4c81000c 0x0 0x18>; 1882 reg-names = "ierb", "prb", "netcmix"; 1883 #address-cells = <2>; 1884 #size-cells = <2>; 1885 ranges; 1886 power-domains = <&scmi_devpd IMX95_PD_NETC>; 1887 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>, 1888 <&scmi_clk IMX95_CLK_ENETREF>; 1889 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 1890 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 1891 assigned-clock-rates = <666666666>, <250000000>; 1892 clocks = <&scmi_clk IMX95_CLK_ENET>; 1893 clock-names = "ipg"; 1894 status = "disabled"; 1895 1896 netc_bus0: pcie@4ca00000 { 1897 compatible = "pci-host-ecam-generic"; 1898 reg = <0x0 0x4ca00000 0x0 0x100000>; 1899 #address-cells = <3>; 1900 #size-cells = <2>; 1901 device_type = "pci"; 1902 bus-range = <0x0 0x0>; 1903 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 1904 <0x10 &its 0x61 0x1>, //ENETC0 VF0 1905 <0x20 &its 0x62 0x1>, //ENETC0 VF1 1906 <0x40 &its 0x63 0x1>, //ENETC1 PF 1907 <0x80 &its 0x64 0x1>, //ENETC2 PF 1908 <0x90 &its 0x65 0x1>, //ENETC2 VF0 1909 <0xa0 &its 0x66 0x1>, //ENETC2 VF1 1910 <0xc0 &its 0x67 0x1>; //NETC Timer 1911 iommu-map = <0x0 &smmu 0x20 0x1>, 1912 <0x10 &smmu 0x21 0x1>, 1913 <0x20 &smmu 0x22 0x1>, 1914 <0x40 &smmu 0x23 0x1>, 1915 <0x80 &smmu 0x24 0x1>, 1916 <0x90 &smmu 0x25 0x1>, 1917 <0xa0 &smmu 0x26 0x1>, 1918 <0xc0 &smmu 0x27 0x1>; 1919 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ 1920 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 1921 /* Timer BAR2 - prefetchable memory */ 1922 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000 1923 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */ 1924 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000 1925 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */ 1926 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>; 1927 1928 enetc_port0: ethernet@0,0 { 1929 compatible = "pci1131,e101"; 1930 reg = <0x000000 0 0 0 0>; 1931 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 1932 clock-names = "ref"; 1933 status = "disabled"; 1934 }; 1935 1936 enetc_port1: ethernet@8,0 { 1937 compatible = "pci1131,e101"; 1938 reg = <0x004000 0 0 0 0>; 1939 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 1940 clock-names = "ref"; 1941 status = "disabled"; 1942 }; 1943 1944 enetc_port2: ethernet@10,0 { 1945 compatible = "pci1131,e101"; 1946 reg = <0x008000 0 0 0 0>; 1947 status = "disabled"; 1948 }; 1949 1950 netc_timer: ethernet@18,0 { 1951 reg = <0x00c000 0 0 0 0>; 1952 status = "disabled"; 1953 }; 1954 }; 1955 1956 netc_bus1: pcie@4cb00000 { 1957 compatible = "pci-host-ecam-generic"; 1958 reg = <0x0 0x4cb00000 0x0 0x100000>; 1959 #address-cells = <3>; 1960 #size-cells = <2>; 1961 device_type = "pci"; 1962 bus-range = <0x1 0x1>; 1963 /* EMDIO BAR0 - non-prefetchable memory */ 1964 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000 1965 /* EMDIO BAR2 - prefetchable memory */ 1966 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>; 1967 1968 netc_emdio: mdio@0,0 { 1969 compatible = "pci1131,ee00"; 1970 reg = <0x010000 0 0 0 0>; 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 status = "disabled"; 1974 }; 1975 }; 1976 }; 1977 1978 ddr-pmu@4e090dc0 { 1979 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 1980 reg = <0x0 0x4e090dc0 0x0 0x200>; 1981 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1982 }; 1983 }; 1984}; 1985