1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Samsung S5P Multi Format Codec v 5.0
4 *
5 * This file contains definitions of enums and structs used by the codec
6 * driver.
7 *
8 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
9 * Kamil Debski, <k.debski@samsung.com>
10 */
11
12 #ifndef S5P_MFC_COMMON_H_
13 #define S5P_MFC_COMMON_H_
14
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-ioctl.h>
20 #include <media/videobuf2-v4l2.h>
21 #include "regs-mfc.h"
22 #include "regs-mfc-v12.h"
23
24 #define S5P_MFC_NAME "s5p-mfc"
25
26 /* Definitions related to MFC memory */
27
28 /* Offset base used to differentiate between CAPTURE and OUTPUT
29 * while mmaping */
30 #define DST_QUEUE_OFF_BASE (1 << 30)
31
32 #define BANK_L_CTX 0
33 #define BANK_R_CTX 1
34 #define BANK_CTX_NUM 2
35
36 #define MFC_BANK1_ALIGN_ORDER 13
37 #define MFC_BANK2_ALIGN_ORDER 13
38 #define MFC_BASE_ALIGN_ORDER 17
39
40 #define MFC_FW_MAX_VERSIONS 2
41
42 #include <media/videobuf2-dma-contig.h>
43
44 /* MFC definitions */
45 #define MFC_MAX_EXTRA_DPB 5
46 #define MFC_MAX_BUFFERS 32
47 #define MFC_NUM_CONTEXTS 4
48 /* Interrupt timeout */
49 #define MFC_INT_TIMEOUT 2000
50 /* Busy wait timeout */
51 #define MFC_BW_TIMEOUT 500
52 /* Watchdog interval */
53 #define MFC_WATCHDOG_INTERVAL 1000
54 /* After how many executions watchdog should assume lock up */
55 #define MFC_WATCHDOG_CNT 10
56 #define MFC_NO_INSTANCE_SET -1
57 #define MFC_ENC_CAP_PLANE_COUNT 1
58 #define MFC_ENC_OUT_PLANE_COUNT 2
59 #define VB2_MAX_PLANE_COUNT 3
60 #define STUFF_BYTE 4
61 #define MFC_MAX_CTRLS 128
62
63 #define S5P_MFC_CODEC_NONE -1
64 #define S5P_MFC_CODEC_H264_DEC 0
65 #define S5P_MFC_CODEC_H264_MVC_DEC 1
66 #define S5P_MFC_CODEC_VC1_DEC 2
67 #define S5P_MFC_CODEC_MPEG4_DEC 3
68 #define S5P_MFC_CODEC_MPEG2_DEC 4
69 #define S5P_MFC_CODEC_H263_DEC 5
70 #define S5P_MFC_CODEC_VC1RCV_DEC 6
71 #define S5P_MFC_CODEC_VP8_DEC 7
72 #define S5P_MFC_CODEC_HEVC_DEC 17
73 #define S5P_MFC_CODEC_VP9_DEC 18
74
75 #define S5P_MFC_CODEC_H264_ENC 20
76 #define S5P_MFC_CODEC_H264_MVC_ENC 21
77 #define S5P_MFC_CODEC_MPEG4_ENC 22
78 #define S5P_MFC_CODEC_H263_ENC 23
79 #define S5P_MFC_CODEC_VP8_ENC 24
80 #define S5P_MFC_CODEC_HEVC_ENC 26
81
82 #define S5P_MFC_R2H_CMD_EMPTY 0
83 #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
84 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
85 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
86 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
87 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
88 #define S5P_MFC_R2H_CMD_SLEEP_RET 7
89 #define S5P_MFC_R2H_CMD_WAKEUP_RET 8
90 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
91 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
92 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
93 #define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
94 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
95 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
96 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
97 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
98 #define S5P_MFC_R2H_CMD_ERR_RET 32
99
100 #define MFC_MAX_CLOCKS 4
101
102 #define mfc_read(dev, offset) readl(dev->regs_base + (offset))
103 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
104 (offset))
105
106 /*
107 * enum s5p_mfc_fmt_type - type of the pixelformat
108 */
109 enum s5p_mfc_fmt_type {
110 MFC_FMT_DEC,
111 MFC_FMT_ENC,
112 MFC_FMT_RAW,
113 };
114
115 /*
116 * enum s5p_mfc_inst_type - The type of an MFC instance.
117 */
118 enum s5p_mfc_inst_type {
119 MFCINST_INVALID,
120 MFCINST_DECODER,
121 MFCINST_ENCODER,
122 };
123
124 /*
125 * enum s5p_mfc_inst_state - The state of an MFC instance.
126 */
127 enum s5p_mfc_inst_state {
128 MFCINST_FREE = 0,
129 MFCINST_INIT = 100,
130 MFCINST_GOT_INST,
131 MFCINST_HEAD_PARSED,
132 MFCINST_HEAD_PRODUCED,
133 MFCINST_BUFS_SET,
134 MFCINST_RUNNING,
135 MFCINST_FINISHING,
136 MFCINST_FINISHED,
137 MFCINST_RETURN_INST,
138 MFCINST_ERROR,
139 MFCINST_ABORT,
140 MFCINST_FLUSH,
141 MFCINST_RES_CHANGE_INIT,
142 MFCINST_RES_CHANGE_FLUSH,
143 MFCINST_RES_CHANGE_END,
144 MFCINST_NAL_ABORT,
145 };
146
147 /*
148 * enum s5p_mfc_queue_state - The state of buffer queue.
149 */
150 enum s5p_mfc_queue_state {
151 QUEUE_FREE,
152 QUEUE_BUFS_REQUESTED,
153 QUEUE_BUFS_QUERIED,
154 QUEUE_BUFS_MMAPED,
155 };
156
157 /*
158 * enum s5p_mfc_decode_arg - type of frame decoding
159 */
160 enum s5p_mfc_decode_arg {
161 MFC_DEC_FRAME,
162 MFC_DEC_LAST_FRAME,
163 MFC_DEC_RES_CHANGE,
164 };
165
166 enum s5p_mfc_fw_ver {
167 MFC_FW_V1,
168 MFC_FW_V2,
169 };
170
171 #define MFC_BUF_FLAG_USED (1 << 0)
172 #define MFC_BUF_FLAG_EOS (1 << 1)
173
174 struct s5p_mfc_ctx;
175
176 /*
177 * struct s5p_mfc_buf - MFC buffer
178 */
179 struct s5p_mfc_buf {
180 struct vb2_v4l2_buffer *b;
181 struct list_head list;
182 union {
183 struct {
184 size_t luma;
185 size_t chroma;
186 size_t chroma_1;
187 } raw;
188 size_t stream;
189 } cookie;
190 int flags;
191 };
192
193 /*
194 * struct s5p_mfc_pm - power management data structure
195 */
196 struct s5p_mfc_pm {
197 struct clk *clock_gate;
198 const char * const *clk_names;
199 struct clk *clocks[MFC_MAX_CLOCKS];
200 int num_clocks;
201 bool use_clock_gating;
202
203 struct device *device;
204 };
205
206 struct s5p_mfc_buf_size_v5 {
207 unsigned int h264_ctx;
208 unsigned int non_h264_ctx;
209 unsigned int dsc;
210 unsigned int shm;
211 };
212
213 struct s5p_mfc_buf_size_v6 {
214 unsigned int dev_ctx;
215 unsigned int h264_dec_ctx;
216 unsigned int other_dec_ctx;
217 unsigned int h264_enc_ctx;
218 unsigned int hevc_enc_ctx;
219 unsigned int other_enc_ctx;
220 };
221
222 struct s5p_mfc_buf_size {
223 unsigned int fw;
224 unsigned int cpb;
225 const void *priv;
226 };
227
228 struct s5p_mfc_variant {
229 unsigned int version;
230 unsigned int port_num;
231 u32 version_bit;
232 const struct s5p_mfc_buf_size *buf_size;
233 const char *fw_name[MFC_FW_MAX_VERSIONS];
234 const char *clk_names[MFC_MAX_CLOCKS];
235 int num_clocks;
236 bool use_clock_gating;
237 };
238
239 /**
240 * struct s5p_mfc_priv_buf - represents internal used buffer
241 * @ofs: offset of each buffer, will be used for MFC
242 * @virt: kernel virtual address, only valid when the
243 * buffer accessed by driver
244 * @dma: DMA address, only valid when kernel DMA API used
245 * @size: size of the buffer
246 * @ctx: memory context (bank) used for this allocation
247 */
248 struct s5p_mfc_priv_buf {
249 unsigned long ofs;
250 void *virt;
251 dma_addr_t dma;
252 size_t size;
253 unsigned int ctx;
254 };
255
256 /**
257 * struct s5p_mfc_dev - The struct containing driver internal parameters.
258 *
259 * @v4l2_dev: v4l2_device
260 * @vfd_dec: video device for decoding
261 * @vfd_enc: video device for encoding
262 * @plat_dev: platform device
263 * @mem_dev: child devices of the memory banks
264 * @regs_base: base address of the MFC hw registers
265 * @irq: irq resource
266 * @dec_ctrl_handler: control framework handler for decoding
267 * @enc_ctrl_handler: control framework handler for encoding
268 * @pm: power management control
269 * @variant: MFC hardware variant information
270 * @num_inst: counter of active MFC instances
271 * @irqlock: lock for operations on videobuf2 queues
272 * @condlock: lock for changing/checking if a context is ready to be
273 * processed
274 * @mfc_mutex: lock for video_device
275 * @int_cond: variable used by the waitqueue
276 * @int_type: type of last interrupt
277 * @int_err: error number for last interrupt
278 * @queue: waitqueue for waiting for completion of device commands
279 * @fw_buf: the firmware buffer data structure
280 * @mem_size: size of the firmware operation memory
281 * @mem_base: base DMA address of the firmware operation memory
282 * @mem_bitmap: bitmap for managing MFC internal buffer allocations
283 * @mem_virt: virtual address of the firmware operation memory
284 * @dma_base: address of the beginning of memory banks
285 * @hw_lock: used for hardware locking
286 * @ctx: array of driver contexts
287 * @curr_ctx: number of the currently running context
288 * @ctx_work_bits: used to mark which contexts are waiting for hardware
289 * @watchdog_cnt: counter for the watchdog
290 * @watchdog_timer: timer for the watchdog
291 * @watchdog_workqueue: workqueue for the watchdog
292 * @watchdog_work: worker for the watchdog
293 * @enter_suspend: flag set when entering suspend
294 * @ctx_buf: common context memory (MFCv6)
295 * @warn_start: hardware error code from which warnings start
296 * @mfc_ops: ops structure holding HW operation function pointers
297 * @mfc_cmds: cmd structure holding HW commands function pointers
298 * @mfc_regs: structure holding MFC registers
299 * @fw_ver: loaded firmware sub-version
300 * @fw_get_done: flag set when request_firmware() is complete and
301 * copied into fw_buf
302 * @risc_on: flag indicates RISC is on or off
303 *
304 */
305 struct s5p_mfc_dev {
306 struct v4l2_device v4l2_dev;
307 struct video_device *vfd_dec;
308 struct video_device *vfd_enc;
309 struct platform_device *plat_dev;
310 struct device *mem_dev[BANK_CTX_NUM];
311 void __iomem *regs_base;
312 int irq;
313 struct v4l2_ctrl_handler dec_ctrl_handler;
314 struct v4l2_ctrl_handler enc_ctrl_handler;
315 struct s5p_mfc_pm pm;
316 const struct s5p_mfc_variant *variant;
317 int num_inst;
318 spinlock_t irqlock; /* lock when operating on context */
319 spinlock_t condlock; /* lock when changing/checking if a context is
320 ready to be processed */
321 struct mutex mfc_mutex; /* video_device lock */
322 int int_cond;
323 int int_type;
324 unsigned int int_err;
325 wait_queue_head_t queue;
326 struct s5p_mfc_priv_buf fw_buf;
327 size_t mem_size;
328 dma_addr_t mem_base;
329 unsigned long *mem_bitmap;
330 void *mem_virt;
331 dma_addr_t dma_base[BANK_CTX_NUM];
332 unsigned long hw_lock;
333 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
334 int curr_ctx;
335 unsigned long ctx_work_bits;
336 atomic_t watchdog_cnt;
337 struct timer_list watchdog_timer;
338 struct workqueue_struct *watchdog_workqueue;
339 struct work_struct watchdog_work;
340 unsigned long enter_suspend;
341
342 struct s5p_mfc_priv_buf ctx_buf;
343 int warn_start;
344 const struct s5p_mfc_hw_ops *mfc_ops;
345 const struct s5p_mfc_hw_cmds *mfc_cmds;
346 const struct s5p_mfc_regs *mfc_regs;
347 enum s5p_mfc_fw_ver fw_ver;
348 bool fw_get_done;
349 bool risc_on; /* indicates if RISC is on or off */
350 };
351
352 /*
353 * struct s5p_mfc_h264_enc_params - encoding parameters for h264
354 */
355 struct s5p_mfc_h264_enc_params {
356 enum v4l2_mpeg_video_h264_profile profile;
357 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
358 s8 loop_filter_alpha;
359 s8 loop_filter_beta;
360 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
361 u8 max_ref_pic;
362 u8 num_ref_pic_4p;
363 int _8x8_transform;
364 int rc_mb_dark;
365 int rc_mb_smooth;
366 int rc_mb_static;
367 int rc_mb_activity;
368 int vui_sar;
369 u8 vui_sar_idc;
370 u16 vui_ext_sar_width;
371 u16 vui_ext_sar_height;
372 int open_gop;
373 u16 open_gop_size;
374 u8 rc_frame_qp;
375 u8 rc_min_qp;
376 u8 rc_max_qp;
377 u8 rc_p_frame_qp;
378 u8 rc_b_frame_qp;
379 enum v4l2_mpeg_video_h264_level level_v4l2;
380 int level;
381 u16 cpb_size;
382 int interlace;
383 u8 hier_qp;
384 u8 hier_qp_type;
385 u8 hier_qp_layer;
386 u8 hier_qp_layer_qp[7];
387 u8 sei_frame_packing;
388 u8 sei_fp_curr_frame_0;
389 u8 sei_fp_arrangement_type;
390
391 u8 fmo;
392 u8 fmo_map_type;
393 u8 fmo_slice_grp;
394 u8 fmo_chg_dir;
395 u32 fmo_chg_rate;
396 u32 fmo_run_len[4];
397 u8 aso;
398 u32 aso_slice_order[8];
399 };
400
401 /*
402 * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
403 */
404 struct s5p_mfc_mpeg4_enc_params {
405 /* MPEG4 Only */
406 enum v4l2_mpeg_video_mpeg4_profile profile;
407 int quarter_pixel;
408 /* Common for MPEG4, H263 */
409 u16 vop_time_res;
410 u16 vop_frm_delta;
411 u8 rc_frame_qp;
412 u8 rc_min_qp;
413 u8 rc_max_qp;
414 u8 rc_p_frame_qp;
415 u8 rc_b_frame_qp;
416 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
417 int level;
418 };
419
420 /*
421 * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
422 */
423 struct s5p_mfc_vp8_enc_params {
424 u8 imd_4x4;
425 enum v4l2_vp8_num_partitions num_partitions;
426 enum v4l2_vp8_num_ref_frames num_ref;
427 u8 filter_level;
428 u8 filter_sharpness;
429 u32 golden_frame_ref_period;
430 enum v4l2_vp8_golden_frame_sel golden_frame_sel;
431 u8 hier_layer;
432 u8 hier_layer_qp[3];
433 u8 rc_min_qp;
434 u8 rc_max_qp;
435 u8 rc_frame_qp;
436 u8 rc_p_frame_qp;
437 u8 profile;
438 };
439
440 struct s5p_mfc_hevc_enc_params {
441 enum v4l2_mpeg_video_hevc_profile profile;
442 int level;
443 enum v4l2_mpeg_video_h264_level level_v4l2;
444 u8 tier;
445 u32 rc_framerate;
446 u8 rc_min_qp;
447 u8 rc_max_qp;
448 u8 rc_lcu_dark;
449 u8 rc_lcu_smooth;
450 u8 rc_lcu_static;
451 u8 rc_lcu_activity;
452 u8 rc_frame_qp;
453 u8 rc_p_frame_qp;
454 u8 rc_b_frame_qp;
455 u8 max_partition_depth;
456 u8 num_refs_for_p;
457 u8 refreshtype;
458 u16 refreshperiod;
459 s32 lf_beta_offset_div2;
460 s32 lf_tc_offset_div2;
461 u8 loopfilter;
462 u8 loopfilter_disable;
463 u8 loopfilter_across;
464 u8 nal_control_length_filed;
465 u8 nal_control_user_ref;
466 u8 nal_control_store_ref;
467 u8 const_intra_period_enable;
468 u8 lossless_cu_enable;
469 u8 wavefront_enable;
470 u8 enable_ltr;
471 u8 hier_qp_enable;
472 enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
473 u8 num_hier_layer;
474 u8 hier_qp_layer[7];
475 u32 hier_bit_layer[7];
476 u8 sign_data_hiding;
477 u8 general_pb_enable;
478 u8 temporal_id_enable;
479 u8 strong_intra_smooth;
480 u8 intra_pu_split_disable;
481 u8 tmv_prediction_disable;
482 u8 max_num_merge_mv;
483 u8 eco_mode_enable;
484 u8 encoding_nostartcode_enable;
485 u8 size_of_length_field;
486 u8 prepend_sps_pps_to_idr;
487 };
488
489 /*
490 * struct s5p_mfc_enc_params - general encoding parameters
491 */
492 struct s5p_mfc_enc_params {
493 u16 width;
494 u16 height;
495 u32 mv_h_range;
496 u32 mv_v_range;
497
498 u16 gop_size;
499 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
500 u16 slice_mb;
501 u32 slice_bit;
502 u16 intra_refresh_mb;
503 int pad;
504 u8 pad_luma;
505 u8 pad_cb;
506 u8 pad_cr;
507 int rc_frame;
508 int rc_mb;
509 u32 rc_bitrate;
510 u16 rc_reaction_coeff;
511 u16 vbv_size;
512 u32 vbv_delay;
513
514 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
515 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
516 int fixed_target_bit;
517
518 u8 num_b_frame;
519 u32 rc_framerate_num;
520 u32 rc_framerate_denom;
521
522 struct {
523 struct s5p_mfc_h264_enc_params h264;
524 struct s5p_mfc_mpeg4_enc_params mpeg4;
525 struct s5p_mfc_vp8_enc_params vp8;
526 struct s5p_mfc_hevc_enc_params hevc;
527 } codec;
528
529 };
530
531 /*
532 * struct s5p_mfc_codec_ops - codec ops, used by encoding
533 */
534 struct s5p_mfc_codec_ops {
535 /* initialization routines */
536 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
537 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
538 /* execution routines */
539 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
540 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
541 };
542
543 #define call_cop(c, op, args...) \
544 (((c)->c_ops->op) ? \
545 ((c)->c_ops->op(args)) : 0)
546
547 /**
548 * struct s5p_mfc_ctx - This struct contains the instance context
549 *
550 * @dev: pointer to the s5p_mfc_dev of the device
551 * @fh: struct v4l2_fh
552 * @num: number of the context that this structure describes
553 * @int_cond: variable used by the waitqueue
554 * @int_type: type of the last interrupt
555 * @int_err: error number received from MFC hw in the interrupt
556 * @queue: waitqueue that can be used to wait for this context to
557 * finish
558 * @src_fmt: source pixelformat information
559 * @dst_fmt: destination pixelformat information
560 * @vq_src: vb2 queue for source buffers
561 * @vq_dst: vb2 queue for destination buffers
562 * @src_queue: driver internal queue for source buffers
563 * @dst_queue: driver internal queue for destination buffers
564 * @src_queue_cnt: number of buffers queued on the source internal queue
565 * @dst_queue_cnt: number of buffers queued on the dest internal queue
566 * @type: type of the instance - decoder or encoder
567 * @state: state of the context
568 * @inst_no: number of hw instance associated with the context
569 * @img_width: width of the image that is decoded or encoded
570 * @img_height: height of the image that is decoded or encoded
571 * @buf_width: width of the buffer for processed image
572 * @buf_height: height of the buffer for processed image
573 * @luma_size: size of a luma plane
574 * @chroma_size: size of a chroma plane
575 * @mv_size: size of a motion vectors buffer
576 * @consumed_stream: number of bytes that have been used so far from the
577 * decoding buffer
578 * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
579 * flushed
580 * @head_processed: flag mentioning whether the header data is processed
581 * completely or not
582 * @bank1: handle to memory allocated for temporary buffers from
583 * memory bank 1
584 * @bank2: handle to memory allocated for temporary buffers from
585 * memory bank 2
586 * @capture_state: state of the capture buffers queue
587 * @output_state: state of the output buffers queue
588 * @src_bufs: information on allocated source buffers
589 * @src_bufs_cnt: number of allocated source buffers
590 * @dst_bufs: information on allocated destination buffers
591 * @dst_bufs_cnt: number of allocated destination buffers
592 * @sequence: counter for the sequence number for v4l2
593 * @dec_dst_flag: flags for buffers queued in the hardware
594 * @dec_src_buf_size: size of the buffer for source buffers in decoding
595 * @codec_mode: number of codec mode used by MFC hw
596 * @slice_interface: slice interface flag
597 * @loop_filter_mpeg4: loop filter for MPEG4 flag
598 * @display_delay: value of the display delay for H264
599 * @display_delay_enable: display delay for H264 enable flag
600 * @after_packed_pb: flag used to track buffer when stream is in
601 * Packed PB format
602 * @sei_fp_parse: enable/disable parsing of frame packing SEI information
603 * @pb_count: count of the DPB buffers required by MFC hw
604 * @total_dpb_count: count of DPB buffers with additional buffers
605 * requested by the application
606 * @ctx: context buffer information
607 * @dsc: descriptor buffer information
608 * @shm: shared memory buffer information
609 * @mv_count: number of MV buffers allocated for decoding
610 * @enc_params: encoding parameters for MFC
611 * @enc_dst_buf_size: size of the buffers for encoder output
612 * @luma_dpb_size: dpb buffer size for luma
613 * @chroma_dpb_size: dpb buffer size for chroma
614 * @me_buffer_size: size of the motion estimation buffer
615 * @tmv_buffer_size: size of temporal predictor motion vector buffer
616 * @ref_queue: list of the reference buffers for encoding
617 * @force_frame_type: encoder's frame type forcing control
618 * @ref_queue_cnt: number of the buffers in the reference list
619 * @slice_size: slice size
620 * @slice_mode: mode of dividing frames into slices
621 * @c_ops: ops for encoding
622 * @ctrls: array of controls, used when adding controls to the
623 * v4l2 control framework
624 * @ctrl_handler: handler for v4l2 framework
625 * @scratch_buf_size: scratch buffer size
626 * @is_10bit: state to check 10bit support
627 * @is_422: state to check YUV422 10bit format
628 * @chroma_size_1: size of a chroma third plane
629 * @stride: size of stride for all planes
630 */
631 struct s5p_mfc_ctx {
632 struct s5p_mfc_dev *dev;
633 struct v4l2_fh fh;
634
635 int num;
636
637 int int_cond;
638 int int_type;
639 unsigned int int_err;
640 wait_queue_head_t queue;
641
642 const struct s5p_mfc_fmt *src_fmt;
643 const struct s5p_mfc_fmt *dst_fmt;
644
645 struct vb2_queue vq_src;
646 struct vb2_queue vq_dst;
647
648 struct list_head src_queue;
649 struct list_head dst_queue;
650
651 unsigned int src_queue_cnt;
652 unsigned int dst_queue_cnt;
653
654 enum s5p_mfc_inst_type type;
655 enum s5p_mfc_inst_state state;
656 int inst_no;
657
658 /* Image parameters */
659 int img_width;
660 int img_height;
661 int buf_width;
662 int buf_height;
663
664 int luma_size;
665 int chroma_size;
666 int chroma_size_1;
667 int mv_size;
668
669 unsigned long consumed_stream;
670
671 unsigned int dpb_flush_flag;
672 unsigned int head_processed;
673
674 struct s5p_mfc_priv_buf bank1;
675 struct s5p_mfc_priv_buf bank2;
676
677 enum s5p_mfc_queue_state capture_state;
678 enum s5p_mfc_queue_state output_state;
679
680 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
681 int src_bufs_cnt;
682 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
683 int dst_bufs_cnt;
684
685 unsigned int sequence;
686 unsigned long dec_dst_flag;
687 size_t dec_src_buf_size;
688
689 /* Control values */
690 int codec_mode;
691 int slice_interface;
692 int loop_filter_mpeg4;
693 int display_delay;
694 int display_delay_enable;
695 int after_packed_pb;
696 int sei_fp_parse;
697
698 int pb_count;
699 int total_dpb_count;
700 int mv_count;
701 /* Buffers */
702 struct s5p_mfc_priv_buf ctx;
703 struct s5p_mfc_priv_buf dsc;
704 struct s5p_mfc_priv_buf shm;
705
706 struct s5p_mfc_enc_params enc_params;
707
708 size_t enc_dst_buf_size;
709 size_t luma_dpb_size;
710 size_t chroma_dpb_size;
711 size_t me_buffer_size;
712 size_t tmv_buffer_size;
713
714 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
715
716 struct list_head ref_queue;
717 unsigned int ref_queue_cnt;
718
719 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
720 union {
721 unsigned int mb;
722 unsigned int bits;
723 } slice_size;
724
725 const struct s5p_mfc_codec_ops *c_ops;
726
727 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
728 struct v4l2_ctrl_handler ctrl_handler;
729 size_t scratch_buf_size;
730 int is_10bit;
731 int is_422;
732 int stride[VB2_MAX_PLANE_COUNT];
733 };
734
735 /*
736 * struct s5p_mfc_fmt - structure used to store information about pixelformats
737 * used by the MFC
738 */
739 struct s5p_mfc_fmt {
740 u32 fourcc;
741 u32 codec_mode;
742 enum s5p_mfc_fmt_type type;
743 u32 num_planes;
744 u32 versions;
745 u32 flags;
746 };
747
748 /*
749 * struct mfc_control - structure used to store information about MFC controls
750 * it is used to initialize the control framework.
751 */
752 struct mfc_control {
753 __u32 id;
754 enum v4l2_ctrl_type type;
755 __u8 name[32]; /* Whatever */
756 __s32 minimum; /* Note signedness */
757 __s32 maximum;
758 __s32 step;
759 __u32 menu_skip_mask;
760 __s32 default_value;
761 __u32 flags;
762 __u32 reserved[2];
763 __u8 is_volatile;
764 };
765
766 /* Macro for making hardware specific calls */
767 #define s5p_mfc_hw_call(f, op, args...) \
768 ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
769
file_to_ctx(struct file * filp)770 static inline struct s5p_mfc_ctx *file_to_ctx(struct file *filp)
771 {
772 return container_of(file_to_v4l2_fh(filp), struct s5p_mfc_ctx, fh);
773 }
774
775 #define ctrl_to_ctx(__ctrl) \
776 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
777
778 void clear_work_bit(struct s5p_mfc_ctx *ctx);
779 void set_work_bit(struct s5p_mfc_ctx *ctx);
780 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
781 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
782 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
783 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
784
785 #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
786 (dev->variant->port_num ? 1 : 0) : 0) : 0)
787 #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
788 #define IS_MFCV6_PLUS(dev) ((dev)->variant->version >= 0x60)
789 #define IS_MFCV7_PLUS(dev) ((dev)->variant->version >= 0x70)
790 #define IS_MFCV8_PLUS(dev) ((dev)->variant->version >= 0x80)
791 #define IS_MFCV10_PLUS(dev) ((dev)->variant->version >= 0xA0)
792 #define IS_MFCV12(dev) ((dev)->variant->version >= 0xC0)
793 #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev))
794
795 #define MFC_V5_BIT BIT(0)
796 #define MFC_V6_BIT BIT(1)
797 #define MFC_V7_BIT BIT(2)
798 #define MFC_V8_BIT BIT(3)
799 #define MFC_V10_BIT BIT(5)
800 #define MFC_V12_BIT BIT(7)
801
802 #define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
803 MFC_V8_BIT | MFC_V10_BIT | MFC_V12_BIT)
804 #define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
805 MFC_V10_BIT | MFC_V12_BIT)
806 #define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT | \
807 MFC_V12_BIT)
808
809 #define MFC_V10PLUS_BITS (MFC_V10_BIT | MFC_V12_BIT)
810
811 #endif /* S5P_MFC_COMMON_H_ */
812