1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * dts file for AppliedMicro (APM) X-Gene Storm SOC 4 * 5 * Copyright (C) 2013, Applied Micro Circuits Corporation 6 */ 7 8/ { 9 compatible = "apm,xgene-storm"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "apm,potenza"; 21 reg = <0x0 0x000>; 22 enable-method = "spin-table"; 23 cpu-release-addr = <0x1 0x0000fff8>; 24 next-level-cache = <&xgene_L2_0>; 25 }; 26 cpu@1 { 27 device_type = "cpu"; 28 compatible = "apm,potenza"; 29 reg = <0x0 0x001>; 30 enable-method = "spin-table"; 31 cpu-release-addr = <0x1 0x0000fff8>; 32 next-level-cache = <&xgene_L2_0>; 33 }; 34 cpu@100 { 35 device_type = "cpu"; 36 compatible = "apm,potenza"; 37 reg = <0x0 0x100>; 38 enable-method = "spin-table"; 39 cpu-release-addr = <0x1 0x0000fff8>; 40 next-level-cache = <&xgene_L2_1>; 41 }; 42 cpu@101 { 43 device_type = "cpu"; 44 compatible = "apm,potenza"; 45 reg = <0x0 0x101>; 46 enable-method = "spin-table"; 47 cpu-release-addr = <0x1 0x0000fff8>; 48 next-level-cache = <&xgene_L2_1>; 49 }; 50 cpu@200 { 51 device_type = "cpu"; 52 compatible = "apm,potenza"; 53 reg = <0x0 0x200>; 54 enable-method = "spin-table"; 55 cpu-release-addr = <0x1 0x0000fff8>; 56 next-level-cache = <&xgene_L2_2>; 57 }; 58 cpu@201 { 59 device_type = "cpu"; 60 compatible = "apm,potenza"; 61 reg = <0x0 0x201>; 62 enable-method = "spin-table"; 63 cpu-release-addr = <0x1 0x0000fff8>; 64 next-level-cache = <&xgene_L2_2>; 65 }; 66 cpu@300 { 67 device_type = "cpu"; 68 compatible = "apm,potenza"; 69 reg = <0x0 0x300>; 70 enable-method = "spin-table"; 71 cpu-release-addr = <0x1 0x0000fff8>; 72 next-level-cache = <&xgene_L2_3>; 73 }; 74 cpu@301 { 75 device_type = "cpu"; 76 compatible = "apm,potenza"; 77 reg = <0x0 0x301>; 78 enable-method = "spin-table"; 79 cpu-release-addr = <0x1 0x0000fff8>; 80 next-level-cache = <&xgene_L2_3>; 81 }; 82 xgene_L2_0: l2-cache-0 { 83 compatible = "cache"; 84 cache-level = <2>; 85 cache-unified; 86 }; 87 xgene_L2_1: l2-cache-1 { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 }; 92 xgene_L2_2: l2-cache-2 { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 }; 97 xgene_L2_3: l2-cache-3 { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 }; 102 }; 103 104 gic: interrupt-controller@78010000 { 105 compatible = "arm,cortex-a15-gic"; 106 #address-cells = <0>; 107 #interrupt-cells = <3>; 108 interrupt-controller; 109 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ 110 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ 111 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ 112 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ 113 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 114 }; 115 116 refclk: clock-100000000 { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <100000000>; 120 clock-output-names = "refclk"; 121 }; 122 123 timer { 124 compatible = "arm,armv8-timer"; 125 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ 126 <1 13 0xff08>, /* Non-secure Phys IRQ */ 127 <1 14 0xff08>, /* Virt IRQ */ 128 <1 15 0xff08>; /* Hyp IRQ */ 129 clock-frequency = <50000000>; 130 }; 131 132 pmu { 133 compatible = "apm,potenza-pmu"; 134 interrupts = <1 12 0xff04>; 135 }; 136 137 i2c { 138 compatible = "apm,xgene-slimpro-i2c"; 139 mboxes = <&mailbox 0>; 140 }; 141 142 hwmonslimpro { 143 compatible = "apm,xgene-slimpro-hwmon"; 144 mboxes = <&mailbox 7>; 145 }; 146 147 soc { 148 compatible = "simple-bus"; 149 #address-cells = <2>; 150 #size-cells = <2>; 151 ranges; 152 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; 153 154 clocks { 155 #address-cells = <2>; 156 #size-cells = <2>; 157 ranges; 158 159 pcppll: pcppll@17000100 { 160 compatible = "apm,xgene-pcppll-clock"; 161 #clock-cells = <1>; 162 clocks = <&refclk>; 163 clock-names = "pcppll"; 164 reg = <0x0 0x17000100 0x0 0x1000>; 165 clock-output-names = "pcppll"; 166 }; 167 168 socpll: socpll@17000120 { 169 compatible = "apm,xgene-socpll-clock"; 170 #clock-cells = <1>; 171 clocks = <&refclk>; 172 clock-names = "socpll"; 173 reg = <0x0 0x17000120 0x0 0x1000>; 174 clock-output-names = "socpll"; 175 }; 176 177 socplldiv2: socplldiv2 { 178 compatible = "fixed-factor-clock"; 179 #clock-cells = <0>; 180 clocks = <&socpll 0>; 181 clock-mult = <1>; 182 clock-div = <2>; 183 clock-output-names = "socplldiv2"; 184 }; 185 186 ahbclk: ahbclk@17000000 { 187 compatible = "apm,xgene-device-clock"; 188 #clock-cells = <1>; 189 clocks = <&socplldiv2>; 190 reg = <0x0 0x17000000 0x0 0x2000>; 191 reg-names = "div-reg"; 192 divider-offset = <0x164>; 193 divider-width = <0x5>; 194 divider-shift = <0x0>; 195 clock-output-names = "ahbclk"; 196 }; 197 198 sdioclk: sdioclk@1f2ac000 { 199 compatible = "apm,xgene-device-clock"; 200 #clock-cells = <1>; 201 clocks = <&socplldiv2>; 202 reg = <0x0 0x1f2ac000 0x0 0x1000 203 0x0 0x17000000 0x0 0x2000>; 204 reg-names = "csr-reg", "div-reg"; 205 csr-offset = <0x0>; 206 csr-mask = <0x2>; 207 enable-offset = <0x8>; 208 enable-mask = <0x2>; 209 divider-offset = <0x178>; 210 divider-width = <0x8>; 211 divider-shift = <0x0>; 212 clock-output-names = "sdioclk"; 213 }; 214 215 ethclk: ethclk { 216 compatible = "apm,xgene-device-clock"; 217 #clock-cells = <1>; 218 clocks = <&socplldiv2>; 219 clock-names = "ethclk"; 220 reg = <0x0 0x17000000 0x0 0x1000>; 221 reg-names = "div-reg"; 222 divider-offset = <0x238>; 223 divider-width = <0x9>; 224 divider-shift = <0x0>; 225 clock-output-names = "ethclk"; 226 }; 227 228 menetclk: menetclk { 229 compatible = "apm,xgene-device-clock"; 230 #clock-cells = <1>; 231 clocks = <ðclk 0>; 232 reg = <0x0 0x1702c000 0x0 0x1000>; 233 reg-names = "csr-reg"; 234 clock-output-names = "menetclk"; 235 }; 236 237 sge0clk: sge0clk@1f21c000 { 238 compatible = "apm,xgene-device-clock"; 239 #clock-cells = <1>; 240 clocks = <&socplldiv2>; 241 reg = <0x0 0x1f21c000 0x0 0x1000>; 242 reg-names = "csr-reg"; 243 csr-mask = <0xa>; 244 enable-mask = <0xf>; 245 clock-output-names = "sge0clk"; 246 }; 247 248 xge0clk: xge0clk@1f61c000 { 249 compatible = "apm,xgene-device-clock"; 250 #clock-cells = <1>; 251 clocks = <&socplldiv2>; 252 reg = <0x0 0x1f61c000 0x0 0x1000>; 253 reg-names = "csr-reg"; 254 csr-mask = <0x3>; 255 clock-output-names = "xge0clk"; 256 }; 257 258 xge1clk: xge1clk@1f62c000 { 259 compatible = "apm,xgene-device-clock"; 260 status = "disabled"; 261 #clock-cells = <1>; 262 clocks = <&socplldiv2>; 263 reg = <0x0 0x1f62c000 0x0 0x1000>; 264 reg-names = "csr-reg"; 265 csr-mask = <0x3>; 266 clock-output-names = "xge1clk"; 267 }; 268 269 sataphy1clk: sataphy1clk@1f21c000 { 270 compatible = "apm,xgene-device-clock"; 271 #clock-cells = <1>; 272 clocks = <&socplldiv2>; 273 reg = <0x0 0x1f21c000 0x0 0x1000>; 274 reg-names = "csr-reg"; 275 clock-output-names = "sataphy1clk"; 276 status = "disabled"; 277 csr-offset = <0x4>; 278 csr-mask = <0x00>; 279 enable-offset = <0x0>; 280 enable-mask = <0x06>; 281 }; 282 283 sataphy2clk: sataphy1clk@1f22c000 { 284 compatible = "apm,xgene-device-clock"; 285 #clock-cells = <1>; 286 clocks = <&socplldiv2>; 287 reg = <0x0 0x1f22c000 0x0 0x1000>; 288 reg-names = "csr-reg"; 289 clock-output-names = "sataphy2clk"; 290 status = "okay"; 291 csr-offset = <0x4>; 292 csr-mask = <0x3a>; 293 enable-offset = <0x0>; 294 enable-mask = <0x06>; 295 }; 296 297 sataphy3clk: sataphy1clk@1f23c000 { 298 compatible = "apm,xgene-device-clock"; 299 #clock-cells = <1>; 300 clocks = <&socplldiv2>; 301 reg = <0x0 0x1f23c000 0x0 0x1000>; 302 reg-names = "csr-reg"; 303 clock-output-names = "sataphy3clk"; 304 status = "okay"; 305 csr-offset = <0x4>; 306 csr-mask = <0x3a>; 307 enable-offset = <0x0>; 308 enable-mask = <0x06>; 309 }; 310 311 sata01clk: sata01clk@1f21c000 { 312 compatible = "apm,xgene-device-clock"; 313 #clock-cells = <1>; 314 clocks = <&socplldiv2>; 315 reg = <0x0 0x1f21c000 0x0 0x1000>; 316 reg-names = "csr-reg"; 317 clock-output-names = "sata01clk"; 318 csr-offset = <0x4>; 319 csr-mask = <0x05>; 320 enable-offset = <0x0>; 321 enable-mask = <0x39>; 322 }; 323 324 sata23clk: sata23clk@1f22c000 { 325 compatible = "apm,xgene-device-clock"; 326 #clock-cells = <1>; 327 clocks = <&socplldiv2>; 328 reg = <0x0 0x1f22c000 0x0 0x1000>; 329 reg-names = "csr-reg"; 330 clock-output-names = "sata23clk"; 331 csr-offset = <0x4>; 332 csr-mask = <0x05>; 333 enable-offset = <0x0>; 334 enable-mask = <0x39>; 335 }; 336 337 sata45clk: sata45clk@1f23c000 { 338 compatible = "apm,xgene-device-clock"; 339 #clock-cells = <1>; 340 clocks = <&socplldiv2>; 341 reg = <0x0 0x1f23c000 0x0 0x1000>; 342 reg-names = "csr-reg"; 343 clock-output-names = "sata45clk"; 344 csr-offset = <0x4>; 345 csr-mask = <0x05>; 346 enable-offset = <0x0>; 347 enable-mask = <0x39>; 348 }; 349 350 rtcclk: rtcclk@17000000 { 351 compatible = "apm,xgene-device-clock"; 352 #clock-cells = <1>; 353 clocks = <&socplldiv2>; 354 reg = <0x0 0x17000000 0x0 0x2000>; 355 reg-names = "csr-reg"; 356 csr-offset = <0xc>; 357 csr-mask = <0x2>; 358 enable-offset = <0x10>; 359 enable-mask = <0x2>; 360 clock-output-names = "rtcclk"; 361 }; 362 363 rngpkaclk: rngpkaclk@17000000 { 364 compatible = "apm,xgene-device-clock"; 365 #clock-cells = <1>; 366 clocks = <&socplldiv2>; 367 reg = <0x0 0x17000000 0x0 0x2000>; 368 reg-names = "csr-reg"; 369 csr-offset = <0xc>; 370 csr-mask = <0x10>; 371 enable-offset = <0x10>; 372 enable-mask = <0x10>; 373 clock-output-names = "rngpkaclk"; 374 }; 375 376 pcie0clk: pcie0clk@1f2bc000 { 377 status = "disabled"; 378 compatible = "apm,xgene-device-clock"; 379 #clock-cells = <1>; 380 clocks = <&socplldiv2>; 381 reg = <0x0 0x1f2bc000 0x0 0x1000>; 382 reg-names = "csr-reg"; 383 clock-output-names = "pcie0clk"; 384 }; 385 386 pcie1clk: pcie1clk@1f2cc000 { 387 status = "disabled"; 388 compatible = "apm,xgene-device-clock"; 389 #clock-cells = <1>; 390 clocks = <&socplldiv2>; 391 reg = <0x0 0x1f2cc000 0x0 0x1000>; 392 reg-names = "csr-reg"; 393 clock-output-names = "pcie1clk"; 394 }; 395 396 pcie2clk: pcie2clk@1f2dc000 { 397 status = "disabled"; 398 compatible = "apm,xgene-device-clock"; 399 #clock-cells = <1>; 400 clocks = <&socplldiv2>; 401 reg = <0x0 0x1f2dc000 0x0 0x1000>; 402 reg-names = "csr-reg"; 403 clock-output-names = "pcie2clk"; 404 }; 405 406 pcie3clk: pcie3clk@1f50c000 { 407 status = "disabled"; 408 compatible = "apm,xgene-device-clock"; 409 #clock-cells = <1>; 410 clocks = <&socplldiv2>; 411 reg = <0x0 0x1f50c000 0x0 0x1000>; 412 reg-names = "csr-reg"; 413 clock-output-names = "pcie3clk"; 414 }; 415 416 pcie4clk: pcie4clk@1f51c000 { 417 status = "disabled"; 418 compatible = "apm,xgene-device-clock"; 419 #clock-cells = <1>; 420 clocks = <&socplldiv2>; 421 reg = <0x0 0x1f51c000 0x0 0x1000>; 422 reg-names = "csr-reg"; 423 clock-output-names = "pcie4clk"; 424 }; 425 426 dmaclk: dmaclk@1f27c000 { 427 compatible = "apm,xgene-device-clock"; 428 #clock-cells = <1>; 429 clocks = <&socplldiv2>; 430 reg = <0x0 0x1f27c000 0x0 0x1000>; 431 reg-names = "csr-reg"; 432 clock-output-names = "dmaclk"; 433 }; 434 }; 435 436 msi: msi@79000000 { 437 compatible = "apm,xgene1-msi"; 438 msi-controller; 439 reg = <0x00 0x79000000 0x0 0x900000>; 440 interrupts = < 0x0 0x10 0x4 441 0x0 0x11 0x4 442 0x0 0x12 0x4 443 0x0 0x13 0x4 444 0x0 0x14 0x4 445 0x0 0x15 0x4 446 0x0 0x16 0x4 447 0x0 0x17 0x4 448 0x0 0x18 0x4 449 0x0 0x19 0x4 450 0x0 0x1a 0x4 451 0x0 0x1b 0x4 452 0x0 0x1c 0x4 453 0x0 0x1d 0x4 454 0x0 0x1e 0x4 455 0x0 0x1f 0x4>; 456 }; 457 458 scu: system-clk-controller@17000000 { 459 compatible = "apm,xgene-scu","syscon"; 460 reg = <0x0 0x17000000 0x0 0x400>; 461 }; 462 463 reboot: reboot@17000014 { 464 compatible = "syscon-reboot"; 465 reg = <0x0 0x17000014 0x0 0x4>; 466 regmap = <&scu>; 467 offset = <0x14>; 468 mask = <0x1>; 469 }; 470 471 csw: csw@7e200000 { 472 compatible = "apm,xgene-csw", "syscon"; 473 reg = <0x0 0x7e200000 0x0 0x1000>; 474 }; 475 476 mcba: mcba@7e700000 { 477 compatible = "apm,xgene-mcb", "syscon"; 478 reg = <0x0 0x7e700000 0x0 0x1000>; 479 }; 480 481 mcbb: mcbb@7e720000 { 482 compatible = "apm,xgene-mcb", "syscon"; 483 reg = <0x0 0x7e720000 0x0 0x1000>; 484 }; 485 486 efuse: efuse@1054a000 { 487 compatible = "apm,xgene-efuse", "syscon"; 488 reg = <0x0 0x1054a000 0x0 0x20>; 489 }; 490 491 rb: rb@7e000000 { 492 compatible = "apm,xgene-rb", "syscon"; 493 reg = <0x0 0x7e000000 0x0 0x10>; 494 }; 495 496 edac@78800000 { 497 compatible = "apm,xgene-edac"; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 regmap-csw = <&csw>; 502 regmap-mcba = <&mcba>; 503 regmap-mcbb = <&mcbb>; 504 regmap-efuse = <&efuse>; 505 regmap-rb = <&rb>; 506 reg = <0x0 0x78800000 0x0 0x100>; 507 interrupts = <0x0 0x20 0x4>, 508 <0x0 0x21 0x4>, 509 <0x0 0x27 0x4>; 510 511 edacmc@7e800000 { 512 compatible = "apm,xgene-edac-mc"; 513 reg = <0x0 0x7e800000 0x0 0x1000>; 514 memory-controller = <0>; 515 }; 516 517 edacmc@7e840000 { 518 compatible = "apm,xgene-edac-mc"; 519 reg = <0x0 0x7e840000 0x0 0x1000>; 520 memory-controller = <1>; 521 }; 522 523 edacmc@7e880000 { 524 compatible = "apm,xgene-edac-mc"; 525 reg = <0x0 0x7e880000 0x0 0x1000>; 526 memory-controller = <2>; 527 }; 528 529 edacmc@7e8c0000 { 530 compatible = "apm,xgene-edac-mc"; 531 reg = <0x0 0x7e8c0000 0x0 0x1000>; 532 memory-controller = <3>; 533 }; 534 535 edacpmd@7c000000 { 536 compatible = "apm,xgene-edac-pmd"; 537 reg = <0x0 0x7c000000 0x0 0x200000>; 538 pmd-controller = <0>; 539 }; 540 541 edacpmd@7c200000 { 542 compatible = "apm,xgene-edac-pmd"; 543 reg = <0x0 0x7c200000 0x0 0x200000>; 544 pmd-controller = <1>; 545 }; 546 547 edacpmd@7c400000 { 548 compatible = "apm,xgene-edac-pmd"; 549 reg = <0x0 0x7c400000 0x0 0x200000>; 550 pmd-controller = <2>; 551 }; 552 553 edacpmd@7c600000 { 554 compatible = "apm,xgene-edac-pmd"; 555 reg = <0x0 0x7c600000 0x0 0x200000>; 556 pmd-controller = <3>; 557 }; 558 559 edacl3@7e600000 { 560 compatible = "apm,xgene-edac-l3"; 561 reg = <0x0 0x7e600000 0x0 0x1000>; 562 }; 563 564 edacsoc@7e930000 { 565 compatible = "apm,xgene-edac-soc-v1"; 566 reg = <0x0 0x7e930000 0x0 0x1000>; 567 }; 568 }; 569 570 pmu: pmu@78810000 { 571 compatible = "apm,xgene-pmu-v2"; 572 #address-cells = <2>; 573 #size-cells = <2>; 574 ranges; 575 regmap-csw = <&csw>; 576 regmap-mcba = <&mcba>; 577 regmap-mcbb = <&mcbb>; 578 reg = <0x0 0x78810000 0x0 0x1000>; 579 interrupts = <0x0 0x22 0x4>; 580 581 pmul3c@7e610000 { 582 compatible = "apm,xgene-pmu-l3c"; 583 reg = <0x0 0x7e610000 0x0 0x1000>; 584 }; 585 586 pmuiob@7e940000 { 587 compatible = "apm,xgene-pmu-iob"; 588 reg = <0x0 0x7e940000 0x0 0x1000>; 589 }; 590 591 pmucmcb@7e710000 { 592 compatible = "apm,xgene-pmu-mcb"; 593 reg = <0x0 0x7e710000 0x0 0x1000>; 594 enable-bit-index = <0>; 595 }; 596 597 pmucmcb@7e730000 { 598 compatible = "apm,xgene-pmu-mcb"; 599 reg = <0x0 0x7e730000 0x0 0x1000>; 600 enable-bit-index = <1>; 601 }; 602 603 pmucmc@7e810000 { 604 compatible = "apm,xgene-pmu-mc"; 605 reg = <0x0 0x7e810000 0x0 0x1000>; 606 enable-bit-index = <0>; 607 }; 608 609 pmucmc@7e850000 { 610 compatible = "apm,xgene-pmu-mc"; 611 reg = <0x0 0x7e850000 0x0 0x1000>; 612 enable-bit-index = <1>; 613 }; 614 615 pmucmc@7e890000 { 616 compatible = "apm,xgene-pmu-mc"; 617 reg = <0x0 0x7e890000 0x0 0x1000>; 618 enable-bit-index = <2>; 619 }; 620 621 pmucmc@7e8d0000 { 622 compatible = "apm,xgene-pmu-mc"; 623 reg = <0x0 0x7e8d0000 0x0 0x1000>; 624 enable-bit-index = <3>; 625 }; 626 }; 627 628 pcie0: pcie@1f2b0000 { 629 status = "disabled"; 630 device_type = "pci"; 631 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 632 #interrupt-cells = <1>; 633 #size-cells = <2>; 634 #address-cells = <3>; 635 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 636 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 637 reg-names = "csr", "cfg"; 638 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 639 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ 640 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ 641 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 642 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 643 bus-range = <0x00 0xff>; 644 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 645 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 646 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 647 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 648 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; 649 dma-coherent; 650 clocks = <&pcie0clk 0>; 651 msi-parent = <&msi>; 652 }; 653 654 pcie1: pcie@1f2c0000 { 655 status = "disabled"; 656 device_type = "pci"; 657 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 658 #interrupt-cells = <1>; 659 #size-cells = <2>; 660 #address-cells = <3>; 661 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 662 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 663 reg-names = "csr", "cfg"; 664 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ 665 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ 666 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ 667 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 668 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 669 bus-range = <0x00 0xff>; 670 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 671 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 672 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 673 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 674 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; 675 dma-coherent; 676 clocks = <&pcie1clk 0>; 677 msi-parent = <&msi>; 678 }; 679 680 pcie2: pcie@1f2d0000 { 681 status = "disabled"; 682 device_type = "pci"; 683 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 684 #interrupt-cells = <1>; 685 #size-cells = <2>; 686 #address-cells = <3>; 687 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ 688 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ 689 reg-names = "csr", "cfg"; 690 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ 691 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ 692 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ 693 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 694 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 695 bus-range = <0x00 0xff>; 696 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 697 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 698 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 699 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 700 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; 701 dma-coherent; 702 clocks = <&pcie2clk 0>; 703 msi-parent = <&msi>; 704 }; 705 706 pcie3: pcie@1f500000 { 707 status = "disabled"; 708 device_type = "pci"; 709 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 710 #interrupt-cells = <1>; 711 #size-cells = <2>; 712 #address-cells = <3>; 713 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ 714 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 715 reg-names = "csr", "cfg"; 716 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 717 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ 718 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 719 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 720 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 721 bus-range = <0x00 0xff>; 722 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 723 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 724 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 725 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 726 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; 727 dma-coherent; 728 clocks = <&pcie3clk 0>; 729 msi-parent = <&msi>; 730 }; 731 732 pcie4: pcie@1f510000 { 733 status = "disabled"; 734 device_type = "pci"; 735 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 736 #interrupt-cells = <1>; 737 #size-cells = <2>; 738 #address-cells = <3>; 739 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ 740 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ 741 reg-names = "csr", "cfg"; 742 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 743 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ 744 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ 745 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 746 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 747 bus-range = <0x00 0xff>; 748 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 749 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 750 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 751 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 752 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; 753 dma-coherent; 754 clocks = <&pcie4clk 0>; 755 msi-parent = <&msi>; 756 }; 757 758 mailbox: mailbox@10540000 { 759 compatible = "apm,xgene-slimpro-mbox"; 760 reg = <0x0 0x10540000 0x0 0xa000>; 761 #mbox-cells = <1>; 762 interrupts = <0x0 0x0 0x4>, 763 <0x0 0x1 0x4>, 764 <0x0 0x2 0x4>, 765 <0x0 0x3 0x4>, 766 <0x0 0x4 0x4>, 767 <0x0 0x5 0x4>, 768 <0x0 0x6 0x4>, 769 <0x0 0x7 0x4>; 770 }; 771 772 serial0: serial@1c020000 { 773 status = "disabled"; 774 compatible = "ns16550a"; 775 reg = <0 0x1c020000 0x0 0x1000>; 776 reg-shift = <2>; 777 clock-frequency = <10000000>; /* Updated by bootloader */ 778 interrupt-parent = <&gic>; 779 interrupts = <0x0 0x4c 0x4>; 780 }; 781 782 serial1: serial@1c021000 { 783 status = "disabled"; 784 compatible = "ns16550a"; 785 reg = <0 0x1c021000 0x0 0x1000>; 786 reg-shift = <2>; 787 clock-frequency = <10000000>; /* Updated by bootloader */ 788 interrupt-parent = <&gic>; 789 interrupts = <0x0 0x4d 0x4>; 790 }; 791 792 serial2: serial@1c022000 { 793 status = "disabled"; 794 compatible = "ns16550a"; 795 reg = <0 0x1c022000 0x0 0x1000>; 796 reg-shift = <2>; 797 clock-frequency = <10000000>; /* Updated by bootloader */ 798 interrupt-parent = <&gic>; 799 interrupts = <0x0 0x4e 0x4>; 800 }; 801 802 serial3: serial@1c023000 { 803 status = "disabled"; 804 compatible = "ns16550a"; 805 reg = <0 0x1c023000 0x0 0x1000>; 806 reg-shift = <2>; 807 clock-frequency = <10000000>; /* Updated by bootloader */ 808 interrupt-parent = <&gic>; 809 interrupts = <0x0 0x4f 0x4>; 810 }; 811 812 mmc0: mmc@1c000000 { 813 compatible = "arasan,sdhci-4.9a"; 814 reg = <0x0 0x1c000000 0x0 0x100>; 815 interrupts = <0x0 0x49 0x4>; 816 dma-coherent; 817 no-1-8-v; 818 clock-names = "clk_xin", "clk_ahb"; 819 clocks = <&sdioclk 0>, <&ahbclk 0>; 820 }; 821 822 gfcgpio: gpio0@1701c000 { 823 compatible = "apm,xgene-gpio"; 824 reg = <0x0 0x1701c000 0x0 0x40>; 825 gpio-controller; 826 #gpio-cells = <2>; 827 }; 828 829 dwgpio: gpio@1c024000 { 830 compatible = "snps,dw-apb-gpio"; 831 reg = <0x0 0x1c024000 0x0 0x1000>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 835 porta: gpio-controller@0 { 836 compatible = "snps,dw-apb-gpio-port"; 837 gpio-controller; 838 #gpio-cells = <2>; 839 snps,nr-gpios = <32>; 840 reg = <0>; 841 }; 842 }; 843 844 i2c0: i2c@10512000 { 845 status = "disabled"; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 compatible = "snps,designware-i2c"; 849 reg = <0x0 0x10512000 0x0 0x1000>; 850 interrupts = <0 0x44 0x4>; 851 clocks = <&ahbclk 0>; 852 }; 853 854 phy1: phy@1f21a000 { 855 compatible = "apm,xgene-phy"; 856 reg = <0x0 0x1f21a000 0x0 0x100>; 857 #phy-cells = <1>; 858 clocks = <&sataphy1clk 0>; 859 status = "disabled"; 860 apm,tx-boost-gain = <30 30 30 30 30 30>; 861 apm,tx-eye-tuning = <2 10 10 2 10 10>; 862 }; 863 864 phy2: phy@1f22a000 { 865 compatible = "apm,xgene-phy"; 866 reg = <0x0 0x1f22a000 0x0 0x100>; 867 #phy-cells = <1>; 868 clocks = <&sataphy2clk 0>; 869 status = "okay"; 870 apm,tx-boost-gain = <30 30 30 30 30 30>; 871 apm,tx-eye-tuning = <1 10 10 2 10 10>; 872 }; 873 874 phy3: phy@1f23a000 { 875 compatible = "apm,xgene-phy"; 876 reg = <0x0 0x1f23a000 0x0 0x100>; 877 #phy-cells = <1>; 878 clocks = <&sataphy3clk 0>; 879 status = "okay"; 880 apm,tx-boost-gain = <31 31 31 31 31 31>; 881 apm,tx-eye-tuning = <2 10 10 2 10 10>; 882 }; 883 884 sata1: sata@1a000000 { 885 compatible = "apm,xgene-ahci"; 886 reg = <0x0 0x1a000000 0x0 0x1000>, 887 <0x0 0x1f210000 0x0 0x1000>, 888 <0x0 0x1f21d000 0x0 0x1000>, 889 <0x0 0x1f21e000 0x0 0x1000>, 890 <0x0 0x1f217000 0x0 0x1000>; 891 interrupts = <0x0 0x86 0x4>; 892 dma-coherent; 893 status = "disabled"; 894 clocks = <&sata01clk 0>; 895 phys = <&phy1 0>; 896 phy-names = "sata-phy"; 897 }; 898 899 sata2: sata@1a400000 { 900 compatible = "apm,xgene-ahci"; 901 reg = <0x0 0x1a400000 0x0 0x1000>, 902 <0x0 0x1f220000 0x0 0x1000>, 903 <0x0 0x1f22d000 0x0 0x1000>, 904 <0x0 0x1f22e000 0x0 0x1000>, 905 <0x0 0x1f227000 0x0 0x1000>; 906 interrupts = <0x0 0x87 0x4>; 907 dma-coherent; 908 status = "okay"; 909 clocks = <&sata23clk 0>; 910 phys = <&phy2 0>; 911 phy-names = "sata-phy"; 912 }; 913 914 sata3: sata@1a800000 { 915 compatible = "apm,xgene-ahci"; 916 reg = <0x0 0x1a800000 0x0 0x1000>, 917 <0x0 0x1f230000 0x0 0x1000>, 918 <0x0 0x1f23d000 0x0 0x1000>, 919 <0x0 0x1f23e000 0x0 0x1000>; 920 interrupts = <0x0 0x88 0x4>; 921 dma-coherent; 922 status = "okay"; 923 clocks = <&sata45clk 0>; 924 phys = <&phy3 0>; 925 phy-names = "sata-phy"; 926 }; 927 928 /* Node-name might need to be coded as dwusb for backward compatibility */ 929 usb0: usb@19000000 { 930 status = "disabled"; 931 compatible = "snps,dwc3"; 932 reg = <0x0 0x19000000 0x0 0x100000>; 933 interrupts = <0x0 0x89 0x4>; 934 dma-coherent; 935 dr_mode = "host"; 936 }; 937 938 usb1: usb@19800000 { 939 status = "disabled"; 940 compatible = "snps,dwc3"; 941 reg = <0x0 0x19800000 0x0 0x100000>; 942 interrupts = <0x0 0x8a 0x4>; 943 dma-coherent; 944 dr_mode = "host"; 945 }; 946 947 sbgpio: gpio@17001000 { 948 compatible = "apm,xgene-gpio-sb"; 949 reg = <0x0 0x17001000 0x0 0x400>; 950 #gpio-cells = <2>; 951 gpio-controller; 952 interrupts = <0x0 0x28 0x1>, 953 <0x0 0x29 0x1>, 954 <0x0 0x2a 0x1>, 955 <0x0 0x2b 0x1>, 956 <0x0 0x2c 0x1>, 957 <0x0 0x2d 0x1>; 958 interrupt-parent = <&gic>; 959 #interrupt-cells = <2>; 960 interrupt-controller; 961 }; 962 963 rtc: rtc@10510000 { 964 compatible = "apm,xgene-rtc"; 965 reg = <0x0 0x10510000 0x0 0x400>; 966 interrupts = <0x0 0x46 0x4>; 967 #clock-cells = <1>; 968 clocks = <&rtcclk 0>; 969 }; 970 971 mdio: mdio@17020000 { 972 compatible = "apm,xgene-mdio-rgmii"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 reg = <0x0 0x17020000 0x0 0xd100>; 976 clocks = <&menetclk 0>; 977 }; 978 979 menet: ethernet@17020000 { 980 compatible = "apm,xgene-enet"; 981 status = "disabled"; 982 reg = <0x0 0x17020000 0x0 0xd100>, 983 <0x0 0x17030000 0x0 0xc300>, 984 <0x0 0x10000000 0x0 0x200>; 985 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 986 interrupts = <0x0 0x3c 0x4>; 987 dma-coherent; 988 clocks = <&menetclk 0>; 989 /* mac address will be overwritten by the bootloader */ 990 local-mac-address = [00 00 00 00 00 00]; 991 phy-connection-type = "rgmii"; 992 phy-handle = <&menetphy>,<&menet0phy>; 993 mdio { 994 compatible = "apm,xgene-mdio"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 menetphy: ethernet-phy@3 { 998 compatible = "ethernet-phy-id001c.c915"; 999 reg = <0x3>; 1000 }; 1001 1002 }; 1003 }; 1004 1005 sgenet0: ethernet@1f210000 { 1006 compatible = "apm,xgene1-sgenet"; 1007 status = "disabled"; 1008 reg = <0x0 0x1f210000 0x0 0xd100>, 1009 <0x0 0x1f200000 0x0 0xc300>, 1010 <0x0 0x1b000000 0x0 0x200>; 1011 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1012 interrupts = <0x0 0xa0 0x4>, 1013 <0x0 0xa1 0x4>; 1014 dma-coherent; 1015 clocks = <&sge0clk 0>; 1016 local-mac-address = [00 00 00 00 00 00]; 1017 phy-connection-type = "sgmii"; 1018 phy-handle = <&sgenet0phy>; 1019 }; 1020 1021 sgenet1: ethernet@1f210030 { 1022 compatible = "apm,xgene1-sgenet"; 1023 status = "disabled"; 1024 reg = <0x0 0x1f210030 0x0 0xd100>, 1025 <0x0 0x1f200000 0x0 0xc300>, 1026 <0x0 0x1b000000 0x0 0x8000>; 1027 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1028 interrupts = <0x0 0xac 0x4>, 1029 <0x0 0xad 0x4>; 1030 port-id = <1>; 1031 dma-coherent; 1032 local-mac-address = [00 00 00 00 00 00]; 1033 phy-connection-type = "sgmii"; 1034 phy-handle = <&sgenet1phy>; 1035 }; 1036 1037 xgenet: ethernet@1f610000 { 1038 compatible = "apm,xgene1-xgenet"; 1039 status = "disabled"; 1040 reg = <0x0 0x1f610000 0x0 0xd100>, 1041 <0x0 0x1f600000 0x0 0xc300>, 1042 <0x0 0x18000000 0x0 0x200>; 1043 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1044 interrupts = <0x0 0x60 0x4>, 1045 <0x0 0x61 0x4>, 1046 <0x0 0x62 0x4>, 1047 <0x0 0x63 0x4>, 1048 <0x0 0x64 0x4>, 1049 <0x0 0x65 0x4>, 1050 <0x0 0x66 0x4>, 1051 <0x0 0x67 0x4>; 1052 channel = <0>; 1053 dma-coherent; 1054 clocks = <&xge0clk 0>; 1055 /* mac address will be overwritten by the bootloader */ 1056 local-mac-address = [00 00 00 00 00 00]; 1057 phy-connection-type = "xgmii"; 1058 }; 1059 1060 xgenet1: ethernet@1f620000 { 1061 compatible = "apm,xgene1-xgenet"; 1062 status = "disabled"; 1063 reg = <0x0 0x1f620000 0x0 0xd100>, 1064 <0x0 0x1f600000 0x0 0xc300>, 1065 <0x0 0x18000000 0x0 0x8000>; 1066 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1067 interrupts = <0x0 0x6c 0x4>, 1068 <0x0 0x6d 0x4>; 1069 port-id = <1>; 1070 dma-coherent; 1071 clocks = <&xge1clk 0>; 1072 /* mac address will be overwritten by the bootloader */ 1073 local-mac-address = [00 00 00 00 00 00]; 1074 phy-connection-type = "xgmii"; 1075 }; 1076 1077 rng: rng@10520000 { 1078 compatible = "apm,xgene-rng"; 1079 reg = <0x0 0x10520000 0x0 0x100>; 1080 interrupts = <0x0 0x41 0x4>; 1081 clocks = <&rngpkaclk 0>; 1082 }; 1083 1084 dma: dma@1f270000 { 1085 compatible = "apm,xgene-storm-dma"; 1086 reg = <0x0 0x1f270000 0x0 0x10000>, 1087 <0x0 0x1f200000 0x0 0x10000>, 1088 <0x0 0x1b000000 0x0 0x400000>, 1089 <0x0 0x1054a000 0x0 0x100>; 1090 interrupts = <0x0 0x82 0x4>, 1091 <0x0 0xb8 0x4>, 1092 <0x0 0xb9 0x4>, 1093 <0x0 0xba 0x4>, 1094 <0x0 0xbb 0x4>; 1095 dma-coherent; 1096 clocks = <&dmaclk 0>; 1097 }; 1098 }; 1099}; 1100