1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/debugfs.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_bridge.h>
17 #include <drm/drm_device.h>
18 #include <drm/drm_panel.h>
19 #include <drm/drm_print.h>
20 #include <drm/drm_probe_helper.h>
21
22 #include "sti_awg_utils.h"
23 #include "sti_drv.h"
24 #include "sti_mixer.h"
25
26 /* DVO registers */
27 #define DVO_AWG_DIGSYNC_CTRL 0x0000
28 #define DVO_DOF_CFG 0x0004
29 #define DVO_LUT_PROG_LOW 0x0008
30 #define DVO_LUT_PROG_MID 0x000C
31 #define DVO_LUT_PROG_HIGH 0x0010
32 #define DVO_DIGSYNC_INSTR_I 0x0100
33
34 #define DVO_AWG_CTRL_EN BIT(0)
35 #define DVO_AWG_FRAME_BASED_SYNC BIT(2)
36
37 #define DVO_DOF_EN_LOWBYTE BIT(0)
38 #define DVO_DOF_EN_MIDBYTE BIT(1)
39 #define DVO_DOF_EN_HIGHBYTE BIT(2)
40 #define DVO_DOF_EN BIT(6)
41 #define DVO_DOF_MOD_COUNT_SHIFT 8
42
43 #define DVO_LUT_ZERO 0
44 #define DVO_LUT_Y_G 1
45 #define DVO_LUT_Y_G_DEL 2
46 #define DVO_LUT_CB_B 3
47 #define DVO_LUT_CB_B_DEL 4
48 #define DVO_LUT_CR_R 5
49 #define DVO_LUT_CR_R_DEL 6
50 #define DVO_LUT_HOLD 7
51
52 struct dvo_config {
53 u32 flags;
54 u32 lowbyte;
55 u32 midbyte;
56 u32 highbyte;
57 int (*awg_fwgen_fct)(
58 struct awg_code_generation_params *fw_gen_params,
59 struct awg_timing *timing);
60 };
61
62 static struct dvo_config rgb_24bit_de_cfg = {
63 .flags = (0L << DVO_DOF_MOD_COUNT_SHIFT),
64 .lowbyte = DVO_LUT_CR_R,
65 .midbyte = DVO_LUT_Y_G,
66 .highbyte = DVO_LUT_CB_B,
67 .awg_fwgen_fct = sti_awg_generate_code_data_enable_mode,
68 };
69
70 /*
71 * STI digital video output structure
72 *
73 * @dev: driver device
74 * @drm_dev: pointer to drm device
75 * @mode: current display mode selected
76 * @regs: dvo registers
77 * @clk_pix: pixel clock for dvo
78 * @clk: clock for dvo
79 * @clk_main_parent: dvo parent clock if main path used
80 * @clk_aux_parent: dvo parent clock if aux path used
81 * @panel_node: panel node reference from device tree
82 * @panel: reference to the panel connected to the dvo
83 * @enabled: true if dvo is enabled else false
84 * @encoder: drm_encoder it is bound
85 */
86 struct sti_dvo {
87 struct device dev;
88 struct drm_device *drm_dev;
89 struct drm_display_mode mode;
90 void __iomem *regs;
91 struct clk *clk_pix;
92 struct clk *clk;
93 struct clk *clk_main_parent;
94 struct clk *clk_aux_parent;
95 struct device_node *panel_node;
96 struct drm_panel *panel;
97 struct dvo_config *config;
98 bool enabled;
99 struct drm_encoder *encoder;
100 struct drm_bridge bridge;
101 };
102
103 struct sti_dvo_connector {
104 struct drm_connector drm_connector;
105 struct drm_encoder *encoder;
106 struct sti_dvo *dvo;
107 };
108
109 #define to_sti_dvo_connector(x) \
110 container_of(x, struct sti_dvo_connector, drm_connector)
111
112 #define BLANKING_LEVEL 16
dvo_awg_generate_code(struct sti_dvo * dvo,u8 * ram_size,u32 * ram_code)113 static int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code)
114 {
115 struct drm_display_mode *mode = &dvo->mode;
116 struct dvo_config *config = dvo->config;
117 struct awg_code_generation_params fw_gen_params;
118 struct awg_timing timing;
119
120 fw_gen_params.ram_code = ram_code;
121 fw_gen_params.instruction_offset = 0;
122
123 timing.total_lines = mode->vtotal;
124 timing.active_lines = mode->vdisplay;
125 timing.blanking_lines = mode->vsync_start - mode->vdisplay;
126 timing.trailing_lines = mode->vtotal - mode->vsync_start;
127 timing.total_pixels = mode->htotal;
128 timing.active_pixels = mode->hdisplay;
129 timing.blanking_pixels = mode->hsync_start - mode->hdisplay;
130 timing.trailing_pixels = mode->htotal - mode->hsync_start;
131 timing.blanking_level = BLANKING_LEVEL;
132
133 if (config->awg_fwgen_fct(&fw_gen_params, &timing)) {
134 DRM_ERROR("AWG firmware not properly generated\n");
135 return -EINVAL;
136 }
137
138 *ram_size = fw_gen_params.instruction_offset;
139
140 return 0;
141 }
142
143 /* Configure AWG, writing instructions
144 *
145 * @dvo: pointer to DVO structure
146 * @awg_ram_code: pointer to AWG instructions table
147 * @nb: nb of AWG instructions
148 */
dvo_awg_configure(struct sti_dvo * dvo,u32 * awg_ram_code,int nb)149 static void dvo_awg_configure(struct sti_dvo *dvo, u32 *awg_ram_code, int nb)
150 {
151 int i;
152
153 DRM_DEBUG_DRIVER("\n");
154
155 for (i = 0; i < nb; i++)
156 writel(awg_ram_code[i],
157 dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4);
158 for (i = nb; i < AWG_MAX_INST; i++)
159 writel(0, dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4);
160
161 writel(DVO_AWG_CTRL_EN, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
162 }
163
164 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
165 readl(dvo->regs + reg))
166
dvo_dbg_awg_microcode(struct seq_file * s,void __iomem * reg)167 static void dvo_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
168 {
169 unsigned int i;
170
171 seq_puts(s, "\n\n");
172 seq_puts(s, " DVO AWG microcode:");
173 for (i = 0; i < AWG_MAX_INST; i++) {
174 if (i % 8 == 0)
175 seq_printf(s, "\n %04X:", i);
176 seq_printf(s, " %04X", readl(reg + i * 4));
177 }
178 }
179
dvo_dbg_show(struct seq_file * s,void * data)180 static int dvo_dbg_show(struct seq_file *s, void *data)
181 {
182 struct drm_info_node *node = s->private;
183 struct sti_dvo *dvo = (struct sti_dvo *)node->info_ent->data;
184
185 seq_printf(s, "DVO: (vaddr = 0x%p)", dvo->regs);
186 DBGFS_DUMP(DVO_AWG_DIGSYNC_CTRL);
187 DBGFS_DUMP(DVO_DOF_CFG);
188 DBGFS_DUMP(DVO_LUT_PROG_LOW);
189 DBGFS_DUMP(DVO_LUT_PROG_MID);
190 DBGFS_DUMP(DVO_LUT_PROG_HIGH);
191 dvo_dbg_awg_microcode(s, dvo->regs + DVO_DIGSYNC_INSTR_I);
192 seq_putc(s, '\n');
193 return 0;
194 }
195
196 static struct drm_info_list dvo_debugfs_files[] = {
197 { "dvo", dvo_dbg_show, 0, NULL },
198 };
199
dvo_debugfs_init(struct sti_dvo * dvo,struct drm_minor * minor)200 static void dvo_debugfs_init(struct sti_dvo *dvo, struct drm_minor *minor)
201 {
202 unsigned int i;
203
204 for (i = 0; i < ARRAY_SIZE(dvo_debugfs_files); i++)
205 dvo_debugfs_files[i].data = dvo;
206
207 drm_debugfs_create_files(dvo_debugfs_files,
208 ARRAY_SIZE(dvo_debugfs_files),
209 minor->debugfs_root, minor);
210 }
211
sti_dvo_disable(struct drm_bridge * bridge)212 static void sti_dvo_disable(struct drm_bridge *bridge)
213 {
214 struct sti_dvo *dvo = bridge->driver_private;
215
216 if (!dvo->enabled)
217 return;
218
219 DRM_DEBUG_DRIVER("\n");
220
221 if (dvo->config->awg_fwgen_fct)
222 writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
223
224 writel(0x00000000, dvo->regs + DVO_DOF_CFG);
225
226 drm_panel_disable(dvo->panel);
227
228 /* Disable/unprepare dvo clock */
229 clk_disable_unprepare(dvo->clk_pix);
230 clk_disable_unprepare(dvo->clk);
231
232 dvo->enabled = false;
233 }
234
sti_dvo_pre_enable(struct drm_bridge * bridge)235 static void sti_dvo_pre_enable(struct drm_bridge *bridge)
236 {
237 struct sti_dvo *dvo = bridge->driver_private;
238 struct dvo_config *config = dvo->config;
239 u32 val;
240
241 DRM_DEBUG_DRIVER("\n");
242
243 if (dvo->enabled)
244 return;
245
246 /* Make sure DVO is disabled */
247 writel(0x00000000, dvo->regs + DVO_DOF_CFG);
248 writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
249
250 if (config->awg_fwgen_fct) {
251 u8 nb_instr;
252 u32 awg_ram_code[AWG_MAX_INST];
253 /* Configure AWG */
254 if (!dvo_awg_generate_code(dvo, &nb_instr, awg_ram_code))
255 dvo_awg_configure(dvo, awg_ram_code, nb_instr);
256 else
257 return;
258 }
259
260 /* Prepare/enable clocks */
261 if (clk_prepare_enable(dvo->clk_pix))
262 DRM_ERROR("Failed to prepare/enable dvo_pix clk\n");
263 if (clk_prepare_enable(dvo->clk))
264 DRM_ERROR("Failed to prepare/enable dvo clk\n");
265
266 drm_panel_enable(dvo->panel);
267
268 /* Set LUT */
269 writel(config->lowbyte, dvo->regs + DVO_LUT_PROG_LOW);
270 writel(config->midbyte, dvo->regs + DVO_LUT_PROG_MID);
271 writel(config->highbyte, dvo->regs + DVO_LUT_PROG_HIGH);
272
273 /* Digital output formatter config */
274 val = (config->flags | DVO_DOF_EN);
275 writel(val, dvo->regs + DVO_DOF_CFG);
276
277 dvo->enabled = true;
278 }
279
sti_dvo_set_mode(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)280 static void sti_dvo_set_mode(struct drm_bridge *bridge,
281 const struct drm_display_mode *mode,
282 const struct drm_display_mode *adjusted_mode)
283 {
284 struct sti_dvo *dvo = bridge->driver_private;
285 struct sti_mixer *mixer = to_sti_mixer(dvo->encoder->crtc);
286 int rate = mode->clock * 1000;
287 struct clk *clkp;
288 int ret;
289
290 DRM_DEBUG_DRIVER("\n");
291
292 drm_mode_copy(&dvo->mode, mode);
293
294 /* According to the path used (main or aux), the dvo clocks should
295 * have a different parent clock. */
296 if (mixer->id == STI_MIXER_MAIN)
297 clkp = dvo->clk_main_parent;
298 else
299 clkp = dvo->clk_aux_parent;
300
301 if (clkp) {
302 clk_set_parent(dvo->clk_pix, clkp);
303 clk_set_parent(dvo->clk, clkp);
304 }
305
306 /* DVO clocks = compositor clock */
307 ret = clk_set_rate(dvo->clk_pix, rate);
308 if (ret < 0) {
309 DRM_ERROR("Cannot set rate (%dHz) for dvo_pix clk\n", rate);
310 return;
311 }
312
313 ret = clk_set_rate(dvo->clk, rate);
314 if (ret < 0) {
315 DRM_ERROR("Cannot set rate (%dHz) for dvo clk\n", rate);
316 return;
317 }
318
319 /* For now, we only support 24bit data enable (DE) synchro format */
320 dvo->config = &rgb_24bit_de_cfg;
321 }
322
sti_dvo_bridge_nope(struct drm_bridge * bridge)323 static void sti_dvo_bridge_nope(struct drm_bridge *bridge)
324 {
325 /* do nothing */
326 }
327
328 static const struct drm_bridge_funcs sti_dvo_bridge_funcs = {
329 .pre_enable = sti_dvo_pre_enable,
330 .enable = sti_dvo_bridge_nope,
331 .disable = sti_dvo_disable,
332 .post_disable = sti_dvo_bridge_nope,
333 .mode_set = sti_dvo_set_mode,
334 };
335
sti_dvo_connector_get_modes(struct drm_connector * connector)336 static int sti_dvo_connector_get_modes(struct drm_connector *connector)
337 {
338 struct sti_dvo_connector *dvo_connector
339 = to_sti_dvo_connector(connector);
340 struct sti_dvo *dvo = dvo_connector->dvo;
341
342 if (dvo->panel)
343 return drm_panel_get_modes(dvo->panel, connector);
344
345 return 0;
346 }
347
348 #define CLK_TOLERANCE_HZ 50
349
350 static enum drm_mode_status
sti_dvo_connector_mode_valid(struct drm_connector * connector,const struct drm_display_mode * mode)351 sti_dvo_connector_mode_valid(struct drm_connector *connector,
352 const struct drm_display_mode *mode)
353 {
354 int target = mode->clock * 1000;
355 int target_min = target - CLK_TOLERANCE_HZ;
356 int target_max = target + CLK_TOLERANCE_HZ;
357 int result;
358 struct sti_dvo_connector *dvo_connector
359 = to_sti_dvo_connector(connector);
360 struct sti_dvo *dvo = dvo_connector->dvo;
361
362 result = clk_round_rate(dvo->clk_pix, target);
363
364 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
365 target, result);
366
367 if ((result < target_min) || (result > target_max)) {
368 DRM_DEBUG_DRIVER("dvo pixclk=%d not supported\n", target);
369 return MODE_BAD;
370 }
371
372 return MODE_OK;
373 }
374
375 static const
376 struct drm_connector_helper_funcs sti_dvo_connector_helper_funcs = {
377 .get_modes = sti_dvo_connector_get_modes,
378 .mode_valid = sti_dvo_connector_mode_valid,
379 };
380
381 static enum drm_connector_status
sti_dvo_connector_detect(struct drm_connector * connector,bool force)382 sti_dvo_connector_detect(struct drm_connector *connector, bool force)
383 {
384 struct sti_dvo_connector *dvo_connector
385 = to_sti_dvo_connector(connector);
386 struct sti_dvo *dvo = dvo_connector->dvo;
387
388 DRM_DEBUG_DRIVER("\n");
389
390 if (!dvo->panel) {
391 dvo->panel = of_drm_find_panel(dvo->panel_node);
392 if (IS_ERR(dvo->panel))
393 dvo->panel = NULL;
394 }
395
396 if (dvo->panel)
397 return connector_status_connected;
398
399 return connector_status_disconnected;
400 }
401
sti_dvo_late_register(struct drm_connector * connector)402 static int sti_dvo_late_register(struct drm_connector *connector)
403 {
404 struct sti_dvo_connector *dvo_connector
405 = to_sti_dvo_connector(connector);
406 struct sti_dvo *dvo = dvo_connector->dvo;
407
408 dvo_debugfs_init(dvo, dvo->drm_dev->primary);
409
410 return 0;
411 }
412
413 static const struct drm_connector_funcs sti_dvo_connector_funcs = {
414 .fill_modes = drm_helper_probe_single_connector_modes,
415 .detect = sti_dvo_connector_detect,
416 .destroy = drm_connector_cleanup,
417 .reset = drm_atomic_helper_connector_reset,
418 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
419 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
420 .late_register = sti_dvo_late_register,
421 };
422
sti_dvo_find_encoder(struct drm_device * dev)423 static struct drm_encoder *sti_dvo_find_encoder(struct drm_device *dev)
424 {
425 struct drm_encoder *encoder;
426
427 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
428 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
429 return encoder;
430 }
431
432 return NULL;
433 }
434
sti_dvo_bind(struct device * dev,struct device * master,void * data)435 static int sti_dvo_bind(struct device *dev, struct device *master, void *data)
436 {
437 struct sti_dvo *dvo = dev_get_drvdata(dev);
438 struct drm_device *drm_dev = data;
439 struct drm_encoder *encoder;
440 struct sti_dvo_connector *connector;
441 struct drm_connector *drm_connector;
442 int err;
443
444 /* Set the drm device handle */
445 dvo->drm_dev = drm_dev;
446
447 encoder = sti_dvo_find_encoder(drm_dev);
448 if (!encoder)
449 return -ENOMEM;
450
451 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
452 if (!connector)
453 return -ENOMEM;
454
455 connector->dvo = dvo;
456
457 dvo->bridge.driver_private = dvo;
458 dvo->bridge.of_node = dvo->dev.of_node;
459 drm_bridge_add(&dvo->bridge);
460
461 err = drm_bridge_attach(encoder, &dvo->bridge, NULL, 0);
462 if (err)
463 return err;
464
465 connector->encoder = encoder;
466 dvo->encoder = encoder;
467
468 drm_connector = (struct drm_connector *)connector;
469
470 drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
471
472 drm_connector_init(drm_dev, drm_connector,
473 &sti_dvo_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
474 drm_connector_helper_add(drm_connector,
475 &sti_dvo_connector_helper_funcs);
476
477 err = drm_connector_attach_encoder(drm_connector, encoder);
478 if (err) {
479 DRM_ERROR("Failed to attach a connector to a encoder\n");
480 goto err_sysfs;
481 }
482
483 return 0;
484
485 err_sysfs:
486 drm_bridge_remove(&dvo->bridge);
487 return -EINVAL;
488 }
489
sti_dvo_unbind(struct device * dev,struct device * master,void * data)490 static void sti_dvo_unbind(struct device *dev,
491 struct device *master, void *data)
492 {
493 struct sti_dvo *dvo = dev_get_drvdata(dev);
494
495 drm_bridge_remove(&dvo->bridge);
496 }
497
498 static const struct component_ops sti_dvo_ops = {
499 .bind = sti_dvo_bind,
500 .unbind = sti_dvo_unbind,
501 };
502
sti_dvo_probe(struct platform_device * pdev)503 static int sti_dvo_probe(struct platform_device *pdev)
504 {
505 struct device *dev = &pdev->dev;
506 struct sti_dvo *dvo;
507 struct device_node *np = dev->of_node;
508
509 DRM_INFO("%s\n", __func__);
510
511 dvo = devm_drm_bridge_alloc(dev, struct sti_dvo, bridge, &sti_dvo_bridge_funcs);
512 if (IS_ERR(dvo)) {
513 DRM_ERROR("Failed to allocate DVO\n");
514 return PTR_ERR(dvo);
515 }
516
517 dvo->dev = pdev->dev;
518 dvo->regs = devm_platform_ioremap_resource_byname(pdev, "dvo-reg");
519 if (IS_ERR(dvo->regs))
520 return PTR_ERR(dvo->regs);
521
522 dvo->clk_pix = devm_clk_get(dev, "dvo_pix");
523 if (IS_ERR(dvo->clk_pix)) {
524 DRM_ERROR("Cannot get dvo_pix clock\n");
525 return PTR_ERR(dvo->clk_pix);
526 }
527
528 dvo->clk = devm_clk_get(dev, "dvo");
529 if (IS_ERR(dvo->clk)) {
530 DRM_ERROR("Cannot get dvo clock\n");
531 return PTR_ERR(dvo->clk);
532 }
533
534 dvo->clk_main_parent = devm_clk_get(dev, "main_parent");
535 if (IS_ERR(dvo->clk_main_parent)) {
536 DRM_DEBUG_DRIVER("Cannot get main_parent clock\n");
537 dvo->clk_main_parent = NULL;
538 }
539
540 dvo->clk_aux_parent = devm_clk_get(dev, "aux_parent");
541 if (IS_ERR(dvo->clk_aux_parent)) {
542 DRM_DEBUG_DRIVER("Cannot get aux_parent clock\n");
543 dvo->clk_aux_parent = NULL;
544 }
545
546 dvo->panel_node = of_parse_phandle(np, "sti,panel", 0);
547 if (!dvo->panel_node)
548 DRM_ERROR("No panel associated to the dvo output\n");
549 of_node_put(dvo->panel_node);
550
551 platform_set_drvdata(pdev, dvo);
552
553 return component_add(&pdev->dev, &sti_dvo_ops);
554 }
555
sti_dvo_remove(struct platform_device * pdev)556 static void sti_dvo_remove(struct platform_device *pdev)
557 {
558 component_del(&pdev->dev, &sti_dvo_ops);
559 }
560
561 static const struct of_device_id dvo_of_match[] = {
562 { .compatible = "st,stih407-dvo", },
563 { /* end node */ }
564 };
565 MODULE_DEVICE_TABLE(of, dvo_of_match);
566
567 struct platform_driver sti_dvo_driver = {
568 .driver = {
569 .name = "sti-dvo",
570 .of_match_table = dvo_of_match,
571 },
572 .probe = sti_dvo_probe,
573 .remove = sti_dvo_remove,
574 };
575
576 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
577 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
578 MODULE_LICENSE("GPL");
579