1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #ifndef __MT7915_H 5 #define __MT7915_H 6 7 #include <linux/interrupt.h> 8 #include <linux/ktime.h> 9 #include "../mt76_connac.h" 10 #include "regs.h" 11 12 #define MT7915_MAX_INTERFACES 19 13 #define MT7915_WTBL_SIZE 288 14 #define MT7916_WTBL_SIZE 544 15 #define MT7915_WTBL_RESERVED (mt7915_wtbl_size(dev) - 1) 16 #define MT7915_WTBL_STA (MT7915_WTBL_RESERVED - \ 17 MT7915_MAX_INTERFACES) 18 19 #define MT7915_WATCHDOG_TIME (HZ / 10) 20 #define MT7915_RESET_TIMEOUT (30 * HZ) 21 22 #define MT7915_TX_RING_SIZE 2048 23 #define MT7915_TX_MCU_RING_SIZE 256 24 #define MT7915_TX_FWDL_RING_SIZE 128 25 26 #define MT7915_RX_RING_SIZE 1536 27 #define MT7915_RX_MCU_RING_SIZE 512 28 29 #define MT7915_FIRMWARE_WA "mediatek/mt7915_wa.bin" 30 #define MT7915_FIRMWARE_WM "mediatek/mt7915_wm.bin" 31 #define MT7915_ROM_PATCH "mediatek/mt7915_rom_patch.bin" 32 33 #define MT7916_FIRMWARE_WA "mediatek/mt7916_wa.bin" 34 #define MT7916_FIRMWARE_WM "mediatek/mt7916_wm.bin" 35 #define MT7916_ROM_PATCH "mediatek/mt7916_rom_patch.bin" 36 37 #define MT7981_FIRMWARE_WA "mediatek/mt7981_wa.bin" 38 #define MT7981_FIRMWARE_WM "mediatek/mt7981_wm.bin" 39 #define MT7981_ROM_PATCH "mediatek/mt7981_rom_patch.bin" 40 41 #define MT7986_FIRMWARE_WA "mediatek/mt7986_wa.bin" 42 #define MT7986_FIRMWARE_WM "mediatek/mt7986_wm.bin" 43 #define MT7986_FIRMWARE_WM_MT7975 "mediatek/mt7986_wm_mt7975.bin" 44 #define MT7986_ROM_PATCH "mediatek/mt7986_rom_patch.bin" 45 #define MT7986_ROM_PATCH_MT7975 "mediatek/mt7986_rom_patch_mt7975.bin" 46 47 #define MT7915_EEPROM_DEFAULT "mediatek/mt7915_eeprom.bin" 48 #define MT7915_EEPROM_DEFAULT_DBDC "mediatek/mt7915_eeprom_dbdc.bin" 49 #define MT7916_EEPROM_DEFAULT "mediatek/mt7916_eeprom.bin" 50 51 #define MT7981_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7981_eeprom_mt7976_dbdc.bin" 52 53 #define MT7986_EEPROM_MT7975_DEFAULT "mediatek/mt7986_eeprom_mt7975.bin" 54 #define MT7986_EEPROM_MT7975_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7975_dual.bin" 55 #define MT7986_EEPROM_MT7976_DEFAULT "mediatek/mt7986_eeprom_mt7976.bin" 56 #define MT7986_EEPROM_MT7976_DEFAULT_DBDC "mediatek/mt7986_eeprom_mt7976_dbdc.bin" 57 #define MT7986_EEPROM_MT7976_DUAL_DEFAULT "mediatek/mt7986_eeprom_mt7976_dual.bin" 58 59 #define MT7915_EEPROM_SIZE 3584 60 #define MT7916_EEPROM_SIZE 4096 61 62 #define MT7915_EEPROM_BLOCK_SIZE 16 63 #define MT7915_HW_TOKEN_SIZE 4096 64 #define MT7915_TOKEN_SIZE 8192 65 66 #define MT7915_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 67 #define MT7915_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 68 69 #define MT7915_THERMAL_THROTTLE_MAX 100 70 #define MT7915_CDEV_THROTTLE_MAX 99 71 72 #define MT7915_SKU_RATE_NUM 161 73 #define MT7915_SKU_PATH_NUM 185 74 75 #define MT7915_MAX_TWT_AGRT 16 76 #define MT7915_MAX_STA_TWT_AGRT 8 77 #define MT7915_MIN_TWT_DUR 64 78 #define MT7915_MAX_QUEUE (MT_RXQ_BAND2 + __MT_MCUQ_MAX + 2) 79 80 #define MT7915_WED_RX_TOKEN_SIZE 12288 81 82 #define MT7915_CRIT_TEMP_IDX 0 83 #define MT7915_MAX_TEMP_IDX 1 84 #define MT7915_CRIT_TEMP 110 85 #define MT7915_MAX_TEMP 120 86 87 #define MT7915_RTS_LEN_THRES 0x92b 88 89 struct mt7915_vif; 90 struct mt7915_sta; 91 struct mt7915_dfs_pulse; 92 struct mt7915_dfs_pattern; 93 94 enum mt7915_txq_id { 95 MT7915_TXQ_FWDL = 16, 96 MT7915_TXQ_MCU_WM, 97 MT7915_TXQ_BAND0, 98 MT7915_TXQ_BAND1, 99 MT7915_TXQ_MCU_WA, 100 }; 101 102 enum mt7915_rxq_id { 103 MT7915_RXQ_BAND0 = 0, 104 MT7915_RXQ_BAND1, 105 MT7915_RXQ_MCU_WM = 0, 106 MT7915_RXQ_MCU_WA, 107 MT7915_RXQ_MCU_WA_EXT, 108 }; 109 110 enum mt7916_rxq_id { 111 MT7916_RXQ_MCU_WM = 0, 112 MT7916_RXQ_MCU_WA, 113 MT7916_RXQ_MCU_WA_MAIN, 114 MT7916_RXQ_MCU_WA_EXT, 115 MT7916_RXQ_BAND0, 116 MT7916_RXQ_BAND1, 117 }; 118 119 struct mt7915_twt_flow { 120 struct list_head list; 121 u64 start_tsf; 122 u64 tsf; 123 u32 duration; 124 u16 wcid; 125 __le16 mantissa; 126 u8 exp; 127 u8 table_id; 128 u8 id; 129 u8 protection:1; 130 u8 flowtype:1; 131 u8 trigger:1; 132 u8 sched:1; 133 }; 134 135 DECLARE_EWMA(avg_signal, 10, 8) 136 137 struct mt7915_sta { 138 struct mt76_wcid wcid; /* must be first */ 139 140 struct mt7915_vif *vif; 141 142 struct list_head rc_list; 143 u32 airtime_ac[8]; 144 145 int ack_signal; 146 struct ewma_avg_signal avg_ack_signal; 147 148 unsigned long changed; 149 unsigned long jiffies; 150 struct mt76_connac_sta_key_conf bip; 151 152 struct { 153 u8 flowid_mask; 154 struct mt7915_twt_flow flow[MT7915_MAX_STA_TWT_AGRT]; 155 } twt; 156 }; 157 158 struct mt7915_vif_cap { 159 bool ht_ldpc:1; 160 bool vht_ldpc:1; 161 bool he_ldpc:1; 162 bool vht_su_ebfer:1; 163 bool vht_su_ebfee:1; 164 bool vht_mu_ebfer:1; 165 bool vht_mu_ebfee:1; 166 bool he_su_ebfer:1; 167 bool he_su_ebfee:1; 168 bool he_mu_ebfer:1; 169 }; 170 171 struct mt7915_vif { 172 struct mt76_vif_link mt76; /* must be first */ 173 174 struct mt7915_vif_cap cap; 175 struct mt7915_sta sta; 176 struct mt7915_phy *phy; 177 178 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 179 struct cfg80211_bitrate_mask bitrate_mask; 180 }; 181 182 /* crash-dump */ 183 struct mt7915_crash_data { 184 guid_t guid; 185 struct timespec64 timestamp; 186 187 u8 *memdump_buf; 188 size_t memdump_buf_len; 189 }; 190 191 struct mt7915_hif { 192 struct list_head list; 193 194 struct device *dev; 195 void __iomem *regs; 196 int irq; 197 u32 index; 198 }; 199 200 struct mt7915_phy { 201 struct mt76_phy *mt76; 202 struct mt7915_dev *dev; 203 204 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 205 206 struct ieee80211_vif *monitor_vif; 207 208 struct thermal_cooling_device *cdev; 209 u8 cdev_state; 210 u8 throttle_state; 211 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 212 213 u32 rxfilter; 214 u64 omac_mask; 215 216 u16 noise; 217 218 s16 coverage_class; 219 u8 slottime; 220 221 u32 trb_ts; 222 223 u32 rx_ampdu_ts; 224 u32 ampdu_ref; 225 226 struct mt76_mib_stats mib; 227 struct mt76_channel_state state_ts; 228 229 bool sku_limit_en:1; 230 bool sku_path_en:1; 231 232 #ifdef CONFIG_NL80211_TESTMODE 233 struct { 234 u32 *reg_backup; 235 236 s32 last_freq_offset; 237 u8 last_rcpi[4]; 238 s8 last_ib_rssi[4]; 239 s8 last_wb_rssi[4]; 240 u8 last_snr; 241 242 u8 spe_idx; 243 } test; 244 #endif 245 }; 246 247 struct mt7915_dev { 248 union { /* must be first */ 249 struct mt76_dev mt76; 250 struct mt76_phy mphy; 251 }; 252 253 struct mt7915_hif *hif2; 254 struct mt7915_reg_desc reg; 255 u8 q_id[MT7915_MAX_QUEUE]; 256 u32 q_int_mask[MT7915_MAX_QUEUE]; 257 u32 wfdma_mask; 258 259 const struct mt76_bus_ops *bus_ops; 260 struct mt7915_phy phy; 261 262 /* monitor rx chain configured channel */ 263 struct cfg80211_chan_def rdd2_chandef; 264 struct mt7915_phy *rdd2_phy; 265 266 u16 chainmask; 267 u16 chainshift; 268 u32 hif_idx; 269 270 struct work_struct init_work; 271 struct work_struct rc_work; 272 struct work_struct dump_work; 273 struct work_struct reset_work; 274 wait_queue_head_t reset_wait; 275 276 struct { 277 u32 state; 278 u32 wa_reset_count; 279 u32 wm_reset_count; 280 bool hw_full_reset:1; 281 bool hw_init_done:1; 282 bool restart:1; 283 } recovery; 284 285 /* protects coredump data */ 286 struct mutex dump_mutex; 287 #ifdef CONFIG_DEV_COREDUMP 288 struct { 289 struct mt7915_crash_data *crash_data; 290 } coredump; 291 #endif 292 293 struct list_head sta_rc_list; 294 struct list_head twt_list; 295 spinlock_t reg_lock; 296 297 u32 hw_pattern; 298 299 bool dbdc_support; 300 bool flash_mode; 301 bool muru_debug; 302 bool ibf; 303 304 u8 monitor_mask; 305 306 struct dentry *debugfs_dir; 307 struct rchan *relay_fwlog; 308 309 void *cal; 310 u32 cur_prek_offset; 311 u8 dpd_chan_num_2g; 312 u8 dpd_chan_num_5g; 313 u8 dpd_chan_num_6g; 314 315 struct { 316 u8 debug_wm; 317 u8 debug_wa; 318 u8 debug_bin; 319 } fw; 320 321 struct { 322 u16 table_mask; 323 u8 n_agrt; 324 } twt; 325 326 struct reset_control *rstc; 327 void __iomem *dcm; 328 void __iomem *sku; 329 }; 330 331 enum { 332 WFDMA0 = 0x0, 333 WFDMA1, 334 WFDMA_EXT, 335 __MT_WFDMA_MAX, 336 }; 337 338 enum rdd_idx { 339 MT_RDD_IDX_BAND0, /* RDD idx for band idx 0 (single-band) */ 340 MT_RDD_IDX_BAND1, /* RDD idx for band idx 1 */ 341 MT_RDD_IDX_BACKGROUND, /* RDD idx for background chain */ 342 }; 343 344 enum mt7915_rdd_cmd { 345 RDD_STOP, 346 RDD_START, 347 RDD_DET_MODE, 348 RDD_RADAR_EMULATE, 349 RDD_START_TXQ = 20, 350 RDD_SET_WF_ANT = 30, 351 RDD_CAC_START = 50, 352 RDD_CAC_END, 353 RDD_NORMAL_START, 354 RDD_DISABLE_DFS_CAL, 355 RDD_PULSE_DBG, 356 RDD_READ_PULSE, 357 RDD_RESUME_BF, 358 RDD_IRQ_OFF, 359 }; 360 361 static inline int 362 mt7915_get_rdd_idx(struct mt7915_phy *phy, bool is_background) 363 { 364 if (!phy->mt76->cap.has_5ghz) 365 return -1; 366 367 if (is_background) 368 return MT_RDD_IDX_BACKGROUND; 369 370 return phy->mt76->band_idx; 371 } 372 373 static inline struct mt7915_phy * 374 mt7915_hw_phy(struct ieee80211_hw *hw) 375 { 376 struct mt76_phy *phy = hw->priv; 377 378 return phy->priv; 379 } 380 381 static inline struct mt7915_dev * 382 mt7915_hw_dev(struct ieee80211_hw *hw) 383 { 384 struct mt76_phy *phy = hw->priv; 385 386 return container_of(phy->dev, struct mt7915_dev, mt76); 387 } 388 389 static inline struct mt7915_phy * 390 mt7915_ext_phy(struct mt7915_dev *dev) 391 { 392 struct mt76_phy *phy = dev->mt76.phys[MT_BAND1]; 393 394 if (!phy) 395 return NULL; 396 397 return phy->priv; 398 } 399 400 static inline u32 mt7915_check_adie(struct mt7915_dev *dev, bool sku) 401 { 402 u32 mask = sku ? MT_CONNINFRA_SKU_MASK : MT_ADIE_TYPE_MASK; 403 if (!is_mt798x(&dev->mt76)) 404 return 0; 405 406 return mt76_rr(dev, MT_CONNINFRA_SKU_DEC_ADDR) & mask; 407 } 408 409 extern const struct ieee80211_ops mt7915_ops; 410 extern const struct mt76_testmode_ops mt7915_testmode_ops; 411 extern struct pci_driver mt7915_pci_driver; 412 extern struct pci_driver mt7915_hif_driver; 413 extern struct platform_driver mt798x_wmac_driver; 414 415 #ifdef CONFIG_MT798X_WMAC 416 int mt7986_wmac_enable(struct mt7915_dev *dev); 417 void mt7986_wmac_disable(struct mt7915_dev *dev); 418 #else 419 static inline int mt7986_wmac_enable(struct mt7915_dev *dev) 420 { 421 return 0; 422 } 423 424 static inline void mt7986_wmac_disable(struct mt7915_dev *dev) 425 { 426 } 427 #endif 428 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, 429 void __iomem *mem_base, u32 device_id); 430 void mt7915_wfsys_reset(struct mt7915_dev *dev); 431 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance); 432 u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif); 433 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); 434 435 int mt7915_register_device(struct mt7915_dev *dev); 436 void mt7915_unregister_device(struct mt7915_dev *dev); 437 int mt7915_eeprom_init(struct mt7915_dev *dev); 438 void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev, 439 struct mt7915_phy *phy); 440 int mt7915_eeprom_get_target_power(struct mt7915_dev *dev, 441 struct ieee80211_channel *chan, 442 u8 chain_idx); 443 s8 mt7915_eeprom_get_power_delta(struct mt7915_dev *dev, int band); 444 bool mt7915_eeprom_has_background_radar(struct mt7915_dev *dev); 445 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2); 446 void mt7915_dma_prefetch(struct mt7915_dev *dev); 447 void mt7915_dma_cleanup(struct mt7915_dev *dev); 448 int mt7915_dma_reset(struct mt7915_dev *dev, bool force); 449 int mt7915_dma_start(struct mt7915_dev *dev, bool reset, bool wed_reset); 450 int mt7915_txbf_init(struct mt7915_dev *dev); 451 void mt7915_init_txpower(struct mt7915_phy *phy); 452 void mt7915_reset(struct mt7915_dev *dev); 453 int mt7915_run(struct ieee80211_hw *hw); 454 int mt7915_mcu_init(struct mt7915_dev *dev); 455 int mt7915_mcu_init_firmware(struct mt7915_dev *dev); 456 int mt7915_mcu_twt_agrt_update(struct mt7915_dev *dev, 457 struct mt7915_vif *mvif, 458 struct mt7915_twt_flow *flow, 459 int cmd); 460 int mt7915_mcu_add_dev_info(struct mt7915_phy *phy, 461 struct ieee80211_vif *vif, bool enable); 462 int mt7915_mcu_add_bss_info(struct mt7915_phy *phy, 463 struct ieee80211_vif *vif, int enable); 464 int mt7915_mcu_add_sta(struct mt7915_dev *dev, struct ieee80211_vif *vif, 465 struct ieee80211_sta *sta, int conn_state, bool newly); 466 int mt7915_mcu_add_tx_ba(struct mt7915_dev *dev, 467 struct ieee80211_ampdu_params *params, 468 bool add); 469 int mt7915_mcu_add_rx_ba(struct mt7915_dev *dev, 470 struct ieee80211_ampdu_params *params, 471 bool add); 472 int mt7915_mcu_update_bss_color(struct mt7915_dev *dev, struct ieee80211_vif *vif, 473 struct cfg80211_he_bss_color *he_bss_color); 474 int mt7915_mcu_add_inband_discov(struct mt7915_dev *dev, struct ieee80211_vif *vif, 475 u32 changed); 476 int mt7915_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 477 int enable, u32 changed); 478 int mt7915_mcu_set_protection(struct mt7915_phy *phy, struct ieee80211_vif *vif, 479 u8 ht_mode, bool use_cts_prot); 480 int mt7915_mcu_add_obss_spr(struct mt7915_phy *phy, struct ieee80211_vif *vif, 481 struct ieee80211_he_obss_pd *he_obss_pd); 482 int mt7915_mcu_add_rate_ctrl(struct mt7915_dev *dev, struct ieee80211_vif *vif, 483 struct ieee80211_sta *sta, bool changed); 484 int mt7915_mcu_add_smps(struct mt7915_dev *dev, struct ieee80211_vif *vif, 485 struct ieee80211_sta *sta); 486 int mt7915_set_channel(struct mt76_phy *mphy); 487 int mt7915_mcu_set_chan_info(struct mt7915_phy *phy, int cmd); 488 int mt7915_mcu_set_tx(struct mt7915_dev *dev, struct ieee80211_vif *vif); 489 int mt7915_mcu_update_edca(struct mt7915_dev *dev, void *req); 490 int mt7915_mcu_set_fixed_rate_ctrl(struct mt7915_dev *dev, 491 struct ieee80211_vif *vif, 492 struct ieee80211_sta *sta, 493 void *data, u32 field); 494 int mt7915_mcu_set_eeprom(struct mt7915_dev *dev); 495 int mt7915_mcu_get_eeprom(struct mt7915_dev *dev, u32 offset, u8 *read_buf); 496 int mt7915_mcu_get_eeprom_free_block(struct mt7915_dev *dev, u8 *block_num); 497 int mt7915_mcu_set_mac(struct mt7915_dev *dev, int band, bool enable, 498 bool hdr_trans); 499 int mt7915_mcu_set_test_param(struct mt7915_dev *dev, u8 param, bool test_mode, 500 u8 en); 501 int mt7915_mcu_set_ser(struct mt7915_dev *dev, u8 action, u8 set, u8 band); 502 int mt7915_mcu_set_sku_en(struct mt7915_phy *phy); 503 int mt7915_mcu_set_txpower_sku(struct mt7915_phy *phy); 504 int mt7915_mcu_get_txpower_sku(struct mt7915_phy *phy, s8 *txpower, int len, 505 u8 category); 506 int mt7915_mcu_set_txpower_frame_min(struct mt7915_phy *phy, s8 txpower); 507 int mt7915_mcu_set_txpower_frame(struct mt7915_phy *phy, 508 struct ieee80211_vif *vif, 509 struct ieee80211_sta *sta, s8 txpower); 510 int mt7915_mcu_set_txbf(struct mt7915_dev *dev, u8 action); 511 int mt7915_mcu_set_fcc5_lpn(struct mt7915_dev *dev, int val); 512 int mt7915_mcu_set_pulse_th(struct mt7915_dev *dev, 513 const struct mt7915_dfs_pulse *pulse); 514 int mt7915_mcu_set_radar_th(struct mt7915_dev *dev, int index, 515 const struct mt7915_dfs_pattern *pattern); 516 int mt7915_mcu_set_muru_ctrl(struct mt7915_dev *dev, u32 cmd, u32 val); 517 int mt7915_mcu_apply_group_cal(struct mt7915_dev *dev); 518 int mt7915_mcu_apply_tx_dpd(struct mt7915_phy *phy); 519 int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch); 520 int mt7915_mcu_get_temperature(struct mt7915_phy *phy); 521 int mt7915_mcu_set_thermal_throttling(struct mt7915_phy *phy, u8 state); 522 int mt7915_mcu_set_thermal_protect(struct mt7915_phy *phy); 523 int mt7915_mcu_get_rx_rate(struct mt7915_phy *phy, struct ieee80211_vif *vif, 524 struct ieee80211_sta *sta, struct rate_info *rate); 525 int mt7915_mcu_rdd_background_enable(struct mt7915_phy *phy, 526 struct cfg80211_chan_def *chandef); 527 int mt7915_mcu_wed_wa_tx_stats(struct mt7915_dev *dev, u16 wcid); 528 int mt7915_mcu_rf_regval(struct mt7915_dev *dev, u32 regidx, u32 *val, bool set); 529 int mt7915_mcu_wa_cmd(struct mt7915_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 530 int mt7915_mcu_fw_log_2_host(struct mt7915_dev *dev, u8 type, u8 ctrl); 531 int mt7915_mcu_fw_dbg_ctrl(struct mt7915_dev *dev, u32 module, u8 level); 532 void mt7915_mcu_rx_event(struct mt7915_dev *dev, struct sk_buff *skb); 533 void mt7915_mcu_exit(struct mt7915_dev *dev); 534 535 static inline u16 mt7915_wtbl_size(struct mt7915_dev *dev) 536 { 537 return is_mt7915(&dev->mt76) ? MT7915_WTBL_SIZE : MT7916_WTBL_SIZE; 538 } 539 540 static inline u16 mt7915_eeprom_size(struct mt7915_dev *dev) 541 { 542 return is_mt7915(&dev->mt76) ? MT7915_EEPROM_SIZE : MT7916_EEPROM_SIZE; 543 } 544 545 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev, bool write_reg, 546 u32 clear, u32 set); 547 548 static inline void mt7915_irq_enable(struct mt7915_dev *dev, u32 mask) 549 { 550 if (dev->hif2) 551 mt7915_dual_hif_set_irq_mask(dev, false, 0, mask); 552 else 553 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 554 555 tasklet_schedule(&dev->mt76.irq_tasklet); 556 } 557 558 static inline void mt7915_irq_disable(struct mt7915_dev *dev, u32 mask) 559 { 560 if (dev->hif2) 561 mt7915_dual_hif_set_irq_mask(dev, true, mask, 0); 562 else 563 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 564 } 565 566 void mt7915_memcpy_fromio(struct mt7915_dev *dev, void *buf, u32 offset, 567 size_t len); 568 569 void mt7915_mac_init(struct mt7915_dev *dev); 570 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw); 571 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask); 572 void mt7915_mac_reset_counters(struct mt7915_phy *phy); 573 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy); 574 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy); 575 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 576 struct ieee80211_vif *vif, bool enable); 577 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 578 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 579 struct ieee80211_key_conf *key, 580 enum mt76_txq_id qid, u32 changed); 581 void mt7915_mac_set_timing(struct mt7915_phy *phy); 582 int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 583 struct ieee80211_sta *sta); 584 int mt7915_mac_sta_event(struct mt76_dev *mdev, struct ieee80211_vif *vif, 585 struct ieee80211_sta *sta, enum mt76_sta_event ev); 586 void mt7915_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 587 struct ieee80211_sta *sta); 588 void mt7915_mac_work(struct work_struct *work); 589 void mt7915_mac_reset_work(struct work_struct *work); 590 void mt7915_mac_dump_work(struct work_struct *work); 591 void mt7915_mac_sta_rc_work(struct work_struct *work); 592 void mt7915_mac_update_stats(struct mt7915_phy *phy); 593 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 594 struct mt7915_sta *msta, 595 u8 flowid); 596 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 597 struct ieee80211_sta *sta, 598 struct ieee80211_twt_setup *twt); 599 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 600 enum mt76_txq_id qid, struct mt76_wcid *wcid, 601 struct ieee80211_sta *sta, 602 struct mt76_tx_info *tx_info); 603 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 604 struct sk_buff *skb, u32 *info); 605 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len); 606 void mt7915_stats_work(struct work_struct *work); 607 int mt76_dfs_start_rdd(struct mt7915_dev *dev, bool force); 608 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy); 609 void mt7915_set_stream_he_caps(struct mt7915_phy *phy); 610 void mt7915_set_stream_vht_txbf_caps(struct mt7915_phy *phy); 611 void mt7915_update_channel(struct mt76_phy *mphy); 612 int mt7915_mcu_muru_debug_set(struct mt7915_dev *dev, bool enable); 613 int mt7915_mcu_muru_debug_get(struct mt7915_phy *phy); 614 int mt7915_mcu_wed_enable_rx_stats(struct mt7915_dev *dev); 615 int mt7915_init_debugfs(struct mt7915_phy *phy); 616 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len); 617 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len); 618 #ifdef CONFIG_MAC80211_DEBUGFS 619 void mt7915_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 620 struct ieee80211_sta *sta, struct dentry *dir); 621 #endif 622 int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, 623 bool pci, int *irq); 624 625 #endif 626