1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "include/logger_interface.h"
29
30 #include "../dce110/irq_service_dce110.h"
31
32 #include "dcn/dcn_1_0_offset.h"
33 #include "dcn/dcn_1_0_sh_mask.h"
34 #include "soc15_hw_ip.h"
35 #include "vega10_ip_offset.h"
36
37 #include "irq_service_dcn10.h"
38
39 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
40
to_dal_irq_source_dcn10(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)41 static enum dc_irq_source to_dal_irq_source_dcn10(struct irq_service *irq_service,
42 uint32_t src_id,
43 uint32_t ext_id)
44 {
45 switch (src_id) {
46 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
47 return DC_IRQ_SOURCE_VBLANK1;
48 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
49 return DC_IRQ_SOURCE_VBLANK2;
50 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
51 return DC_IRQ_SOURCE_VBLANK3;
52 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
53 return DC_IRQ_SOURCE_VBLANK4;
54 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
55 return DC_IRQ_SOURCE_VBLANK5;
56 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
57 return DC_IRQ_SOURCE_VBLANK6;
58 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
59 return DC_IRQ_SOURCE_DC1_VLINE0;
60 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
61 return DC_IRQ_SOURCE_DC2_VLINE0;
62 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
63 return DC_IRQ_SOURCE_DC3_VLINE0;
64 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
65 return DC_IRQ_SOURCE_DC4_VLINE0;
66 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
67 return DC_IRQ_SOURCE_DC5_VLINE0;
68 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
69 return DC_IRQ_SOURCE_DC6_VLINE0;
70 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
71 return DC_IRQ_SOURCE_VUPDATE1;
72 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
73 return DC_IRQ_SOURCE_VUPDATE2;
74 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
75 return DC_IRQ_SOURCE_VUPDATE3;
76 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
77 return DC_IRQ_SOURCE_VUPDATE4;
78 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
79 return DC_IRQ_SOURCE_VUPDATE5;
80 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
81 return DC_IRQ_SOURCE_VUPDATE6;
82 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
83 return DC_IRQ_SOURCE_PFLIP1;
84 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
85 return DC_IRQ_SOURCE_PFLIP2;
86 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
87 return DC_IRQ_SOURCE_PFLIP3;
88 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
89 return DC_IRQ_SOURCE_PFLIP4;
90 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
91 return DC_IRQ_SOURCE_PFLIP5;
92 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
93 return DC_IRQ_SOURCE_PFLIP6;
94
95 case DCN_1_0__SRCID__DC_HPD1_INT:
96 /* generic src_id for all HPD and HPDRX interrupts */
97 switch (ext_id) {
98 case DCN_1_0__CTXID__DC_HPD1_INT:
99 return DC_IRQ_SOURCE_HPD1;
100 case DCN_1_0__CTXID__DC_HPD2_INT:
101 return DC_IRQ_SOURCE_HPD2;
102 case DCN_1_0__CTXID__DC_HPD3_INT:
103 return DC_IRQ_SOURCE_HPD3;
104 case DCN_1_0__CTXID__DC_HPD4_INT:
105 return DC_IRQ_SOURCE_HPD4;
106 case DCN_1_0__CTXID__DC_HPD5_INT:
107 return DC_IRQ_SOURCE_HPD5;
108 case DCN_1_0__CTXID__DC_HPD6_INT:
109 return DC_IRQ_SOURCE_HPD6;
110 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
111 return DC_IRQ_SOURCE_HPD1RX;
112 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
113 return DC_IRQ_SOURCE_HPD2RX;
114 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
115 return DC_IRQ_SOURCE_HPD3RX;
116 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
117 return DC_IRQ_SOURCE_HPD4RX;
118 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
119 return DC_IRQ_SOURCE_HPD5RX;
120 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
121 return DC_IRQ_SOURCE_HPD6RX;
122 default:
123 return DC_IRQ_SOURCE_INVALID;
124 }
125 break;
126
127 default:
128 return DC_IRQ_SOURCE_INVALID;
129 }
130 }
131
132 static struct irq_source_info_funcs hpd_irq_info_funcs = {
133 .set = NULL,
134 .ack = hpd0_ack
135 };
136
137 static struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
138 .set = NULL,
139 .ack = NULL
140 };
141
142 static struct irq_source_info_funcs pflip_irq_info_funcs = {
143 .set = NULL,
144 .ack = NULL
145 };
146
147 static struct irq_source_info_funcs vblank_irq_info_funcs = {
148 .set = NULL,
149 .ack = NULL
150 };
151
152 static struct irq_source_info_funcs vline0_irq_info_funcs = {
153 .set = NULL,
154 .ack = NULL
155 };
156
157 static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
158 .set = NULL,
159 .ack = NULL
160 };
161
162 #define BASE_INNER(seg) \
163 DCE_BASE__INST0_SEG ## seg
164
165 #define BASE(seg) \
166 BASE_INNER(seg)
167
168 #define SRI(reg_name, block, id)\
169 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 mm ## block ## id ## _ ## reg_name
171
172
173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
174 .enable_reg = SRI(reg1, block, reg_num),\
175 .enable_mask = \
176 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
177 .enable_value = {\
178 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
179 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
180 },\
181 .ack_reg = SRI(reg2, block, reg_num),\
182 .ack_mask = \
183 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
184 .ack_value = \
185 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
186
187 #define hpd_int_entry(reg_num)\
188 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
189 IRQ_REG_ENTRY(HPD, reg_num,\
190 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
191 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
192 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
193 .funcs = &hpd_irq_info_funcs\
194 }
195
196 #define hpd_rx_int_entry(reg_num)\
197 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
198 IRQ_REG_ENTRY(HPD, reg_num,\
199 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
200 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
201 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
202 .funcs = &hpd_rx_irq_info_funcs\
203 }
204 #define pflip_int_entry(reg_num)\
205 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
206 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
207 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
208 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
209 .funcs = &pflip_irq_info_funcs\
210 }
211
212 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
213 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
214 */
215 #define vupdate_no_lock_int_entry(reg_num)\
216 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
217 IRQ_REG_ENTRY(OTG, reg_num,\
218 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
219 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
220 .funcs = &vupdate_no_lock_irq_info_funcs\
221 }
222
223 #define vblank_int_entry(reg_num)\
224 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
225 IRQ_REG_ENTRY(OTG, reg_num,\
226 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
227 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
228 .funcs = &vblank_irq_info_funcs\
229 }
230
231 #define vline0_int_entry(reg_num)\
232 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
233 IRQ_REG_ENTRY(OTG, reg_num,\
234 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
235 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
236 .funcs = &vline0_irq_info_funcs\
237 }
238
239 #define dummy_irq_entry() \
240 {\
241 .funcs = &dummy_irq_info_funcs\
242 }
243
244 #define i2c_int_entry(reg_num) \
245 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
246
247 #define dp_sink_int_entry(reg_num) \
248 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
249
250 #define gpio_pad_int_entry(reg_num) \
251 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
252
253 #define dc_underflow_int_entry(reg_num) \
254 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
255
256 static struct irq_source_info_funcs dummy_irq_info_funcs = {
257 .set = dal_irq_service_dummy_set,
258 .ack = dal_irq_service_dummy_ack
259 };
260
261 static const struct irq_source_info
262 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = {
263 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
264 hpd_int_entry(0),
265 hpd_int_entry(1),
266 hpd_int_entry(2),
267 hpd_int_entry(3),
268 hpd_int_entry(4),
269 hpd_int_entry(5),
270 hpd_rx_int_entry(0),
271 hpd_rx_int_entry(1),
272 hpd_rx_int_entry(2),
273 hpd_rx_int_entry(3),
274 hpd_rx_int_entry(4),
275 hpd_rx_int_entry(5),
276 i2c_int_entry(1),
277 i2c_int_entry(2),
278 i2c_int_entry(3),
279 i2c_int_entry(4),
280 i2c_int_entry(5),
281 i2c_int_entry(6),
282 dp_sink_int_entry(1),
283 dp_sink_int_entry(2),
284 dp_sink_int_entry(3),
285 dp_sink_int_entry(4),
286 dp_sink_int_entry(5),
287 dp_sink_int_entry(6),
288 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
289 pflip_int_entry(0),
290 pflip_int_entry(1),
291 pflip_int_entry(2),
292 pflip_int_entry(3),
293 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
294 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
295 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
296 gpio_pad_int_entry(0),
297 gpio_pad_int_entry(1),
298 gpio_pad_int_entry(2),
299 gpio_pad_int_entry(3),
300 gpio_pad_int_entry(4),
301 gpio_pad_int_entry(5),
302 gpio_pad_int_entry(6),
303 gpio_pad_int_entry(7),
304 gpio_pad_int_entry(8),
305 gpio_pad_int_entry(9),
306 gpio_pad_int_entry(10),
307 gpio_pad_int_entry(11),
308 gpio_pad_int_entry(12),
309 gpio_pad_int_entry(13),
310 gpio_pad_int_entry(14),
311 gpio_pad_int_entry(15),
312 gpio_pad_int_entry(16),
313 gpio_pad_int_entry(17),
314 gpio_pad_int_entry(18),
315 gpio_pad_int_entry(19),
316 gpio_pad_int_entry(20),
317 gpio_pad_int_entry(21),
318 gpio_pad_int_entry(22),
319 gpio_pad_int_entry(23),
320 gpio_pad_int_entry(24),
321 gpio_pad_int_entry(25),
322 gpio_pad_int_entry(26),
323 gpio_pad_int_entry(27),
324 gpio_pad_int_entry(28),
325 gpio_pad_int_entry(29),
326 gpio_pad_int_entry(30),
327 dc_underflow_int_entry(1),
328 dc_underflow_int_entry(2),
329 dc_underflow_int_entry(3),
330 dc_underflow_int_entry(4),
331 dc_underflow_int_entry(5),
332 dc_underflow_int_entry(6),
333 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
334 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
335 vupdate_no_lock_int_entry(0),
336 vupdate_no_lock_int_entry(1),
337 vupdate_no_lock_int_entry(2),
338 vupdate_no_lock_int_entry(3),
339 vupdate_no_lock_int_entry(4),
340 vupdate_no_lock_int_entry(5),
341 vblank_int_entry(0),
342 vblank_int_entry(1),
343 vblank_int_entry(2),
344 vblank_int_entry(3),
345 vblank_int_entry(4),
346 vblank_int_entry(5),
347 vline0_int_entry(0),
348 vline0_int_entry(1),
349 vline0_int_entry(2),
350 vline0_int_entry(3),
351 vline0_int_entry(4),
352 vline0_int_entry(5),
353 };
354
355 static const struct irq_service_funcs irq_service_funcs_dcn10 = {
356 .to_dal_irq_source = to_dal_irq_source_dcn10
357 };
358
dcn10_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)359 static void dcn10_irq_construct(
360 struct irq_service *irq_service,
361 struct irq_service_init_data *init_data)
362 {
363 dal_irq_service_construct(irq_service, init_data);
364
365 irq_service->info = irq_source_info_dcn10;
366 irq_service->funcs = &irq_service_funcs_dcn10;
367 }
368
dal_irq_service_dcn10_create(struct irq_service_init_data * init_data)369 struct irq_service *dal_irq_service_dcn10_create(
370 struct irq_service_init_data *init_data)
371 {
372 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
373 GFP_KERNEL);
374
375 if (!irq_service)
376 return NULL;
377
378 dcn10_irq_construct(irq_service, init_data);
379 return irq_service;
380 }
381