1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
24 #include "qemu/log.h"
25 #include "exec/page-vary.h"
26 #include "exec/tswap.h"
27 #include "target/arm/idau.h"
28 #include "qemu/module.h"
29 #include "qapi/error.h"
30 #include "cpu.h"
31 #ifdef CONFIG_TCG
32 #include "exec/translation-block.h"
33 #include "accel/tcg/cpu-ops.h"
34 #endif /* CONFIG_TCG */
35 #include "internals.h"
36 #include "cpu-features.h"
37 #include "exec/target_page.h"
38 #include "hw/qdev-properties.h"
39 #if !defined(CONFIG_USER_ONLY)
40 #include "hw/loader.h"
41 #include "hw/boards.h"
42 #ifdef CONFIG_TCG
43 #include "hw/intc/armv7m_nvic.h"
44 #endif /* CONFIG_TCG */
45 #endif /* !CONFIG_USER_ONLY */
46 #include "system/tcg.h"
47 #include "system/qtest.h"
48 #include "system/hw_accel.h"
49 #include "kvm_arm.h"
50 #include "disas/capstone.h"
51 #include "fpu/softfloat.h"
52 #include "cpregs.h"
53 #include "target/arm/cpu-qom.h"
54 #include "target/arm/gtimer.h"
55
arm_cpu_set_pc(CPUState * cs,vaddr value)56 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
57 {
58 ARMCPU *cpu = ARM_CPU(cs);
59 CPUARMState *env = &cpu->env;
60
61 if (is_a64(env)) {
62 env->pc = value;
63 env->thumb = false;
64 } else {
65 env->regs[15] = value & ~1;
66 env->thumb = value & 1;
67 }
68 }
69
arm_cpu_get_pc(CPUState * cs)70 static vaddr arm_cpu_get_pc(CPUState *cs)
71 {
72 ARMCPU *cpu = ARM_CPU(cs);
73 CPUARMState *env = &cpu->env;
74
75 if (is_a64(env)) {
76 return env->pc;
77 } else {
78 return env->regs[15];
79 }
80 }
81
82 #ifdef CONFIG_TCG
arm_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)83 void arm_cpu_synchronize_from_tb(CPUState *cs,
84 const TranslationBlock *tb)
85 {
86 /* The program counter is always up to date with CF_PCREL. */
87 if (!(tb_cflags(tb) & CF_PCREL)) {
88 CPUARMState *env = cpu_env(cs);
89 /*
90 * It's OK to look at env for the current mode here, because it's
91 * never possible for an AArch64 TB to chain to an AArch32 TB.
92 */
93 if (is_a64(env)) {
94 env->pc = tb->pc;
95 } else {
96 env->regs[15] = tb->pc;
97 }
98 }
99 }
100
arm_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)101 void arm_restore_state_to_opc(CPUState *cs,
102 const TranslationBlock *tb,
103 const uint64_t *data)
104 {
105 CPUARMState *env = cpu_env(cs);
106
107 if (is_a64(env)) {
108 if (tb_cflags(tb) & CF_PCREL) {
109 env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
110 } else {
111 env->pc = data[0];
112 }
113 env->condexec_bits = 0;
114 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
115 } else {
116 if (tb_cflags(tb) & CF_PCREL) {
117 env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
118 } else {
119 env->regs[15] = data[0];
120 }
121 env->condexec_bits = data[1];
122 env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
123 }
124 }
125
arm_cpu_mmu_index(CPUState * cs,bool ifetch)126 int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
127 {
128 return arm_env_mmu_index(cpu_env(cs));
129 }
130
131 #endif /* CONFIG_TCG */
132
133 #ifndef CONFIG_USER_ONLY
134 /*
135 * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with
136 * IRQ without Superpriority. Moreover, if the GIC is configured so that
137 * FEAT_GICv3_NMI is only set if FEAT_NMI is set, then we won't ever see
138 * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
139 * unconditionally.
140 */
arm_cpu_has_work(CPUState * cs)141 static bool arm_cpu_has_work(CPUState *cs)
142 {
143 ARMCPU *cpu = ARM_CPU(cs);
144
145 return (cpu->power_state != PSCI_OFF)
146 && cs->interrupt_request &
147 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
148 | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI
149 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR
150 | CPU_INTERRUPT_EXITTB);
151 }
152 #endif /* !CONFIG_USER_ONLY */
153
arm_register_pre_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)154 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
155 void *opaque)
156 {
157 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
158
159 entry->hook = hook;
160 entry->opaque = opaque;
161
162 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
163 }
164
arm_register_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)165 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
166 void *opaque)
167 {
168 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
169
170 entry->hook = hook;
171 entry->opaque = opaque;
172
173 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
174 }
175
cp_reg_reset(gpointer key,gpointer value,gpointer opaque)176 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
177 {
178 /* Reset a single ARMCPRegInfo register */
179 ARMCPRegInfo *ri = value;
180 ARMCPU *cpu = opaque;
181
182 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) {
183 return;
184 }
185
186 if (ri->resetfn) {
187 ri->resetfn(&cpu->env, ri);
188 return;
189 }
190
191 /* A zero offset is never possible as it would be regs[0]
192 * so we use it to indicate that reset is being handled elsewhere.
193 * This is basically only used for fields in non-core coprocessors
194 * (like the pxa2xx ones).
195 */
196 if (!ri->fieldoffset) {
197 return;
198 }
199
200 if (cpreg_field_is_64bit(ri)) {
201 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
202 } else {
203 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
204 }
205 }
206
cp_reg_check_reset(gpointer key,gpointer value,gpointer opaque)207 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
208 {
209 /* Purely an assertion check: we've already done reset once,
210 * so now check that running the reset for the cpreg doesn't
211 * change its value. This traps bugs where two different cpregs
212 * both try to reset the same state field but to different values.
213 */
214 ARMCPRegInfo *ri = value;
215 ARMCPU *cpu = opaque;
216 uint64_t oldvalue, newvalue;
217
218 if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
219 return;
220 }
221
222 oldvalue = read_raw_cp_reg(&cpu->env, ri);
223 cp_reg_reset(key, value, opaque);
224 newvalue = read_raw_cp_reg(&cpu->env, ri);
225 assert(oldvalue == newvalue);
226 }
227
arm_cpu_reset_hold(Object * obj,ResetType type)228 static void arm_cpu_reset_hold(Object *obj, ResetType type)
229 {
230 CPUState *cs = CPU(obj);
231 ARMCPU *cpu = ARM_CPU(cs);
232 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
233 CPUARMState *env = &cpu->env;
234
235 if (acc->parent_phases.hold) {
236 acc->parent_phases.hold(obj, type);
237 }
238
239 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
240
241 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
242 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
243
244 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
245 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
246 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
247 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
248
249 cpu->power_state = cs->start_powered_off ? PSCI_OFF : PSCI_ON;
250
251 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
252 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
253 }
254
255 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
256 /* 64 bit CPUs always start in 64 bit mode */
257 env->aarch64 = true;
258 #if defined(CONFIG_USER_ONLY)
259 env->pstate = PSTATE_MODE_EL0t;
260 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
261 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
262 /* Enable all PAC keys. */
263 env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
264 SCTLR_EnDA | SCTLR_EnDB);
265 /* Trap on btype=3 for PACIxSP. */
266 env->cp15.sctlr_el[1] |= SCTLR_BT0;
267 /* Trap on implementation defined registers. */
268 if (cpu_isar_feature(aa64_tidcp1, cpu)) {
269 env->cp15.sctlr_el[1] |= SCTLR_TIDCP;
270 }
271 /* and to the FP/Neon instructions */
272 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
273 CPACR_EL1, FPEN, 3);
274 /* and to the SVE instructions, with default vector length */
275 if (cpu_isar_feature(aa64_sve, cpu)) {
276 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
277 CPACR_EL1, ZEN, 3);
278 env->vfp.zcr_el[1] = cpu->sve_default_vq - 1;
279 }
280 /* and for SME instructions, with default vector length, and TPIDR2 */
281 if (cpu_isar_feature(aa64_sme, cpu)) {
282 env->cp15.sctlr_el[1] |= SCTLR_EnTP2;
283 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
284 CPACR_EL1, SMEN, 3);
285 env->vfp.smcr_el[1] = cpu->sme_default_vq - 1;
286 if (cpu_isar_feature(aa64_sme_fa64, cpu)) {
287 env->vfp.smcr_el[1] = FIELD_DP64(env->vfp.smcr_el[1],
288 SMCR, FA64, 1);
289 }
290 }
291 /*
292 * Enable 48-bit address space (TODO: take reserved_va into account).
293 * Enable TBI0 but not TBI1.
294 * Note that this must match useronly_clean_ptr.
295 */
296 env->cp15.tcr_el[1] = 5 | (1ULL << 37);
297
298 /* Enable MTE */
299 if (cpu_isar_feature(aa64_mte, cpu)) {
300 /* Enable tag access, but leave TCF0 as No Effect (0). */
301 env->cp15.sctlr_el[1] |= SCTLR_ATA0;
302 /*
303 * Exclude all tags, so that tag 0 is always used.
304 * This corresponds to Linux current->thread.gcr_incl = 0.
305 *
306 * Set RRND, so that helper_irg() will generate a seed later.
307 * Here in cpu_reset(), the crypto subsystem has not yet been
308 * initialized.
309 */
310 env->cp15.gcr_el1 = 0x1ffff;
311 }
312 /*
313 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
314 * This is not yet exposed from the Linux kernel in any way.
315 */
316 env->cp15.sctlr_el[1] |= SCTLR_TSCXT;
317 /* Disable access to Debug Communication Channel (DCC). */
318 env->cp15.mdscr_el1 |= 1 << 12;
319 /* Enable FEAT_MOPS */
320 env->cp15.sctlr_el[1] |= SCTLR_MSCEN;
321 #else
322 /* Reset into the highest available EL */
323 if (arm_feature(env, ARM_FEATURE_EL3)) {
324 env->pstate = PSTATE_MODE_EL3h;
325 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
326 env->pstate = PSTATE_MODE_EL2h;
327 } else {
328 env->pstate = PSTATE_MODE_EL1h;
329 }
330
331 /* Sample rvbar at reset. */
332 env->cp15.rvbar = cpu->rvbar_prop;
333 env->pc = env->cp15.rvbar;
334 #endif
335 } else {
336 #if defined(CONFIG_USER_ONLY)
337 /* Userspace expects access to cp10 and cp11 for FP/Neon */
338 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
339 CPACR, CP10, 3);
340 env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1,
341 CPACR, CP11, 3);
342 #endif
343 if (arm_feature(env, ARM_FEATURE_V8)) {
344 env->cp15.rvbar = cpu->rvbar_prop;
345 env->regs[15] = cpu->rvbar_prop;
346 }
347 }
348
349 #if defined(CONFIG_USER_ONLY)
350 env->uncached_cpsr = ARM_CPU_MODE_USR;
351 /* For user mode we must enable access to coprocessors */
352 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
353 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
354 env->cp15.c15_cpar = 3;
355 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
356 env->cp15.c15_cpar = 1;
357 }
358 #else
359
360 /*
361 * If the highest available EL is EL2, AArch32 will start in Hyp
362 * mode; otherwise it starts in SVC. Note that if we start in
363 * AArch64 then these values in the uncached_cpsr will be ignored.
364 */
365 if (arm_feature(env, ARM_FEATURE_EL2) &&
366 !arm_feature(env, ARM_FEATURE_EL3)) {
367 env->uncached_cpsr = ARM_CPU_MODE_HYP;
368 } else {
369 env->uncached_cpsr = ARM_CPU_MODE_SVC;
370 }
371 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
372
373 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
374 * executing as AArch32 then check if highvecs are enabled and
375 * adjust the PC accordingly.
376 */
377 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
378 env->regs[15] = 0xFFFF0000;
379 }
380
381 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
382 #endif
383
384 if (arm_feature(env, ARM_FEATURE_M)) {
385 #ifndef CONFIG_USER_ONLY
386 uint32_t initial_msp; /* Loaded from 0x0 */
387 uint32_t initial_pc; /* Loaded from 0x4 */
388 uint8_t *rom;
389 uint32_t vecbase;
390 #endif
391
392 if (cpu_isar_feature(aa32_lob, cpu)) {
393 /*
394 * LTPSIZE is constant 4 if MVE not implemented, and resets
395 * to an UNKNOWN value if MVE is implemented. We choose to
396 * always reset to 4.
397 */
398 env->v7m.ltpsize = 4;
399 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
400 env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
401 env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
402 }
403
404 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
405 env->v7m.secure = true;
406 } else {
407 /* This bit resets to 0 if security is supported, but 1 if
408 * it is not. The bit is not present in v7M, but we set it
409 * here so we can avoid having to make checks on it conditional
410 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
411 */
412 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
413 /*
414 * Set NSACR to indicate "NS access permitted to everything";
415 * this avoids having to have all the tests of it being
416 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
417 * v8.1M the guest-visible value of NSACR in a CPU without the
418 * Security Extension is 0xcff.
419 */
420 env->v7m.nsacr = 0xcff;
421 }
422
423 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
424 * that it resets to 1, so QEMU always does that rather than making
425 * it dependent on CPU model. In v8M it is RES1.
426 */
427 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
428 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
429 if (arm_feature(env, ARM_FEATURE_V8)) {
430 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
431 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
432 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
433 }
434 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
435 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
436 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
437 }
438
439 if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
440 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
441 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
442 R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
443 }
444
445 #ifndef CONFIG_USER_ONLY
446 /* Unlike A/R profile, M profile defines the reset LR value */
447 env->regs[14] = 0xffffffff;
448
449 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
450 env->v7m.vecbase[M_REG_NS] = cpu->init_nsvtor & 0xffffff80;
451
452 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
453 vecbase = env->v7m.vecbase[env->v7m.secure];
454 rom = rom_ptr_for_as(cs->as, vecbase, 8);
455 if (rom) {
456 /* Address zero is covered by ROM which hasn't yet been
457 * copied into physical memory.
458 */
459 initial_msp = ldl_p(rom);
460 initial_pc = ldl_p(rom + 4);
461 } else {
462 /* Address zero not covered by a ROM blob, or the ROM blob
463 * is in non-modifiable memory and this is a second reset after
464 * it got copied into memory. In the latter case, rom_ptr
465 * will return a NULL pointer and we should use ldl_phys instead.
466 */
467 initial_msp = ldl_phys(cs->as, vecbase);
468 initial_pc = ldl_phys(cs->as, vecbase + 4);
469 }
470
471 qemu_log_mask(CPU_LOG_INT,
472 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
473 initial_msp, initial_pc);
474
475 env->regs[13] = initial_msp & 0xFFFFFFFC;
476 env->regs[15] = initial_pc & ~1;
477 env->thumb = initial_pc & 1;
478 #else
479 /*
480 * For user mode we run non-secure and with access to the FPU.
481 * The FPU context is active (ie does not need further setup)
482 * and is owned by non-secure.
483 */
484 env->v7m.secure = false;
485 env->v7m.nsacr = 0xcff;
486 env->v7m.cpacr[M_REG_NS] = 0xf0ffff;
487 env->v7m.fpccr[M_REG_S] &=
488 ~(R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK);
489 env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK;
490 #endif
491 }
492
493 /* M profile requires that reset clears the exclusive monitor;
494 * A profile does not, but clearing it makes more sense than having it
495 * set with an exclusive access on address zero.
496 */
497 arm_clear_exclusive(env);
498
499 if (arm_feature(env, ARM_FEATURE_PMSA)) {
500 if (cpu->pmsav7_dregion > 0) {
501 if (arm_feature(env, ARM_FEATURE_V8)) {
502 memset(env->pmsav8.rbar[M_REG_NS], 0,
503 sizeof(*env->pmsav8.rbar[M_REG_NS])
504 * cpu->pmsav7_dregion);
505 memset(env->pmsav8.rlar[M_REG_NS], 0,
506 sizeof(*env->pmsav8.rlar[M_REG_NS])
507 * cpu->pmsav7_dregion);
508 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
509 memset(env->pmsav8.rbar[M_REG_S], 0,
510 sizeof(*env->pmsav8.rbar[M_REG_S])
511 * cpu->pmsav7_dregion);
512 memset(env->pmsav8.rlar[M_REG_S], 0,
513 sizeof(*env->pmsav8.rlar[M_REG_S])
514 * cpu->pmsav7_dregion);
515 }
516 } else if (arm_feature(env, ARM_FEATURE_V7)) {
517 memset(env->pmsav7.drbar, 0,
518 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
519 memset(env->pmsav7.drsr, 0,
520 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
521 memset(env->pmsav7.dracr, 0,
522 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
523 }
524 }
525
526 if (cpu->pmsav8r_hdregion > 0) {
527 memset(env->pmsav8.hprbar, 0,
528 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
529 memset(env->pmsav8.hprlar, 0,
530 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
531 }
532
533 env->pmsav7.rnr[M_REG_NS] = 0;
534 env->pmsav7.rnr[M_REG_S] = 0;
535 env->pmsav8.mair0[M_REG_NS] = 0;
536 env->pmsav8.mair0[M_REG_S] = 0;
537 env->pmsav8.mair1[M_REG_NS] = 0;
538 env->pmsav8.mair1[M_REG_S] = 0;
539 }
540
541 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
542 if (cpu->sau_sregion > 0) {
543 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
544 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
545 }
546 env->sau.rnr = 0;
547 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
548 * the Cortex-M33 does.
549 */
550 env->sau.ctrl = 0;
551 }
552
553 set_flush_to_zero(1, &env->vfp.fp_status[FPST_STD]);
554 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_STD]);
555 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD]);
556 set_default_nan_mode(1, &env->vfp.fp_status[FPST_STD_F16]);
557 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32]);
558 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64]);
559 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD]);
560 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A32_F16]);
561 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_A64_F16]);
562 arm_set_default_fp_behaviours(&env->vfp.fp_status[FPST_STD_F16]);
563 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH]);
564 set_flush_to_zero(1, &env->vfp.fp_status[FPST_AH]);
565 set_flush_inputs_to_zero(1, &env->vfp.fp_status[FPST_AH]);
566 arm_set_ah_fp_behaviours(&env->vfp.fp_status[FPST_AH_F16]);
567
568 #ifndef CONFIG_USER_ONLY
569 if (kvm_enabled()) {
570 kvm_arm_reset_vcpu(cpu);
571 }
572 #endif
573
574 if (tcg_enabled()) {
575 hw_breakpoint_update_all(cpu);
576 hw_watchpoint_update_all(cpu);
577
578 arm_rebuild_hflags(env);
579 }
580 }
581
arm_emulate_firmware_reset(CPUState * cpustate,int target_el)582 void arm_emulate_firmware_reset(CPUState *cpustate, int target_el)
583 {
584 ARMCPU *cpu = ARM_CPU(cpustate);
585 CPUARMState *env = &cpu->env;
586 bool have_el3 = arm_feature(env, ARM_FEATURE_EL3);
587 bool have_el2 = arm_feature(env, ARM_FEATURE_EL2);
588
589 /*
590 * Check we have the EL we're aiming for. If that is the
591 * highest implemented EL, then cpu_reset has already done
592 * all the work.
593 */
594 switch (target_el) {
595 case 3:
596 assert(have_el3);
597 return;
598 case 2:
599 assert(have_el2);
600 if (!have_el3) {
601 return;
602 }
603 break;
604 case 1:
605 if (!have_el3 && !have_el2) {
606 return;
607 }
608 break;
609 default:
610 g_assert_not_reached();
611 }
612
613 if (have_el3) {
614 /*
615 * Set the EL3 state so code can run at EL2. This should match
616 * the requirements set by Linux in its booting spec.
617 */
618 if (env->aarch64) {
619 env->cp15.scr_el3 |= SCR_RW;
620 if (cpu_isar_feature(aa64_pauth, cpu)) {
621 env->cp15.scr_el3 |= SCR_API | SCR_APK;
622 }
623 if (cpu_isar_feature(aa64_mte, cpu)) {
624 env->cp15.scr_el3 |= SCR_ATA;
625 }
626 if (cpu_isar_feature(aa64_sve, cpu)) {
627 env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
628 env->vfp.zcr_el[3] = 0xf;
629 }
630 if (cpu_isar_feature(aa64_sme, cpu)) {
631 env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
632 env->cp15.scr_el3 |= SCR_ENTP2;
633 env->vfp.smcr_el[3] = 0xf;
634 }
635 if (cpu_isar_feature(aa64_hcx, cpu)) {
636 env->cp15.scr_el3 |= SCR_HXEN;
637 }
638 if (cpu_isar_feature(aa64_fgt, cpu)) {
639 env->cp15.scr_el3 |= SCR_FGTEN;
640 }
641 }
642
643 if (target_el == 2) {
644 /* If the guest is at EL2 then Linux expects the HVC insn to work */
645 env->cp15.scr_el3 |= SCR_HCE;
646 }
647
648 /* Put CPU into non-secure state */
649 env->cp15.scr_el3 |= SCR_NS;
650 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
651 env->cp15.nsacr |= 3 << 10;
652 }
653
654 if (have_el2 && target_el < 2) {
655 /* Set EL2 state so code can run at EL1. */
656 if (env->aarch64) {
657 env->cp15.hcr_el2 |= HCR_RW;
658 }
659 }
660
661 /* Set the CPU to the desired state */
662 if (env->aarch64) {
663 env->pstate = aarch64_pstate_mode(target_el, true);
664 } else {
665 static const uint32_t mode_for_el[] = {
666 0,
667 ARM_CPU_MODE_SVC,
668 ARM_CPU_MODE_HYP,
669 ARM_CPU_MODE_SVC,
670 };
671
672 cpsr_write(env, mode_for_el[target_el], CPSR_M, CPSRWriteRaw);
673 }
674 }
675
676
677 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
678
arm_excp_unmasked(CPUState * cs,unsigned int excp_idx,unsigned int target_el,unsigned int cur_el,bool secure,uint64_t hcr_el2)679 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
680 unsigned int target_el,
681 unsigned int cur_el, bool secure,
682 uint64_t hcr_el2)
683 {
684 CPUARMState *env = cpu_env(cs);
685 bool pstate_unmasked;
686 bool unmasked = false;
687 bool allIntMask = false;
688
689 /*
690 * Don't take exceptions if they target a lower EL.
691 * This check should catch any exceptions that would not be taken
692 * but left pending.
693 */
694 if (cur_el > target_el) {
695 return false;
696 }
697
698 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
699 env->cp15.sctlr_el[target_el] & SCTLR_NMI && cur_el == target_el) {
700 allIntMask = env->pstate & PSTATE_ALLINT ||
701 ((env->cp15.sctlr_el[target_el] & SCTLR_SPINTMASK) &&
702 (env->pstate & PSTATE_SP));
703 }
704
705 switch (excp_idx) {
706 case EXCP_NMI:
707 pstate_unmasked = !allIntMask;
708 break;
709
710 case EXCP_VINMI:
711 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
712 /* VINMIs are only taken when hypervized. */
713 return false;
714 }
715 return !allIntMask;
716 case EXCP_VFNMI:
717 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
718 /* VFNMIs are only taken when hypervized. */
719 return false;
720 }
721 return !allIntMask;
722 case EXCP_FIQ:
723 pstate_unmasked = (!(env->daif & PSTATE_F)) && (!allIntMask);
724 break;
725
726 case EXCP_IRQ:
727 pstate_unmasked = (!(env->daif & PSTATE_I)) && (!allIntMask);
728 break;
729
730 case EXCP_VFIQ:
731 if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
732 /* VFIQs are only taken when hypervized. */
733 return false;
734 }
735 return !(env->daif & PSTATE_F) && (!allIntMask);
736 case EXCP_VIRQ:
737 if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
738 /* VIRQs are only taken when hypervized. */
739 return false;
740 }
741 return !(env->daif & PSTATE_I) && (!allIntMask);
742 case EXCP_VSERR:
743 if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) {
744 /* VIRQs are only taken when hypervized. */
745 return false;
746 }
747 return !(env->daif & PSTATE_A);
748 default:
749 g_assert_not_reached();
750 }
751
752 /*
753 * Use the target EL, current execution state and SCR/HCR settings to
754 * determine whether the corresponding CPSR bit is used to mask the
755 * interrupt.
756 */
757 if ((target_el > cur_el) && (target_el != 1)) {
758 /* Exceptions targeting a higher EL may not be maskable */
759 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
760 switch (target_el) {
761 case 2:
762 /*
763 * According to ARM DDI 0487H.a, an interrupt can be masked
764 * when HCR_E2H and HCR_TGE are both set regardless of the
765 * current Security state. Note that we need to revisit this
766 * part again once we need to support NMI.
767 */
768 if ((hcr_el2 & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
769 unmasked = true;
770 }
771 break;
772 case 3:
773 /* Interrupt cannot be masked when the target EL is 3 */
774 unmasked = true;
775 break;
776 default:
777 g_assert_not_reached();
778 }
779 } else {
780 /*
781 * The old 32-bit-only environment has a more complicated
782 * masking setup. HCR and SCR bits not only affect interrupt
783 * routing but also change the behaviour of masking.
784 */
785 bool hcr, scr;
786
787 switch (excp_idx) {
788 case EXCP_FIQ:
789 /*
790 * If FIQs are routed to EL3 or EL2 then there are cases where
791 * we override the CPSR.F in determining if the exception is
792 * masked or not. If neither of these are set then we fall back
793 * to the CPSR.F setting otherwise we further assess the state
794 * below.
795 */
796 hcr = hcr_el2 & HCR_FMO;
797 scr = (env->cp15.scr_el3 & SCR_FIQ);
798
799 /*
800 * When EL3 is 32-bit, the SCR.FW bit controls whether the
801 * CPSR.F bit masks FIQ interrupts when taken in non-secure
802 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
803 * when non-secure but only when FIQs are only routed to EL3.
804 */
805 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
806 break;
807 case EXCP_IRQ:
808 /*
809 * When EL3 execution state is 32-bit, if HCR.IMO is set then
810 * we may override the CPSR.I masking when in non-secure state.
811 * The SCR.IRQ setting has already been taken into consideration
812 * when setting the target EL, so it does not have a further
813 * affect here.
814 */
815 hcr = hcr_el2 & HCR_IMO;
816 scr = false;
817 break;
818 default:
819 g_assert_not_reached();
820 }
821
822 if ((scr || hcr) && !secure) {
823 unmasked = true;
824 }
825 }
826 }
827
828 /*
829 * The PSTATE bits only mask the interrupt if we have not overridden the
830 * ability above.
831 */
832 return unmasked || pstate_unmasked;
833 }
834
arm_cpu_exec_interrupt(CPUState * cs,int interrupt_request)835 static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
836 {
837 CPUARMState *env = cpu_env(cs);
838 uint32_t cur_el = arm_current_el(env);
839 bool secure = arm_is_secure(env);
840 uint64_t hcr_el2 = arm_hcr_el2_eff(env);
841 uint32_t target_el;
842 uint32_t excp_idx;
843
844 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
845
846 if (cpu_isar_feature(aa64_nmi, env_archcpu(env)) &&
847 (arm_sctlr(env, cur_el) & SCTLR_NMI)) {
848 if (interrupt_request & CPU_INTERRUPT_NMI) {
849 excp_idx = EXCP_NMI;
850 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
851 if (arm_excp_unmasked(cs, excp_idx, target_el,
852 cur_el, secure, hcr_el2)) {
853 goto found;
854 }
855 }
856 if (interrupt_request & CPU_INTERRUPT_VINMI) {
857 excp_idx = EXCP_VINMI;
858 target_el = 1;
859 if (arm_excp_unmasked(cs, excp_idx, target_el,
860 cur_el, secure, hcr_el2)) {
861 goto found;
862 }
863 }
864 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
865 excp_idx = EXCP_VFNMI;
866 target_el = 1;
867 if (arm_excp_unmasked(cs, excp_idx, target_el,
868 cur_el, secure, hcr_el2)) {
869 goto found;
870 }
871 }
872 } else {
873 /*
874 * NMI disabled: interrupts with superpriority are handled
875 * as if they didn't have it
876 */
877 if (interrupt_request & CPU_INTERRUPT_NMI) {
878 interrupt_request |= CPU_INTERRUPT_HARD;
879 }
880 if (interrupt_request & CPU_INTERRUPT_VINMI) {
881 interrupt_request |= CPU_INTERRUPT_VIRQ;
882 }
883 if (interrupt_request & CPU_INTERRUPT_VFNMI) {
884 interrupt_request |= CPU_INTERRUPT_VFIQ;
885 }
886 }
887
888 if (interrupt_request & CPU_INTERRUPT_FIQ) {
889 excp_idx = EXCP_FIQ;
890 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
891 if (arm_excp_unmasked(cs, excp_idx, target_el,
892 cur_el, secure, hcr_el2)) {
893 goto found;
894 }
895 }
896 if (interrupt_request & CPU_INTERRUPT_HARD) {
897 excp_idx = EXCP_IRQ;
898 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
899 if (arm_excp_unmasked(cs, excp_idx, target_el,
900 cur_el, secure, hcr_el2)) {
901 goto found;
902 }
903 }
904 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
905 excp_idx = EXCP_VIRQ;
906 target_el = 1;
907 if (arm_excp_unmasked(cs, excp_idx, target_el,
908 cur_el, secure, hcr_el2)) {
909 goto found;
910 }
911 }
912 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
913 excp_idx = EXCP_VFIQ;
914 target_el = 1;
915 if (arm_excp_unmasked(cs, excp_idx, target_el,
916 cur_el, secure, hcr_el2)) {
917 goto found;
918 }
919 }
920 if (interrupt_request & CPU_INTERRUPT_VSERR) {
921 excp_idx = EXCP_VSERR;
922 target_el = 1;
923 if (arm_excp_unmasked(cs, excp_idx, target_el,
924 cur_el, secure, hcr_el2)) {
925 /* Taking a virtual abort clears HCR_EL2.VSE */
926 env->cp15.hcr_el2 &= ~HCR_VSE;
927 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
928 goto found;
929 }
930 }
931 return false;
932
933 found:
934 cs->exception_index = excp_idx;
935 env->exception.target_el = target_el;
936 cs->cc->tcg_ops->do_interrupt(cs);
937 return true;
938 }
939
940 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
941
arm_cpu_update_virq(ARMCPU * cpu)942 void arm_cpu_update_virq(ARMCPU *cpu)
943 {
944 /*
945 * Update the interrupt level for VIRQ, which is the logical OR of
946 * the HCR_EL2.VI bit and the input line level from the GIC.
947 */
948 CPUARMState *env = &cpu->env;
949 CPUState *cs = CPU(cpu);
950
951 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
952 !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
953 (env->irq_line_state & CPU_INTERRUPT_VIRQ);
954
955 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
956 if (new_state) {
957 cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
958 } else {
959 cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
960 }
961 }
962 }
963
arm_cpu_update_vfiq(ARMCPU * cpu)964 void arm_cpu_update_vfiq(ARMCPU *cpu)
965 {
966 /*
967 * Update the interrupt level for VFIQ, which is the logical OR of
968 * the HCR_EL2.VF bit and the input line level from the GIC.
969 */
970 CPUARMState *env = &cpu->env;
971 CPUState *cs = CPU(cpu);
972
973 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VF) &&
974 !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) ||
975 (env->irq_line_state & CPU_INTERRUPT_VFIQ);
976
977 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
978 if (new_state) {
979 cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
980 } else {
981 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
982 }
983 }
984 }
985
arm_cpu_update_vinmi(ARMCPU * cpu)986 void arm_cpu_update_vinmi(ARMCPU *cpu)
987 {
988 /*
989 * Update the interrupt level for VINMI, which is the logical OR of
990 * the HCRX_EL2.VINMI bit and the input line level from the GIC.
991 */
992 CPUARMState *env = &cpu->env;
993 CPUState *cs = CPU(cpu);
994
995 bool new_state = ((arm_hcr_el2_eff(env) & HCR_VI) &&
996 (arm_hcrx_el2_eff(env) & HCRX_VINMI)) ||
997 (env->irq_line_state & CPU_INTERRUPT_VINMI);
998
999 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VINMI) != 0)) {
1000 if (new_state) {
1001 cpu_interrupt(cs, CPU_INTERRUPT_VINMI);
1002 } else {
1003 cpu_reset_interrupt(cs, CPU_INTERRUPT_VINMI);
1004 }
1005 }
1006 }
1007
arm_cpu_update_vfnmi(ARMCPU * cpu)1008 void arm_cpu_update_vfnmi(ARMCPU *cpu)
1009 {
1010 /*
1011 * Update the interrupt level for VFNMI, which is the HCRX_EL2.VFNMI bit.
1012 */
1013 CPUARMState *env = &cpu->env;
1014 CPUState *cs = CPU(cpu);
1015
1016 bool new_state = (arm_hcr_el2_eff(env) & HCR_VF) &&
1017 (arm_hcrx_el2_eff(env) & HCRX_VFNMI);
1018
1019 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) != 0)) {
1020 if (new_state) {
1021 cpu_interrupt(cs, CPU_INTERRUPT_VFNMI);
1022 } else {
1023 cpu_reset_interrupt(cs, CPU_INTERRUPT_VFNMI);
1024 }
1025 }
1026 }
1027
arm_cpu_update_vserr(ARMCPU * cpu)1028 void arm_cpu_update_vserr(ARMCPU *cpu)
1029 {
1030 /*
1031 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
1032 */
1033 CPUARMState *env = &cpu->env;
1034 CPUState *cs = CPU(cpu);
1035
1036 bool new_state = env->cp15.hcr_el2 & HCR_VSE;
1037
1038 if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VSERR) != 0)) {
1039 if (new_state) {
1040 cpu_interrupt(cs, CPU_INTERRUPT_VSERR);
1041 } else {
1042 cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR);
1043 }
1044 }
1045 }
1046
1047 #ifndef CONFIG_USER_ONLY
arm_cpu_set_irq(void * opaque,int irq,int level)1048 static void arm_cpu_set_irq(void *opaque, int irq, int level)
1049 {
1050 ARMCPU *cpu = opaque;
1051 CPUARMState *env = &cpu->env;
1052 CPUState *cs = CPU(cpu);
1053 static const int mask[] = {
1054 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
1055 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
1056 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
1057 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ,
1058 [ARM_CPU_NMI] = CPU_INTERRUPT_NMI,
1059 [ARM_CPU_VINMI] = CPU_INTERRUPT_VINMI,
1060 };
1061
1062 if (!arm_feature(env, ARM_FEATURE_EL2) &&
1063 (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) {
1064 /*
1065 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
1066 * have EL2 support we don't care. (Unless the guest is doing something
1067 * silly this will only be calls saying "level is still 0".)
1068 */
1069 return;
1070 }
1071
1072 if (level) {
1073 env->irq_line_state |= mask[irq];
1074 } else {
1075 env->irq_line_state &= ~mask[irq];
1076 }
1077
1078 switch (irq) {
1079 case ARM_CPU_VIRQ:
1080 arm_cpu_update_virq(cpu);
1081 break;
1082 case ARM_CPU_VFIQ:
1083 arm_cpu_update_vfiq(cpu);
1084 break;
1085 case ARM_CPU_VINMI:
1086 arm_cpu_update_vinmi(cpu);
1087 break;
1088 case ARM_CPU_IRQ:
1089 case ARM_CPU_FIQ:
1090 case ARM_CPU_NMI:
1091 if (level) {
1092 cpu_interrupt(cs, mask[irq]);
1093 } else {
1094 cpu_reset_interrupt(cs, mask[irq]);
1095 }
1096 break;
1097 default:
1098 g_assert_not_reached();
1099 }
1100 }
1101
arm_cpu_virtio_is_big_endian(CPUState * cs)1102 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
1103 {
1104 ARMCPU *cpu = ARM_CPU(cs);
1105 CPUARMState *env = &cpu->env;
1106
1107 cpu_synchronize_state(cs);
1108 return arm_cpu_data_is_big_endian(env);
1109 }
1110
1111 #ifdef CONFIG_TCG
arm_cpu_exec_halt(CPUState * cs)1112 bool arm_cpu_exec_halt(CPUState *cs)
1113 {
1114 bool leave_halt = cpu_has_work(cs);
1115
1116 if (leave_halt) {
1117 /* We're about to come out of WFI/WFE: disable the WFxT timer */
1118 ARMCPU *cpu = ARM_CPU(cs);
1119 if (cpu->wfxt_timer) {
1120 timer_del(cpu->wfxt_timer);
1121 }
1122 }
1123 return leave_halt;
1124 }
1125 #endif
1126
arm_wfxt_timer_cb(void * opaque)1127 static void arm_wfxt_timer_cb(void *opaque)
1128 {
1129 ARMCPU *cpu = opaque;
1130 CPUState *cs = CPU(cpu);
1131
1132 /*
1133 * We expect the CPU to be halted; this will cause arm_cpu_is_work()
1134 * to return true (so we will come out of halt even with no other
1135 * pending interrupt), and the TCG accelerator's cpu_exec_interrupt()
1136 * function auto-clears the CPU_INTERRUPT_EXITTB flag for us.
1137 */
1138 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
1139 }
1140 #endif
1141
arm_disas_set_info(CPUState * cpu,disassemble_info * info)1142 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
1143 {
1144 ARMCPU *ac = ARM_CPU(cpu);
1145 CPUARMState *env = &ac->env;
1146 bool sctlr_b = arm_sctlr_b(env);
1147
1148 if (is_a64(env)) {
1149 info->cap_arch = CS_ARCH_ARM64;
1150 info->cap_insn_unit = 4;
1151 info->cap_insn_split = 4;
1152 } else {
1153 int cap_mode;
1154 if (env->thumb) {
1155 info->cap_insn_unit = 2;
1156 info->cap_insn_split = 4;
1157 cap_mode = CS_MODE_THUMB;
1158 } else {
1159 info->cap_insn_unit = 4;
1160 info->cap_insn_split = 4;
1161 cap_mode = CS_MODE_ARM;
1162 }
1163 if (arm_feature(env, ARM_FEATURE_V8)) {
1164 cap_mode |= CS_MODE_V8;
1165 }
1166 if (arm_feature(env, ARM_FEATURE_M)) {
1167 cap_mode |= CS_MODE_MCLASS;
1168 }
1169 info->cap_arch = CS_ARCH_ARM;
1170 info->cap_mode = cap_mode;
1171 }
1172
1173 info->endian = BFD_ENDIAN_LITTLE;
1174 if (bswap_code(sctlr_b)) {
1175 info->endian = target_big_endian() ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
1176 }
1177 info->flags &= ~INSN_ARM_BE32;
1178 #ifndef CONFIG_USER_ONLY
1179 if (sctlr_b) {
1180 info->flags |= INSN_ARM_BE32;
1181 }
1182 #endif
1183 }
1184
aarch64_cpu_dump_state(CPUState * cs,FILE * f,int flags)1185 static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1186 {
1187 ARMCPU *cpu = ARM_CPU(cs);
1188 CPUARMState *env = &cpu->env;
1189 uint32_t psr = pstate_read(env);
1190 int i, j;
1191 int el = arm_current_el(env);
1192 uint64_t hcr = arm_hcr_el2_eff(env);
1193 const char *ns_status;
1194 bool sve;
1195
1196 qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
1197 for (i = 0; i < 32; i++) {
1198 if (i == 31) {
1199 qemu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
1200 } else {
1201 qemu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
1202 (i + 2) % 3 ? " " : "\n");
1203 }
1204 }
1205
1206 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
1207 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1208 } else {
1209 ns_status = "";
1210 }
1211 qemu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1212 psr,
1213 psr & PSTATE_N ? 'N' : '-',
1214 psr & PSTATE_Z ? 'Z' : '-',
1215 psr & PSTATE_C ? 'C' : '-',
1216 psr & PSTATE_V ? 'V' : '-',
1217 ns_status,
1218 el,
1219 psr & PSTATE_SP ? 'h' : 't');
1220
1221 if (cpu_isar_feature(aa64_sme, cpu)) {
1222 qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
1223 env->svcr,
1224 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
1225 (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
1226 }
1227 if (cpu_isar_feature(aa64_bti, cpu)) {
1228 qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
1229 }
1230 qemu_fprintf(f, "%s%s%s",
1231 (hcr & HCR_NV) ? " NV" : "",
1232 (hcr & HCR_NV1) ? " NV1" : "",
1233 (hcr & HCR_NV2) ? " NV2" : "");
1234 if (!(flags & CPU_DUMP_FPU)) {
1235 qemu_fprintf(f, "\n");
1236 return;
1237 }
1238 if (fp_exception_el(env, el) != 0) {
1239 qemu_fprintf(f, " FPU disabled\n");
1240 return;
1241 }
1242 qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
1243 vfp_get_fpcr(env), vfp_get_fpsr(env));
1244
1245 if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
1246 sve = sme_exception_el(env, el) == 0;
1247 } else if (cpu_isar_feature(aa64_sve, cpu)) {
1248 sve = sve_exception_el(env, el) == 0;
1249 } else {
1250 sve = false;
1251 }
1252
1253 if (sve) {
1254 int zcr_len = sve_vqm1_for_el(env, el);
1255
1256 for (i = 0; i <= FFR_PRED_NUM; i++) {
1257 bool eol;
1258 if (i == FFR_PRED_NUM) {
1259 qemu_fprintf(f, "FFR=");
1260 /* It's last, so end the line. */
1261 eol = true;
1262 } else {
1263 qemu_fprintf(f, "P%02d=", i);
1264 switch (zcr_len) {
1265 case 0:
1266 eol = i % 8 == 7;
1267 break;
1268 case 1:
1269 eol = i % 6 == 5;
1270 break;
1271 case 2:
1272 case 3:
1273 eol = i % 3 == 2;
1274 break;
1275 default:
1276 /* More than one quadword per predicate. */
1277 eol = true;
1278 break;
1279 }
1280 }
1281 for (j = zcr_len / 4; j >= 0; j--) {
1282 int digits;
1283 if (j * 4 + 4 <= zcr_len + 1) {
1284 digits = 16;
1285 } else {
1286 digits = (zcr_len % 4 + 1) * 4;
1287 }
1288 qemu_fprintf(f, "%0*" PRIx64 "%s", digits,
1289 env->vfp.pregs[i].p[j],
1290 j ? ":" : eol ? "\n" : " ");
1291 }
1292 }
1293
1294 if (zcr_len == 0) {
1295 /*
1296 * With vl=16, there are only 37 columns per register,
1297 * so output two registers per line.
1298 */
1299 for (i = 0; i < 32; i++) {
1300 qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1301 i, env->vfp.zregs[i].d[1],
1302 env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
1303 }
1304 } else {
1305 for (i = 0; i < 32; i++) {
1306 qemu_fprintf(f, "Z%02d=", i);
1307 for (j = zcr_len; j >= 0; j--) {
1308 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
1309 env->vfp.zregs[i].d[j * 2 + 1],
1310 env->vfp.zregs[i].d[j * 2 + 0],
1311 j ? ":" : "\n");
1312 }
1313 }
1314 }
1315 } else {
1316 for (i = 0; i < 32; i++) {
1317 uint64_t *q = aa64_vfp_qreg(env, i);
1318 qemu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
1319 i, q[1], q[0], (i & 1 ? "\n" : " "));
1320 }
1321 }
1322
1323 if (cpu_isar_feature(aa64_sme, cpu) &&
1324 FIELD_EX64(env->svcr, SVCR, ZA) &&
1325 sme_exception_el(env, el) == 0) {
1326 int zcr_len = sve_vqm1_for_el_sm(env, el, true);
1327 int svl = (zcr_len + 1) * 16;
1328 int svl_lg10 = svl < 100 ? 2 : 3;
1329
1330 for (i = 0; i < svl; i++) {
1331 qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i);
1332 for (j = zcr_len; j >= 0; --j) {
1333 qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c",
1334 env->zarray[i].d[2 * j + 1],
1335 env->zarray[i].d[2 * j],
1336 j ? ':' : '\n');
1337 }
1338 }
1339 }
1340 }
1341
arm_cpu_dump_state(CPUState * cs,FILE * f,int flags)1342 static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
1343 {
1344 ARMCPU *cpu = ARM_CPU(cs);
1345 CPUARMState *env = &cpu->env;
1346 int i;
1347
1348 if (is_a64(env)) {
1349 aarch64_cpu_dump_state(cs, f, flags);
1350 return;
1351 }
1352
1353 for (i = 0; i < 16; i++) {
1354 qemu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
1355 if ((i % 4) == 3) {
1356 qemu_fprintf(f, "\n");
1357 } else {
1358 qemu_fprintf(f, " ");
1359 }
1360 }
1361
1362 if (arm_feature(env, ARM_FEATURE_M)) {
1363 uint32_t xpsr = xpsr_read(env);
1364 const char *mode;
1365 const char *ns_status = "";
1366
1367 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1368 ns_status = env->v7m.secure ? "S " : "NS ";
1369 }
1370
1371 if (xpsr & XPSR_EXCP) {
1372 mode = "handler";
1373 } else {
1374 if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MASK) {
1375 mode = "unpriv-thread";
1376 } else {
1377 mode = "priv-thread";
1378 }
1379 }
1380
1381 qemu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n",
1382 xpsr,
1383 xpsr & XPSR_N ? 'N' : '-',
1384 xpsr & XPSR_Z ? 'Z' : '-',
1385 xpsr & XPSR_C ? 'C' : '-',
1386 xpsr & XPSR_V ? 'V' : '-',
1387 xpsr & XPSR_T ? 'T' : 'A',
1388 ns_status,
1389 mode);
1390 } else {
1391 uint32_t psr = cpsr_read(env);
1392 const char *ns_status = "";
1393
1394 if (arm_feature(env, ARM_FEATURE_EL3) &&
1395 (psr & CPSR_M) != ARM_CPU_MODE_MON) {
1396 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
1397 }
1398
1399 qemu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1400 psr,
1401 psr & CPSR_N ? 'N' : '-',
1402 psr & CPSR_Z ? 'Z' : '-',
1403 psr & CPSR_C ? 'C' : '-',
1404 psr & CPSR_V ? 'V' : '-',
1405 psr & CPSR_T ? 'T' : 'A',
1406 ns_status,
1407 aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26);
1408 }
1409
1410 if (flags & CPU_DUMP_FPU) {
1411 int numvfpregs = 0;
1412 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1413 numvfpregs = 32;
1414 } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
1415 numvfpregs = 16;
1416 }
1417 for (i = 0; i < numvfpregs; i++) {
1418 uint64_t v = *aa32_vfp_dreg(env, i);
1419 qemu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
1420 i * 2, (uint32_t)v,
1421 i * 2 + 1, (uint32_t)(v >> 32),
1422 i, v);
1423 }
1424 qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env));
1425 if (cpu_isar_feature(aa32_mve, cpu)) {
1426 qemu_fprintf(f, "VPR: %08x\n", env->v7m.vpr);
1427 }
1428 }
1429 }
1430
arm_build_mp_affinity(int idx,uint8_t clustersz)1431 uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
1432 {
1433 uint32_t Aff1 = idx / clustersz;
1434 uint32_t Aff0 = idx % clustersz;
1435 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
1436 }
1437
arm_cpu_mp_affinity(ARMCPU * cpu)1438 uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
1439 {
1440 return cpu->mp_affinity;
1441 }
1442
arm_cpu_initfn(Object * obj)1443 static void arm_cpu_initfn(Object *obj)
1444 {
1445 ARMCPU *cpu = ARM_CPU(obj);
1446
1447 cpu->cp_regs = g_hash_table_new_full(g_direct_hash, g_direct_equal,
1448 NULL, g_free);
1449
1450 QLIST_INIT(&cpu->pre_el_change_hooks);
1451 QLIST_INIT(&cpu->el_change_hooks);
1452
1453 #ifdef CONFIG_USER_ONLY
1454 # ifdef TARGET_AARCH64
1455 /*
1456 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1457 * These values were chosen to fit within the default signal frame.
1458 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1459 * and our corresponding cpu property.
1460 */
1461 cpu->sve_default_vq = 4;
1462 cpu->sme_default_vq = 2;
1463 # endif
1464 #else
1465 /* Our inbound IRQ and FIQ lines */
1466 if (kvm_enabled()) {
1467 /*
1468 * VIRQ, VFIQ, NMI, VINMI are unused with KVM but we add
1469 * them to maintain the same interface as non-KVM CPUs.
1470 */
1471 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 6);
1472 } else {
1473 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 6);
1474 }
1475
1476 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
1477 ARRAY_SIZE(cpu->gt_timer_outputs));
1478
1479 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
1480 "gicv3-maintenance-interrupt", 1);
1481 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
1482 "pmu-interrupt", 1);
1483 #endif
1484
1485 /* DTB consumers generally don't in fact care what the 'compatible'
1486 * string is, so always provide some string and trust that a hypothetical
1487 * picky DTB consumer will also provide a helpful error message.
1488 */
1489 cpu->dtb_compatible = "qemu,unknown";
1490 cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */
1491 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
1492
1493 if (tcg_enabled() || hvf_enabled()) {
1494 /* TCG and HVF implement PSCI 1.1 */
1495 cpu->psci_version = QEMU_PSCI_VERSION_1_1;
1496 }
1497 }
1498
1499 /*
1500 * 0 means "unset, use the default value". That default might vary depending
1501 * on the CPU type, and is set in the realize fn.
1502 */
1503 static const Property arm_cpu_gt_cntfrq_property =
1504 DEFINE_PROP_UINT64("cntfrq", ARMCPU, gt_cntfrq_hz, 0);
1505
1506 static const Property arm_cpu_reset_cbar_property =
1507 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
1508
1509 static const Property arm_cpu_reset_hivecs_property =
1510 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
1511
1512 #ifndef CONFIG_USER_ONLY
1513 static const Property arm_cpu_has_el2_property =
1514 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
1515
1516 static const Property arm_cpu_has_el3_property =
1517 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
1518 #endif
1519
1520 static const Property arm_cpu_cfgend_property =
1521 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
1522
1523 static const Property arm_cpu_has_vfp_property =
1524 DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
1525
1526 static const Property arm_cpu_has_vfp_d32_property =
1527 DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true);
1528
1529 static const Property arm_cpu_has_neon_property =
1530 DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true);
1531
1532 static const Property arm_cpu_has_dsp_property =
1533 DEFINE_PROP_BOOL("dsp", ARMCPU, has_dsp, true);
1534
1535 static const Property arm_cpu_has_mpu_property =
1536 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
1537
1538 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1539 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1540 * the right value for that particular CPU type, and we don't want
1541 * to override that with an incorrect constant value.
1542 */
1543 static const Property arm_cpu_pmsav7_dregion_property =
1544 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
1545 pmsav7_dregion,
1546 qdev_prop_uint32, uint32_t);
1547
arm_get_pmu(Object * obj,Error ** errp)1548 static bool arm_get_pmu(Object *obj, Error **errp)
1549 {
1550 ARMCPU *cpu = ARM_CPU(obj);
1551
1552 return cpu->has_pmu;
1553 }
1554
arm_set_pmu(Object * obj,bool value,Error ** errp)1555 static void arm_set_pmu(Object *obj, bool value, Error **errp)
1556 {
1557 ARMCPU *cpu = ARM_CPU(obj);
1558
1559 if (value) {
1560 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1561 error_setg(errp, "'pmu' feature not supported by KVM on this host");
1562 return;
1563 }
1564 set_feature(&cpu->env, ARM_FEATURE_PMU);
1565 } else {
1566 unset_feature(&cpu->env, ARM_FEATURE_PMU);
1567 }
1568 cpu->has_pmu = value;
1569 }
1570
aarch64_cpu_get_aarch64(Object * obj,Error ** errp)1571 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
1572 {
1573 ARMCPU *cpu = ARM_CPU(obj);
1574
1575 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
1576 }
1577
aarch64_cpu_set_aarch64(Object * obj,bool value,Error ** errp)1578 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
1579 {
1580 ARMCPU *cpu = ARM_CPU(obj);
1581
1582 /*
1583 * At this time, this property is only allowed if KVM is enabled. This
1584 * restriction allows us to avoid fixing up functionality that assumes a
1585 * uniform execution state like do_interrupt.
1586 */
1587 if (value == false) {
1588 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
1589 error_setg(errp, "'aarch64' feature cannot be disabled "
1590 "unless KVM is enabled and 32-bit EL1 "
1591 "is supported");
1592 return;
1593 }
1594 unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
1595 } else {
1596 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
1597 }
1598 }
1599
gt_cntfrq_period_ns(ARMCPU * cpu)1600 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
1601 {
1602 /*
1603 * The exact approach to calculating guest ticks is:
1604 *
1605 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1606 * NANOSECONDS_PER_SECOND);
1607 *
1608 * We don't do that. Rather we intentionally use integer division
1609 * truncation below and in the caller for the conversion of host monotonic
1610 * time to guest ticks to provide the exact inverse for the semantics of
1611 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1612 * it loses precision when representing frequencies where
1613 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1614 * provide an exact inverse leads to scheduling timers with negative
1615 * periods, which in turn leads to sticky behaviour in the guest.
1616 *
1617 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1618 * cannot become zero.
1619 */
1620 return NANOSECONDS_PER_SECOND > cpu->gt_cntfrq_hz ?
1621 NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
1622 }
1623
arm_cpu_propagate_feature_implications(ARMCPU * cpu)1624 static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
1625 {
1626 CPUARMState *env = &cpu->env;
1627 bool no_aa32 = false;
1628
1629 /*
1630 * Some features automatically imply others: set the feature
1631 * bits explicitly for these cases.
1632 */
1633
1634 if (arm_feature(env, ARM_FEATURE_M)) {
1635 set_feature(env, ARM_FEATURE_PMSA);
1636 }
1637
1638 if (arm_feature(env, ARM_FEATURE_V8)) {
1639 if (arm_feature(env, ARM_FEATURE_M)) {
1640 set_feature(env, ARM_FEATURE_V7);
1641 } else {
1642 set_feature(env, ARM_FEATURE_V7VE);
1643 }
1644 }
1645
1646 /*
1647 * There exist AArch64 cpus without AArch32 support. When KVM
1648 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1649 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1650 * As a general principle, we also do not make ID register
1651 * consistency checks anywhere unless using TCG, because only
1652 * for TCG would a consistency-check failure be a QEMU bug.
1653 */
1654 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1655 no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
1656 }
1657
1658 if (arm_feature(env, ARM_FEATURE_V7VE)) {
1659 /*
1660 * v7 Virtualization Extensions. In real hardware this implies
1661 * EL2 and also the presence of the Security Extensions.
1662 * For QEMU, for backwards-compatibility we implement some
1663 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1664 * include the various other features that V7VE implies.
1665 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1666 * Security Extensions is ARM_FEATURE_EL3.
1667 */
1668 assert(!tcg_enabled() || no_aa32 ||
1669 cpu_isar_feature(aa32_arm_div, cpu));
1670 set_feature(env, ARM_FEATURE_LPAE);
1671 set_feature(env, ARM_FEATURE_V7);
1672 }
1673 if (arm_feature(env, ARM_FEATURE_V7)) {
1674 set_feature(env, ARM_FEATURE_VAPA);
1675 set_feature(env, ARM_FEATURE_THUMB2);
1676 set_feature(env, ARM_FEATURE_MPIDR);
1677 if (!arm_feature(env, ARM_FEATURE_M)) {
1678 set_feature(env, ARM_FEATURE_V6K);
1679 } else {
1680 set_feature(env, ARM_FEATURE_V6);
1681 }
1682
1683 /*
1684 * Always define VBAR for V7 CPUs even if it doesn't exist in
1685 * non-EL3 configs. This is needed by some legacy boards.
1686 */
1687 set_feature(env, ARM_FEATURE_VBAR);
1688 }
1689 if (arm_feature(env, ARM_FEATURE_V6K)) {
1690 set_feature(env, ARM_FEATURE_V6);
1691 set_feature(env, ARM_FEATURE_MVFR);
1692 }
1693 if (arm_feature(env, ARM_FEATURE_V6)) {
1694 set_feature(env, ARM_FEATURE_V5);
1695 if (!arm_feature(env, ARM_FEATURE_M)) {
1696 assert(!tcg_enabled() || no_aa32 ||
1697 cpu_isar_feature(aa32_jazelle, cpu));
1698 set_feature(env, ARM_FEATURE_AUXCR);
1699 }
1700 }
1701 if (arm_feature(env, ARM_FEATURE_V5)) {
1702 set_feature(env, ARM_FEATURE_V4T);
1703 }
1704 if (arm_feature(env, ARM_FEATURE_LPAE)) {
1705 set_feature(env, ARM_FEATURE_V7MP);
1706 }
1707 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1708 set_feature(env, ARM_FEATURE_CBAR);
1709 }
1710 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1711 !arm_feature(env, ARM_FEATURE_M)) {
1712 set_feature(env, ARM_FEATURE_THUMB_DSP);
1713 }
1714 }
1715
arm_cpu_post_init(Object * obj)1716 void arm_cpu_post_init(Object *obj)
1717 {
1718 ARMCPU *cpu = ARM_CPU(obj);
1719
1720 /*
1721 * Some features imply others. Figure this out now, because we
1722 * are going to look at the feature bits in deciding which
1723 * properties to add.
1724 */
1725 arm_cpu_propagate_feature_implications(cpu);
1726
1727 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1728 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
1729 aarch64_cpu_set_aarch64);
1730 object_property_set_description(obj, "aarch64",
1731 "Set on/off to enable/disable aarch64 "
1732 "execution state ");
1733 }
1734 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
1735 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
1736 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
1737 }
1738
1739 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
1740 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
1741 }
1742
1743 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
1744 object_property_add_uint64_ptr(obj, "rvbar",
1745 &cpu->rvbar_prop,
1746 OBJ_PROP_FLAG_READWRITE);
1747 }
1748
1749 #ifndef CONFIG_USER_ONLY
1750 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1751 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1752 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1753 */
1754 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
1755
1756 object_property_add_link(obj, "secure-memory",
1757 TYPE_MEMORY_REGION,
1758 (Object **)&cpu->secure_memory,
1759 qdev_prop_allow_set_link_before_realize,
1760 OBJ_PROP_LINK_STRONG);
1761 }
1762
1763 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
1764 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
1765 }
1766 #endif
1767
1768 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
1769 cpu->has_pmu = true;
1770 object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu);
1771 }
1772
1773 /*
1774 * Allow user to turn off VFP and Neon support, but only for TCG --
1775 * KVM does not currently allow us to lie to the guest about its
1776 * ID/feature registers, so the guest always sees what the host has.
1777 */
1778 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1779 if (cpu_isar_feature(aa64_fp_simd, cpu)) {
1780 cpu->has_vfp = true;
1781 cpu->has_vfp_d32 = true;
1782 if (tcg_enabled() || qtest_enabled()) {
1783 qdev_property_add_static(DEVICE(obj),
1784 &arm_cpu_has_vfp_property);
1785 }
1786 }
1787 } else if (cpu_isar_feature(aa32_vfp, cpu)) {
1788 cpu->has_vfp = true;
1789 if (tcg_enabled() || qtest_enabled()) {
1790 qdev_property_add_static(DEVICE(obj),
1791 &arm_cpu_has_vfp_property);
1792 }
1793 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
1794 cpu->has_vfp_d32 = true;
1795 /*
1796 * The permitted values of the SIMDReg bits [3:0] on
1797 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1798 * make sure that has_vfp_d32 can not be set to false.
1799 */
1800 if ((tcg_enabled() || qtest_enabled())
1801 && !(arm_feature(&cpu->env, ARM_FEATURE_V8)
1802 && !arm_feature(&cpu->env, ARM_FEATURE_M))) {
1803 qdev_property_add_static(DEVICE(obj),
1804 &arm_cpu_has_vfp_d32_property);
1805 }
1806 }
1807 }
1808
1809 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
1810 cpu->has_neon = true;
1811 if (!kvm_enabled()) {
1812 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
1813 }
1814 }
1815
1816 if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
1817 arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
1818 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
1819 }
1820
1821 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
1822 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
1823 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1824 qdev_property_add_static(DEVICE(obj),
1825 &arm_cpu_pmsav7_dregion_property);
1826 }
1827 }
1828
1829 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
1830 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
1831 qdev_prop_allow_set_link_before_realize,
1832 OBJ_PROP_LINK_STRONG);
1833 /*
1834 * M profile: initial value of the Secure VTOR. We can't just use
1835 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1836 * the property to be set after realize.
1837 */
1838 object_property_add_uint32_ptr(obj, "init-svtor",
1839 &cpu->init_svtor,
1840 OBJ_PROP_FLAG_READWRITE);
1841 }
1842 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
1843 /*
1844 * Initial value of the NS VTOR (for cores without the Security
1845 * extension, this is the only VTOR)
1846 */
1847 object_property_add_uint32_ptr(obj, "init-nsvtor",
1848 &cpu->init_nsvtor,
1849 OBJ_PROP_FLAG_READWRITE);
1850 }
1851
1852 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1853 object_property_add_uint32_ptr(obj, "psci-conduit",
1854 &cpu->psci_conduit,
1855 OBJ_PROP_FLAG_READWRITE);
1856
1857 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
1858
1859 if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1860 qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
1861 }
1862
1863 if (kvm_enabled()) {
1864 kvm_arm_add_vcpu_properties(cpu);
1865 }
1866
1867 #ifndef CONFIG_USER_ONLY
1868 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) &&
1869 cpu_isar_feature(aa64_mte, cpu)) {
1870 object_property_add_link(obj, "tag-memory",
1871 TYPE_MEMORY_REGION,
1872 (Object **)&cpu->tag_memory,
1873 qdev_prop_allow_set_link_before_realize,
1874 OBJ_PROP_LINK_STRONG);
1875
1876 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
1877 object_property_add_link(obj, "secure-tag-memory",
1878 TYPE_MEMORY_REGION,
1879 (Object **)&cpu->secure_tag_memory,
1880 qdev_prop_allow_set_link_before_realize,
1881 OBJ_PROP_LINK_STRONG);
1882 }
1883 }
1884 #endif
1885 }
1886
arm_cpu_finalizefn(Object * obj)1887 static void arm_cpu_finalizefn(Object *obj)
1888 {
1889 ARMCPU *cpu = ARM_CPU(obj);
1890 ARMELChangeHook *hook, *next;
1891
1892 g_hash_table_destroy(cpu->cp_regs);
1893
1894 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
1895 QLIST_REMOVE(hook, node);
1896 g_free(hook);
1897 }
1898 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
1899 QLIST_REMOVE(hook, node);
1900 g_free(hook);
1901 }
1902 #ifndef CONFIG_USER_ONLY
1903 if (cpu->pmu_timer) {
1904 timer_free(cpu->pmu_timer);
1905 }
1906 if (cpu->wfxt_timer) {
1907 timer_free(cpu->wfxt_timer);
1908 }
1909 #endif
1910 }
1911
arm_cpu_finalize_features(ARMCPU * cpu,Error ** errp)1912 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
1913 {
1914 Error *local_err = NULL;
1915
1916 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1917 arm_cpu_sve_finalize(cpu, &local_err);
1918 if (local_err != NULL) {
1919 error_propagate(errp, local_err);
1920 return;
1921 }
1922
1923 /*
1924 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1925 * FEAT_SME_FA64 is present). However our implementation currently
1926 * assumes it, so if the user asked for sve=off then turn off SME also.
1927 * (KVM doesn't currently support SME at all.)
1928 */
1929 if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) {
1930 object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort);
1931 }
1932
1933 arm_cpu_sme_finalize(cpu, &local_err);
1934 if (local_err != NULL) {
1935 error_propagate(errp, local_err);
1936 return;
1937 }
1938
1939 arm_cpu_pauth_finalize(cpu, &local_err);
1940 if (local_err != NULL) {
1941 error_propagate(errp, local_err);
1942 return;
1943 }
1944
1945 arm_cpu_lpa2_finalize(cpu, &local_err);
1946 if (local_err != NULL) {
1947 error_propagate(errp, local_err);
1948 return;
1949 }
1950 }
1951
1952 if (kvm_enabled()) {
1953 kvm_arm_steal_time_finalize(cpu, &local_err);
1954 if (local_err != NULL) {
1955 error_propagate(errp, local_err);
1956 return;
1957 }
1958 }
1959 }
1960
arm_cpu_realizefn(DeviceState * dev,Error ** errp)1961 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
1962 {
1963 CPUState *cs = CPU(dev);
1964 ARMCPU *cpu = ARM_CPU(dev);
1965 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
1966 CPUARMState *env = &cpu->env;
1967 Error *local_err = NULL;
1968
1969 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1970 /* Use pc-relative instructions in system-mode */
1971 tcg_cflags_set(cs, CF_PCREL);
1972 #endif
1973
1974 /* If we needed to query the host kernel for the CPU features
1975 * then it's possible that might have failed in the initfn, but
1976 * this is the first point where we can report it.
1977 */
1978 if (cpu->host_cpu_probe_failed) {
1979 if (!kvm_enabled() && !hvf_enabled()) {
1980 error_setg(errp, "The 'host' CPU type can only be used with KVM or HVF");
1981 } else {
1982 error_setg(errp, "Failed to retrieve host CPU features");
1983 }
1984 return;
1985 }
1986
1987 if (!cpu->gt_cntfrq_hz) {
1988 /*
1989 * 0 means "the board didn't set a value, use the default". (We also
1990 * get here for the CONFIG_USER_ONLY case.)
1991 * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
1992 * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
1993 * which gives a 16ns tick period.
1994 *
1995 * We will use the back-compat value:
1996 * - for QEMU CPU types added before we standardized on 1GHz
1997 * - for versioned machine types with a version of 9.0 or earlier
1998 */
1999 if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
2000 cpu->backcompat_cntfrq) {
2001 cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
2002 } else {
2003 cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
2004 }
2005 }
2006
2007 #ifndef CONFIG_USER_ONLY
2008 /* The NVIC and M-profile CPU are two halves of a single piece of
2009 * hardware; trying to use one without the other is a command line
2010 * error and will result in segfaults if not caught here.
2011 */
2012 if (arm_feature(env, ARM_FEATURE_M)) {
2013 if (!env->nvic) {
2014 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
2015 return;
2016 }
2017 } else {
2018 if (env->nvic) {
2019 error_setg(errp, "This board can only be used with Cortex-M CPUs");
2020 return;
2021 }
2022 }
2023
2024 if (!tcg_enabled() && !qtest_enabled()) {
2025 /*
2026 * We assume that no accelerator except TCG (and the "not really an
2027 * accelerator" qtest) can handle these features, because Arm hardware
2028 * virtualization can't virtualize them.
2029 *
2030 * Catch all the cases which might cause us to create more than one
2031 * address space for the CPU (otherwise we will assert() later in
2032 * cpu_address_space_init()).
2033 */
2034 if (arm_feature(env, ARM_FEATURE_M)) {
2035 error_setg(errp,
2036 "Cannot enable %s when using an M-profile guest CPU",
2037 current_accel_name());
2038 return;
2039 }
2040 if (cpu->has_el3) {
2041 error_setg(errp,
2042 "Cannot enable %s when guest CPU has EL3 enabled",
2043 current_accel_name());
2044 return;
2045 }
2046 if (cpu->tag_memory) {
2047 error_setg(errp,
2048 "Cannot enable %s when guest CPUs has MTE enabled",
2049 current_accel_name());
2050 return;
2051 }
2052 }
2053
2054 {
2055 uint64_t scale = gt_cntfrq_period_ns(cpu);
2056
2057 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2058 arm_gt_ptimer_cb, cpu);
2059 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2060 arm_gt_vtimer_cb, cpu);
2061 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2062 arm_gt_htimer_cb, cpu);
2063 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2064 arm_gt_stimer_cb, cpu);
2065 cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2066 arm_gt_hvtimer_cb, cpu);
2067 cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2068 arm_gt_sel2timer_cb, cpu);
2069 cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
2070 arm_gt_sel2vtimer_cb, cpu);
2071 }
2072 #endif
2073
2074 cpu_exec_realizefn(cs, &local_err);
2075 if (local_err != NULL) {
2076 error_propagate(errp, local_err);
2077 return;
2078 }
2079
2080 arm_cpu_finalize_features(cpu, &local_err);
2081 if (local_err != NULL) {
2082 error_propagate(errp, local_err);
2083 return;
2084 }
2085
2086 #ifdef CONFIG_USER_ONLY
2087 /*
2088 * User mode relies on IC IVAU instructions to catch modification of
2089 * dual-mapped code.
2090 *
2091 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
2092 * IC IVAU even if the emulated processor does not normally require it.
2093 */
2094 cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0);
2095 #endif
2096
2097 if (arm_feature(env, ARM_FEATURE_AARCH64) &&
2098 cpu->has_vfp != cpu->has_neon) {
2099 /*
2100 * This is an architectural requirement for AArch64; AArch32 is
2101 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
2102 */
2103 error_setg(errp,
2104 "AArch64 CPUs must have both VFP and Neon or neither");
2105 return;
2106 }
2107
2108 if (cpu->has_vfp_d32 != cpu->has_neon) {
2109 error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neither");
2110 return;
2111 }
2112
2113 if (!cpu->has_vfp_d32) {
2114 uint32_t u;
2115
2116 u = cpu->isar.mvfr0;
2117 u = FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */
2118 cpu->isar.mvfr0 = u;
2119 }
2120
2121 if (!cpu->has_vfp) {
2122 uint64_t t;
2123 uint32_t u;
2124
2125 t = cpu->isar.id_aa64isar1;
2126 t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
2127 cpu->isar.id_aa64isar1 = t;
2128
2129 t = cpu->isar.id_aa64pfr0;
2130 t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
2131 cpu->isar.id_aa64pfr0 = t;
2132
2133 u = cpu->isar.id_isar6;
2134 u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
2135 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2136 cpu->isar.id_isar6 = u;
2137
2138 u = cpu->isar.mvfr0;
2139 u = FIELD_DP32(u, MVFR0, FPSP, 0);
2140 u = FIELD_DP32(u, MVFR0, FPDP, 0);
2141 u = FIELD_DP32(u, MVFR0, FPDIVIDE, 0);
2142 u = FIELD_DP32(u, MVFR0, FPSQRT, 0);
2143 u = FIELD_DP32(u, MVFR0, FPROUND, 0);
2144 if (!arm_feature(env, ARM_FEATURE_M)) {
2145 u = FIELD_DP32(u, MVFR0, FPTRAP, 0);
2146 u = FIELD_DP32(u, MVFR0, FPSHVEC, 0);
2147 }
2148 cpu->isar.mvfr0 = u;
2149
2150 u = cpu->isar.mvfr1;
2151 u = FIELD_DP32(u, MVFR1, FPFTZ, 0);
2152 u = FIELD_DP32(u, MVFR1, FPDNAN, 0);
2153 u = FIELD_DP32(u, MVFR1, FPHP, 0);
2154 if (arm_feature(env, ARM_FEATURE_M)) {
2155 u = FIELD_DP32(u, MVFR1, FP16, 0);
2156 }
2157 cpu->isar.mvfr1 = u;
2158
2159 u = cpu->isar.mvfr2;
2160 u = FIELD_DP32(u, MVFR2, FPMISC, 0);
2161 cpu->isar.mvfr2 = u;
2162 }
2163
2164 if (!cpu->has_neon) {
2165 uint64_t t;
2166 uint32_t u;
2167
2168 unset_feature(env, ARM_FEATURE_NEON);
2169
2170 t = cpu->isar.id_aa64isar0;
2171 t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
2172 t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
2173 t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
2174 t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0);
2175 t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
2176 t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
2177 t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
2178 cpu->isar.id_aa64isar0 = t;
2179
2180 t = cpu->isar.id_aa64isar1;
2181 t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
2182 t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
2183 t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
2184 cpu->isar.id_aa64isar1 = t;
2185
2186 t = cpu->isar.id_aa64pfr0;
2187 t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
2188 cpu->isar.id_aa64pfr0 = t;
2189
2190 u = cpu->isar.id_isar5;
2191 u = FIELD_DP32(u, ID_ISAR5, AES, 0);
2192 u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
2193 u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
2194 u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
2195 u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
2196 cpu->isar.id_isar5 = u;
2197
2198 u = cpu->isar.id_isar6;
2199 u = FIELD_DP32(u, ID_ISAR6, DP, 0);
2200 u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
2201 u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
2202 u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
2203 cpu->isar.id_isar6 = u;
2204
2205 if (!arm_feature(env, ARM_FEATURE_M)) {
2206 u = cpu->isar.mvfr1;
2207 u = FIELD_DP32(u, MVFR1, SIMDLS, 0);
2208 u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
2209 u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
2210 u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
2211 cpu->isar.mvfr1 = u;
2212
2213 u = cpu->isar.mvfr2;
2214 u = FIELD_DP32(u, MVFR2, SIMDMISC, 0);
2215 cpu->isar.mvfr2 = u;
2216 }
2217 }
2218
2219 if (!cpu->has_neon && !cpu->has_vfp) {
2220 uint64_t t;
2221 uint32_t u;
2222
2223 t = cpu->isar.id_aa64isar0;
2224 t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
2225 cpu->isar.id_aa64isar0 = t;
2226
2227 t = cpu->isar.id_aa64isar1;
2228 t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
2229 cpu->isar.id_aa64isar1 = t;
2230
2231 u = cpu->isar.mvfr0;
2232 u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
2233 cpu->isar.mvfr0 = u;
2234
2235 /* Despite the name, this field covers both VFP and Neon */
2236 u = cpu->isar.mvfr1;
2237 u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
2238 cpu->isar.mvfr1 = u;
2239 }
2240
2241 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
2242 uint32_t u;
2243
2244 unset_feature(env, ARM_FEATURE_THUMB_DSP);
2245
2246 u = cpu->isar.id_isar1;
2247 u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
2248 cpu->isar.id_isar1 = u;
2249
2250 u = cpu->isar.id_isar2;
2251 u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
2252 u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
2253 cpu->isar.id_isar2 = u;
2254
2255 u = cpu->isar.id_isar3;
2256 u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
2257 u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
2258 cpu->isar.id_isar3 = u;
2259 }
2260
2261
2262 /*
2263 * We rely on no XScale CPU having VFP so we can use the same bits in the
2264 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2265 */
2266 assert(arm_feature(env, ARM_FEATURE_AARCH64) ||
2267 !cpu_isar_feature(aa32_vfp_simd, cpu) ||
2268 !arm_feature(env, ARM_FEATURE_XSCALE));
2269
2270 #ifndef CONFIG_USER_ONLY
2271 {
2272 int pagebits;
2273 if (arm_feature(env, ARM_FEATURE_V7) &&
2274 !arm_feature(env, ARM_FEATURE_M) &&
2275 !arm_feature(env, ARM_FEATURE_PMSA)) {
2276 /*
2277 * v7VMSA drops support for the old ARMv5 tiny pages,
2278 * so we can use 4K pages.
2279 */
2280 pagebits = 12;
2281 } else {
2282 /*
2283 * For CPUs which might have tiny 1K pages, or which have an
2284 * MPU and might have small region sizes, stick with 1K pages.
2285 */
2286 pagebits = 10;
2287 }
2288 if (!set_preferred_target_page_bits(pagebits)) {
2289 /*
2290 * This can only ever happen for hotplugging a CPU, or if
2291 * the board code incorrectly creates a CPU which it has
2292 * promised via minimum_page_size that it will not.
2293 */
2294 error_setg(errp, "This CPU requires a smaller page size "
2295 "than the system is using");
2296 return;
2297 }
2298 }
2299 #endif
2300
2301 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2302 * We don't support setting cluster ID ([16..23]) (known as Aff2
2303 * in later ARM ARM versions), or any of the higher affinity level fields,
2304 * so these bits always RAZ.
2305 */
2306 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
2307 cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index,
2308 ARM_DEFAULT_CPUS_PER_CLUSTER);
2309 }
2310
2311 if (cpu->reset_hivecs) {
2312 cpu->reset_sctlr |= (1 << 13);
2313 }
2314
2315 if (cpu->cfgend) {
2316 if (arm_feature(env, ARM_FEATURE_V7)) {
2317 cpu->reset_sctlr |= SCTLR_EE;
2318 } else {
2319 cpu->reset_sctlr |= SCTLR_B;
2320 }
2321 }
2322
2323 if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
2324 /* If the has_el3 CPU property is disabled then we need to disable the
2325 * feature.
2326 */
2327 unset_feature(env, ARM_FEATURE_EL3);
2328
2329 /*
2330 * Disable the security extension feature bits in the processor
2331 * feature registers as well.
2332 */
2333 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
2334 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
2335 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2336 ID_AA64PFR0, EL3, 0);
2337
2338 /* Disable the realm management extension, which requires EL3. */
2339 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2340 ID_AA64PFR0, RME, 0);
2341 }
2342
2343 if (!cpu->has_el2) {
2344 unset_feature(env, ARM_FEATURE_EL2);
2345 }
2346
2347 if (!cpu->has_pmu) {
2348 unset_feature(env, ARM_FEATURE_PMU);
2349 }
2350 if (arm_feature(env, ARM_FEATURE_PMU)) {
2351 pmu_init(cpu);
2352
2353 if (!kvm_enabled()) {
2354 arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
2355 arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
2356 }
2357
2358 #ifndef CONFIG_USER_ONLY
2359 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
2360 cpu);
2361 #endif
2362 } else {
2363 cpu->isar.id_aa64dfr0 =
2364 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
2365 cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
2366 cpu->pmceid0 = 0;
2367 cpu->pmceid1 = 0;
2368 }
2369
2370 if (!arm_feature(env, ARM_FEATURE_EL2)) {
2371 /*
2372 * Disable the hypervisor feature bits in the processor feature
2373 * registers if we don't have EL2.
2374 */
2375 cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
2376 ID_AA64PFR0, EL2, 0);
2377 cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
2378 ID_PFR1, VIRTUALIZATION, 0);
2379 }
2380
2381 if (cpu_isar_feature(aa64_mte, cpu)) {
2382 /*
2383 * The architectural range of GM blocksize is 2-6, however qemu
2384 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2385 */
2386 if (tcg_enabled()) {
2387 assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
2388 }
2389
2390 #ifndef CONFIG_USER_ONLY
2391 /*
2392 * If we run with TCG and do not have tag-memory provided by
2393 * the machine, then reduce MTE support to instructions enabled at EL0.
2394 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2395 */
2396 if (tcg_enabled() && cpu->tag_memory == NULL) {
2397 cpu->isar.id_aa64pfr1 =
2398 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
2399 }
2400
2401 /*
2402 * If MTE is supported by the host, however it should not be
2403 * enabled on the guest (i.e mte=off), clear guest's MTE bits."
2404 */
2405 if (kvm_enabled() && !cpu->kvm_mte) {
2406 FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
2407 }
2408 #endif
2409 }
2410
2411 #ifndef CONFIG_USER_ONLY
2412 if (tcg_enabled() && cpu_isar_feature(aa64_wfxt, cpu)) {
2413 cpu->wfxt_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2414 arm_wfxt_timer_cb, cpu);
2415 }
2416 #endif
2417
2418 if (tcg_enabled()) {
2419 /*
2420 * Don't report some architectural features in the ID registers
2421 * where TCG does not yet implement it (not even a minimal
2422 * stub version). This avoids guests falling over when they
2423 * try to access the non-existent system registers for them.
2424 */
2425 /* FEAT_SPE (Statistical Profiling Extension) */
2426 cpu->isar.id_aa64dfr0 =
2427 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
2428 /* FEAT_TRBE (Trace Buffer Extension) */
2429 cpu->isar.id_aa64dfr0 =
2430 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
2431 /* FEAT_TRF (Self-hosted Trace Extension) */
2432 cpu->isar.id_aa64dfr0 =
2433 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
2434 cpu->isar.id_dfr0 =
2435 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
2436 /* Trace Macrocell system register access */
2437 cpu->isar.id_aa64dfr0 =
2438 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0);
2439 cpu->isar.id_dfr0 =
2440 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
2441 /* Memory mapped trace */
2442 cpu->isar.id_dfr0 =
2443 FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
2444 /* FEAT_AMU (Activity Monitors Extension) */
2445 cpu->isar.id_aa64pfr0 =
2446 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0);
2447 cpu->isar.id_pfr0 =
2448 FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
2449 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2450 cpu->isar.id_aa64pfr0 =
2451 FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
2452 }
2453
2454 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2455 * to false or by setting pmsav7-dregion to 0.
2456 */
2457 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
2458 cpu->has_mpu = false;
2459 cpu->pmsav7_dregion = 0;
2460 cpu->pmsav8r_hdregion = 0;
2461 }
2462
2463 if (arm_feature(env, ARM_FEATURE_PMSA) &&
2464 arm_feature(env, ARM_FEATURE_V7)) {
2465 uint32_t nr = cpu->pmsav7_dregion;
2466
2467 if (nr > 0xff) {
2468 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
2469 return;
2470 }
2471
2472 if (nr) {
2473 if (arm_feature(env, ARM_FEATURE_V8)) {
2474 /* PMSAv8 */
2475 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
2476 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
2477 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2478 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
2479 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
2480 }
2481 } else {
2482 env->pmsav7.drbar = g_new0(uint32_t, nr);
2483 env->pmsav7.drsr = g_new0(uint32_t, nr);
2484 env->pmsav7.dracr = g_new0(uint32_t, nr);
2485 }
2486 }
2487
2488 if (cpu->pmsav8r_hdregion > 0xff) {
2489 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
2490 cpu->pmsav8r_hdregion);
2491 return;
2492 }
2493
2494 if (cpu->pmsav8r_hdregion) {
2495 env->pmsav8.hprbar = g_new0(uint32_t,
2496 cpu->pmsav8r_hdregion);
2497 env->pmsav8.hprlar = g_new0(uint32_t,
2498 cpu->pmsav8r_hdregion);
2499 }
2500 }
2501
2502 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2503 uint32_t nr = cpu->sau_sregion;
2504
2505 if (nr > 0xff) {
2506 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
2507 return;
2508 }
2509
2510 if (nr) {
2511 env->sau.rbar = g_new0(uint32_t, nr);
2512 env->sau.rlar = g_new0(uint32_t, nr);
2513 }
2514 }
2515
2516 if (arm_feature(env, ARM_FEATURE_EL3)) {
2517 set_feature(env, ARM_FEATURE_VBAR);
2518 }
2519
2520 #ifndef CONFIG_USER_ONLY
2521 if (tcg_enabled() && cpu_isar_feature(aa64_rme, cpu)) {
2522 arm_register_el_change_hook(cpu, >_rme_post_el_change, 0);
2523 }
2524 #endif
2525
2526 register_cp_regs_for_features(cpu);
2527 arm_cpu_register_gdb_regs_for_features(cpu);
2528 arm_cpu_register_gdb_commands(cpu);
2529
2530 init_cpreg_list(cpu);
2531
2532 #ifndef CONFIG_USER_ONLY
2533 MachineState *ms = MACHINE(qdev_get_machine());
2534 unsigned int smp_cpus = ms->smp.cpus;
2535 bool has_secure = cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY);
2536
2537 /*
2538 * We must set cs->num_ases to the final value before
2539 * the first call to cpu_address_space_init.
2540 */
2541 if (cpu->tag_memory != NULL) {
2542 cs->num_ases = 3 + has_secure;
2543 } else {
2544 cs->num_ases = 1 + has_secure;
2545 }
2546
2547 if (has_secure) {
2548 if (!cpu->secure_memory) {
2549 cpu->secure_memory = cs->memory;
2550 }
2551 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
2552 cpu->secure_memory);
2553 }
2554
2555 if (cpu->tag_memory != NULL) {
2556 cpu_address_space_init(cs, ARMASIdx_TagNS, "cpu-tag-memory",
2557 cpu->tag_memory);
2558 if (has_secure) {
2559 cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
2560 cpu->secure_tag_memory);
2561 }
2562 }
2563
2564 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
2565
2566 /* No core_count specified, default to smp_cpus. */
2567 if (cpu->core_count == -1) {
2568 cpu->core_count = smp_cpus;
2569 }
2570 #endif
2571
2572 if (tcg_enabled()) {
2573 int dcz_blocklen = 4 << cpu->dcz_blocksize;
2574
2575 /*
2576 * We only support DCZ blocklen that fits on one page.
2577 *
2578 * Architectually this is always true. However TARGET_PAGE_SIZE
2579 * is variable and, for compatibility with -machine virt-2.7,
2580 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2581 * But even then, while the largest architectural DCZ blocklen
2582 * is 2KiB, no cpu actually uses such a large blocklen.
2583 */
2584 assert(dcz_blocklen <= TARGET_PAGE_SIZE);
2585
2586 /*
2587 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2588 * both nibbles of each byte storing tag data may be written at once.
2589 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2590 */
2591 if (cpu_isar_feature(aa64_mte, cpu)) {
2592 assert(dcz_blocklen >= 2 * TAG_GRANULE);
2593 }
2594 }
2595
2596 qemu_init_vcpu(cs);
2597 cpu_reset(cs);
2598
2599 acc->parent_realize(dev, errp);
2600 }
2601
arm_cpu_class_by_name(const char * cpu_model)2602 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
2603 {
2604 ObjectClass *oc;
2605 char *typename;
2606 char **cpuname;
2607 const char *cpunamestr;
2608
2609 cpuname = g_strsplit(cpu_model, ",", 1);
2610 cpunamestr = cpuname[0];
2611 #ifdef CONFIG_USER_ONLY
2612 /* For backwards compatibility usermode emulation allows "-cpu any",
2613 * which has the same semantics as "-cpu max".
2614 */
2615 if (!strcmp(cpunamestr, "any")) {
2616 cpunamestr = "max";
2617 }
2618 #endif
2619 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
2620 oc = object_class_by_name(typename);
2621 g_strfreev(cpuname);
2622 g_free(typename);
2623
2624 return oc;
2625 }
2626
2627 static const Property arm_cpu_properties[] = {
2628 DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
2629 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2630 mp_affinity, ARM64_AFFINITY_INVALID),
2631 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2632 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2633 /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
2634 DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
2635 DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU,
2636 backcompat_pauth_default_use_qarma5, false),
2637 };
2638
arm_gdb_arch_name(CPUState * cs)2639 static const gchar *arm_gdb_arch_name(CPUState *cs)
2640 {
2641 ARMCPU *cpu = ARM_CPU(cs);
2642 CPUARMState *env = &cpu->env;
2643
2644 if (arm_gdbstub_is_aarch64(cpu)) {
2645 return "aarch64";
2646 }
2647 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2648 return "iwmmxt";
2649 }
2650 return "arm";
2651 }
2652
arm_gdb_get_core_xml_file(CPUState * cs)2653 static const char *arm_gdb_get_core_xml_file(CPUState *cs)
2654 {
2655 ARMCPU *cpu = ARM_CPU(cs);
2656 CPUARMState *env = &cpu->env;
2657
2658 if (arm_gdbstub_is_aarch64(cpu)) {
2659 return "aarch64-core.xml";
2660 }
2661 if (arm_feature(env, ARM_FEATURE_M)) {
2662 return "arm-m-profile.xml";
2663 }
2664 return "arm-core.xml";
2665 }
2666
2667 #ifdef CONFIG_USER_ONLY
2668 /**
2669 * aarch64_untagged_addr:
2670 *
2671 * Remove any address tag from @x. This is explicitly related to the
2672 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general.
2673 *
2674 * There should be a better place to put this, but we need this in
2675 * include/exec/cpu_ldst.h, and not some place linux-user specific.
2676 *
2677 * Note that arm-*-user will never set tagged_addr_enable.
2678 */
aarch64_untagged_addr(CPUState * cs,vaddr x)2679 static vaddr aarch64_untagged_addr(CPUState *cs, vaddr x)
2680 {
2681 CPUARMState *env = cpu_env(cs);
2682 if (env->tagged_addr_enable) {
2683 /*
2684 * TBI is enabled for userspace but not kernelspace addresses.
2685 * Only clear the tag if bit 55 is clear.
2686 */
2687 x &= sextract64(x, 0, 56);
2688 }
2689 return x;
2690 }
2691 #else
2692 #include "hw/core/sysemu-cpu-ops.h"
2693
2694 static const struct SysemuCPUOps arm_sysemu_ops = {
2695 .has_work = arm_cpu_has_work,
2696 .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
2697 .asidx_from_attrs = arm_asidx_from_attrs,
2698 .write_elf32_note = arm_cpu_write_elf32_note,
2699 .write_elf64_note = arm_cpu_write_elf64_note,
2700 .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
2701 .legacy_vmsd = &vmstate_arm_cpu,
2702 };
2703 #endif
2704
2705 #ifdef CONFIG_TCG
2706 #ifndef CONFIG_USER_ONLY
aprofile_pointer_wrap(CPUState * cs,int mmu_idx,vaddr result,vaddr base)2707 static vaddr aprofile_pointer_wrap(CPUState *cs, int mmu_idx,
2708 vaddr result, vaddr base)
2709 {
2710 /*
2711 * The Stage2 and Phys indexes are only used for ptw on arm32,
2712 * and all pte's are aligned, so we never produce a wrap for these.
2713 * Double check that we're not truncating a 40-bit physical address.
2714 */
2715 assert((unsigned)mmu_idx < (ARMMMUIdx_Stage2_S & ARM_MMU_IDX_COREIDX_MASK));
2716
2717 if (!is_a64(cpu_env(cs))) {
2718 return (uint32_t)result;
2719 }
2720
2721 /*
2722 * TODO: For FEAT_CPA2, decide how to we want to resolve
2723 * Unpredictable_CPACHECK in AddressIncrement.
2724 */
2725 return result;
2726 }
2727 #endif /* !CONFIG_USER_ONLY */
2728
2729 static const TCGCPUOps arm_tcg_ops = {
2730 .mttcg_supported = true,
2731 /* ARM processors have a weak memory model */
2732 .guest_default_memory_order = 0,
2733
2734 .initialize = arm_translate_init,
2735 .translate_code = arm_translate_code,
2736 .get_tb_cpu_state = arm_get_tb_cpu_state,
2737 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
2738 .debug_excp_handler = arm_debug_excp_handler,
2739 .restore_state_to_opc = arm_restore_state_to_opc,
2740 .mmu_index = arm_cpu_mmu_index,
2741
2742 #ifdef CONFIG_USER_ONLY
2743 .record_sigsegv = arm_cpu_record_sigsegv,
2744 .record_sigbus = arm_cpu_record_sigbus,
2745 .untagged_addr = aarch64_untagged_addr,
2746 #else
2747 .tlb_fill_align = arm_cpu_tlb_fill_align,
2748 .pointer_wrap = aprofile_pointer_wrap,
2749 .cpu_exec_interrupt = arm_cpu_exec_interrupt,
2750 .cpu_exec_halt = arm_cpu_exec_halt,
2751 .cpu_exec_reset = cpu_reset,
2752 .do_interrupt = arm_cpu_do_interrupt,
2753 .do_transaction_failed = arm_cpu_do_transaction_failed,
2754 .do_unaligned_access = arm_cpu_do_unaligned_access,
2755 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
2756 .debug_check_watchpoint = arm_debug_check_watchpoint,
2757 .debug_check_breakpoint = arm_debug_check_breakpoint,
2758 #endif /* !CONFIG_USER_ONLY */
2759 };
2760 #endif /* CONFIG_TCG */
2761
arm_cpu_class_init(ObjectClass * oc,const void * data)2762 static void arm_cpu_class_init(ObjectClass *oc, const void *data)
2763 {
2764 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2765 CPUClass *cc = CPU_CLASS(acc);
2766 DeviceClass *dc = DEVICE_CLASS(oc);
2767 ResettableClass *rc = RESETTABLE_CLASS(oc);
2768
2769 device_class_set_parent_realize(dc, arm_cpu_realizefn,
2770 &acc->parent_realize);
2771
2772 device_class_set_props(dc, arm_cpu_properties);
2773
2774 resettable_class_set_parent_phases(rc, NULL, arm_cpu_reset_hold, NULL,
2775 &acc->parent_phases);
2776
2777 cc->class_by_name = arm_cpu_class_by_name;
2778 cc->dump_state = arm_cpu_dump_state;
2779 cc->set_pc = arm_cpu_set_pc;
2780 cc->get_pc = arm_cpu_get_pc;
2781 cc->gdb_read_register = arm_cpu_gdb_read_register;
2782 cc->gdb_write_register = arm_cpu_gdb_write_register;
2783 #ifndef CONFIG_USER_ONLY
2784 cc->sysemu_ops = &arm_sysemu_ops;
2785 #endif
2786 cc->gdb_arch_name = arm_gdb_arch_name;
2787 cc->gdb_get_core_xml_file = arm_gdb_get_core_xml_file;
2788 cc->gdb_stop_before_watchpoint = true;
2789 cc->disas_set_info = arm_disas_set_info;
2790
2791 #ifdef CONFIG_TCG
2792 cc->tcg_ops = &arm_tcg_ops;
2793 #endif /* CONFIG_TCG */
2794 }
2795
arm_cpu_instance_init(Object * obj)2796 static void arm_cpu_instance_init(Object *obj)
2797 {
2798 ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2799
2800 acc->info->initfn(obj);
2801 arm_cpu_post_init(obj);
2802 }
2803
cpu_register_class_init(ObjectClass * oc,const void * data)2804 static void cpu_register_class_init(ObjectClass *oc, const void *data)
2805 {
2806 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2807 CPUClass *cc = CPU_CLASS(acc);
2808
2809 acc->info = data;
2810 if (acc->info->deprecation_note) {
2811 cc->deprecation_note = acc->info->deprecation_note;
2812 }
2813 }
2814
arm_cpu_register(const ARMCPUInfo * info)2815 void arm_cpu_register(const ARMCPUInfo *info)
2816 {
2817 TypeInfo type_info = {
2818 .parent = TYPE_ARM_CPU,
2819 .instance_init = arm_cpu_instance_init,
2820 .class_init = info->class_init ?: cpu_register_class_init,
2821 .class_data = info,
2822 };
2823
2824 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2825 type_register_static(&type_info);
2826 g_free((void *)type_info.name);
2827 }
2828
2829 static const TypeInfo arm_cpu_type_info = {
2830 .name = TYPE_ARM_CPU,
2831 .parent = TYPE_CPU,
2832 .instance_size = sizeof(ARMCPU),
2833 .instance_align = __alignof__(ARMCPU),
2834 .instance_init = arm_cpu_initfn,
2835 .instance_finalize = arm_cpu_finalizefn,
2836 .abstract = true,
2837 .class_size = sizeof(ARMCPUClass),
2838 .class_init = arm_cpu_class_init,
2839 };
2840
arm_cpu_register_types(void)2841 static void arm_cpu_register_types(void)
2842 {
2843 type_register_static(&arm_cpu_type_info);
2844 }
2845
2846 type_init(arm_cpu_register_types)
2847