1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2021-25 Axiado Corporation (or its affiliates). All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/memreserve/ 0x3c0013a0 0x00000008; /* cpu-release-addr */ 12/ { 13 model = "Axiado AX3000"; 14 interrupt-parent = <&gic500>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a53"; 25 reg = <0x0 0x0>; 26 enable-method = "spin-table"; 27 cpu-release-addr = <0x0 0x3c0013a0>; 28 d-cache-size = <0x8000>; 29 d-cache-line-size = <64>; 30 d-cache-sets = <128>; 31 i-cache-size = <0x8000>; 32 i-cache-line-size = <64>; 33 i-cache-sets = <256>; 34 next-level-cache = <&l2>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x0 0x1>; 41 enable-method = "spin-table"; 42 cpu-release-addr = <0x0 0x3c0013a0>; 43 d-cache-size = <0x8000>; 44 d-cache-line-size = <64>; 45 d-cache-sets = <128>; 46 i-cache-size = <0x8000>; 47 i-cache-line-size = <64>; 48 i-cache-sets = <256>; 49 next-level-cache = <&l2>; 50 }; 51 52 cpu2: cpu@2 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53"; 55 reg = <0x0 0x2>; 56 enable-method = "spin-table"; 57 cpu-release-addr = <0x0 0x3c0013a0>; 58 d-cache-size = <0x8000>; 59 d-cache-line-size = <64>; 60 d-cache-sets = <128>; 61 i-cache-size = <0x8000>; 62 i-cache-line-size = <64>; 63 i-cache-sets = <256>; 64 next-level-cache = <&l2>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x0 0x3>; 71 enable-method = "spin-table"; 72 cpu-release-addr = <0x0 0x3c0013a0>; 73 d-cache-size = <0x8000>; 74 d-cache-line-size = <64>; 75 d-cache-sets = <128>; 76 i-cache-size = <0x8000>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <256>; 79 next-level-cache = <&l2>; 80 }; 81 82 l2: l2-cache0 { 83 compatible = "cache"; 84 cache-size = <0x100000>; 85 cache-unified; 86 cache-line-size = <64>; 87 cache-sets = <1024>; 88 cache-level = <2>; 89 }; 90 }; 91 92 clocks { 93 clk_xin: clock-200000000 { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <200000000>; 97 clock-output-names = "clk_xin"; 98 }; 99 100 refclk: clock-125000000 { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <125000000>; 104 }; 105 }; 106 107 soc { 108 compatible = "simple-bus"; 109 ranges; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 interrupt-parent = <&gic500>; 113 114 gic500: interrupt-controller@80300000 { 115 compatible = "arm,gic-v3"; 116 reg = <0x00 0x80300000 0x00 0x10000>, 117 <0x00 0x80380000 0x00 0x80000>; 118 ranges; 119 #interrupt-cells = <3>; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 interrupt-controller; 123 #redistributor-regions = <1>; 124 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 125 }; 126 127 /* GPIO Controller banks 0 - 7 */ 128 gpio0: gpio-controller@80500000 { 129 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 130 reg = <0x00 0x80500000 0x00 0x400>; 131 clocks = <&refclk>; 132 interrupt-parent = <&gic500>; 133 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 134 gpio-controller; 135 #gpio-cells = <2>; 136 interrupt-controller; 137 #interrupt-cells = <2>; 138 status = "disabled"; 139 }; 140 141 gpio1: gpio-controller@80580000 { 142 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 143 reg = <0x00 0x80580000 0x00 0x400>; 144 clocks = <&refclk>; 145 interrupt-parent = <&gic500>; 146 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 147 gpio-controller; 148 #gpio-cells = <2>; 149 interrupt-controller; 150 #interrupt-cells = <2>; 151 status = "disabled"; 152 }; 153 154 gpio2: gpio-controller@80600000 { 155 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 156 reg = <0x00 0x80600000 0x00 0x400>; 157 clocks = <&refclk>; 158 interrupt-parent = <&gic500>; 159 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 160 gpio-controller; 161 #gpio-cells = <2>; 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 status = "disabled"; 165 }; 166 167 gpio3: gpio-controller@80680000 { 168 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 169 reg = <0x00 0x80680000 0x00 0x400>; 170 clocks = <&refclk>; 171 interrupt-parent = <&gic500>; 172 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 173 gpio-controller; 174 #gpio-cells = <2>; 175 interrupt-controller; 176 #interrupt-cells = <2>; 177 status = "disabled"; 178 }; 179 180 gpio4: gpio-controller@80700000 { 181 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 182 reg = <0x00 0x80700000 0x00 0x400>; 183 clocks = <&refclk>; 184 interrupt-parent = <&gic500>; 185 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 186 gpio-controller; 187 #gpio-cells = <2>; 188 interrupt-controller; 189 #interrupt-cells = <2>; 190 status = "disabled"; 191 }; 192 193 gpio5: gpio-controller@80780000 { 194 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 195 reg = <0x00 0x80780000 0x00 0x400>; 196 clocks = <&refclk>; 197 interrupt-parent = <&gic500>; 198 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 199 gpio-controller; 200 #gpio-cells = <2>; 201 interrupt-controller; 202 #interrupt-cells = <2>; 203 status = "disabled"; 204 }; 205 206 gpio6: gpio-controller@80800000 { 207 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 208 reg = <0x00 0x80800000 0x00 0x400>; 209 clocks = <&refclk>; 210 interrupt-parent = <&gic500>; 211 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 212 gpio-controller; 213 #gpio-cells = <2>; 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 status = "disabled"; 217 }; 218 219 gpio7: gpio-controller@80880000 { 220 compatible = "axiado,ax3000-gpio", "cdns,gpio-r1p02"; 221 reg = <0x00 0x80880000 0x00 0x400>; 222 clocks = <&refclk>; 223 interrupt-parent = <&gic500>; 224 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 status = "disabled"; 230 }; 231 232 /* I3C Controller 0 - 16 */ 233 i3c0: i3c@80500400 { 234 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 235 reg = <0x00 0x80500400 0x00 0x400>; 236 clocks = <&refclk &clk_xin>; 237 clock-names = "pclk", "sysclk"; 238 interrupt-parent = <&gic500>; 239 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 240 i2c-scl-hz = <100000>; 241 i3c-scl-hz = <400000>; 242 #address-cells = <3>; 243 #size-cells = <0>; 244 status = "disabled"; 245 }; 246 247 i3c1: i3c@80500800 { 248 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 249 reg = <0x00 0x80500800 0x00 0x400>; 250 clocks = <&refclk &clk_xin>; 251 clock-names = "pclk", "sysclk"; 252 interrupt-parent = <&gic500>; 253 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 254 i2c-scl-hz = <100000>; 255 i3c-scl-hz = <400000>; 256 #address-cells = <3>; 257 #size-cells = <0>; 258 status = "disabled"; 259 }; 260 261 i3c2: i3c@80580400 { 262 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 263 reg = <0x00 0x80580400 0x00 0x400>; 264 clocks = <&refclk &clk_xin>; 265 clock-names = "pclk", "sysclk"; 266 interrupt-parent = <&gic500>; 267 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 268 i2c-scl-hz = <100000>; 269 i3c-scl-hz = <400000>; 270 #address-cells = <3>; 271 #size-cells = <0>; 272 status = "disabled"; 273 }; 274 275 i3c3: i3c@80580800 { 276 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 277 reg = <0x00 0x80580800 0x00 0x400>; 278 clocks = <&refclk &clk_xin>; 279 clock-names = "pclk", "sysclk"; 280 interrupt-parent = <&gic500>; 281 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 282 i2c-scl-hz = <100000>; 283 i3c-scl-hz = <400000>; 284 #address-cells = <3>; 285 #size-cells = <0>; 286 status = "disabled"; 287 }; 288 289 i3c4: i3c@80600400 { 290 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 291 reg = <0x00 0x80600400 0x00 0x400>; 292 clocks = <&refclk &clk_xin>; 293 clock-names = "pclk", "sysclk"; 294 interrupt-parent = <&gic500>; 295 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 296 i2c-scl-hz = <100000>; 297 i3c-scl-hz = <400000>; 298 #address-cells = <3>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 i3c5: i3c@80600800 { 304 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 305 reg = <0x00 0x80600800 0x00 0x400>; 306 clocks = <&refclk &clk_xin>; 307 clock-names = "pclk", "sysclk"; 308 interrupt-parent = <&gic500>; 309 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 310 i2c-scl-hz = <100000>; 311 i3c-scl-hz = <400000>; 312 #address-cells = <3>; 313 #size-cells = <0>; 314 status = "disabled"; 315 }; 316 317 i3c6: i3c@80680400 { 318 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 319 reg = <0x00 0x80680400 0x00 0x400>; 320 clocks = <&refclk &clk_xin>; 321 clock-names = "pclk", "sysclk"; 322 interrupt-parent = <&gic500>; 323 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 324 i2c-scl-hz = <100000>; 325 i3c-scl-hz = <400000>; 326 #address-cells = <3>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 i3c7: i3c@80680800 { 332 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 333 reg = <0x00 0x80680800 0x00 0x400>; 334 clocks = <&refclk &clk_xin>; 335 clock-names = "pclk", "sysclk"; 336 interrupt-parent = <&gic500>; 337 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 338 i2c-scl-hz = <100000>; 339 i3c-scl-hz = <400000>; 340 #address-cells = <3>; 341 #size-cells = <0>; 342 status = "disabled"; 343 }; 344 345 i3c8: i3c@80700400 { 346 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 347 reg = <0x00 0x80700400 0x00 0x400>; 348 clocks = <&refclk &clk_xin>; 349 clock-names = "pclk", "sysclk"; 350 interrupt-parent = <&gic500>; 351 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 352 i2c-scl-hz = <100000>; 353 i3c-scl-hz = <400000>; 354 #address-cells = <3>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 359 i3c9: i3c@80700800 { 360 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 361 reg = <0x00 0x80700800 0x00 0x400>; 362 clocks = <&refclk &clk_xin>; 363 clock-names = "pclk", "sysclk"; 364 interrupt-parent = <&gic500>; 365 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 366 i2c-scl-hz = <100000>; 367 i3c-scl-hz = <400000>; 368 #address-cells = <3>; 369 #size-cells = <0>; 370 status = "disabled"; 371 }; 372 373 i3c10: i3c@80780400 { 374 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 375 reg = <0x00 0x80780400 0x00 0x400>; 376 clocks = <&refclk &clk_xin>; 377 clock-names = "pclk", "sysclk"; 378 interrupt-parent = <&gic500>; 379 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 380 i2c-scl-hz = <100000>; 381 i3c-scl-hz = <400000>; 382 #address-cells = <3>; 383 #size-cells = <0>; 384 status = "disabled"; 385 }; 386 387 i3c11: i3c@80780800 { 388 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 389 reg = <0x00 0x80780800 0x00 0x400>; 390 clocks = <&refclk &clk_xin>; 391 clock-names = "pclk", "sysclk"; 392 interrupt-parent = <&gic500>; 393 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 394 i2c-scl-hz = <100000>; 395 i3c-scl-hz = <400000>; 396 #address-cells = <3>; 397 #size-cells = <0>; 398 status = "disabled"; 399 }; 400 401 i3c12: i3c@80800400 { 402 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 403 reg = <0x00 0x80800400 0x00 0x400>; 404 clocks = <&refclk &clk_xin>; 405 clock-names = "pclk", "sysclk"; 406 interrupt-parent = <&gic500>; 407 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 408 i2c-scl-hz = <100000>; 409 i3c-scl-hz = <400000>; 410 #address-cells = <3>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 i3c13: i3c@80800800 { 416 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 417 reg = <0x00 0x80800800 0x00 0x400>; 418 clocks = <&refclk &clk_xin>; 419 clock-names = "pclk", "sysclk"; 420 interrupt-parent = <&gic500>; 421 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 422 i2c-scl-hz = <100000>; 423 i3c-scl-hz = <400000>; 424 #address-cells = <3>; 425 #size-cells = <0>; 426 status = "disabled"; 427 }; 428 429 i3c14: i3c@80880400 { 430 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 431 reg = <0x00 0x80880400 0x00 0x400>; 432 clocks = <&refclk &clk_xin>; 433 clock-names = "pclk", "sysclk"; 434 interrupt-parent = <&gic500>; 435 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 436 i2c-scl-hz = <100000>; 437 i3c-scl-hz = <400000>; 438 #address-cells = <3>; 439 #size-cells = <0>; 440 status = "disabled"; 441 }; 442 443 i3c15: i3c@80880800 { 444 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 445 reg = <0x00 0x80880800 0x00 0x400>; 446 clocks = <&refclk &clk_xin>; 447 clock-names = "pclk", "sysclk"; 448 interrupt-parent = <&gic500>; 449 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 450 i2c-scl-hz = <100000>; 451 i3c-scl-hz = <400000>; 452 #address-cells = <3>; 453 #size-cells = <0>; 454 status = "disabled"; 455 }; 456 457 i3c16: i3c@80620400 { 458 compatible = "axiado,ax3000-i3c", "cdns,i3c-master"; 459 reg = <0x00 0x80620400 0x00 0x400>; 460 clocks = <&refclk &clk_xin>; 461 clock-names = "pclk", "sysclk"; 462 interrupt-parent = <&gic500>; 463 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 464 i2c-scl-hz = <100000>; 465 i3c-scl-hz = <400000>; 466 #address-cells = <3>; 467 #size-cells = <0>; 468 status = "disabled"; 469 }; 470 471 uart0: serial@80520000 { 472 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"; 473 reg = <0x00 0x80520000 0x00 0x100>; 474 interrupt-parent = <&gic500>; 475 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 476 clock-names = "uart_clk", "pclk"; 477 clocks = <&refclk &refclk>; 478 status = "disabled"; 479 }; 480 481 uart1: serial@805a0000 { 482 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"; 483 reg = <0x00 0x805A0000 0x00 0x100>; 484 interrupt-parent = <&gic500>; 485 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 486 clock-names = "uart_clk", "pclk"; 487 clocks = <&refclk &refclk>; 488 status = "disabled"; 489 }; 490 491 uart2: serial@80620000 { 492 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"; 493 reg = <0x00 0x80620000 0x00 0x100>; 494 interrupt-parent = <&gic500>; 495 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 496 clock-names = "uart_clk", "pclk"; 497 clocks = <&refclk &refclk>; 498 status = "disabled"; 499 }; 500 501 uart3: serial@80520800 { 502 compatible = "axiado,ax3000-uart", "cdns,uart-r1p12"; 503 reg = <0x00 0x80520800 0x00 0x100>; 504 interrupt-parent = <&gic500>; 505 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 506 clock-names = "uart_clk", "pclk"; 507 clocks = <&refclk &refclk>; 508 status = "disabled"; 509 }; 510 }; 511 512 timer { 513 compatible = "arm,armv8-timer"; 514 interrupt-parent = <&gic500>; 515 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 519 }; 520}; 521