xref: /qemu/target/arm/tcg/translate.h (revision df6fe2abf2e990f767ce755d426bc439c7bba336)
1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
3 
4 #include "cpu.h"
5 #include "tcg/tcg-op.h"
6 #include "tcg/tcg-op-gvec.h"
7 #include "exec/translator.h"
8 #include "exec/translation-block.h"
9 #include "exec/helper-gen.h"
10 #include "internals.h"
11 #include "cpu-features.h"
12 
13 /* internal defines */
14 
15 /*
16  * Save pc_save across a branch, so that we may restore the value from
17  * before the branch at the point the label is emitted.
18  */
19 typedef struct DisasLabel {
20     TCGLabel *label;
21     target_ulong pc_save;
22 } DisasLabel;
23 
24 typedef struct DisasContext {
25     DisasContextBase base;
26     const ARMISARegisters *isar;
27 
28     /* The address of the current instruction being translated. */
29     target_ulong pc_curr;
30     /*
31      * For CF_PCREL, the full value of cpu_pc is not known
32      * (although the page offset is known).  For convenience, the
33      * translation loop uses the full virtual address that triggered
34      * the translation, from base.pc_start through pc_curr.
35      * For efficiency, we do not update cpu_pc for every instruction.
36      * Instead, pc_save has the value of pc_curr at the time of the
37      * last update to cpu_pc, which allows us to compute the addend
38      * needed to bring cpu_pc current: pc_curr - pc_save.
39      * If cpu_pc now contains the destination of an indirect branch,
40      * pc_save contains -1 to indicate that relative updates are no
41      * longer possible.
42      */
43     target_ulong pc_save;
44     target_ulong page_start;
45     uint32_t insn;
46     /* Nonzero if this instruction has been conditionally skipped.  */
47     int condjmp;
48     /* The label that will be jumped to when the instruction is skipped.  */
49     DisasLabel condlabel;
50     /* Thumb-2 conditional execution bits.  */
51     int condexec_mask;
52     int condexec_cond;
53     /* M-profile ECI/ICI exception-continuable instruction state */
54     int eci;
55     /*
56      * trans_ functions for insns which are continuable should set this true
57      * after decode (ie after any UNDEF checks)
58      */
59     bool eci_handled;
60     int sctlr_b;
61     MemOp be_data;
62 #if !defined(CONFIG_USER_ONLY)
63     int user;
64 #endif
65     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
66     uint8_t tbii;      /* TBI1|TBI0 for insns */
67     uint8_t tbid;      /* TBI1|TBI0 for data */
68     uint8_t tcma;      /* TCMA1|TCMA0 for MTE */
69     bool ns;        /* Use non-secure CPREG bank on access */
70     int fp_excp_el; /* FP exception EL or 0 if enabled */
71     int sve_excp_el; /* SVE exception EL or 0 if enabled */
72     int sme_excp_el; /* SME exception EL or 0 if enabled */
73     int zt0_excp_el; /* ZT0 exception EL or 0 if enabled */
74     int vl;          /* current vector length in bytes */
75     int svl;         /* current streaming vector length in bytes */
76     int max_svl;     /* maximum implemented streaming vector length */
77     bool vfp_enabled; /* FP enabled via FPSCR.EN */
78     int vec_len;
79     int vec_stride;
80     bool v7m_handler_mode;
81     bool v8m_secure; /* true if v8M and we're in Secure mode */
82     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
83     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
84     bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
85     bool v7m_lspact; /* FPCCR.LSPACT set */
86     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
87      * so that top level loop can generate correct syndrome information.
88      */
89     uint32_t svc_imm;
90     int current_el;
91     GHashTable *cp_regs;
92     uint64_t features; /* CPU features bits */
93     bool aarch64;
94     bool thumb;
95     bool lse2;
96     /*
97      * Because unallocated encodings generate different exception syndrome
98      * information from traps due to FP being disabled, we can't do a single
99      * "is fp access disabled" check at a high level in the decode tree.
100      * To help in catching bugs where the access check was forgotten in some
101      * code path, we set this flag when the access check is done, and assert
102      * that it is set at the point where we actually touch the FP regs.
103      *   0: not checked,
104      *   1: checked, access ok
105      *  -1: checked, access denied
106      */
107     int8_t fp_access_checked;
108     int8_t sve_access_checked;
109     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
110      * single-step support).
111      */
112     bool ss_active;
113     bool pstate_ss;
114     /* True if the insn just emitted was a load-exclusive instruction
115      * (necessary for syndrome information for single step exceptions),
116      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
117      */
118     bool is_ldex;
119     /* True if AccType_UNPRIV should be used for LDTR et al */
120     bool unpriv;
121     /* True if v8.3-PAuth is active.  */
122     bool pauth_active;
123     /* True if v8.5-MTE access to tags is enabled; index with is_unpriv.  */
124     bool ata[2];
125     /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv.  */
126     bool mte_active[2];
127     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
128     bool bt;
129     /* True if any CP15 access is trapped by HSTR_EL2 */
130     bool hstr_active;
131     /* True if memory operations require alignment */
132     bool align_mem;
133     /* True if PSTATE.IL is set */
134     bool pstate_il;
135     /* True if PSTATE.SM is set. */
136     bool pstate_sm;
137     /* True if PSTATE.ZA is set. */
138     bool pstate_za;
139     /* True if non-streaming insns should raise an SME Streaming exception. */
140     bool sme_trap_nonstreaming;
141     /* True if the current instruction is non-streaming. */
142     bool is_nonstreaming;
143     /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
144     bool mve_no_pred;
145     /* True if fine-grained traps are active */
146     bool fgt_active;
147     /* True if fine-grained trap on SVC is enabled */
148     bool fgt_svc;
149     /* True if a trap on ERET is enabled (FGT or NV) */
150     bool trap_eret;
151     /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */
152     bool naa;
153     /* True if FEAT_NV HCR_EL2.NV is enabled */
154     bool nv;
155     /* True if NV enabled and HCR_EL2.NV1 is set */
156     bool nv1;
157     /* True if NV enabled and HCR_EL2.NV2 is set */
158     bool nv2;
159     /* True if NV2 enabled and NV2 RAM accesses use EL2&0 translation regime */
160     bool nv2_mem_e20;
161     /* True if NV2 enabled and NV2 RAM accesses are big-endian */
162     bool nv2_mem_be;
163     /* True if FPCR.AH is 1 (alternate floating point handling) */
164     bool fpcr_ah;
165     /* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handling) */
166     bool fpcr_nep;
167     /*
168      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
169      *  < 0, set by the current instruction.
170      */
171     int8_t btype;
172     /* A copy of cpu->dcz_blocksize. */
173     uint8_t dcz_blocksize;
174     /* A copy of cpu->gm_blocksize. */
175     uint8_t gm_blocksize;
176     /* True if the current insn_start has been updated. */
177     bool insn_start_updated;
178     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
179     int c15_cpar;
180     /* Offset from VNCR_EL2 when FEAT_NV2 redirects this reg to memory */
181     uint32_t nv2_redirect_offset;
182 } DisasContext;
183 
184 typedef struct DisasCompare {
185     TCGCond cond;
186     TCGv_i32 value;
187 } DisasCompare;
188 
189 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
190 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
191 extern TCGv_i64 cpu_exclusive_addr;
192 extern TCGv_i64 cpu_exclusive_val;
193 
194 /*
195  * Constant expanders for the decoders.
196  */
197 
198 static inline int negate(DisasContext *s, int x)
199 {
200     return -x;
201 }
202 
203 static inline int plus_1(DisasContext *s, int x)
204 {
205     return x + 1;
206 }
207 
208 static inline int plus_2(DisasContext *s, int x)
209 {
210     return x + 2;
211 }
212 
213 static inline int plus_8(DisasContext *s, int x)
214 {
215     return x + 8;
216 }
217 
218 static inline int plus_12(DisasContext *s, int x)
219 {
220     return x + 12;
221 }
222 
223 static inline int times_2(DisasContext *s, int x)
224 {
225     return x * 2;
226 }
227 
228 static inline int times_4(DisasContext *s, int x)
229 {
230     return x * 4;
231 }
232 
233 static inline int times_8(DisasContext *s, int x)
234 {
235     return x * 8;
236 }
237 
238 static inline int times_2_plus_1(DisasContext *s, int x)
239 {
240     return x * 2 + 1;
241 }
242 
243 static inline int rsub_64(DisasContext *s, int x)
244 {
245     return 64 - x;
246 }
247 
248 static inline int rsub_32(DisasContext *s, int x)
249 {
250     return 32 - x;
251 }
252 
253 static inline int rsub_16(DisasContext *s, int x)
254 {
255     return 16 - x;
256 }
257 
258 static inline int rsub_8(DisasContext *s, int x)
259 {
260     return 8 - x;
261 }
262 
263 static inline int shl_12(DisasContext *s, int x)
264 {
265     return x << 12;
266 }
267 
268 static inline int xor_2(DisasContext *s, int x)
269 {
270     return x ^ 2;
271 }
272 
273 static inline int neon_3same_fp_size(DisasContext *s, int x)
274 {
275     /* Convert 0==fp32, 1==fp16 into a MO_* value */
276     return MO_32 - x;
277 }
278 
279 static inline int arm_dc_feature(DisasContext *dc, int feature)
280 {
281     return (dc->features & (1ULL << feature)) != 0;
282 }
283 
284 static inline int get_mem_index(DisasContext *s)
285 {
286     return arm_to_core_mmu_idx(s->mmu_idx);
287 }
288 
289 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
290 {
291     /* We don't need to save all of the syndrome so we mask and shift
292      * out unneeded bits to help the sleb128 encoder do a better job.
293      */
294     syn &= ARM_INSN_START_WORD2_MASK;
295     syn >>= ARM_INSN_START_WORD2_SHIFT;
296 
297     /* Check for multiple updates.  */
298     assert(!s->insn_start_updated);
299     s->insn_start_updated = true;
300     tcg_set_insn_start_param(s->base.insn_start, 2, syn);
301 }
302 
303 static inline int curr_insn_len(DisasContext *s)
304 {
305     return s->base.pc_next - s->pc_curr;
306 }
307 
308 /* is_jmp field values */
309 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
310 /* CPU state was modified dynamically; exit to main loop for interrupts. */
311 #define DISAS_UPDATE_EXIT  DISAS_TARGET_1
312 /* These instructions trap after executing, so the A32/T32 decoder must
313  * defer them until after the conditional execution state has been updated.
314  * WFI also needs special handling when single-stepping.
315  */
316 #define DISAS_WFI       DISAS_TARGET_2
317 #define DISAS_SWI       DISAS_TARGET_3
318 /* WFE */
319 #define DISAS_WFE       DISAS_TARGET_4
320 #define DISAS_HVC       DISAS_TARGET_5
321 #define DISAS_SMC       DISAS_TARGET_6
322 #define DISAS_YIELD     DISAS_TARGET_7
323 /* M profile branch which might be an exception return (and so needs
324  * custom end-of-TB code)
325  */
326 #define DISAS_BX_EXCRET DISAS_TARGET_8
327 /*
328  * For instructions which want an immediate exit to the main loop, as opposed
329  * to attempting to use lookup_and_goto_ptr.  Unlike DISAS_UPDATE_EXIT, this
330  * doesn't write the PC on exiting the translation loop so you need to ensure
331  * something (gen_a64_update_pc or runtime helper) has done so before we reach
332  * return from cpu_tb_exec.
333  */
334 #define DISAS_EXIT      DISAS_TARGET_9
335 /* CPU state was modified dynamically; no need to exit, but do not chain. */
336 #define DISAS_UPDATE_NOCHAIN  DISAS_TARGET_10
337 
338 #ifdef TARGET_AARCH64
339 void a64_translate_init(void);
340 void gen_a64_update_pc(DisasContext *s, target_long diff);
341 extern const TranslatorOps aarch64_translator_ops;
342 #else
343 static inline void a64_translate_init(void)
344 {
345 }
346 
347 static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
348 {
349 }
350 #endif
351 
352 void arm_test_cc(DisasCompare *cmp, int cc);
353 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
354 void arm_gen_test_cc(int cc, TCGLabel *label);
355 MemOp pow2_align(unsigned i);
356 void unallocated_encoding(DisasContext *s);
357 void gen_exception_internal(int excp);
358 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
359                            uint32_t syn, uint32_t target_el);
360 void gen_exception_insn(DisasContext *s, target_long pc_diff,
361                         int excp, uint32_t syn);
362 
363 /* Return state of Alternate Half-precision flag, caller frees result */
364 static inline TCGv_i32 get_ahp_flag(void)
365 {
366     TCGv_i32 ret = tcg_temp_new_i32();
367 
368     tcg_gen_ld_i32(ret, tcg_env, offsetoflow32(CPUARMState, vfp.fpcr));
369     tcg_gen_extract_i32(ret, ret, 26, 1);
370 
371     return ret;
372 }
373 
374 /* Set bits within PSTATE.  */
375 static inline void set_pstate_bits(uint32_t bits)
376 {
377     TCGv_i32 p = tcg_temp_new_i32();
378 
379     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
380 
381     tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
382     tcg_gen_ori_i32(p, p, bits);
383     tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
384 }
385 
386 /* Clear bits within PSTATE.  */
387 static inline void clear_pstate_bits(uint32_t bits)
388 {
389     TCGv_i32 p = tcg_temp_new_i32();
390 
391     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
392 
393     tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
394     tcg_gen_andi_i32(p, p, ~bits);
395     tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
396 }
397 
398 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
399 static inline void gen_ss_advance(DisasContext *s)
400 {
401     if (s->ss_active) {
402         s->pstate_ss = 0;
403         clear_pstate_bits(PSTATE_SS);
404     }
405 }
406 
407 /* Generate an architectural singlestep exception */
408 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
409 {
410     /* Fill in the same_el field of the syndrome in the helper. */
411     uint32_t syn = syn_swstep(false, isv, ex);
412     gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn));
413 }
414 
415 /*
416  * Given a VFP floating point constant encoded into an 8 bit immediate in an
417  * instruction, expand it to the actual constant value of the specified
418  * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
419  */
420 uint64_t vfp_expand_imm(int size, uint8_t imm8);
421 
422 static inline void gen_vfp_absh(TCGv_i32 d, TCGv_i32 s)
423 {
424     tcg_gen_andi_i32(d, s, INT16_MAX);
425 }
426 
427 static inline void gen_vfp_abss(TCGv_i32 d, TCGv_i32 s)
428 {
429     tcg_gen_andi_i32(d, s, INT32_MAX);
430 }
431 
432 static inline void gen_vfp_absd(TCGv_i64 d, TCGv_i64 s)
433 {
434     tcg_gen_andi_i64(d, s, INT64_MAX);
435 }
436 
437 static inline void gen_vfp_negh(TCGv_i32 d, TCGv_i32 s)
438 {
439     tcg_gen_xori_i32(d, s, 1u << 15);
440 }
441 
442 static inline void gen_vfp_negs(TCGv_i32 d, TCGv_i32 s)
443 {
444     tcg_gen_xori_i32(d, s, 1u << 31);
445 }
446 
447 static inline void gen_vfp_negd(TCGv_i64 d, TCGv_i64 s)
448 {
449     tcg_gen_xori_i64(d, s, 1ull << 63);
450 }
451 
452 /* Vector operations shared between ARM and AArch64.  */
453 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
454                    uint32_t opr_sz, uint32_t max_sz);
455 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
456                    uint32_t opr_sz, uint32_t max_sz);
457 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
458                    uint32_t opr_sz, uint32_t max_sz);
459 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
460                    uint32_t opr_sz, uint32_t max_sz);
461 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
462                    uint32_t opr_sz, uint32_t max_sz);
463 
464 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
465                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
466 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
467                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
468 
469 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
470                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
471 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
472                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
473 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
474                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
475 void gen_gvec_srshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
476                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
477 void gen_gvec_urshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
478                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
479 void gen_neon_sqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
480                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
481 void gen_neon_uqshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
482                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
483 void gen_neon_sqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
484                      uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
485 void gen_neon_uqrshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
486                      uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
487 
488 void gen_neon_sqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
489                      int64_t c, uint32_t opr_sz, uint32_t max_sz);
490 void gen_neon_uqshli(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
491                      int64_t c, uint32_t opr_sz, uint32_t max_sz);
492 void gen_neon_sqshlui(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
493                       int64_t c, uint32_t opr_sz, uint32_t max_sz);
494 
495 void gen_gvec_shadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
496                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
497 void gen_gvec_uhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
498                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
499 void gen_gvec_shsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
500                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
501 void gen_gvec_uhsub(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
502                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
503 void gen_gvec_srhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
504                      uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
505 void gen_gvec_urhadd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
506                      uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
507 
508 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
509 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
510 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
511 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
512 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
513 
514 void gen_uqadd_bhs(TCGv_i64 res, TCGv_i64 qc,
515                    TCGv_i64 a, TCGv_i64 b, MemOp esz);
516 void gen_uqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b);
517 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
518                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
519 
520 void gen_sqadd_bhs(TCGv_i64 res, TCGv_i64 qc,
521                    TCGv_i64 a, TCGv_i64 b, MemOp esz);
522 void gen_sqadd_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b);
523 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
524                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
525 
526 void gen_uqsub_bhs(TCGv_i64 res, TCGv_i64 qc,
527                    TCGv_i64 a, TCGv_i64 b, MemOp esz);
528 void gen_uqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b);
529 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
530                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
531 
532 void gen_sqsub_bhs(TCGv_i64 res, TCGv_i64 qc,
533                    TCGv_i64 a, TCGv_i64 b, MemOp esz);
534 void gen_sqsub_d(TCGv_i64 d, TCGv_i64 q, TCGv_i64 a, TCGv_i64 b);
535 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
536                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
537 
538 void gen_gvec_sshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
539                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
540 void gen_gvec_ushr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
541                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
542 
543 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
544                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
545 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
546                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
547 
548 void gen_srshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh);
549 void gen_srshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh);
550 void gen_urshr32_i32(TCGv_i32 d, TCGv_i32 a, int32_t sh);
551 void gen_urshr64_i64(TCGv_i64 d, TCGv_i64 a, int64_t sh);
552 
553 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
554                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
555 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
556                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
557 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
558                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
559 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
560                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
561 
562 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
563                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
564 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
565                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
566 
567 void gen_gvec_sqdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
568                          uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
569 void gen_gvec_sqrdmulh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
570                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
571 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
572                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
573 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
574                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
575 
576 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
577                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
578 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
579                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
580 
581 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
582                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
583 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
584                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
585 
586 void gen_gvec_addp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
587                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
588 void gen_gvec_smaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
589                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
590 void gen_gvec_sminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
591                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
592 void gen_gvec_umaxp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
593                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
594 void gen_gvec_uminp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
595                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
596 
597 void gen_gvec_cls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
598                   uint32_t opr_sz, uint32_t max_sz);
599 void gen_gvec_clz(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
600                   uint32_t opr_sz, uint32_t max_sz);
601 void gen_gvec_cnt(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
602                   uint32_t opr_sz, uint32_t max_sz);
603 void gen_gvec_rbit(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
604                    uint32_t opr_sz, uint32_t max_sz);
605 void gen_gvec_rev16(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
606                     uint32_t opr_sz, uint32_t max_sz);
607 void gen_gvec_rev32(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
608                     uint32_t opr_sz, uint32_t max_sz);
609 void gen_gvec_rev64(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
610                     uint32_t opr_sz, uint32_t max_sz);
611 
612 void gen_gvec_saddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
613                      uint32_t opr_sz, uint32_t max_sz);
614 void gen_gvec_sadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
615                      uint32_t opr_sz, uint32_t max_sz);
616 void gen_gvec_uaddlp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
617                      uint32_t opr_sz, uint32_t max_sz);
618 void gen_gvec_uadalp(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
619                      uint32_t opr_sz, uint32_t max_sz);
620 
621 /* These exclusively manipulate the sign bit. */
622 void gen_gvec_fabs(unsigned vece, uint32_t dofs, uint32_t aofs,
623                    uint32_t oprsz, uint32_t maxsz);
624 void gen_gvec_fneg(unsigned vece, uint32_t dofs, uint32_t aofs,
625                    uint32_t oprsz, uint32_t maxsz);
626 
627 void gen_gvec_urecpe(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
628                      uint32_t opr_sz, uint32_t max_sz);
629 void gen_gvec_ursqrte(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
630                       uint32_t opr_sz, uint32_t max_sz);
631 
632 /*
633  * Forward to the isar_feature_* tests given a DisasContext pointer.
634  */
635 #define dc_isar_feature(name, ctx) \
636     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
637 
638 /* Note that the gvec expanders operate on offsets + sizes.  */
639 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
640 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
641                          uint32_t, uint32_t);
642 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
643                         uint32_t, uint32_t, uint32_t);
644 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
645                         uint32_t, uint32_t, uint32_t);
646 typedef void GVecGen3FnVar(unsigned, TCGv_ptr, uint32_t, TCGv_ptr, uint32_t,
647                            TCGv_ptr, uint32_t, uint32_t, uint32_t);
648 
649 /* Function prototype for gen_ functions for calling Neon helpers */
650 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
651 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
652 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
653 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
654 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
655                                  TCGv_i32, TCGv_i32);
656 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
657 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
658 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
659 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
660 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
661 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
662 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
663 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
664 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
665 typedef void NeonGenOne64OpEnvFn(TCGv_i64, TCGv_env, TCGv_i64);
666 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
667 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
668 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
669 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
670 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
671 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
672 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
673 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
674 
675 /**
676  * arm_tbflags_from_tb:
677  * @tb: the TranslationBlock
678  *
679  * Extract the flag values from @tb.
680  */
681 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
682 {
683     return (CPUARMTBFlags){ tb->flags, tb->cs_base };
684 }
685 
686 /**
687  * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
688  *
689  * We have multiple softfloat float_status fields in the Arm CPU state struct
690  * (see the comment in cpu.h for details). Return a TCGv_ptr which has
691  * been set up to point to the requested field in the CPU state struct.
692  */
693 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
694 {
695     TCGv_ptr statusptr = tcg_temp_new_ptr();
696     int offset = offsetof(CPUARMState, vfp.fp_status[flavour]);
697 
698     tcg_gen_addi_ptr(statusptr, tcg_env, offset);
699     return statusptr;
700 }
701 
702 /**
703  * finalize_memop_atom:
704  * @s: DisasContext
705  * @opc: size+sign+align of the memory operation
706  * @atom: atomicity of the memory operation
707  *
708  * Build the complete MemOp for a memory operation, including alignment,
709  * endianness, and atomicity.
710  *
711  * If (op & MO_AMASK) then the operation already contains the required
712  * alignment, e.g. for AccType_ATOMIC.  Otherwise, this an optionally
713  * unaligned operation, e.g. for AccType_NORMAL.
714  *
715  * In the latter case, there are configuration bits that require alignment,
716  * and this is applied here.  Note that there is no way to indicate that
717  * no alignment should ever be enforced; this must be handled manually.
718  */
719 static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom)
720 {
721     if (s->align_mem && !(opc & MO_AMASK)) {
722         opc |= MO_ALIGN;
723     }
724     return opc | atom | s->be_data;
725 }
726 
727 /**
728  * finalize_memop:
729  * @s: DisasContext
730  * @opc: size+sign+align of the memory operation
731  *
732  * Like finalize_memop_atom, but with default atomicity.
733  */
734 static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
735 {
736     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN;
737     return finalize_memop_atom(s, opc, atom);
738 }
739 
740 /**
741  * finalize_memop_pair:
742  * @s: DisasContext
743  * @opc: size+sign+align of the memory operation
744  *
745  * Like finalize_memop_atom, but with atomicity for a pair.
746  * C.f. Pseudocode for Mem[], operand ispair.
747  */
748 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc)
749 {
750     MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR;
751     return finalize_memop_atom(s, opc, atom);
752 }
753 
754 /**
755  * finalize_memop_asimd:
756  * @s: DisasContext
757  * @opc: size+sign+align of the memory operation
758  *
759  * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD.
760  */
761 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc)
762 {
763     /*
764      * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16,
765      * if IsAligned(8), the first case provides separate atomicity for
766      * the pair of 64-bit accesses.  If !IsAligned(8), the middle cases
767      * do not apply, and we're left with the final case of no atomicity.
768      * Thus MO_ATOM_IFALIGN_PAIR.
769      *
770      * For other sizes, normal LSE2 rules apply.
771      */
772     if ((opc & MO_SIZE) == MO_128) {
773         return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR);
774     }
775     return finalize_memop(s, opc);
776 }
777 
778 /**
779  * asimd_imm_const: Expand an encoded SIMD constant value
780  *
781  * Expand a SIMD constant value. This is essentially the pseudocode
782  * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
783  * VMVN and VBIC (when cmode < 14 && op == 1).
784  *
785  * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
786  * callers must catch this; we return the 64-bit constant value defined
787  * for AArch64.
788  *
789  * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
790  * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
791  * we produce an immediate constant value of 0 in these cases.
792  */
793 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
794 
795 /*
796  * gen_disas_label:
797  * Create a label and cache a copy of pc_save.
798  */
799 static inline DisasLabel gen_disas_label(DisasContext *s)
800 {
801     return (DisasLabel){
802         .label = gen_new_label(),
803         .pc_save = s->pc_save,
804     };
805 }
806 
807 /*
808  * set_disas_label:
809  * Emit a label and restore the cached copy of pc_save.
810  */
811 static inline void set_disas_label(DisasContext *s, DisasLabel l)
812 {
813     gen_set_label(l.label);
814     s->pc_save = l.pc_save;
815 }
816 
817 static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
818 {
819     TCGv_ptr ret = tcg_temp_new_ptr();
820     gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key));
821     return ret;
822 }
823 
824 /*
825  * Set and reset rounding mode around another operation.
826  */
827 static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
828 {
829     TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
830     TCGv_i32 old = tcg_temp_new_i32();
831 
832     gen_helper_set_rmode(old, new, fpst);
833     return old;
834 }
835 
836 static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
837 {
838     gen_helper_set_rmode(old, old, fpst);
839 }
840 
841 /*
842  * Helpers for implementing sets of trans_* functions.
843  * Defer the implementation of NAME to FUNC, with optional extra arguments.
844  */
845 #define TRANS(NAME, FUNC, ...) \
846     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
847     { return FUNC(s, __VA_ARGS__); }
848 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
849     static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
850     { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
851 
852 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...)            \
853     static bool trans_##NAME(DisasContext *s, arg_##NAME *a)      \
854     {                                                             \
855         s->is_nonstreaming = true;                                \
856         return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__);  \
857     }
858 
859 #endif /* TARGET_ARM_TRANSLATE_H */
860