1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3036-cru.h> 8#include <dt-bindings/soc/rockchip,boot-mode.h> 9#include <dt-bindings/power/rk3036-power.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 compatible = "rockchip,rk3036"; 16 17 interrupt-parent = <&gic>; 18 19 aliases { 20 gpio0 = &gpio0; 21 gpio1 = &gpio1; 22 gpio2 = &gpio2; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 spi = &spi; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 enable-method = "rockchip,rk3036-smp"; 36 37 cpu0: cpu@f00 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a7"; 40 reg = <0xf00>; 41 resets = <&cru SRST_CORE0>; 42 operating-points = < 43 /* KHz uV */ 44 816000 1000000 45 >; 46 clock-latency = <40000>; 47 clocks = <&cru ARMCLK>; 48 }; 49 50 cpu1: cpu@f01 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a7"; 53 reg = <0xf01>; 54 resets = <&cru SRST_CORE1>; 55 }; 56 }; 57 58 arm-pmu { 59 compatible = "arm,cortex-a7-pmu"; 60 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-affinity = <&cpu0>, <&cpu1>; 63 }; 64 65 display-subsystem { 66 compatible = "rockchip,display-subsystem"; 67 ports = <&vop_out>; 68 }; 69 70 timer { 71 compatible = "arm,armv7-timer"; 72 arm,cpu-registers-not-fw-configured; 73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 74 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 75 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 76 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 77 clock-frequency = <24000000>; 78 }; 79 80 xin24m: oscillator { 81 compatible = "fixed-clock"; 82 clock-frequency = <24000000>; 83 clock-output-names = "xin24m"; 84 #clock-cells = <0>; 85 }; 86 87 bus_intmem: sram@10080000 { 88 compatible = "mmio-sram"; 89 reg = <0x10080000 0x2000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0 0x10080000 0x2000>; 93 94 smp-sram@0 { 95 compatible = "rockchip,rk3066-smp-sram"; 96 reg = <0x00 0x10>; 97 }; 98 }; 99 100 gpu: gpu@10090000 { 101 compatible = "rockchip,rk3036-mali", "arm,mali-400"; 102 reg = <0x10090000 0x10000>; 103 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 107 interrupt-names = "gp", 108 "gpmmu", 109 "pp0", 110 "ppmmu0"; 111 assigned-clocks = <&cru SCLK_GPU>; 112 assigned-clock-rates = <100000000>; 113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>; 114 clock-names = "bus", "core"; 115 power-domains = <&power RK3036_PD_GPU>; 116 resets = <&cru SRST_GPU>; 117 status = "disabled"; 118 }; 119 120 vpu: video-codec@10108000 { 121 compatible = "rockchip,rk3036-vpu"; 122 reg = <0x10108000 0x800>; 123 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 124 interrupt-names = "vdpu"; 125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 126 clock-names = "aclk", "hclk"; 127 iommus = <&vpu_mmu>; 128 power-domains = <&power RK3036_PD_VPU>; 129 }; 130 131 vpu_mmu: iommu@10108800 { 132 compatible = "rockchip,iommu"; 133 reg = <0x10108800 0x100>; 134 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 136 clock-names = "aclk", "iface"; 137 power-domains = <&power RK3036_PD_VPU>; 138 #iommu-cells = <0>; 139 }; 140 141 vop: vop@10118000 { 142 compatible = "rockchip,rk3036-vop"; 143 reg = <0x10118000 0x19c>; 144 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; 146 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 147 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; 148 reset-names = "axi", "ahb", "dclk"; 149 iommus = <&vop_mmu>; 150 power-domains = <&power RK3036_PD_VIO>; 151 status = "disabled"; 152 153 vop_out: port { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 vop_out_hdmi: endpoint@0 { 157 reg = <0>; 158 remote-endpoint = <&hdmi_in_vop>; 159 }; 160 }; 161 }; 162 163 vop_mmu: iommu@10118300 { 164 compatible = "rockchip,iommu"; 165 reg = <0x10118300 0x100>; 166 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>; 168 clock-names = "aclk", "iface"; 169 power-domains = <&power RK3036_PD_VIO>; 170 #iommu-cells = <0>; 171 status = "disabled"; 172 }; 173 174 qos_gpu: qos@1012d000 { 175 compatible = "rockchip,rk3036-qos", "syscon"; 176 reg = <0x1012d000 0x20>; 177 }; 178 179 qos_vpu: qos@1012e000 { 180 compatible = "rockchip,rk3036-qos", "syscon"; 181 reg = <0x1012e000 0x20>; 182 }; 183 184 qos_vio: qos@1012f000 { 185 compatible = "rockchip,rk3036-qos", "syscon"; 186 reg = <0x1012f000 0x20>; 187 }; 188 189 gic: interrupt-controller@10139000 { 190 compatible = "arm,gic-400"; 191 interrupt-controller; 192 #interrupt-cells = <3>; 193 #address-cells = <0>; 194 195 reg = <0x10139000 0x1000>, 196 <0x1013a000 0x2000>, 197 <0x1013c000 0x2000>, 198 <0x1013e000 0x2000>; 199 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 200 }; 201 202 usb_otg: usb@10180000 { 203 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 204 "snps,dwc2"; 205 reg = <0x10180000 0x40000>; 206 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&cru HCLK_OTG0>; 208 clock-names = "otg"; 209 dr_mode = "otg"; 210 g-np-tx-fifo-size = <16>; 211 g-rx-fifo-size = <275>; 212 g-tx-fifo-size = <256 128 128 64 64 32>; 213 phys = <&usb2phy_otg>; 214 phy-names = "usb2-phy"; 215 status = "disabled"; 216 }; 217 218 usb_host: usb@101c0000 { 219 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", 220 "snps,dwc2"; 221 reg = <0x101c0000 0x40000>; 222 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&cru HCLK_OTG1>; 224 clock-names = "otg"; 225 dr_mode = "host"; 226 phys = <&usb2phy_host>; 227 phy-names = "usb2-phy"; 228 status = "disabled"; 229 }; 230 231 emac: ethernet@10200000 { 232 compatible = "rockchip,rk3036-emac"; 233 reg = <0x10200000 0x4000>; 234 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 235 rockchip,grf = <&grf>; 236 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>; 237 clock-names = "hclk", "macref", "macclk"; 238 /* 239 * Fix the emac parent clock is DPLL instead of APLL. 240 * since that will cause some unstable things if the cpufreq 241 * is working. (e.g: the accurate 50MHz what mac_ref need) 242 */ 243 assigned-clocks = <&cru SCLK_MACPLL>; 244 assigned-clock-parents = <&cru PLL_DPLL>; 245 max-speed = <100>; 246 phy-mode = "rmii"; 247 status = "disabled"; 248 }; 249 250 sdmmc: mmc@10214000 { 251 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 252 reg = <0x10214000 0x4000>; 253 clock-frequency = <37500000>; 254 max-frequency = <37500000>; 255 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 256 clock-names = "biu", "ciu"; 257 fifo-depth = <0x100>; 258 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 259 resets = <&cru SRST_MMC0>; 260 reset-names = "reset"; 261 status = "disabled"; 262 }; 263 264 sdio: mmc@10218000 { 265 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 266 reg = <0x10218000 0x4000>; 267 max-frequency = <37500000>; 268 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 269 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 270 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 271 fifo-depth = <0x100>; 272 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 273 resets = <&cru SRST_SDIO>; 274 reset-names = "reset"; 275 status = "disabled"; 276 }; 277 278 emmc: mmc@1021c000 { 279 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; 280 reg = <0x1021c000 0x4000>; 281 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 282 bus-width = <8>; 283 cap-mmc-highspeed; 284 clock-frequency = <37500000>; 285 max-frequency = <37500000>; 286 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 287 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 288 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 289 disable-wp; 290 dmas = <&pdma 12>; 291 dma-names = "rx-tx"; 292 fifo-depth = <0x100>; 293 mmc-ddr-1_8v; 294 non-removable; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 297 resets = <&cru SRST_EMMC>; 298 reset-names = "reset"; 299 status = "disabled"; 300 }; 301 302 i2s: i2s@10220000 { 303 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s"; 304 reg = <0x10220000 0x4000>; 305 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 306 clock-names = "i2s_clk", "i2s_hclk"; 307 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; 308 dmas = <&pdma 0>, <&pdma 1>; 309 dma-names = "tx", "rx"; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&i2s_bus>; 312 #sound-dai-cells = <0>; 313 status = "disabled"; 314 }; 315 316 nfc: nand-controller@10500000 { 317 compatible = "rockchip,rk3036-nfc", 318 "rockchip,rk2928-nfc"; 319 reg = <0x10500000 0x4000>; 320 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 322 clock-names = "ahb", "nfc"; 323 assigned-clocks = <&cru SCLK_NANDC>; 324 assigned-clock-rates = <150000000>; 325 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 326 &flash_rdn &flash_rdy &flash_wrn>; 327 pinctrl-names = "default"; 328 status = "disabled"; 329 }; 330 331 cru: clock-controller@20000000 { 332 compatible = "rockchip,rk3036-cru"; 333 reg = <0x20000000 0x1000>; 334 clocks = <&xin24m>; 335 clock-names = "xin24m"; 336 rockchip,grf = <&grf>; 337 #clock-cells = <1>; 338 #reset-cells = <1>; 339 assigned-clocks = <&cru PLL_GPLL>; 340 assigned-clock-rates = <594000000>; 341 }; 342 343 grf: syscon@20008000 { 344 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; 345 reg = <0x20008000 0x1000>; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 349 usb2phy: usb2phy@17c { 350 compatible = "rockchip,rk3036-usb2phy"; 351 reg = <0x017c 0x20>; 352 clocks = <&cru SCLK_OTGPHY0>; 353 clock-names = "phyclk"; 354 clock-output-names = "usb480m_phy"; 355 assigned-clocks = <&cru SCLK_USB480M>; 356 assigned-clock-parents = <&usb2phy>; 357 #clock-cells = <0>; 358 status = "disabled"; 359 360 usb2phy_host: host-port { 361 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-names = "linestate"; 363 #phy-cells = <0>; 364 status = "disabled"; 365 }; 366 367 usb2phy_otg: otg-port { 368 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "otg-bvalid", "otg-id", 372 "linestate"; 373 #phy-cells = <0>; 374 status = "disabled"; 375 }; 376 }; 377 378 power: power-controller { 379 compatible = "rockchip,rk3036-power-controller"; 380 #power-domain-cells = <1>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 384 power-domain@RK3036_PD_VIO { 385 reg = <RK3036_PD_VIO>; 386 clocks = <&cru ACLK_LCDC>, 387 <&cru HCLK_LCDC>, 388 <&cru SCLK_LCDC>; 389 pm_qos = <&qos_vio>; 390 #power-domain-cells = <0>; 391 }; 392 393 power-domain@RK3036_PD_VPU { 394 reg = <RK3036_PD_VPU>; 395 clocks = <&cru ACLK_VCODEC>, 396 <&cru HCLK_VCODEC>; 397 pm_qos = <&qos_vpu>; 398 #power-domain-cells = <0>; 399 }; 400 401 power-domain@RK3036_PD_GPU { 402 reg = <RK3036_PD_GPU>; 403 clocks = <&cru SCLK_GPU>; 404 pm_qos = <&qos_gpu>; 405 #power-domain-cells = <0>; 406 }; 407 }; 408 409 reboot-mode { 410 compatible = "syscon-reboot-mode"; 411 offset = <0x1d8>; 412 mode-normal = <BOOT_NORMAL>; 413 mode-recovery = <BOOT_RECOVERY>; 414 mode-bootloader = <BOOT_FASTBOOT>; 415 mode-loader = <BOOT_BL_DOWNLOAD>; 416 }; 417 }; 418 419 acodec: audio-codec@20030000 { 420 compatible = "rockchip,rk3036-codec"; 421 reg = <0x20030000 0x4000>; 422 clock-names = "acodec_pclk"; 423 clocks = <&cru PCLK_ACODEC>; 424 rockchip,grf = <&grf>; 425 #sound-dai-cells = <0>; 426 status = "disabled"; 427 }; 428 429 hdmi: hdmi@20034000 { 430 compatible = "rockchip,rk3036-inno-hdmi"; 431 reg = <0x20034000 0x4000>; 432 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cru PCLK_HDMI>, <&cru SCLK_LCDC>; 434 clock-names = "pclk", "ref"; 435 rockchip,grf = <&grf>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&hdmi_ctl>; 438 #sound-dai-cells = <0>; 439 status = "disabled"; 440 441 ports { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 445 hdmi_in: port@0 { 446 reg = <0>; 447 448 hdmi_in_vop: endpoint { 449 remote-endpoint = <&vop_out_hdmi>; 450 }; 451 }; 452 453 hdmi_out: port@1 { 454 reg = <1>; 455 }; 456 }; 457 }; 458 459 timer: timer@20044000 { 460 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; 461 reg = <0x20044000 0x20>; 462 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&cru PCLK_TIMER>, <&xin24m>; 464 clock-names = "pclk", "timer"; 465 }; 466 467 pwm0: pwm@20050000 { 468 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 469 reg = <0x20050000 0x10>; 470 #pwm-cells = <3>; 471 clocks = <&cru PCLK_PWM>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&pwm0_pin>; 474 status = "disabled"; 475 }; 476 477 pwm1: pwm@20050010 { 478 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 479 reg = <0x20050010 0x10>; 480 #pwm-cells = <3>; 481 clocks = <&cru PCLK_PWM>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&pwm1_pin>; 484 status = "disabled"; 485 }; 486 487 pwm2: pwm@20050020 { 488 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 489 reg = <0x20050020 0x10>; 490 #pwm-cells = <3>; 491 clocks = <&cru PCLK_PWM>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&pwm2_pin>; 494 status = "disabled"; 495 }; 496 497 pwm3: pwm@20050030 { 498 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm"; 499 reg = <0x20050030 0x10>; 500 #pwm-cells = <2>; 501 clocks = <&cru PCLK_PWM>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pwm3_pin>; 504 status = "disabled"; 505 }; 506 507 i2c1: i2c@20056000 { 508 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 509 reg = <0x20056000 0x1000>; 510 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 clock-names = "i2c"; 514 clocks = <&cru PCLK_I2C1>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&i2c1_xfer>; 517 status = "disabled"; 518 }; 519 520 i2c2: i2c@2005a000 { 521 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 522 reg = <0x2005a000 0x1000>; 523 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clock-names = "i2c"; 527 clocks = <&cru PCLK_I2C2>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&i2c2_xfer>; 530 status = "disabled"; 531 }; 532 533 uart0: serial@20060000 { 534 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 535 reg = <0x20060000 0x100>; 536 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 537 reg-shift = <2>; 538 reg-io-width = <4>; 539 clock-frequency = <24000000>; 540 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 541 clock-names = "baudclk", "apb_pclk"; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 544 status = "disabled"; 545 }; 546 547 uart1: serial@20064000 { 548 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 549 reg = <0x20064000 0x100>; 550 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 551 reg-shift = <2>; 552 reg-io-width = <4>; 553 clock-frequency = <24000000>; 554 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 555 clock-names = "baudclk", "apb_pclk"; 556 pinctrl-names = "default"; 557 pinctrl-0 = <&uart1_xfer>; 558 status = "disabled"; 559 }; 560 561 uart2: serial@20068000 { 562 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart"; 563 reg = <0x20068000 0x100>; 564 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 565 reg-shift = <2>; 566 reg-io-width = <4>; 567 clock-frequency = <24000000>; 568 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 569 clock-names = "baudclk", "apb_pclk"; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&uart2_xfer>; 572 status = "disabled"; 573 }; 574 575 i2c0: i2c@20072000 { 576 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; 577 reg = <0x20072000 0x1000>; 578 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 clock-names = "i2c"; 582 clocks = <&cru PCLK_I2C0>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&i2c0_xfer>; 585 status = "disabled"; 586 }; 587 588 spi: spi@20074000 { 589 compatible = "rockchip,rk3036-spi"; 590 reg = <0x20074000 0x1000>; 591 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 593 clock-names = "spiclk", "apb_pclk"; 594 dmas = <&pdma 8>, <&pdma 9>; 595 dma-names = "tx", "rx"; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 pdma: dma-controller@20078000 { 604 compatible = "arm,pl330", "arm,primecell"; 605 reg = <0x20078000 0x4000>; 606 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 608 #dma-cells = <1>; 609 arm,pl330-broken-no-flushp; 610 arm,pl330-periph-burst; 611 clocks = <&cru ACLK_DMAC2>; 612 clock-names = "apb_pclk"; 613 }; 614 615 pinctrl: pinctrl { 616 compatible = "rockchip,rk3036-pinctrl"; 617 rockchip,grf = <&grf>; 618 #address-cells = <1>; 619 #size-cells = <1>; 620 ranges; 621 622 gpio0: gpio@2007c000 { 623 compatible = "rockchip,gpio-bank"; 624 reg = <0x2007c000 0x100>; 625 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 626 clocks = <&cru PCLK_GPIO0>; 627 628 gpio-controller; 629 #gpio-cells = <2>; 630 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 635 gpio1: gpio@20080000 { 636 compatible = "rockchip,gpio-bank"; 637 reg = <0x20080000 0x100>; 638 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&cru PCLK_GPIO1>; 640 641 gpio-controller; 642 #gpio-cells = <2>; 643 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 648 gpio2: gpio@20084000 { 649 compatible = "rockchip,gpio-bank"; 650 reg = <0x20084000 0x100>; 651 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 652 clocks = <&cru PCLK_GPIO2>; 653 654 gpio-controller; 655 #gpio-cells = <2>; 656 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 }; 660 661 pcfg_pull_default: pcfg-pull-default { 662 bias-pull-pin-default; 663 }; 664 665 pcfg_pull_none: pcfg-pull-none { 666 bias-disable; 667 }; 668 669 pwm0 { 670 pwm0_pin: pwm0-pin { 671 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 672 }; 673 }; 674 675 pwm1 { 676 pwm1_pin: pwm1-pin { 677 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 678 }; 679 }; 680 681 pwm2 { 682 pwm2_pin: pwm2-pin { 683 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; 684 }; 685 }; 686 687 pwm3 { 688 pwm3_pin: pwm3-pin { 689 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 690 }; 691 }; 692 693 sdmmc { 694 sdmmc_clk: sdmmc-clk { 695 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; 696 }; 697 698 sdmmc_cmd: sdmmc-cmd { 699 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; 700 }; 701 702 sdmmc_cd: sdmmc-cd { 703 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>; 704 }; 705 706 sdmmc_bus1: sdmmc-bus1 { 707 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>; 708 }; 709 710 sdmmc_bus4: sdmmc-bus4 { 711 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, 712 <1 RK_PC3 1 &pcfg_pull_default>, 713 <1 RK_PC4 1 &pcfg_pull_default>, 714 <1 RK_PC5 1 &pcfg_pull_default>; 715 }; 716 }; 717 718 sdio { 719 sdio_bus1: sdio-bus1 { 720 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>; 721 }; 722 723 sdio_bus4: sdio-bus4 { 724 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>, 725 <0 RK_PB4 1 &pcfg_pull_default>, 726 <0 RK_PB5 1 &pcfg_pull_default>, 727 <0 RK_PB6 1 &pcfg_pull_default>; 728 }; 729 730 sdio_cmd: sdio-cmd { 731 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>; 732 }; 733 734 sdio_clk: sdio-clk { 735 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>; 736 }; 737 }; 738 739 emmc { 740 /* 741 * We run eMMC at max speed; bump up drive strength. 742 * We also have external pulls, so disable the internal ones. 743 */ 744 emmc_clk: emmc-clk { 745 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 746 }; 747 748 emmc_cmd: emmc-cmd { 749 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>; 750 }; 751 752 emmc_bus8: emmc-bus8 { 753 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, 754 <1 RK_PD1 2 &pcfg_pull_default>, 755 <1 RK_PD2 2 &pcfg_pull_default>, 756 <1 RK_PD3 2 &pcfg_pull_default>, 757 <1 RK_PD4 2 &pcfg_pull_default>, 758 <1 RK_PD5 2 &pcfg_pull_default>, 759 <1 RK_PD6 2 &pcfg_pull_default>, 760 <1 RK_PD7 2 &pcfg_pull_default>; 761 }; 762 }; 763 764 nfc { 765 flash_ale: flash-ale { 766 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>; 767 }; 768 769 flash_bus8: flash-bus8 { 770 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>, 771 <1 RK_PD1 1 &pcfg_pull_default>, 772 <1 RK_PD2 1 &pcfg_pull_default>, 773 <1 RK_PD3 1 &pcfg_pull_default>, 774 <1 RK_PD4 1 &pcfg_pull_default>, 775 <1 RK_PD5 1 &pcfg_pull_default>, 776 <1 RK_PD6 1 &pcfg_pull_default>, 777 <1 RK_PD7 1 &pcfg_pull_default>; 778 }; 779 780 flash_cle: flash-cle { 781 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>; 782 }; 783 784 flash_csn0: flash-csn0 { 785 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>; 786 }; 787 788 flash_rdn: flash-rdn { 789 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>; 790 }; 791 792 flash_rdy: flash-rdy { 793 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>; 794 }; 795 796 flash_wrn: flash-wrn { 797 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>; 798 }; 799 }; 800 801 emac { 802 emac_xfer: emac-xfer { 803 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ 804 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */ 805 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */ 806 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */ 807 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */ 808 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */ 809 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */ 810 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */ 811 }; 812 813 emac_mdio: emac-mdio { 814 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */ 815 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */ 816 }; 817 }; 818 819 i2c0 { 820 i2c0_xfer: i2c0-xfer { 821 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, 822 <0 RK_PA1 1 &pcfg_pull_none>; 823 }; 824 }; 825 826 i2c1 { 827 i2c1_xfer: i2c1-xfer { 828 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, 829 <0 RK_PA3 1 &pcfg_pull_none>; 830 }; 831 }; 832 833 i2c2 { 834 i2c2_xfer: i2c2-xfer { 835 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, 836 <2 RK_PC5 1 &pcfg_pull_none>; 837 }; 838 }; 839 840 i2s { 841 i2s_bus: i2s-bus { 842 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, 843 <1 RK_PA1 1 &pcfg_pull_default>, 844 <1 RK_PA2 1 &pcfg_pull_default>, 845 <1 RK_PA3 1 &pcfg_pull_default>, 846 <1 RK_PA4 1 &pcfg_pull_default>, 847 <1 RK_PA5 1 &pcfg_pull_default>; 848 }; 849 }; 850 851 hdmi { 852 hdmi_ctl: hdmi-ctl { 853 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>, 854 <1 RK_PB1 1 &pcfg_pull_none>, 855 <1 RK_PB2 1 &pcfg_pull_none>, 856 <1 RK_PB3 1 &pcfg_pull_none>; 857 }; 858 }; 859 860 uart0 { 861 uart0_xfer: uart0-xfer { 862 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>, 863 <0 RK_PC1 1 &pcfg_pull_none>; 864 }; 865 866 uart0_cts: uart0-cts { 867 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>; 868 }; 869 870 uart0_rts: uart0-rts { 871 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; 872 }; 873 }; 874 875 uart1 { 876 uart1_xfer: uart1-xfer { 877 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>, 878 <2 RK_PC7 1 &pcfg_pull_none>; 879 }; 880 /* no rts / cts for uart1 */ 881 }; 882 883 uart2 { 884 uart2_xfer: uart2-xfer { 885 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, 886 <1 RK_PC3 2 &pcfg_pull_none>; 887 }; 888 /* no rts / cts for uart2 */ 889 }; 890 891 spi-pins { 892 spi_txd:spi-txd { 893 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; 894 }; 895 896 spi_rxd:spi-rxd { 897 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; 898 }; 899 900 spi_clk:spi-clk { 901 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; 902 }; 903 904 spi_cs0:spi-cs0 { 905 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; 906 907 }; 908 909 spi_cs1:spi-cs1 { 910 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; 911 912 }; 913 }; 914 }; 915}; 916