1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020, AngeloGioacchino Del Regno
5 * <angelogioacchino.delregno@somainline.org>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/clk-provider.h>
10 #include <linux/err.h>
11 #include <linux/kernel.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16
17 #include <dt-bindings/clock/qcom,gpucc-sdm660.h>
18
19 #include "clk-alpha-pll.h"
20 #include "common.h"
21 #include "clk-regmap.h"
22 #include "clk-pll.h"
23 #include "clk-rcg.h"
24 #include "clk-branch.h"
25 #include "gdsc.h"
26 #include "reset.h"
27
28 enum {
29 P_GPU_XO,
30 P_GPLL0_OUT_MAIN,
31 P_GPLL0_OUT_MAIN_DIV,
32 P_GPU_PLL0_PLL_OUT_MAIN,
33 P_GPU_PLL1_PLL_OUT_MAIN,
34 };
35
36 static struct clk_branch gpucc_cxo_clk = {
37 .halt_reg = 0x1020,
38 .clkr = {
39 .enable_reg = 0x1020,
40 .enable_mask = BIT(0),
41 .hw.init = &(struct clk_init_data){
42 .name = "gpucc_cxo_clk",
43 .parent_data = &(const struct clk_parent_data){
44 .fw_name = "xo"
45 },
46 .num_parents = 1,
47 .ops = &clk_branch2_ops,
48 .flags = CLK_IS_CRITICAL,
49 },
50 },
51 };
52
53 static const struct pll_vco gpu_vco[] = {
54 { 1000000000, 2000000000, 0 },
55 { 500000000, 1000000000, 2 },
56 { 250000000, 500000000, 3 },
57 };
58
59 static struct clk_alpha_pll gpu_pll0_pll_out_main = {
60 .offset = 0x0,
61 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
62 .vco_table = gpu_vco,
63 .num_vco = ARRAY_SIZE(gpu_vco),
64 .clkr.hw.init = &(struct clk_init_data){
65 .name = "gpu_pll0_pll_out_main",
66 .parent_hws = (const struct clk_hw*[]){
67 &gpucc_cxo_clk.clkr.hw,
68 },
69 .num_parents = 1,
70 .ops = &clk_alpha_pll_ops,
71 },
72 };
73
74 static struct clk_alpha_pll gpu_pll1_pll_out_main = {
75 .offset = 0x40,
76 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
77 .vco_table = gpu_vco,
78 .num_vco = ARRAY_SIZE(gpu_vco),
79 .clkr.hw.init = &(struct clk_init_data){
80 .name = "gpu_pll1_pll_out_main",
81 .parent_hws = (const struct clk_hw*[]){
82 &gpucc_cxo_clk.clkr.hw,
83 },
84 .num_parents = 1,
85 .ops = &clk_alpha_pll_ops,
86 },
87 };
88
89 static const struct parent_map gpucc_parent_map_1[] = {
90 { P_GPU_XO, 0 },
91 { P_GPU_PLL0_PLL_OUT_MAIN, 1 },
92 { P_GPU_PLL1_PLL_OUT_MAIN, 3 },
93 { P_GPLL0_OUT_MAIN, 5 },
94 };
95
96 static const struct clk_parent_data gpucc_parent_data_1[] = {
97 { .hw = &gpucc_cxo_clk.clkr.hw },
98 { .hw = &gpu_pll0_pll_out_main.clkr.hw },
99 { .hw = &gpu_pll1_pll_out_main.clkr.hw },
100 { .fw_name = "gcc_gpu_gpll0_clk" },
101 };
102
103 static struct clk_rcg2_gfx3d gfx3d_clk_src = {
104 .div = 2,
105 .rcg = {
106 .cmd_rcgr = 0x1070,
107 .mnd_width = 0,
108 .hid_width = 5,
109 .parent_map = gpucc_parent_map_1,
110 .clkr.hw.init = &(struct clk_init_data){
111 .name = "gfx3d_clk_src",
112 .parent_data = gpucc_parent_data_1,
113 .num_parents = ARRAY_SIZE(gpucc_parent_data_1),
114 .ops = &clk_gfx3d_ops,
115 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
116 },
117 },
118 .hws = (struct clk_hw*[]){
119 &gpucc_cxo_clk.clkr.hw,
120 &gpu_pll0_pll_out_main.clkr.hw,
121 &gpu_pll1_pll_out_main.clkr.hw,
122 }
123 };
124
125 static struct clk_branch gpucc_gfx3d_clk = {
126 .halt_reg = 0x1098,
127 .halt_check = BRANCH_HALT,
128 .hwcg_reg = 0x1098,
129 .hwcg_bit = 1,
130 .clkr = {
131 .enable_reg = 0x1098,
132 .enable_mask = BIT(0),
133 .hw.init = &(struct clk_init_data){
134 .name = "gpucc_gfx3d_clk",
135 .parent_hws = (const struct clk_hw*[]){
136 &gfx3d_clk_src.rcg.clkr.hw,
137 },
138 .num_parents = 1,
139 .ops = &clk_branch2_ops,
140 .flags = CLK_SET_RATE_PARENT,
141 },
142 },
143 };
144
145 static const struct parent_map gpucc_parent_map_0[] = {
146 { P_GPU_XO, 0 },
147 { P_GPLL0_OUT_MAIN, 5 },
148 { P_GPLL0_OUT_MAIN_DIV, 6 },
149 };
150
151 static const struct clk_parent_data gpucc_parent_data_0[] = {
152 { .hw = &gpucc_cxo_clk.clkr.hw },
153 { .fw_name = "gcc_gpu_gpll0_clk" },
154 { .fw_name = "gcc_gpu_gpll0_div_clk" },
155 };
156
157 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
158 F(19200000, P_GPU_XO, 1, 0, 0),
159 { }
160 };
161
162 static struct clk_rcg2 rbbmtimer_clk_src = {
163 .cmd_rcgr = 0x10b0,
164 .mnd_width = 0,
165 .hid_width = 5,
166 .parent_map = gpucc_parent_map_0,
167 .freq_tbl = ftbl_rbbmtimer_clk_src,
168 .clkr.hw.init = &(struct clk_init_data){
169 .name = "rbbmtimer_clk_src",
170 .parent_data = gpucc_parent_data_0,
171 .num_parents = ARRAY_SIZE(gpucc_parent_data_0),
172 .ops = &clk_rcg2_ops,
173 },
174 };
175
176 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
177 F(19200000, P_GPU_XO, 1, 0, 0),
178 F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
179 { }
180 };
181
182 static struct clk_rcg2 rbcpr_clk_src = {
183 .cmd_rcgr = 0x1030,
184 .mnd_width = 0,
185 .hid_width = 5,
186 .parent_map = gpucc_parent_map_0,
187 .freq_tbl = ftbl_rbcpr_clk_src,
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "rbcpr_clk_src",
190 .parent_data = gpucc_parent_data_0,
191 .num_parents = ARRAY_SIZE(gpucc_parent_data_0),
192 .ops = &clk_rcg2_ops,
193 },
194 };
195
196 static struct clk_branch gpucc_rbbmtimer_clk = {
197 .halt_reg = 0x10d0,
198 .halt_check = BRANCH_HALT,
199 .clkr = {
200 .enable_reg = 0x10d0,
201 .enable_mask = BIT(0),
202 .hw.init = &(struct clk_init_data){
203 .name = "gpucc_rbbmtimer_clk",
204 .parent_hws = (const struct clk_hw*[]){
205 &rbbmtimer_clk_src.clkr.hw,
206 },
207 .num_parents = 1,
208 .flags = CLK_SET_RATE_PARENT,
209 .ops = &clk_branch2_ops,
210 },
211 },
212 };
213
214 static struct clk_branch gpucc_rbcpr_clk = {
215 .halt_reg = 0x1054,
216 .halt_check = BRANCH_HALT,
217 .clkr = {
218 .enable_reg = 0x1054,
219 .enable_mask = BIT(0),
220 .hw.init = &(struct clk_init_data){
221 .name = "gpucc_rbcpr_clk",
222 .parent_hws = (const struct clk_hw*[]){
223 &rbcpr_clk_src.clkr.hw,
224 },
225 .num_parents = 1,
226 .flags = CLK_SET_RATE_PARENT,
227 .ops = &clk_branch2_ops,
228 },
229 },
230 };
231
232 static struct gdsc gpu_cx_gdsc = {
233 .gdscr = 0x1004,
234 .gds_hw_ctrl = 0x1008,
235 .pd = {
236 .name = "gpu_cx",
237 },
238 .pwrsts = PWRSTS_OFF_ON,
239 .flags = VOTABLE,
240 };
241
242 static struct gdsc gpu_gx_gdsc = {
243 .gdscr = 0x1094,
244 .clamp_io_ctrl = 0x130,
245 .resets = (unsigned int []){ GPU_GX_BCR },
246 .reset_count = 1,
247 .cxcs = (unsigned int []){ 0x1098 },
248 .cxc_count = 1,
249 .pd = {
250 .name = "gpu_gx",
251 },
252 .parent = &gpu_cx_gdsc.pd,
253 .pwrsts = PWRSTS_OFF | PWRSTS_ON | PWRSTS_RET,
254 .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH,
255 };
256
257 static struct gdsc *gpucc_sdm660_gdscs[] = {
258 [GPU_CX_GDSC] = &gpu_cx_gdsc,
259 [GPU_GX_GDSC] = &gpu_gx_gdsc,
260 };
261
262 static const struct qcom_reset_map gpucc_sdm660_resets[] = {
263 [GPU_CX_BCR] = { 0x1000 },
264 [RBCPR_BCR] = { 0x1050 },
265 [GPU_GX_BCR] = { 0x1090 },
266 [SPDM_BCR] = { 0x10E0 },
267 };
268
269 static struct clk_regmap *gpucc_sdm660_clocks[] = {
270 [GPUCC_CXO_CLK] = &gpucc_cxo_clk.clkr,
271 [GPU_PLL0_PLL] = &gpu_pll0_pll_out_main.clkr,
272 [GPU_PLL1_PLL] = &gpu_pll1_pll_out_main.clkr,
273 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
274 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
275 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
276 [GPUCC_RBCPR_CLK] = &gpucc_rbcpr_clk.clkr,
277 [GPUCC_GFX3D_CLK] = &gpucc_gfx3d_clk.clkr,
278 [GPUCC_RBBMTIMER_CLK] = &gpucc_rbbmtimer_clk.clkr,
279 };
280
281 static const struct regmap_config gpucc_660_regmap_config = {
282 .reg_bits = 32,
283 .reg_stride = 4,
284 .val_bits = 32,
285 .max_register = 0x9034,
286 .fast_io = true,
287 };
288
289 static const struct qcom_cc_desc gpucc_sdm660_desc = {
290 .config = &gpucc_660_regmap_config,
291 .clks = gpucc_sdm660_clocks,
292 .num_clks = ARRAY_SIZE(gpucc_sdm660_clocks),
293 .resets = gpucc_sdm660_resets,
294 .num_resets = ARRAY_SIZE(gpucc_sdm660_resets),
295 .gdscs = gpucc_sdm660_gdscs,
296 .num_gdscs = ARRAY_SIZE(gpucc_sdm660_gdscs),
297 };
298
299 static const struct of_device_id gpucc_sdm660_match_table[] = {
300 { .compatible = "qcom,gpucc-sdm660" },
301 { .compatible = "qcom,gpucc-sdm630" },
302 { }
303 };
304 MODULE_DEVICE_TABLE(of, gpucc_sdm660_match_table);
305
gpucc_sdm660_probe(struct platform_device * pdev)306 static int gpucc_sdm660_probe(struct platform_device *pdev)
307 {
308 struct regmap *regmap;
309 struct alpha_pll_config gpu_pll_config = {
310 .config_ctl_val = 0x4001055b,
311 .alpha = 0xaaaaab00,
312 .alpha_en_mask = BIT(24),
313 .vco_val = 0x2 << 20,
314 .vco_mask = 0x3 << 20,
315 .main_output_mask = 0x1,
316 };
317
318 regmap = qcom_cc_map(pdev, &gpucc_sdm660_desc);
319 if (IS_ERR(regmap))
320 return PTR_ERR(regmap);
321
322 /* 800MHz configuration for GPU PLL0 */
323 gpu_pll_config.l = 0x29;
324 gpu_pll_config.alpha_hi = 0xaa;
325 clk_alpha_pll_configure(&gpu_pll0_pll_out_main, regmap, &gpu_pll_config);
326
327 /* 740MHz configuration for GPU PLL1 */
328 gpu_pll_config.l = 0x26;
329 gpu_pll_config.alpha_hi = 0x8a;
330 clk_alpha_pll_configure(&gpu_pll1_pll_out_main, regmap, &gpu_pll_config);
331
332 return qcom_cc_really_probe(&pdev->dev, &gpucc_sdm660_desc, regmap);
333 }
334
335 static struct platform_driver gpucc_sdm660_driver = {
336 .probe = gpucc_sdm660_probe,
337 .driver = {
338 .name = "gpucc-sdm660",
339 .of_match_table = gpucc_sdm660_match_table,
340 },
341 };
342 module_platform_driver(gpucc_sdm660_driver);
343
344 MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 GPUCC Driver");
345 MODULE_LICENSE("GPL v2");
346