1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97 reset-names = "host1x", "mc"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 186 clock-names = "tsec"; 187 resets = <&tegra_car 83>; 188 reset-names = "tsec"; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 status = "disabled"; 257 }; 258 259 dsib: dsi@54400000 { 260 compatible = "nvidia,tegra210-dsi"; 261 reg = <0x0 0x54400000 0x0 0x00040000>; 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263 <&tegra_car TEGRA210_CLK_DSIBLP>, 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265 clock-names = "dsi", "lp", "parent"; 266 resets = <&tegra_car 82>; 267 reset-names = "dsi"; 268 power-domains = <&pd_sor>; 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270 271 status = "disabled"; 272 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 nvdec@54480000 { 278 compatible = "nvidia,tegra210-nvdec"; 279 reg = <0x0 0x54480000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 nvenc@544c0000 { 284 compatible = "nvidia,tegra210-nvenc"; 285 reg = <0x0 0x544c0000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 tsec@54500000 { 290 compatible = "nvidia,tegra210-tsec"; 291 reg = <0x0 0x54500000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 294 clock-names = "tsec"; 295 resets = <&tegra_car 206>; 296 reset-names = "tsec"; 297 status = "disabled"; 298 }; 299 300 sor0: sor@54540000 { 301 compatible = "nvidia,tegra210-sor"; 302 reg = <0x0 0x54540000 0x0 0x00040000>; 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307 <&tegra_car TEGRA210_CLK_PLL_DP>, 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309 clock-names = "sor", "out", "parent", "dp", "safe"; 310 resets = <&tegra_car 182>; 311 reset-names = "sor"; 312 pinctrl-0 = <&state_dpaux_aux>; 313 pinctrl-1 = <&state_dpaux_i2c>; 314 pinctrl-2 = <&state_dpaux_off>; 315 pinctrl-names = "aux", "i2c", "off"; 316 power-domains = <&pd_sor>; 317 status = "disabled"; 318 }; 319 320 sor1: sor@54580000 { 321 compatible = "nvidia,tegra210-sor1"; 322 reg = <0x0 0x54580000 0x0 0x00040000>; 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327 <&tegra_car TEGRA210_CLK_PLL_DP>, 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 329 clock-names = "sor", "out", "parent", "dp", "safe"; 330 resets = <&tegra_car 183>; 331 reset-names = "sor"; 332 pinctrl-0 = <&state_dpaux1_aux>; 333 pinctrl-1 = <&state_dpaux1_i2c>; 334 pinctrl-2 = <&state_dpaux1_off>; 335 pinctrl-names = "aux", "i2c", "off"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 }; 339 340 dpaux: dpaux@545c0000 { 341 compatible = "nvidia,tegra210-dpaux"; 342 reg = <0x0 0x545c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345 <&tegra_car TEGRA210_CLK_PLL_DP>; 346 clock-names = "dpaux", "parent"; 347 resets = <&tegra_car 181>; 348 reset-names = "dpaux"; 349 power-domains = <&pd_sor>; 350 status = "disabled"; 351 352 state_dpaux_aux: pinmux-aux { 353 groups = "dpaux-io"; 354 function = "aux"; 355 }; 356 357 state_dpaux_i2c: pinmux-i2c { 358 groups = "dpaux-io"; 359 function = "i2c"; 360 }; 361 362 state_dpaux_off: pinmux-off { 363 groups = "dpaux-io"; 364 function = "off"; 365 }; 366 367 i2c-bus { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 }; 372 373 isp@54600000 { 374 compatible = "nvidia,tegra210-isp"; 375 reg = <0x0 0x54600000 0x0 0x00040000>; 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 378 resets = <&tegra_car 23>; 379 reset-names = "isp"; 380 status = "disabled"; 381 }; 382 383 isp@54680000 { 384 compatible = "nvidia,tegra210-isp"; 385 reg = <0x0 0x54680000 0x0 0x00040000>; 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 388 resets = <&tegra_car 3>; 389 reset-names = "isp"; 390 status = "disabled"; 391 }; 392 393 i2c@546c0000 { 394 compatible = "nvidia,tegra210-i2c-vi"; 395 reg = <0x0 0x546c0000 0x0 0x00040000>; 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398 <&tegra_car TEGRA210_CLK_I2CSLOW>; 399 clock-names = "div-clk", "slow"; 400 resets = <&tegra_car 208>; 401 reset-names = "i2c"; 402 power-domains = <&pd_venc>; 403 status = "disabled"; 404 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 }; 409 410 gic: interrupt-controller@50041000 { 411 compatible = "arm,gic-400"; 412 #interrupt-cells = <3>; 413 interrupt-controller; 414 reg = <0x0 0x50041000 0x0 0x1000>, 415 <0x0 0x50042000 0x0 0x2000>, 416 <0x0 0x50044000 0x0 0x2000>, 417 <0x0 0x50046000 0x0 0x2000>; 418 interrupts = <GIC_PPI 9 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420 interrupt-parent = <&gic>; 421 }; 422 423 gpu@57000000 { 424 compatible = "nvidia,gm20b"; 425 reg = <0x0 0x57000000 0x0 0x01000000>, 426 <0x0 0x58000000 0x0 0x01000000>; 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "stall", "nonstall"; 430 clocks = <&tegra_car TEGRA210_CLK_GPU>, 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 433 clock-names = "gpu", "pwr", "ref"; 434 resets = <&tegra_car 184>; 435 reset-names = "gpu"; 436 437 iommus = <&mc TEGRA_SWGROUP_GPU>; 438 439 status = "disabled"; 440 }; 441 442 lic: interrupt-controller@60004000 { 443 compatible = "nvidia,tegra210-ictlr"; 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450 interrupt-controller; 451 #interrupt-cells = <3>; 452 interrupt-parent = <&gic>; 453 }; 454 455 timer@60005000 { 456 compatible = "nvidia,tegra210-timer"; 457 reg = <0x0 0x60005000 0x0 0x400>; 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473 clock-names = "timer"; 474 }; 475 476 tegra_car: clock@60006000 { 477 compatible = "nvidia,tegra210-car"; 478 reg = <0x0 0x60006000 0x0 0x1000>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 481 }; 482 483 flow-controller@60007000 { 484 compatible = "nvidia,tegra210-flowctrl"; 485 reg = <0x0 0x60007000 0x0 0x1000>; 486 }; 487 488 gpio: gpio@6000d000 { 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490 reg = <0x0 0x6000d000 0x0 0x1000>; 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499 #gpio-cells = <2>; 500 gpio-controller; 501 #interrupt-cells = <2>; 502 interrupt-controller; 503 }; 504 505 apbdma: dma@60020000 { 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507 reg = <0x0 0x60020000 0x0 0x1400>; 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541 clock-names = "dma"; 542 resets = <&tegra_car 34>; 543 reset-names = "dma"; 544 #dma-cells = <1>; 545 }; 546 547 apbmisc@70000800 { 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551 }; 552 553 pinmux: pinmux@700008d4 { 554 compatible = "nvidia,tegra210-pinmux"; 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 558 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 559 sdmmc1 { 560 nvidia,pins = "drive_sdmmc1"; 561 nvidia,pull-down-strength = <0x4>; 562 nvidia,pull-up-strength = <0x3>; 563 }; 564 }; 565 566 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 567 sdmmc1 { 568 nvidia,pins = "drive_sdmmc1"; 569 nvidia,pull-down-strength = <0x8>; 570 nvidia,pull-up-strength = <0x8>; 571 }; 572 }; 573 574 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 575 sdmmc2 { 576 nvidia,pins = "drive_sdmmc2"; 577 nvidia,pull-down-strength = <0x10>; 578 nvidia,pull-up-strength = <0x10>; 579 }; 580 }; 581 582 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 583 sdmmc3 { 584 nvidia,pins = "drive_sdmmc3"; 585 nvidia,pull-down-strength = <0x4>; 586 nvidia,pull-up-strength = <0x3>; 587 }; 588 }; 589 590 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 591 sdmmc3 { 592 nvidia,pins = "drive_sdmmc3"; 593 nvidia,pull-down-strength = <0x8>; 594 nvidia,pull-up-strength = <0x8>; 595 }; 596 }; 597 598 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 599 sdmmc4 { 600 nvidia,pins = "drive_sdmmc4"; 601 nvidia,pull-down-strength = <0x10>; 602 nvidia,pull-up-strength = <0x10>; 603 }; 604 }; 605 }; 606 607 /* 608 * There are two serial driver i.e. 8250 based simple serial 609 * driver and APB DMA based serial driver for higher baudrate 610 * and performance. To enable the 8250 based driver, the compatible 611 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 612 * the APB DMA based serial driver, the compatible is 613 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 614 */ 615 uarta: serial@70006000 { 616 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 617 reg = <0x0 0x70006000 0x0 0x40>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 621 resets = <&tegra_car 6>; 622 dmas = <&apbdma 8>, <&apbdma 8>; 623 dma-names = "rx", "tx"; 624 status = "disabled"; 625 }; 626 627 uartb: serial@70006040 { 628 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 629 reg = <0x0 0x70006040 0x0 0x40>; 630 reg-shift = <2>; 631 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 633 resets = <&tegra_car 7>; 634 dmas = <&apbdma 9>, <&apbdma 9>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 uartc: serial@70006200 { 640 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 641 reg = <0x0 0x70006200 0x0 0x40>; 642 reg-shift = <2>; 643 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 645 resets = <&tegra_car 55>; 646 dmas = <&apbdma 10>, <&apbdma 10>; 647 dma-names = "rx", "tx"; 648 status = "disabled"; 649 }; 650 651 uartd: serial@70006300 { 652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 653 reg = <0x0 0x70006300 0x0 0x40>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 657 resets = <&tegra_car 65>; 658 dmas = <&apbdma 19>, <&apbdma 19>; 659 dma-names = "rx", "tx"; 660 status = "disabled"; 661 }; 662 663 pwm: pwm@7000a000 { 664 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 665 reg = <0x0 0x7000a000 0x0 0x100>; 666 #pwm-cells = <2>; 667 clocks = <&tegra_car TEGRA210_CLK_PWM>; 668 resets = <&tegra_car 17>; 669 reset-names = "pwm"; 670 status = "disabled"; 671 }; 672 673 i2c@7000c000 { 674 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 675 reg = <0x0 0x7000c000 0x0 0x100>; 676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 680 clock-names = "div-clk"; 681 resets = <&tegra_car 12>; 682 reset-names = "i2c"; 683 dmas = <&apbdma 21>, <&apbdma 21>; 684 dma-names = "rx", "tx"; 685 status = "disabled"; 686 }; 687 688 i2c@7000c400 { 689 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 690 reg = <0x0 0x7000c400 0x0 0x100>; 691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 695 clock-names = "div-clk"; 696 resets = <&tegra_car 54>; 697 reset-names = "i2c"; 698 dmas = <&apbdma 22>, <&apbdma 22>; 699 dma-names = "rx", "tx"; 700 status = "disabled"; 701 }; 702 703 i2c@7000c500 { 704 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 705 reg = <0x0 0x7000c500 0x0 0x100>; 706 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 710 clock-names = "div-clk"; 711 resets = <&tegra_car 67>; 712 reset-names = "i2c"; 713 dmas = <&apbdma 23>, <&apbdma 23>; 714 dma-names = "rx", "tx"; 715 status = "disabled"; 716 }; 717 718 i2c@7000c700 { 719 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 720 reg = <0x0 0x7000c700 0x0 0x100>; 721 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 725 clock-names = "div-clk"; 726 resets = <&tegra_car 103>; 727 reset-names = "i2c"; 728 dmas = <&apbdma 26>, <&apbdma 26>; 729 dma-names = "rx", "tx"; 730 pinctrl-0 = <&state_dpaux1_i2c>; 731 pinctrl-1 = <&state_dpaux1_off>; 732 pinctrl-names = "default", "idle"; 733 status = "disabled"; 734 }; 735 736 i2c@7000d000 { 737 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 738 reg = <0x0 0x7000d000 0x0 0x100>; 739 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 743 clock-names = "div-clk"; 744 resets = <&tegra_car 47>; 745 reset-names = "i2c"; 746 dmas = <&apbdma 24>, <&apbdma 24>; 747 dma-names = "rx", "tx"; 748 status = "disabled"; 749 }; 750 751 i2c@7000d100 { 752 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 753 reg = <0x0 0x7000d100 0x0 0x100>; 754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 758 clock-names = "div-clk"; 759 resets = <&tegra_car 166>; 760 reset-names = "i2c"; 761 dmas = <&apbdma 30>, <&apbdma 30>; 762 dma-names = "rx", "tx"; 763 pinctrl-0 = <&state_dpaux_i2c>; 764 pinctrl-1 = <&state_dpaux_off>; 765 pinctrl-names = "default", "idle"; 766 status = "disabled"; 767 }; 768 769 spi@7000d400 { 770 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 771 reg = <0x0 0x7000d400 0x0 0x200>; 772 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 776 clock-names = "spi"; 777 resets = <&tegra_car 41>; 778 reset-names = "spi"; 779 dmas = <&apbdma 15>, <&apbdma 15>; 780 dma-names = "rx", "tx"; 781 status = "disabled"; 782 }; 783 784 spi@7000d600 { 785 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 786 reg = <0x0 0x7000d600 0x0 0x200>; 787 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 791 clock-names = "spi"; 792 resets = <&tegra_car 44>; 793 reset-names = "spi"; 794 dmas = <&apbdma 16>, <&apbdma 16>; 795 dma-names = "rx", "tx"; 796 status = "disabled"; 797 }; 798 799 spi@7000d800 { 800 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 801 reg = <0x0 0x7000d800 0x0 0x200>; 802 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 806 clock-names = "spi"; 807 resets = <&tegra_car 46>; 808 reset-names = "spi"; 809 dmas = <&apbdma 17>, <&apbdma 17>; 810 dma-names = "rx", "tx"; 811 status = "disabled"; 812 }; 813 814 spi@7000da00 { 815 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 816 reg = <0x0 0x7000da00 0x0 0x200>; 817 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 821 clock-names = "spi"; 822 resets = <&tegra_car 68>; 823 reset-names = "spi"; 824 dmas = <&apbdma 18>, <&apbdma 18>; 825 dma-names = "rx", "tx"; 826 status = "disabled"; 827 }; 828 829 rtc@7000e000 { 830 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 831 reg = <0x0 0x7000e000 0x0 0x100>; 832 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-parent = <&tegra_pmc>; 834 clocks = <&tegra_car TEGRA210_CLK_RTC>; 835 clock-names = "rtc"; 836 }; 837 838 tegra_pmc: pmc@7000e400 { 839 compatible = "nvidia,tegra210-pmc"; 840 reg = <0x0 0x7000e400 0x0 0x400>; 841 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 842 clock-names = "pclk", "clk32k_in"; 843 #clock-cells = <1>; 844 #interrupt-cells = <2>; 845 interrupt-controller; 846 847 pinmux { 848 pex_dpd_disable: pex-dpd-disable { 849 pins = "pex-bias", "pex-clk1", "pex-clk2"; 850 low-power-disable; 851 }; 852 853 pex_dpd_enable: pex-dpd-enable { 854 pins = "pex-bias", "pex-clk1", "pex-clk2"; 855 low-power-enable; 856 }; 857 858 sdmmc1_1v8: sdmmc1-1v8 { 859 pins = "sdmmc1"; 860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 861 }; 862 863 sdmmc1_3v3: sdmmc1-3v3 { 864 pins = "sdmmc1"; 865 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 866 }; 867 868 sdmmc3_1v8: sdmmc3-1v8 { 869 pins = "sdmmc3"; 870 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 871 }; 872 873 sdmmc3_3v3: sdmmc3-3v3 { 874 pins = "sdmmc3"; 875 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 876 }; 877 878 gpio_1v8: gpio-1v8 { 879 pins = "gpio"; 880 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 881 }; 882 883 gpio_3v3: gpio-3v3 { 884 pins = "gpio"; 885 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 886 }; 887 }; 888 889 powergates { 890 pd_audio: aud { 891 clocks = <&tegra_car TEGRA210_CLK_APE>, 892 <&tegra_car TEGRA210_CLK_APB2APE>; 893 resets = <&tegra_car 198>; 894 #power-domain-cells = <0>; 895 }; 896 897 pd_sor: sor { 898 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 899 <&tegra_car TEGRA210_CLK_SOR1>, 900 <&tegra_car TEGRA210_CLK_CILAB>, 901 <&tegra_car TEGRA210_CLK_CILCD>, 902 <&tegra_car TEGRA210_CLK_CILE>, 903 <&tegra_car TEGRA210_CLK_DSIA>, 904 <&tegra_car TEGRA210_CLK_DSIB>, 905 <&tegra_car TEGRA210_CLK_DPAUX>, 906 <&tegra_car TEGRA210_CLK_DPAUX1>, 907 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 908 resets = <&tegra_car TEGRA210_CLK_SOR0>, 909 <&tegra_car TEGRA210_CLK_SOR1>, 910 <&tegra_car TEGRA210_CLK_DSIA>, 911 <&tegra_car TEGRA210_CLK_DSIB>, 912 <&tegra_car TEGRA210_CLK_DPAUX>, 913 <&tegra_car TEGRA210_CLK_DPAUX1>, 914 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 915 #power-domain-cells = <0>; 916 }; 917 918 pd_venc: venc { 919 clocks = <&tegra_car TEGRA210_CLK_VI>, 920 <&tegra_car TEGRA210_CLK_CSI>; 921 resets = <&mc TEGRA210_MC_RESET_VI>, 922 <&tegra_car 20>, 923 <&tegra_car 52>; 924 #power-domain-cells = <0>; 925 }; 926 927 pd_vic: vic { 928 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 929 resets = <&tegra_car 178>; 930 #power-domain-cells = <0>; 931 }; 932 933 pd_xusbss: xusba { 934 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 935 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 936 #power-domain-cells = <0>; 937 }; 938 939 pd_xusbdev: xusbb { 940 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 941 resets = <&tegra_car 95>; 942 #power-domain-cells = <0>; 943 }; 944 945 pd_xusbhost: xusbc { 946 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 947 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 948 #power-domain-cells = <0>; 949 }; 950 }; 951 }; 952 953 fuse@7000f800 { 954 compatible = "nvidia,tegra210-efuse"; 955 reg = <0x0 0x7000f800 0x0 0x400>; 956 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 957 clock-names = "fuse"; 958 resets = <&tegra_car 39>; 959 reset-names = "fuse"; 960 }; 961 962 mc: memory-controller@70019000 { 963 compatible = "nvidia,tegra210-mc"; 964 reg = <0x0 0x70019000 0x0 0x1000>; 965 clocks = <&tegra_car TEGRA210_CLK_MC>; 966 clock-names = "mc"; 967 968 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 969 970 #iommu-cells = <1>; 971 #reset-cells = <1>; 972 }; 973 974 emc: external-memory-controller@7001b000 { 975 compatible = "nvidia,tegra210-emc"; 976 reg = <0x0 0x7001b000 0x0 0x1000>, 977 <0x0 0x7001e000 0x0 0x1000>, 978 <0x0 0x7001f000 0x0 0x1000>; 979 clocks = <&tegra_car TEGRA210_CLK_EMC>; 980 clock-names = "emc"; 981 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 982 nvidia,memory-controller = <&mc>; 983 #cooling-cells = <2>; 984 }; 985 986 sata@70020000 { 987 compatible = "nvidia,tegra210-ahci"; 988 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 989 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 990 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 991 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&tegra_car TEGRA210_CLK_SATA>, 993 <&tegra_car TEGRA210_CLK_SATA_OOB>; 994 clock-names = "sata", "sata-oob"; 995 resets = <&tegra_car 124>, 996 <&tegra_car 129>, 997 <&tegra_car 123>; 998 reset-names = "sata", "sata-cold", "sata-oob"; 999 status = "disabled"; 1000 }; 1001 1002 hda@70030000 { 1003 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 1004 reg = <0x0 0x70030000 0x0 0x10000>; 1005 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1007 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1008 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1009 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1010 resets = <&tegra_car 125>, /* hda */ 1011 <&tegra_car 128>, /* hda2hdmi */ 1012 <&tegra_car 111>; /* hda2codec_2x */ 1013 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1014 power-domains = <&pd_sor>; 1015 status = "disabled"; 1016 }; 1017 1018 usb@70090000 { 1019 compatible = "nvidia,tegra210-xusb"; 1020 reg = <0x0 0x70090000 0x0 0x8000>, 1021 <0x0 0x70098000 0x0 0x1000>, 1022 <0x0 0x70099000 0x0 0x1000>; 1023 reg-names = "hcd", "fpci", "ipfs"; 1024 1025 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1027 1028 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1029 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1030 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1031 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1032 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1033 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1034 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1035 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1036 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1037 <&tegra_car TEGRA210_CLK_CLK_M>, 1038 <&tegra_car TEGRA210_CLK_PLL_E>; 1039 clock-names = "xusb_host", "xusb_host_src", 1040 "xusb_falcon_src", "xusb_ss", 1041 "xusb_ss_div2", "xusb_ss_src", 1042 "xusb_hs_src", "xusb_fs_src", 1043 "pll_u_480m", "clk_m", "pll_e"; 1044 resets = <&tegra_car 89>, <&tegra_car 156>, 1045 <&tegra_car 143>; 1046 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1047 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1048 power-domain-names = "xusb_host", "xusb_ss"; 1049 1050 nvidia,xusb-padctl = <&padctl>; 1051 1052 status = "disabled"; 1053 }; 1054 1055 padctl: padctl@7009f000 { 1056 compatible = "nvidia,tegra210-xusb-padctl"; 1057 reg = <0x0 0x7009f000 0x0 0x1000>; 1058 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1059 resets = <&tegra_car 142>; 1060 reset-names = "padctl"; 1061 nvidia,pmc = <&tegra_pmc>; 1062 1063 status = "disabled"; 1064 1065 pads { 1066 usb2 { 1067 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1068 clock-names = "trk"; 1069 status = "disabled"; 1070 1071 lanes { 1072 usb2-0 { 1073 status = "disabled"; 1074 #phy-cells = <0>; 1075 }; 1076 1077 usb2-1 { 1078 status = "disabled"; 1079 #phy-cells = <0>; 1080 }; 1081 1082 usb2-2 { 1083 status = "disabled"; 1084 #phy-cells = <0>; 1085 }; 1086 1087 usb2-3 { 1088 status = "disabled"; 1089 #phy-cells = <0>; 1090 }; 1091 }; 1092 }; 1093 1094 hsic { 1095 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1096 clock-names = "trk"; 1097 status = "disabled"; 1098 1099 lanes { 1100 hsic-0 { 1101 status = "disabled"; 1102 #phy-cells = <0>; 1103 }; 1104 1105 hsic-1 { 1106 status = "disabled"; 1107 #phy-cells = <0>; 1108 }; 1109 }; 1110 }; 1111 1112 pcie { 1113 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1114 clock-names = "pll"; 1115 resets = <&tegra_car 205>; 1116 reset-names = "phy"; 1117 status = "disabled"; 1118 1119 lanes { 1120 pcie-0 { 1121 status = "disabled"; 1122 #phy-cells = <0>; 1123 }; 1124 1125 pcie-1 { 1126 status = "disabled"; 1127 #phy-cells = <0>; 1128 }; 1129 1130 pcie-2 { 1131 status = "disabled"; 1132 #phy-cells = <0>; 1133 }; 1134 1135 pcie-3 { 1136 status = "disabled"; 1137 #phy-cells = <0>; 1138 }; 1139 1140 pcie-4 { 1141 status = "disabled"; 1142 #phy-cells = <0>; 1143 }; 1144 1145 pcie-5 { 1146 status = "disabled"; 1147 #phy-cells = <0>; 1148 }; 1149 1150 pcie-6 { 1151 status = "disabled"; 1152 #phy-cells = <0>; 1153 }; 1154 }; 1155 }; 1156 1157 sata { 1158 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1159 clock-names = "pll"; 1160 resets = <&tegra_car 204>; 1161 reset-names = "phy"; 1162 status = "disabled"; 1163 1164 lanes { 1165 sata-0 { 1166 status = "disabled"; 1167 #phy-cells = <0>; 1168 }; 1169 }; 1170 }; 1171 }; 1172 1173 ports { 1174 usb2-0 { 1175 status = "disabled"; 1176 }; 1177 1178 usb2-1 { 1179 status = "disabled"; 1180 }; 1181 1182 usb2-2 { 1183 status = "disabled"; 1184 }; 1185 1186 usb2-3 { 1187 status = "disabled"; 1188 }; 1189 1190 hsic-0 { 1191 status = "disabled"; 1192 }; 1193 1194 usb3-0 { 1195 status = "disabled"; 1196 }; 1197 1198 usb3-1 { 1199 status = "disabled"; 1200 }; 1201 1202 usb3-2 { 1203 status = "disabled"; 1204 }; 1205 1206 usb3-3 { 1207 status = "disabled"; 1208 }; 1209 }; 1210 }; 1211 1212 mmc@700b0000 { 1213 compatible = "nvidia,tegra210-sdhci"; 1214 reg = <0x0 0x700b0000 0x0 0x200>; 1215 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1217 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1218 clock-names = "sdhci", "tmclk"; 1219 resets = <&tegra_car 14>; 1220 reset-names = "sdhci"; 1221 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1222 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1223 pinctrl-0 = <&sdmmc1_3v3>; 1224 pinctrl-1 = <&sdmmc1_1v8>; 1225 pinctrl-2 = <&sdmmc1_3v3_drv>; 1226 pinctrl-3 = <&sdmmc1_1v8_drv>; 1227 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1228 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1229 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1230 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1231 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x0>; 1232 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x0>; 1233 nvidia,default-tap = <0x2>; 1234 nvidia,default-trim = <0x4>; 1235 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1236 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1237 <&tegra_car TEGRA210_CLK_PLL_C4>; 1238 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1239 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1240 status = "disabled"; 1241 }; 1242 1243 mmc@700b0200 { 1244 compatible = "nvidia,tegra210-sdhci"; 1245 reg = <0x0 0x700b0200 0x0 0x200>; 1246 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1248 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1249 clock-names = "sdhci", "tmclk"; 1250 resets = <&tegra_car 9>; 1251 reset-names = "sdhci"; 1252 pinctrl-names = "sdmmc-1v8-drv"; 1253 pinctrl-0 = <&sdmmc2_1v8_drv>; 1254 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1255 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1256 nvidia,default-tap = <0x8>; 1257 nvidia,default-trim = <0x0>; 1258 status = "disabled"; 1259 }; 1260 1261 mmc@700b0400 { 1262 compatible = "nvidia,tegra210-sdhci"; 1263 reg = <0x0 0x700b0400 0x0 0x200>; 1264 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1266 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1267 clock-names = "sdhci", "tmclk"; 1268 resets = <&tegra_car 69>; 1269 reset-names = "sdhci"; 1270 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1271 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1272 pinctrl-0 = <&sdmmc3_3v3>; 1273 pinctrl-1 = <&sdmmc3_1v8>; 1274 pinctrl-2 = <&sdmmc3_3v3_drv>; 1275 pinctrl-3 = <&sdmmc3_1v8_drv>; 1276 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1277 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1278 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1279 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1280 nvidia,default-tap = <0x3>; 1281 nvidia,default-trim = <0x3>; 1282 status = "disabled"; 1283 }; 1284 1285 mmc@700b0600 { 1286 compatible = "nvidia,tegra210-sdhci"; 1287 reg = <0x0 0x700b0600 0x0 0x200>; 1288 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1290 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1291 clock-names = "sdhci", "tmclk"; 1292 resets = <&tegra_car 15>; 1293 reset-names = "sdhci"; 1294 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1295 pinctrl-0 = <&sdmmc4_1v8_drv>; 1296 pinctrl-1 = <&sdmmc4_1v8_drv>; 1297 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1298 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1299 nvidia,default-tap = <0x8>; 1300 nvidia,default-trim = <0x0>; 1301 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1302 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1303 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1304 nvidia,dqs-trim = <40>; 1305 mmc-hs400-1_8v; 1306 status = "disabled"; 1307 }; 1308 1309 usb@700d0000 { 1310 compatible = "nvidia,tegra210-xudc"; 1311 reg = <0x0 0x700d0000 0x0 0x8000>, 1312 <0x0 0x700d8000 0x0 0x1000>, 1313 <0x0 0x700d9000 0x0 0x1000>; 1314 reg-names = "base", "fpci", "ipfs"; 1315 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1317 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1318 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1319 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1320 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1321 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1322 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1323 power-domain-names = "dev", "ss"; 1324 nvidia,xusb-padctl = <&padctl>; 1325 status = "disabled"; 1326 }; 1327 1328 soctherm: thermal-sensor@700e2000 { 1329 compatible = "nvidia,tegra210-soctherm"; 1330 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1331 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1332 reg-names = "soctherm-reg", "car-reg"; 1333 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1335 interrupt-names = "thermal", "edp"; 1336 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1337 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1338 clock-names = "tsensor", "soctherm"; 1339 resets = <&tegra_car 78>; 1340 reset-names = "soctherm"; 1341 #thermal-sensor-cells = <1>; 1342 1343 throttle-cfgs { 1344 throttle_heavy: heavy { 1345 nvidia,priority = <100>; 1346 nvidia,cpu-throt-percent = <85>; 1347 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1348 1349 #cooling-cells = <2>; 1350 }; 1351 }; 1352 }; 1353 1354 mipi: mipi@700e3000 { 1355 compatible = "nvidia,tegra210-mipi"; 1356 reg = <0x0 0x700e3000 0x0 0x100>; 1357 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1358 clock-names = "mipi-cal"; 1359 power-domains = <&pd_sor>; 1360 #nvidia,mipi-calibrate-cells = <1>; 1361 }; 1362 1363 dfll: clock@70110000 { 1364 compatible = "nvidia,tegra210-dfll"; 1365 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1366 <0 0x70110000 0 0x100>, /* I2C output control */ 1367 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1368 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1369 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1370 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1371 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1372 <&tegra_car TEGRA210_CLK_I2C5>; 1373 clock-names = "soc", "ref", "i2c"; 1374 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1375 <&tegra_car 155>; 1376 reset-names = "dvco", "dfll"; 1377 #clock-cells = <0>; 1378 clock-output-names = "dfllCPU_out"; 1379 status = "disabled"; 1380 }; 1381 1382 aconnect@702c0000 { 1383 compatible = "nvidia,tegra210-aconnect"; 1384 clocks = <&tegra_car TEGRA210_CLK_APE>, 1385 <&tegra_car TEGRA210_CLK_APB2APE>; 1386 clock-names = "ape", "apb2ape"; 1387 power-domains = <&pd_audio>; 1388 #address-cells = <1>; 1389 #size-cells = <1>; 1390 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1391 status = "disabled"; 1392 1393 tegra_ahub: ahub@702d0800 { 1394 compatible = "nvidia,tegra210-ahub"; 1395 reg = <0x702d0800 0x800>; 1396 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1397 clock-names = "ahub"; 1398 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1399 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>; 1400 assigned-clock-rates = <81600000>; 1401 #address-cells = <1>; 1402 #size-cells = <1>; 1403 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1404 status = "disabled"; 1405 1406 tegra_admaif: admaif@702d0000 { 1407 compatible = "nvidia,tegra210-admaif"; 1408 reg = <0x702d0000 0x800>; 1409 dmas = <&adma 1>, <&adma 1>, 1410 <&adma 2>, <&adma 2>, 1411 <&adma 3>, <&adma 3>, 1412 <&adma 4>, <&adma 4>, 1413 <&adma 5>, <&adma 5>, 1414 <&adma 6>, <&adma 6>, 1415 <&adma 7>, <&adma 7>, 1416 <&adma 8>, <&adma 8>, 1417 <&adma 9>, <&adma 9>, 1418 <&adma 10>, <&adma 10>; 1419 dma-names = "rx1", "tx1", 1420 "rx2", "tx2", 1421 "rx3", "tx3", 1422 "rx4", "tx4", 1423 "rx5", "tx5", 1424 "rx6", "tx6", 1425 "rx7", "tx7", 1426 "rx8", "tx8", 1427 "rx9", "tx9", 1428 "rx10", "tx10"; 1429 status = "disabled"; 1430 1431 ports { 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 1435 admaif1_port: port@0 { 1436 reg = <0>; 1437 1438 admaif1_ep: endpoint { 1439 remote-endpoint = <&xbar_admaif1_ep>; 1440 }; 1441 }; 1442 1443 admaif2_port: port@1 { 1444 reg = <1>; 1445 1446 admaif2_ep: endpoint { 1447 remote-endpoint = <&xbar_admaif2_ep>; 1448 }; 1449 }; 1450 1451 admaif3_port: port@2 { 1452 reg = <2>; 1453 1454 admaif3_ep: endpoint { 1455 remote-endpoint = <&xbar_admaif3_ep>; 1456 }; 1457 }; 1458 1459 admaif4_port: port@3 { 1460 reg = <3>; 1461 1462 admaif4_ep: endpoint { 1463 remote-endpoint = <&xbar_admaif4_ep>; 1464 }; 1465 }; 1466 1467 admaif5_port: port@4 { 1468 reg = <4>; 1469 1470 admaif5_ep: endpoint { 1471 remote-endpoint = <&xbar_admaif5_ep>; 1472 }; 1473 }; 1474 1475 admaif6_port: port@5 { 1476 reg = <5>; 1477 1478 admaif6_ep: endpoint { 1479 remote-endpoint = <&xbar_admaif6_ep>; 1480 }; 1481 }; 1482 1483 admaif7_port: port@6 { 1484 reg = <6>; 1485 1486 admaif7_ep: endpoint { 1487 remote-endpoint = <&xbar_admaif7_ep>; 1488 }; 1489 }; 1490 1491 admaif8_port: port@7 { 1492 reg = <7>; 1493 1494 admaif8_ep: endpoint { 1495 remote-endpoint = <&xbar_admaif8_ep>; 1496 }; 1497 }; 1498 1499 admaif9_port: port@8 { 1500 reg = <8>; 1501 1502 admaif9_ep: endpoint { 1503 remote-endpoint = <&xbar_admaif9_ep>; 1504 }; 1505 }; 1506 1507 admaif10_port: port@9 { 1508 reg = <9>; 1509 1510 admaif10_ep: endpoint { 1511 remote-endpoint = <&xbar_admaif10_ep>; 1512 }; 1513 }; 1514 }; 1515 }; 1516 1517 tegra_i2s1: i2s@702d1000 { 1518 compatible = "nvidia,tegra210-i2s"; 1519 reg = <0x702d1000 0x100>; 1520 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1521 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1522 clock-names = "i2s", "sync_input"; 1523 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1524 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1525 assigned-clock-rates = <1536000>; 1526 sound-name-prefix = "I2S1"; 1527 status = "disabled"; 1528 }; 1529 1530 tegra_i2s2: i2s@702d1100 { 1531 compatible = "nvidia,tegra210-i2s"; 1532 reg = <0x702d1100 0x100>; 1533 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1534 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1535 clock-names = "i2s", "sync_input"; 1536 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1537 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1538 assigned-clock-rates = <1536000>; 1539 sound-name-prefix = "I2S2"; 1540 status = "disabled"; 1541 }; 1542 1543 tegra_i2s3: i2s@702d1200 { 1544 compatible = "nvidia,tegra210-i2s"; 1545 reg = <0x702d1200 0x100>; 1546 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1547 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1548 clock-names = "i2s", "sync_input"; 1549 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1550 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1551 assigned-clock-rates = <1536000>; 1552 sound-name-prefix = "I2S3"; 1553 status = "disabled"; 1554 }; 1555 1556 tegra_i2s4: i2s@702d1300 { 1557 compatible = "nvidia,tegra210-i2s"; 1558 reg = <0x702d1300 0x100>; 1559 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1560 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1561 clock-names = "i2s", "sync_input"; 1562 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1563 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1564 assigned-clock-rates = <1536000>; 1565 sound-name-prefix = "I2S4"; 1566 status = "disabled"; 1567 }; 1568 1569 tegra_i2s5: i2s@702d1400 { 1570 compatible = "nvidia,tegra210-i2s"; 1571 reg = <0x702d1400 0x100>; 1572 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1573 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1574 clock-names = "i2s", "sync_input"; 1575 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1576 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1577 assigned-clock-rates = <1536000>; 1578 sound-name-prefix = "I2S5"; 1579 status = "disabled"; 1580 }; 1581 1582 tegra_sfc1: sfc@702d2000 { 1583 compatible = "nvidia,tegra210-sfc"; 1584 reg = <0x702d2000 0x200>; 1585 sound-name-prefix = "SFC1"; 1586 status = "disabled"; 1587 }; 1588 1589 tegra_sfc2: sfc@702d2200 { 1590 compatible = "nvidia,tegra210-sfc"; 1591 reg = <0x702d2200 0x200>; 1592 sound-name-prefix = "SFC2"; 1593 status = "disabled"; 1594 }; 1595 1596 tegra_sfc3: sfc@702d2400 { 1597 compatible = "nvidia,tegra210-sfc"; 1598 reg = <0x702d2400 0x200>; 1599 sound-name-prefix = "SFC3"; 1600 status = "disabled"; 1601 }; 1602 1603 tegra_sfc4: sfc@702d2600 { 1604 compatible = "nvidia,tegra210-sfc"; 1605 reg = <0x702d2600 0x200>; 1606 sound-name-prefix = "SFC4"; 1607 status = "disabled"; 1608 }; 1609 1610 tegra_amx1: amx@702d3000 { 1611 compatible = "nvidia,tegra210-amx"; 1612 reg = <0x702d3000 0x100>; 1613 sound-name-prefix = "AMX1"; 1614 status = "disabled"; 1615 }; 1616 1617 tegra_amx2: amx@702d3100 { 1618 compatible = "nvidia,tegra210-amx"; 1619 reg = <0x702d3100 0x100>; 1620 sound-name-prefix = "AMX2"; 1621 status = "disabled"; 1622 }; 1623 1624 tegra_adx1: adx@702d3800 { 1625 compatible = "nvidia,tegra210-adx"; 1626 reg = <0x702d3800 0x100>; 1627 sound-name-prefix = "ADX1"; 1628 status = "disabled"; 1629 }; 1630 1631 tegra_adx2: adx@702d3900 { 1632 compatible = "nvidia,tegra210-adx"; 1633 reg = <0x702d3900 0x100>; 1634 sound-name-prefix = "ADX2"; 1635 status = "disabled"; 1636 }; 1637 1638 tegra_dmic1: dmic@702d4000 { 1639 compatible = "nvidia,tegra210-dmic"; 1640 reg = <0x702d4000 0x100>; 1641 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1642 clock-names = "dmic"; 1643 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1644 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1645 assigned-clock-rates = <3072000>; 1646 sound-name-prefix = "DMIC1"; 1647 status = "disabled"; 1648 }; 1649 1650 tegra_dmic2: dmic@702d4100 { 1651 compatible = "nvidia,tegra210-dmic"; 1652 reg = <0x702d4100 0x100>; 1653 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1654 clock-names = "dmic"; 1655 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1656 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1657 assigned-clock-rates = <3072000>; 1658 sound-name-prefix = "DMIC2"; 1659 status = "disabled"; 1660 }; 1661 1662 tegra_dmic3: dmic@702d4200 { 1663 compatible = "nvidia,tegra210-dmic"; 1664 reg = <0x702d4200 0x100>; 1665 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1666 clock-names = "dmic"; 1667 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1668 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1669 assigned-clock-rates = <3072000>; 1670 sound-name-prefix = "DMIC3"; 1671 status = "disabled"; 1672 }; 1673 1674 tegra_ope1: processing-engine@702d8000 { 1675 compatible = "nvidia,tegra210-ope"; 1676 reg = <0x702d8000 0x100>; 1677 #address-cells = <1>; 1678 #size-cells = <1>; 1679 ranges; 1680 sound-name-prefix = "OPE1"; 1681 status = "disabled"; 1682 1683 equalizer@702d8100 { 1684 compatible = "nvidia,tegra210-peq"; 1685 reg = <0x702d8100 0x100>; 1686 }; 1687 1688 dynamic-range-compressor@702d8200 { 1689 compatible = "nvidia,tegra210-mbdrc"; 1690 reg = <0x702d8200 0x200>; 1691 }; 1692 }; 1693 1694 tegra_ope2: processing-engine@702d8400 { 1695 compatible = "nvidia,tegra210-ope"; 1696 reg = <0x702d8400 0x100>; 1697 #address-cells = <1>; 1698 #size-cells = <1>; 1699 ranges; 1700 sound-name-prefix = "OPE2"; 1701 status = "disabled"; 1702 1703 equalizer@702d8500 { 1704 compatible = "nvidia,tegra210-peq"; 1705 reg = <0x702d8500 0x100>; 1706 }; 1707 1708 dynamic-range-compressor@702d8600 { 1709 compatible = "nvidia,tegra210-mbdrc"; 1710 reg = <0x702d8600 0x200>; 1711 }; 1712 }; 1713 1714 tegra_mvc1: mvc@702da000 { 1715 compatible = "nvidia,tegra210-mvc"; 1716 reg = <0x702da000 0x200>; 1717 sound-name-prefix = "MVC1"; 1718 status = "disabled"; 1719 }; 1720 1721 tegra_mvc2: mvc@702da200 { 1722 compatible = "nvidia,tegra210-mvc"; 1723 reg = <0x702da200 0x200>; 1724 sound-name-prefix = "MVC2"; 1725 status = "disabled"; 1726 }; 1727 1728 tegra_amixer: amixer@702dbb00 { 1729 compatible = "nvidia,tegra210-amixer"; 1730 reg = <0x702dbb00 0x800>; 1731 sound-name-prefix = "MIXER1"; 1732 status = "disabled"; 1733 }; 1734 1735 ports { 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 1739 port@0 { 1740 reg = <0x0>; 1741 1742 xbar_admaif1_ep: endpoint { 1743 remote-endpoint = <&admaif1_ep>; 1744 }; 1745 }; 1746 1747 port@1 { 1748 reg = <0x1>; 1749 1750 xbar_admaif2_ep: endpoint { 1751 remote-endpoint = <&admaif2_ep>; 1752 }; 1753 }; 1754 1755 port@2 { 1756 reg = <0x2>; 1757 1758 xbar_admaif3_ep: endpoint { 1759 remote-endpoint = <&admaif3_ep>; 1760 }; 1761 }; 1762 1763 port@3 { 1764 reg = <0x3>; 1765 1766 xbar_admaif4_ep: endpoint { 1767 remote-endpoint = <&admaif4_ep>; 1768 }; 1769 }; 1770 1771 port@4 { 1772 reg = <0x4>; 1773 xbar_admaif5_ep: endpoint { 1774 remote-endpoint = <&admaif5_ep>; 1775 }; 1776 }; 1777 port@5 { 1778 reg = <0x5>; 1779 1780 xbar_admaif6_ep: endpoint { 1781 remote-endpoint = <&admaif6_ep>; 1782 }; 1783 }; 1784 1785 port@6 { 1786 reg = <0x6>; 1787 1788 xbar_admaif7_ep: endpoint { 1789 remote-endpoint = <&admaif7_ep>; 1790 }; 1791 }; 1792 1793 port@7 { 1794 reg = <0x7>; 1795 1796 xbar_admaif8_ep: endpoint { 1797 remote-endpoint = <&admaif8_ep>; 1798 }; 1799 }; 1800 1801 port@8 { 1802 reg = <0x8>; 1803 1804 xbar_admaif9_ep: endpoint { 1805 remote-endpoint = <&admaif9_ep>; 1806 }; 1807 }; 1808 1809 port@9 { 1810 reg = <0x9>; 1811 1812 xbar_admaif10_ep: endpoint { 1813 remote-endpoint = <&admaif10_ep>; 1814 }; 1815 }; 1816 }; 1817 }; 1818 1819 adma: dma-controller@702e2000 { 1820 compatible = "nvidia,tegra210-adma"; 1821 reg = <0x702e2000 0x2000>; 1822 interrupt-parent = <&agic>; 1823 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1845 #dma-cells = <1>; 1846 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1847 clock-names = "d_audio"; 1848 status = "disabled"; 1849 }; 1850 1851 agic: interrupt-controller@702f9000 { 1852 compatible = "nvidia,tegra210-agic"; 1853 #interrupt-cells = <3>; 1854 interrupt-controller; 1855 reg = <0x702f9000 0x1000>, 1856 <0x702fa000 0x2000>; 1857 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1858 clocks = <&tegra_car TEGRA210_CLK_APE>; 1859 clock-names = "clk"; 1860 status = "disabled"; 1861 }; 1862 }; 1863 1864 spi@70410000 { 1865 compatible = "nvidia,tegra210-qspi"; 1866 reg = <0x0 0x70410000 0x0 0x1000>; 1867 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1871 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1872 clock-names = "qspi", "qspi_out"; 1873 resets = <&tegra_car 211>; 1874 dmas = <&apbdma 5>, <&apbdma 5>; 1875 dma-names = "rx", "tx"; 1876 status = "disabled"; 1877 }; 1878 1879 usb@7d000000 { 1880 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1881 reg = <0x0 0x7d000000 0x0 0x4000>; 1882 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1883 phy_type = "utmi"; 1884 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1885 clock-names = "usb"; 1886 resets = <&tegra_car 22>; 1887 reset-names = "usb"; 1888 nvidia,phy = <&phy1>; 1889 status = "disabled"; 1890 }; 1891 1892 phy1: usb-phy@7d000000 { 1893 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1894 reg = <0x0 0x7d000000 0x0 0x4000>, 1895 <0x0 0x7d000000 0x0 0x4000>; 1896 phy_type = "utmi"; 1897 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1898 <&tegra_car TEGRA210_CLK_PLL_U>, 1899 <&tegra_car TEGRA210_CLK_USBD>; 1900 clock-names = "reg", "pll_u", "utmi-pads"; 1901 resets = <&tegra_car 22>, <&tegra_car 22>; 1902 reset-names = "usb", "utmi-pads"; 1903 nvidia,hssync-start-delay = <0>; 1904 nvidia,idle-wait-delay = <17>; 1905 nvidia,elastic-limit = <16>; 1906 nvidia,term-range-adj = <6>; 1907 nvidia,xcvr-setup = <9>; 1908 nvidia,xcvr-lsfslew = <0>; 1909 nvidia,xcvr-lsrslew = <3>; 1910 nvidia,hssquelch-level = <2>; 1911 nvidia,hsdiscon-level = <5>; 1912 nvidia,xcvr-hsslew = <12>; 1913 nvidia,has-utmi-pad-registers; 1914 status = "disabled"; 1915 }; 1916 1917 usb@7d004000 { 1918 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1919 reg = <0x0 0x7d004000 0x0 0x4000>; 1920 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1921 phy_type = "utmi"; 1922 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1923 clock-names = "usb"; 1924 resets = <&tegra_car 58>; 1925 reset-names = "usb"; 1926 nvidia,phy = <&phy2>; 1927 status = "disabled"; 1928 }; 1929 1930 phy2: usb-phy@7d004000 { 1931 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1932 reg = <0x0 0x7d004000 0x0 0x4000>, 1933 <0x0 0x7d000000 0x0 0x4000>; 1934 phy_type = "utmi"; 1935 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1936 <&tegra_car TEGRA210_CLK_PLL_U>, 1937 <&tegra_car TEGRA210_CLK_USBD>; 1938 clock-names = "reg", "pll_u", "utmi-pads"; 1939 resets = <&tegra_car 58>, <&tegra_car 22>; 1940 reset-names = "usb", "utmi-pads"; 1941 nvidia,hssync-start-delay = <0>; 1942 nvidia,idle-wait-delay = <17>; 1943 nvidia,elastic-limit = <16>; 1944 nvidia,term-range-adj = <6>; 1945 nvidia,xcvr-setup = <9>; 1946 nvidia,xcvr-lsfslew = <0>; 1947 nvidia,xcvr-lsrslew = <3>; 1948 nvidia,hssquelch-level = <2>; 1949 nvidia,hsdiscon-level = <5>; 1950 nvidia,xcvr-hsslew = <12>; 1951 status = "disabled"; 1952 }; 1953 1954 cpus { 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 1958 cpu@0 { 1959 device_type = "cpu"; 1960 compatible = "arm,cortex-a57"; 1961 reg = <0>; 1962 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1963 <&tegra_car TEGRA210_CLK_PLL_X>, 1964 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1965 <&dfll>; 1966 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1967 clock-latency = <300000>; 1968 cpu-idle-states = <&CPU_SLEEP>; 1969 next-level-cache = <&L2>; 1970 }; 1971 1972 cpu@1 { 1973 device_type = "cpu"; 1974 compatible = "arm,cortex-a57"; 1975 reg = <1>; 1976 cpu-idle-states = <&CPU_SLEEP>; 1977 next-level-cache = <&L2>; 1978 }; 1979 1980 cpu@2 { 1981 device_type = "cpu"; 1982 compatible = "arm,cortex-a57"; 1983 reg = <2>; 1984 cpu-idle-states = <&CPU_SLEEP>; 1985 next-level-cache = <&L2>; 1986 }; 1987 1988 cpu@3 { 1989 device_type = "cpu"; 1990 compatible = "arm,cortex-a57"; 1991 reg = <3>; 1992 cpu-idle-states = <&CPU_SLEEP>; 1993 next-level-cache = <&L2>; 1994 }; 1995 1996 idle-states { 1997 entry-method = "psci"; 1998 1999 CPU_SLEEP: cpu-sleep { 2000 compatible = "arm,idle-state"; 2001 arm,psci-suspend-param = <0x40000007>; 2002 entry-latency-us = <100>; 2003 exit-latency-us = <30>; 2004 min-residency-us = <1000>; 2005 wakeup-latency-us = <130>; 2006 idle-state-name = "cpu-sleep"; 2007 status = "disabled"; 2008 }; 2009 }; 2010 2011 L2: l2-cache { 2012 compatible = "cache"; 2013 cache-level = <2>; 2014 cache-unified; 2015 }; 2016 }; 2017 2018 pmu { 2019 compatible = "arm,cortex-a57-pmu"; 2020 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2021 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2022 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2023 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2024 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2025 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2026 }; 2027 2028 sound { 2029 status = "disabled"; 2030 2031 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2032 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2033 clock-names = "pll_a", "plla_out0"; 2034 2035 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2036 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2037 <&tegra_car TEGRA210_CLK_EXTERN1>; 2038 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2039 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2040 }; 2041 2042 thermal-zones { 2043 cpu-thermal { 2044 polling-delay-passive = <1000>; 2045 polling-delay = <0>; 2046 2047 thermal-sensors = 2048 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2049 2050 trips { 2051 cpu-shutdown-trip { 2052 temperature = <102500>; 2053 hysteresis = <0>; 2054 type = "critical"; 2055 }; 2056 2057 cpu_throttle_trip: throttle-trip { 2058 temperature = <98500>; 2059 hysteresis = <1000>; 2060 type = "hot"; 2061 }; 2062 }; 2063 2064 cooling-maps { 2065 map0 { 2066 trip = <&cpu_throttle_trip>; 2067 cooling-device = <&throttle_heavy 1 1>; 2068 }; 2069 }; 2070 }; 2071 2072 mem-thermal { 2073 polling-delay-passive = <0>; 2074 polling-delay = <0>; 2075 2076 thermal-sensors = 2077 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2078 2079 trips { 2080 dram_nominal: mem-nominal-trip { 2081 temperature = <50000>; 2082 hysteresis = <1000>; 2083 type = "passive"; 2084 }; 2085 2086 dram_throttle: mem-throttle-trip { 2087 temperature = <70000>; 2088 hysteresis = <1000>; 2089 type = "active"; 2090 }; 2091 2092 mem-hot-trip { 2093 temperature = <100000>; 2094 hysteresis = <1000>; 2095 type = "hot"; 2096 }; 2097 2098 mem-shutdown-trip { 2099 temperature = <103000>; 2100 hysteresis = <0>; 2101 type = "critical"; 2102 }; 2103 }; 2104 2105 cooling-maps { 2106 dram-passive { 2107 cooling-device = <&emc 0 0>; 2108 trip = <&dram_nominal>; 2109 }; 2110 2111 dram-active { 2112 cooling-device = <&emc 1 1>; 2113 trip = <&dram_throttle>; 2114 }; 2115 }; 2116 }; 2117 2118 gpu-thermal { 2119 polling-delay-passive = <1000>; 2120 polling-delay = <0>; 2121 2122 thermal-sensors = 2123 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2124 2125 trips { 2126 gpu-shutdown-trip { 2127 temperature = <103000>; 2128 hysteresis = <0>; 2129 type = "critical"; 2130 }; 2131 2132 gpu_throttle_trip: throttle-trip { 2133 temperature = <100000>; 2134 hysteresis = <1000>; 2135 type = "hot"; 2136 }; 2137 }; 2138 2139 cooling-maps { 2140 map0 { 2141 trip = <&gpu_throttle_trip>; 2142 cooling-device = <&throttle_heavy 1 1>; 2143 }; 2144 }; 2145 }; 2146 2147 pllx-thermal { 2148 polling-delay-passive = <0>; 2149 polling-delay = <0>; 2150 2151 thermal-sensors = 2152 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2153 2154 trips { 2155 pllx-shutdown-trip { 2156 temperature = <103000>; 2157 hysteresis = <0>; 2158 type = "critical"; 2159 }; 2160 2161 pllx-throttle-trip { 2162 temperature = <100000>; 2163 hysteresis = <1000>; 2164 type = "hot"; 2165 }; 2166 }; 2167 2168 cooling-maps { 2169 /* 2170 * There are currently no cooling maps, 2171 * because there are no cooling devices. 2172 */ 2173 }; 2174 }; 2175 }; 2176 2177 timer { 2178 compatible = "arm,armv8-timer"; 2179 interrupts = <GIC_PPI 13 2180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2181 <GIC_PPI 14 2182 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2183 <GIC_PPI 11 2184 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2185 <GIC_PPI 10 2186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2187 interrupt-parent = <&gic>; 2188 arm,no-tick-in-suspend; 2189 }; 2190}; 2191