1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r9a06g032-sysctrl.h> 11 12/ { 13 compatible = "renesas,r9a06g032"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a7"; 25 reg = <0>; 26 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 27 }; 28 29 cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a7"; 32 reg = <1>; 33 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 34 enable-method = "renesas,r9a06g032-smp"; 35 cpu-release-addr = <0 0x4000c204>; 36 }; 37 }; 38 39 ext_jtag_clk: extjtagclk { 40 #clock-cells = <0>; 41 compatible = "fixed-clock"; 42 clock-frequency = <0>; 43 }; 44 45 ext_mclk: extmclk { 46 #clock-cells = <0>; 47 compatible = "fixed-clock"; 48 clock-frequency = <40000000>; 49 }; 50 51 ext_rgmii_ref: extrgmiiref { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <0>; 55 }; 56 57 ext_rtc_clk: extrtcclk { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <0>; 61 }; 62 63 soc { 64 compatible = "simple-bus"; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 ranges; 68 69 rtc0: rtc@40006000 { 70 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; 71 reg = <0x40006000 0x1000>; 72 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 73 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 74 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 75 interrupt-names = "alarm", "timer", "pps"; 76 clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>; 77 clock-names = "hclk", "xtal"; 78 power-domains = <&sysctrl>; 79 status = "disabled"; 80 }; 81 82 wdt0: watchdog@40008000 { 83 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 84 reg = <0x40008000 0x1000>; 85 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 87 status = "disabled"; 88 }; 89 90 wdt1: watchdog@40009000 { 91 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 92 reg = <0x40009000 0x1000>; 93 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; 94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 95 status = "disabled"; 96 }; 97 98 sysctrl: system-controller@4000c000 { 99 compatible = "renesas,r9a06g032-sysctrl"; 100 reg = <0x4000c000 0x1000>; 101 status = "okay"; 102 #clock-cells = <1>; 103 #power-domain-cells = <0>; 104 105 clocks = <&ext_mclk>, <&ext_rtc_clk>, 106 <&ext_jtag_clk>, <&ext_rgmii_ref>; 107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 111 dmamux: dma-router@a0 { 112 compatible = "renesas,rzn1-dmamux"; 113 reg = <0xa0 4>; 114 #dma-cells = <6>; 115 dma-requests = <32>; 116 dma-masters = <&dma0 &dma1>; 117 }; 118 }; 119 120 udc: usb@4001e000 { 121 compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; 122 reg = <0x4001e000 0x2000>; 123 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&sysctrl R9A06G032_HCLK_USBF>, 126 <&sysctrl R9A06G032_HCLK_USBPM>; 127 clock-names = "hclkf", "hclkpm"; 128 power-domains = <&sysctrl>; 129 status = "disabled"; 130 }; 131 132 pci_usb: pci@40030000 { 133 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; 134 device_type = "pci"; 135 clocks = <&sysctrl R9A06G032_HCLK_USBH>, 136 <&sysctrl R9A06G032_HCLK_USBPM>, 137 <&sysctrl R9A06G032_CLK_PCI_USB>; 138 clock-names = "hclkh", "hclkpm", "pciclk"; 139 power-domains = <&sysctrl>; 140 reg = <0x40030000 0xc00>, 141 <0x40020000 0x1100>; 142 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 145 bus-range = <0 0>; 146 #address-cells = <3>; 147 #size-cells = <2>; 148 #interrupt-cells = <1>; 149 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; 150 /* Should map all possible DDR as inbound ranges, but 151 * the IP only supports a 256MB, 512MB, or 1GB window. 152 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) 153 */ 154 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; 155 interrupt-map-mask = <0xf800 0 0 0x7>; 156 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 157 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 158 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 159 160 usb@1,0 { 161 reg = <0x800 0 0 0 0>; 162 phys = <&usbphy>; 163 phy-names = "usb"; 164 }; 165 166 usb@2,0 { 167 reg = <0x1000 0 0 0 0>; 168 phys = <&usbphy>; 169 phy-names = "usb"; 170 }; 171 }; 172 173 uart0: serial@40060000 { 174 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 175 reg = <0x40060000 0x400>; 176 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 177 reg-shift = <2>; 178 reg-io-width = <4>; 179 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; 180 clock-names = "baudclk", "apb_pclk"; 181 status = "disabled"; 182 }; 183 184 uart1: serial@40061000 { 185 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 186 reg = <0x40061000 0x400>; 187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 188 reg-shift = <2>; 189 reg-io-width = <4>; 190 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; 191 clock-names = "baudclk", "apb_pclk"; 192 status = "disabled"; 193 }; 194 195 uart2: serial@40062000 { 196 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 197 reg = <0x40062000 0x400>; 198 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 199 reg-shift = <2>; 200 reg-io-width = <4>; 201 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; 202 clock-names = "baudclk", "apb_pclk"; 203 status = "disabled"; 204 }; 205 206 uart3: serial@50000000 { 207 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 208 reg = <0x50000000 0x400>; 209 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 210 reg-shift = <2>; 211 reg-io-width = <4>; 212 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; 213 clock-names = "baudclk", "apb_pclk"; 214 dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>; 215 dma-names = "tx", "rx"; 216 status = "disabled"; 217 }; 218 219 uart4: serial@50001000 { 220 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 221 reg = <0x50001000 0x400>; 222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; 226 clock-names = "baudclk", "apb_pclk"; 227 dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>; 228 dma-names = "tx", "rx"; 229 status = "disabled"; 230 }; 231 232 uart5: serial@50002000 { 233 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 234 reg = <0x50002000 0x400>; 235 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; 239 clock-names = "baudclk", "apb_pclk"; 240 dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>; 241 dma-names = "tx", "rx"; 242 status = "disabled"; 243 }; 244 245 uart6: serial@50003000 { 246 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 247 reg = <0x50003000 0x400>; 248 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 249 reg-shift = <2>; 250 reg-io-width = <4>; 251 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; 252 clock-names = "baudclk", "apb_pclk"; 253 dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>; 254 dma-names = "tx", "rx"; 255 status = "disabled"; 256 }; 257 258 uart7: serial@50004000 { 259 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 260 reg = <0x50004000 0x400>; 261 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; 265 clock-names = "baudclk", "apb_pclk"; 266 dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>; 267 dma-names = "tx", "rx"; 268 status = "disabled"; 269 }; 270 271 i2c1: i2c@40063000 { 272 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; 273 reg = <0x40063000 0x100>; 274 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>; 276 clock-names = "ref", "pclk"; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 282 i2c2: i2c@40064000 { 283 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; 284 reg = <0x40064000 0x100>; 285 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>; 287 clock-names = "ref", "pclk"; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 }; 292 293 adc: adc@40065000 { 294 compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc"; 295 reg = <0x40065000 0x200>; 296 clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>; 297 clock-names = "pclk", "adc"; 298 power-domains = <&sysctrl>; 299 #io-channel-cells = <1>; 300 status = "disabled"; 301 }; 302 303 pinctrl: pinctrl@40067000 { 304 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; 305 reg = <0x40067000 0x1000>, <0x51000000 0x480>; 306 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; 307 clock-names = "bus"; 308 status = "okay"; 309 }; 310 311 sdio1: mmc@40100000 { 312 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; 313 reg = <0x40100000 0x1000>; 314 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 316 interrupt-names = "int", "wakeup"; 317 clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>; 318 clock-names = "clk_xin", "clk_ahb"; 319 no-1-8-v; 320 status = "disabled"; 321 }; 322 323 sdio2: mmc@40101000 { 324 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; 325 reg = <0x40101000 0x1000>; 326 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 328 interrupt-names = "int", "wakeup"; 329 clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>; 330 clock-names = "clk_xin", "clk_ahb"; 331 no-1-8-v; 332 status = "disabled"; 333 }; 334 335 nand_controller: nand-controller@40102000 { 336 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; 337 reg = <0x40102000 0x2000>; 338 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; 340 clock-names = "hclk", "eclk"; 341 power-domains = <&sysctrl>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 status = "disabled"; 345 }; 346 347 dma0: dma-controller@40104000 { 348 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 349 reg = <0x40104000 0x1000>; 350 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 351 clock-names = "hclk"; 352 clocks = <&sysctrl R9A06G032_HCLK_DMA0>; 353 dma-channels = <8>; 354 dma-requests = <16>; 355 dma-masters = <1>; 356 #dma-cells = <3>; 357 block_size = <0xfff>; 358 data-width = <8>; 359 }; 360 361 dma1: dma-controller@40105000 { 362 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 363 reg = <0x40105000 0x1000>; 364 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 365 clock-names = "hclk"; 366 clocks = <&sysctrl R9A06G032_HCLK_DMA1>; 367 dma-channels = <8>; 368 dma-requests = <16>; 369 dma-masters = <1>; 370 #dma-cells = <3>; 371 block_size = <0xfff>; 372 data-width = <8>; 373 }; 374 375 gmac1: ethernet@44000000 { 376 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 377 reg = <0x44000000 0x2000>; 378 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 381 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 382 clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; 383 clock-names = "stmmaceth"; 384 power-domains = <&sysctrl>; 385 snps,multicast-filter-bins = <256>; 386 snps,perfect-filter-entries = <128>; 387 tx-fifo-depth = <2048>; 388 rx-fifo-depth = <4096>; 389 pcs-handle = <&mii_conv1>; 390 status = "disabled"; 391 }; 392 393 gmac2: ethernet@44002000 { 394 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 395 reg = <0x44002000 0x2000>; 396 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 399 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 400 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; 401 clock-names = "stmmaceth"; 402 power-domains = <&sysctrl>; 403 snps,multicast-filter-bins = <256>; 404 snps,perfect-filter-entries = <128>; 405 tx-fifo-depth = <2048>; 406 rx-fifo-depth = <4096>; 407 status = "disabled"; 408 }; 409 410 eth_miic: eth-miic@44030000 { 411 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <0x44030000 0x10000>; 415 clocks = <&sysctrl R9A06G032_CLK_MII_REF>, 416 <&sysctrl R9A06G032_CLK_RGMII_REF>, 417 <&sysctrl R9A06G032_CLK_RMII_REF>, 418 <&sysctrl R9A06G032_HCLK_SWITCH_RG>; 419 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 420 power-domains = <&sysctrl>; 421 status = "disabled"; 422 423 mii_conv1: mii-conv@1 { 424 reg = <1>; 425 status = "disabled"; 426 }; 427 428 mii_conv2: mii-conv@2 { 429 reg = <2>; 430 status = "disabled"; 431 }; 432 433 mii_conv3: mii-conv@3 { 434 reg = <3>; 435 status = "disabled"; 436 }; 437 438 mii_conv4: mii-conv@4 { 439 reg = <4>; 440 status = "disabled"; 441 }; 442 443 mii_conv5: mii-conv@5 { 444 reg = <5>; 445 status = "disabled"; 446 }; 447 }; 448 449 switch: switch@44050000 { 450 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; 451 reg = <0x44050000 0x10000>; 452 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, 453 <&sysctrl R9A06G032_CLK_SWITCH>; 454 clock-names = "hclk", "clk"; 455 power-domains = <&sysctrl>; 456 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "dlr", "switch", "prp", "hub", "ptrn"; 462 status = "disabled"; 463 464 ethernet-ports { 465 #address-cells = <1>; 466 #size-cells = <0>; 467 468 switch_port0: port@0 { 469 reg = <0>; 470 pcs-handle = <&mii_conv5>; 471 status = "disabled"; 472 }; 473 474 switch_port1: port@1 { 475 reg = <1>; 476 pcs-handle = <&mii_conv4>; 477 status = "disabled"; 478 }; 479 480 switch_port2: port@2 { 481 reg = <2>; 482 pcs-handle = <&mii_conv3>; 483 status = "disabled"; 484 }; 485 486 switch_port3: port@3 { 487 reg = <3>; 488 pcs-handle = <&mii_conv2>; 489 status = "disabled"; 490 }; 491 492 switch_port4: port@4 { 493 reg = <4>; 494 ethernet = <&gmac2>; 495 label = "cpu"; 496 phy-mode = "internal"; 497 status = "disabled"; 498 fixed-link { 499 speed = <1000>; 500 full-duplex; 501 }; 502 }; 503 }; 504 }; 505 506 gic: interrupt-controller@44101000 { 507 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 508 interrupt-controller; 509 #interrupt-cells = <3>; 510 reg = <0x44101000 0x1000>, /* Distributer */ 511 <0x44102000 0x2000>, /* CPU interface */ 512 <0x44104000 0x2000>, /* Virt interface control */ 513 <0x44106000 0x2000>; /* Virt CPU interface */ 514 interrupts = 515 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 516 }; 517 518 /* 519 * The GPIO mapping to the corresponding pins is not obvious. 520 * See the hardware documentation for details. 521 */ 522 gpio0: gpio@5000b000 { 523 compatible = "snps,dw-apb-gpio"; 524 reg = <0x5000b000 0x80>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 clocks = <&sysctrl R9A06G032_HCLK_GPIO0>; 528 clock-names = "bus"; 529 530 /* GPIO0a[0] connected to pin GPIO0 */ 531 /* GPIO0a[1..2] connected to pins GPIO3..4 */ 532 /* GPIO0a[3..4] connected to pins GPIO9..10 */ 533 /* GPIO0a[5] connected to pin GPIO12 */ 534 /* GPIO0a[6..7] connected to pins GPIO15..16 */ 535 /* GPIO0a[8..9] connected to pins GPIO21..22 */ 536 /* GPIO0a[10] connected to pin GPIO24 */ 537 /* GPIO0a[11..12] connected to pins GPIO27..28 */ 538 /* GPIO0a[13..14] connected to pins GPIO33..34 */ 539 /* GPIO0a[15] connected to pin GPIO36 */ 540 /* GPIO0a[16..17] connected to pins GPIO39..40 */ 541 /* GPIO0a[18..19] connected to pins GPIO45..46 */ 542 /* GPIO0a[20] connected to pin GPIO48 */ 543 /* GPIO0a[21..22] connected to pins GPIO51..52 */ 544 /* GPIO0a[23..24] connected to pins GPIO57..58 */ 545 /* GPIO0a[25..31] connected to pins GPIO62..68 */ 546 gpio0a: gpio-port@0 { 547 compatible = "snps,dw-apb-gpio-port"; 548 reg = <0>; 549 gpio-controller; 550 #gpio-cells = <2>; 551 snps,nr-gpios = <32>; 552 553 interrupt-controller; 554 interrupt-parent = <&gpioirqmux>; 555 interrupts = < 0 1 2 3 4 5 6 7 556 8 9 10 11 12 13 14 15 557 16 17 18 19 20 21 22 23 558 24 25 26 27 28 29 30 31>; 559 #interrupt-cells = <2>; 560 }; 561 562 /* GPIO0b[0..1] connected to pins GPIO1..2 */ 563 /* GPIO0b[2..5] connected to pins GPIO5..8 */ 564 /* GPIO0b[6] connected to pin GPIO11 */ 565 /* GPIO0b[7..8] connected to pins GPIO13..14 */ 566 /* GPIO0b[9..12] connected to pins GPIO17..20 */ 567 /* GPIO0b[13] connected to pin GPIO23 */ 568 /* GPIO0b[14..15] connected to pins GPIO25..26 */ 569 /* GPIO0b[16..19] connected to pins GPIO29..32 */ 570 /* GPIO0b[20] connected to pin GPIO35 */ 571 /* GPIO0b[21..22] connected to pins GPIO37..38 */ 572 /* GPIO0b[23..26] connected to pins GPIO41..44 */ 573 /* GPIO0b[27] connected to pin GPIO47 */ 574 /* GPIO0b[28..29] connected to pins GPIO49..50 */ 575 /* GPIO0b[30..31] connected to pins GPIO53..54 */ 576 gpio0b: gpio-port@1 { 577 compatible = "snps,dw-apb-gpio-port"; 578 reg = <1>; 579 gpio-controller; 580 #gpio-cells = <2>; 581 snps,nr-gpios = <32>; 582 }; 583 }; 584 585 gpio1: gpio@5000c000 { 586 compatible = "snps,dw-apb-gpio"; 587 reg = <0x5000c000 0x80>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 clocks = <&sysctrl R9A06G032_HCLK_GPIO1>; 591 clock-names = "bus"; 592 593 /* GPIO1a[0..4] connected to pins GPIO69..73 */ 594 /* GPIO1a[5..31] connected to pins GPIO95..121 */ 595 gpio1a: gpio-port@0 { 596 compatible = "snps,dw-apb-gpio-port"; 597 reg = <0>; 598 gpio-controller; 599 #gpio-cells = <2>; 600 snps,nr-gpios = <32>; 601 602 interrupt-controller; 603 interrupt-parent = <&gpioirqmux>; 604 interrupts = <32 33 34 35 36 37 38 39 605 40 41 42 43 44 45 46 47 606 48 49 50 51 52 53 54 55 607 56 57 58 59 60 61 62 63>; 608 #interrupt-cells = <2>; 609 }; 610 611 /* GPIO1b[0..1] connected to pins GPIO55..56 */ 612 /* GPIO1b[2..4] connected to pins GPIO59..61 */ 613 /* GPIO1b[5..25] connected to pins GPIO74..94 */ 614 /* GPIO1b[26..31] connected to pins GPIO150..155 */ 615 gpio1b: gpio-port@1 { 616 compatible = "snps,dw-apb-gpio-port"; 617 reg = <1>; 618 gpio-controller; 619 #gpio-cells = <2>; 620 snps,nr-gpios = <32>; 621 }; 622 }; 623 624 gpio2: gpio@5000d000 { 625 compatible = "snps,dw-apb-gpio"; 626 reg = <0x5000d000 0x80>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 clocks = <&sysctrl R9A06G032_HCLK_GPIO2>; 630 clock-names = "bus"; 631 632 /* GPIO2a[0..27] connected to pins GPIO122..149 */ 633 /* GPIO2a[28..31] connected to pins GPIO156..159 */ 634 gpio2a: gpio-port@0 { 635 compatible = "snps,dw-apb-gpio-port"; 636 reg = <0>; 637 gpio-controller; 638 #gpio-cells = <2>; 639 snps,nr-gpios = <32>; 640 641 interrupt-controller; 642 interrupt-parent = <&gpioirqmux>; 643 interrupts = <64 65 66 67 68 69 70 71 644 72 73 74 75 76 77 78 79 645 80 81 82 83 84 85 86 87 646 88 89 90 91 92 93 94 95>; 647 #interrupt-cells = <2>; 648 }; 649 650 /* GPIO2b[0..9] connected to pins GPIO160..169 */ 651 gpio2b: gpio-port@1 { 652 compatible = "snps,dw-apb-gpio-port"; 653 reg = <1>; 654 gpio-controller; 655 #gpio-cells = <2>; 656 snps,nr-gpios = <10>; 657 }; 658 }; 659 660 gpioirqmux: interrupt-controller@51000480 { 661 compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; 662 reg = <0x51000480 0x20>; 663 #interrupt-cells = <1>; 664 #address-cells = <0>; 665 interrupt-map-mask = <0x7f>; 666 667 /* 668 * Example mapping entry. Board DTs need to overwrite 669 * 'interrupt-map' with their specific mapping. Check 670 * the irqmux binding documentation for details. 671 */ 672 interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 673 674 status = "disabled"; 675 }; 676 677 can0: can@52104000 { 678 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 679 reg = <0x52104000 0x800>; 680 reg-io-width = <4>; 681 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&sysctrl R9A06G032_HCLK_CAN0>; 683 power-domains = <&sysctrl>; 684 status = "disabled"; 685 }; 686 687 can1: can@52105000 { 688 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 689 reg = <0x52105000 0x800>; 690 reg-io-width = <4>; 691 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&sysctrl R9A06G032_HCLK_CAN1>; 693 power-domains = <&sysctrl>; 694 status = "disabled"; 695 }; 696 }; 697 698 timer { 699 compatible = "arm,armv7-timer"; 700 arm,cpu-registers-not-fw-configured; 701 always-on; 702 interrupts = 703 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 704 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 705 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 706 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 707 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 708 }; 709 710 usbphy: usb-phy { 711 #phy-cells = <0>; 712 compatible = "usb-nop-xceiv"; 713 status = "disabled"; 714 }; 715}; 716