1/* 2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "../armv7-m.dtsi" 44#include <dt-bindings/clock/stm32fx-clock.h> 45#include <dt-bindings/mfd/stm32f7-rcc.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47 48/ { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 52 clocks { 53 clk_hse: clk-hse { 54 #clock-cells = <0>; 55 compatible = "fixed-clock"; 56 clock-frequency = <0>; 57 }; 58 59 clk-lse { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <32768>; 63 }; 64 65 clk-lsi { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <32000>; 69 }; 70 71 clk_i2s_ckin: clk-i2s-ckin { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <48000000>; 75 }; 76 }; 77 78 soc { 79 timers2: timers@40000000 { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 compatible = "st,stm32-timers"; 83 reg = <0x40000000 0x400>; 84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; 85 clock-names = "int"; 86 status = "disabled"; 87 88 pwm { 89 compatible = "st,stm32-pwm"; 90 #pwm-cells = <3>; 91 status = "disabled"; 92 }; 93 94 timer@1 { 95 compatible = "st,stm32-timer-trigger"; 96 reg = <1>; 97 status = "disabled"; 98 }; 99 }; 100 101 timers3: timers@40000400 { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 compatible = "st,stm32-timers"; 105 reg = <0x40000400 0x400>; 106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; 107 clock-names = "int"; 108 status = "disabled"; 109 110 pwm { 111 compatible = "st,stm32-pwm"; 112 #pwm-cells = <3>; 113 status = "disabled"; 114 }; 115 116 timer@2 { 117 compatible = "st,stm32-timer-trigger"; 118 reg = <2>; 119 status = "disabled"; 120 }; 121 }; 122 123 timers4: timers@40000800 { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 compatible = "st,stm32-timers"; 127 reg = <0x40000800 0x400>; 128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; 129 clock-names = "int"; 130 status = "disabled"; 131 132 pwm { 133 compatible = "st,stm32-pwm"; 134 #pwm-cells = <3>; 135 status = "disabled"; 136 }; 137 138 timer@3 { 139 compatible = "st,stm32-timer-trigger"; 140 reg = <3>; 141 status = "disabled"; 142 }; 143 }; 144 145 timers5: timers@40000c00 { 146 #address-cells = <1>; 147 #size-cells = <0>; 148 compatible = "st,stm32-timers"; 149 reg = <0x40000C00 0x400>; 150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; 151 clock-names = "int"; 152 status = "disabled"; 153 154 pwm { 155 compatible = "st,stm32-pwm"; 156 #pwm-cells = <3>; 157 status = "disabled"; 158 }; 159 160 timer@4 { 161 compatible = "st,stm32-timer-trigger"; 162 reg = <4>; 163 status = "disabled"; 164 }; 165 }; 166 167 timers6: timers@40001000 { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "st,stm32-timers"; 171 reg = <0x40001000 0x400>; 172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; 173 clock-names = "int"; 174 status = "disabled"; 175 176 timer@5 { 177 compatible = "st,stm32-timer-trigger"; 178 reg = <5>; 179 status = "disabled"; 180 }; 181 }; 182 183 timers7: timers@40001400 { 184 #address-cells = <1>; 185 #size-cells = <0>; 186 compatible = "st,stm32-timers"; 187 reg = <0x40001400 0x400>; 188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; 189 clock-names = "int"; 190 status = "disabled"; 191 192 timer@6 { 193 compatible = "st,stm32-timer-trigger"; 194 reg = <6>; 195 status = "disabled"; 196 }; 197 }; 198 199 timers12: timers@40001800 { 200 #address-cells = <1>; 201 #size-cells = <0>; 202 compatible = "st,stm32-timers"; 203 reg = <0x40001800 0x400>; 204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>; 205 clock-names = "int"; 206 status = "disabled"; 207 208 pwm { 209 compatible = "st,stm32-pwm"; 210 #pwm-cells = <3>; 211 status = "disabled"; 212 }; 213 214 timer@11 { 215 compatible = "st,stm32-timer-trigger"; 216 reg = <11>; 217 status = "disabled"; 218 }; 219 }; 220 221 timers13: timers@40001c00 { 222 compatible = "st,stm32-timers"; 223 reg = <0x40001C00 0x400>; 224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; 225 clock-names = "int"; 226 status = "disabled"; 227 228 pwm { 229 compatible = "st,stm32-pwm"; 230 #pwm-cells = <3>; 231 status = "disabled"; 232 }; 233 }; 234 235 timers14: timers@40002000 { 236 compatible = "st,stm32-timers"; 237 reg = <0x40002000 0x400>; 238 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; 239 clock-names = "int"; 240 status = "disabled"; 241 242 pwm { 243 compatible = "st,stm32-pwm"; 244 #pwm-cells = <3>; 245 status = "disabled"; 246 }; 247 }; 248 249 lptimer1: timer@40002400 { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 compatible = "st,stm32-lptimer"; 253 reg = <0x40002400 0x400>; 254 interrupts-extended = <&exti 23 IRQ_TYPE_EDGE_RISING>; 255 clocks = <&rcc 1 CLK_LPTIMER>; 256 clock-names = "mux"; 257 status = "disabled"; 258 259 pwm { 260 compatible = "st,stm32-pwm-lp"; 261 #pwm-cells = <3>; 262 status = "disabled"; 263 }; 264 265 trigger@0 { 266 compatible = "st,stm32-lptimer-trigger"; 267 reg = <0>; 268 status = "disabled"; 269 }; 270 271 counter { 272 compatible = "st,stm32-lptimer-counter"; 273 status = "disabled"; 274 }; 275 276 timer { 277 compatible = "st,stm32-lptimer-timer"; 278 status = "disabled"; 279 }; 280 }; 281 282 rtc: rtc@40002800 { 283 compatible = "st,stm32-rtc"; 284 reg = <0x40002800 0x400>; 285 clocks = <&rcc 1 CLK_RTC>; 286 assigned-clocks = <&rcc 1 CLK_RTC>; 287 assigned-clock-parents = <&rcc 1 CLK_LSE>; 288 interrupt-parent = <&exti>; 289 interrupts = <17 1>; 290 st,syscfg = <&pwrcfg 0x00 0x100>; 291 status = "disabled"; 292 }; 293 294 spi2: spi@40003800 { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 compatible = "st,stm32f7-spi"; 298 reg = <0x40003800 0x400>; 299 interrupts = <36>; 300 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI2)>; 301 status = "disabled"; 302 }; 303 304 spi3: spi@40003c00 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "st,stm32f7-spi"; 308 reg = <0x40003c00 0x400>; 309 interrupts = <51>; 310 clocks = <&rcc 0 STM32F7_APB1_CLOCK(SPI3)>; 311 status = "disabled"; 312 }; 313 314 usart2: serial@40004400 { 315 compatible = "st,stm32f7-uart"; 316 reg = <0x40004400 0x400>; 317 interrupts = <38>; 318 clocks = <&rcc 1 CLK_USART2>; 319 status = "disabled"; 320 }; 321 322 usart3: serial@40004800 { 323 compatible = "st,stm32f7-uart"; 324 reg = <0x40004800 0x400>; 325 interrupts = <39>; 326 clocks = <&rcc 1 CLK_USART3>; 327 status = "disabled"; 328 }; 329 330 usart4: serial@40004c00 { 331 compatible = "st,stm32f7-uart"; 332 reg = <0x40004c00 0x400>; 333 interrupts = <52>; 334 clocks = <&rcc 1 CLK_UART4>; 335 status = "disabled"; 336 }; 337 338 usart5: serial@40005000 { 339 compatible = "st,stm32f7-uart"; 340 reg = <0x40005000 0x400>; 341 interrupts = <53>; 342 clocks = <&rcc 1 CLK_UART5>; 343 status = "disabled"; 344 }; 345 346 i2c1: i2c@40005400 { 347 compatible = "st,stm32f7-i2c"; 348 reg = <0x40005400 0x400>; 349 interrupts = <31>, 350 <32>; 351 resets = <&rcc STM32F7_APB1_RESET(I2C1)>; 352 clocks = <&rcc 1 CLK_I2C1>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 }; 357 358 i2c2: i2c@40005800 { 359 compatible = "st,stm32f7-i2c"; 360 reg = <0x40005800 0x400>; 361 interrupts = <33>, 362 <34>; 363 resets = <&rcc STM32F7_APB1_RESET(I2C2)>; 364 clocks = <&rcc 1 CLK_I2C2>; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 status = "disabled"; 368 }; 369 370 i2c3: i2c@40005c00 { 371 compatible = "st,stm32f7-i2c"; 372 reg = <0x40005c00 0x400>; 373 interrupts = <72>, 374 <73>; 375 resets = <&rcc STM32F7_APB1_RESET(I2C3)>; 376 clocks = <&rcc 1 CLK_I2C3>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 status = "disabled"; 380 }; 381 382 i2c4: i2c@40006000 { 383 compatible = "st,stm32f7-i2c"; 384 reg = <0x40006000 0x400>; 385 interrupts = <95>, 386 <96>; 387 resets = <&rcc STM32F7_APB1_RESET(I2C4)>; 388 clocks = <&rcc 1 CLK_I2C4>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 status = "disabled"; 392 }; 393 394 can1: can@40006400 { 395 compatible = "st,stm32f4-bxcan"; 396 reg = <0x40006400 0x200>; 397 interrupts = <19>, <20>, <21>, <22>; 398 interrupt-names = "tx", "rx0", "rx1", "sce"; 399 resets = <&rcc STM32F7_APB1_RESET(CAN1)>; 400 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 401 st,can-primary; 402 st,gcan = <&gcan1>; 403 status = "disabled"; 404 }; 405 406 gcan1: gcan@40006600 { 407 compatible = "st,stm32f4-gcan", "syscon"; 408 reg = <0x40006600 0x200>; 409 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; 410 }; 411 412 can2: can@40006800 { 413 compatible = "st,stm32f4-bxcan"; 414 reg = <0x40006800 0x200>; 415 interrupts = <63>, <64>, <65>, <66>; 416 interrupt-names = "tx", "rx0", "rx1", "sce"; 417 resets = <&rcc STM32F7_APB1_RESET(CAN2)>; 418 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; 419 st,can-secondary; 420 st,gcan = <&gcan1>; 421 status = "disabled"; 422 }; 423 424 cec: cec@40006c00 { 425 compatible = "st,stm32-cec"; 426 reg = <0x40006C00 0x400>; 427 interrupts = <94>; 428 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>; 429 clock-names = "cec", "hdmi-cec"; 430 status = "disabled"; 431 }; 432 433 usart7: serial@40007800 { 434 compatible = "st,stm32f7-uart"; 435 reg = <0x40007800 0x400>; 436 interrupts = <82>; 437 clocks = <&rcc 1 CLK_UART7>; 438 status = "disabled"; 439 }; 440 441 usart8: serial@40007c00 { 442 compatible = "st,stm32f7-uart"; 443 reg = <0x40007c00 0x400>; 444 interrupts = <83>; 445 clocks = <&rcc 1 CLK_UART8>; 446 status = "disabled"; 447 }; 448 449 timers1: timers@40010000 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "st,stm32-timers"; 453 reg = <0x40010000 0x400>; 454 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>; 455 clock-names = "int"; 456 status = "disabled"; 457 458 pwm { 459 compatible = "st,stm32-pwm"; 460 #pwm-cells = <3>; 461 status = "disabled"; 462 }; 463 464 timer@0 { 465 compatible = "st,stm32-timer-trigger"; 466 reg = <0>; 467 status = "disabled"; 468 }; 469 }; 470 471 timers8: timers@40010400 { 472 #address-cells = <1>; 473 #size-cells = <0>; 474 compatible = "st,stm32-timers"; 475 reg = <0x40010400 0x400>; 476 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>; 477 clock-names = "int"; 478 status = "disabled"; 479 480 pwm { 481 compatible = "st,stm32-pwm"; 482 #pwm-cells = <3>; 483 status = "disabled"; 484 }; 485 486 timer@7 { 487 compatible = "st,stm32-timer-trigger"; 488 reg = <7>; 489 status = "disabled"; 490 }; 491 }; 492 493 usart1: serial@40011000 { 494 compatible = "st,stm32f7-uart"; 495 reg = <0x40011000 0x400>; 496 interrupts = <37>; 497 clocks = <&rcc 1 CLK_USART1>; 498 status = "disabled"; 499 }; 500 501 usart6: serial@40011400 { 502 compatible = "st,stm32f7-uart"; 503 reg = <0x40011400 0x400>; 504 interrupts = <71>; 505 clocks = <&rcc 1 CLK_USART6>; 506 status = "disabled"; 507 }; 508 509 sdio2: mmc@40011c00 { 510 compatible = "arm,pl180", "arm,primecell"; 511 arm,primecell-periphid = <0x00880180>; 512 reg = <0x40011c00 0x400>; 513 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>; 514 clock-names = "apb_pclk"; 515 interrupts = <103>; 516 max-frequency = <48000000>; 517 status = "disabled"; 518 }; 519 520 sdio1: mmc@40012c00 { 521 compatible = "arm,pl180", "arm,primecell"; 522 arm,primecell-periphid = <0x00880180>; 523 reg = <0x40012c00 0x400>; 524 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>; 525 clock-names = "apb_pclk"; 526 interrupts = <49>; 527 max-frequency = <48000000>; 528 status = "disabled"; 529 }; 530 531 spi1: spi@40013000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "st,stm32f7-spi"; 535 reg = <0x40013000 0x400>; 536 interrupts = <35>; 537 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI1)>; 538 status = "disabled"; 539 }; 540 541 spi4: spi@40013400 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 compatible = "st,stm32f7-spi"; 545 reg = <0x40013400 0x400>; 546 interrupts = <84>; 547 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI4)>; 548 status = "disabled"; 549 }; 550 551 syscfg: syscon@40013800 { 552 compatible = "st,stm32-syscfg", "syscon"; 553 reg = <0x40013800 0x400>; 554 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SYSCFG)>; 555 }; 556 557 exti: interrupt-controller@40013c00 { 558 compatible = "st,stm32-exti"; 559 interrupt-controller; 560 #interrupt-cells = <2>; 561 reg = <0x40013C00 0x400>; 562 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>; 563 }; 564 565 timers9: timers@40014000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "st,stm32-timers"; 569 reg = <0x40014000 0x400>; 570 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>; 571 clock-names = "int"; 572 status = "disabled"; 573 574 pwm { 575 compatible = "st,stm32-pwm"; 576 #pwm-cells = <3>; 577 status = "disabled"; 578 }; 579 580 timer@8 { 581 compatible = "st,stm32-timer-trigger"; 582 reg = <8>; 583 status = "disabled"; 584 }; 585 }; 586 587 timers10: timers@40014400 { 588 compatible = "st,stm32-timers"; 589 reg = <0x40014400 0x400>; 590 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; 591 clock-names = "int"; 592 status = "disabled"; 593 594 pwm { 595 compatible = "st,stm32-pwm"; 596 #pwm-cells = <3>; 597 status = "disabled"; 598 }; 599 }; 600 601 timers11: timers@40014800 { 602 compatible = "st,stm32-timers"; 603 reg = <0x40014800 0x400>; 604 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; 605 clock-names = "int"; 606 status = "disabled"; 607 608 pwm { 609 compatible = "st,stm32-pwm"; 610 #pwm-cells = <3>; 611 status = "disabled"; 612 }; 613 }; 614 615 spi5: spi@40015000 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 compatible = "st,stm32f7-spi"; 619 reg = <0x40015000 0x400>; 620 interrupts = <85>; 621 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI5)>; 622 status = "disabled"; 623 }; 624 625 spi6: spi@40015400 { 626 #address-cells = <1>; 627 #size-cells = <0>; 628 compatible = "st,stm32f7-spi"; 629 reg = <0x40015400 0x400>; 630 interrupts = <86>; 631 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SPI6)>; 632 status = "disabled"; 633 }; 634 635 ltdc: display-controller@40016800 { 636 compatible = "st,stm32-ltdc"; 637 reg = <0x40016800 0x200>; 638 interrupts = <88>, <89>; 639 resets = <&rcc STM32F7_APB2_RESET(LTDC)>; 640 clocks = <&rcc 1 CLK_LCD>; 641 clock-names = "lcd"; 642 status = "disabled"; 643 }; 644 645 pwrcfg: power-config@40007000 { 646 compatible = "st,stm32-power-config", "syscon"; 647 reg = <0x40007000 0x400>; 648 }; 649 650 crc: crc@40023000 { 651 compatible = "st,stm32f7-crc"; 652 reg = <0x40023000 0x400>; 653 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; 654 status = "disabled"; 655 }; 656 657 rcc: rcc@40023800 { 658 #reset-cells = <1>; 659 #clock-cells = <2>; 660 compatible = "st,stm32f746-rcc", "st,stm32-rcc"; 661 reg = <0x40023800 0x400>; 662 clocks = <&clk_hse>, <&clk_i2s_ckin>; 663 st,syscfg = <&pwrcfg>; 664 assigned-clocks = <&rcc 1 CLK_HSE_RTC>; 665 assigned-clock-rates = <1000000>; 666 }; 667 668 dma1: dma-controller@40026000 { 669 compatible = "st,stm32-dma"; 670 reg = <0x40026000 0x400>; 671 interrupts = <11>, 672 <12>, 673 <13>, 674 <14>, 675 <15>, 676 <16>, 677 <17>, 678 <47>; 679 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>; 680 #dma-cells = <4>; 681 status = "disabled"; 682 }; 683 684 dma2: dma-controller@40026400 { 685 compatible = "st,stm32-dma"; 686 reg = <0x40026400 0x400>; 687 interrupts = <56>, 688 <57>, 689 <58>, 690 <59>, 691 <60>, 692 <68>, 693 <69>, 694 <70>; 695 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>; 696 #dma-cells = <4>; 697 st,mem2mem; 698 status = "disabled"; 699 }; 700 701 usbotg_hs: usb@40040000 { 702 compatible = "st,stm32f7-hsotg"; 703 reg = <0x40040000 0x40000>; 704 interrupts = <77>; 705 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>; 706 clock-names = "otg"; 707 g-rx-fifo-size = <256>; 708 g-np-tx-fifo-size = <32>; 709 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 710 status = "disabled"; 711 }; 712 713 usbotg_fs: usb@50000000 { 714 compatible = "st,stm32f4x9-fsotg"; 715 reg = <0x50000000 0x40000>; 716 interrupts = <67>; 717 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>; 718 clock-names = "otg"; 719 status = "disabled"; 720 }; 721 }; 722}; 723 724&systick { 725 clocks = <&rcc 1 0>; 726 status = "okay"; 727}; 728