1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn35_clk_mgr.h"
28
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37
38
39 #include "reg_helper.h"
40 #include "core_types.h"
41 #include "dcn35_smu.h"
42 #include "dm_helpers.h"
43
44 #include "dcn31/dcn31_clk_mgr.h"
45
46 #include "dc_dmub_srv.h"
47 #include "link.h"
48 #include "logger_types.h"
49
50 #undef DC_LOGGER
51 #define DC_LOGGER \
52 clk_mgr->base.base.ctx->logger
53
54 #define DCN_BASE__INST0_SEG1 0x000000C0
55 #define mmCLK1_CLK_PLL_REQ 0x16E37
56
57 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
58 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
59 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
60 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
61 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
62 #define mmCLK1_CLK5_DFS_CNTL 0x16E78
63
64 #define mmCLK1_CLK0_CURRENT_CNT 0x16EFB
65 #define mmCLK1_CLK1_CURRENT_CNT 0x16EFC
66 #define mmCLK1_CLK2_CURRENT_CNT 0x16EFD
67 #define mmCLK1_CLK3_CURRENT_CNT 0x16EFE
68 #define mmCLK1_CLK4_CURRENT_CNT 0x16EFF
69 #define mmCLK1_CLK5_CURRENT_CNT 0x16F00
70
71 #define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A
72 #define mmCLK1_CLK1_BYPASS_CNTL 0x16E93
73 #define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C
74 #define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5
75 #define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE
76 #define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7
77
78 #define mmCLK1_CLK0_DS_CNTL 0x16E83
79 #define mmCLK1_CLK1_DS_CNTL 0x16E8C
80 #define mmCLK1_CLK2_DS_CNTL 0x16E95
81 #define mmCLK1_CLK3_DS_CNTL 0x16E9E
82 #define mmCLK1_CLK4_DS_CNTL 0x16EA7
83 #define mmCLK1_CLK5_DS_CNTL 0x16EB0
84
85 #define mmCLK1_CLK0_ALLOW_DS 0x16E84
86 #define mmCLK1_CLK1_ALLOW_DS 0x16E8D
87 #define mmCLK1_CLK2_ALLOW_DS 0x16E96
88 #define mmCLK1_CLK3_ALLOW_DS 0x16E9F
89 #define mmCLK1_CLK4_ALLOW_DS 0x16EA8
90 #define mmCLK1_CLK5_ALLOW_DS 0x16EB1
91
92 #define mmCLK5_spll_field_8 0x1B24B
93 #define mmCLK6_spll_field_8 0x1B24B
94 #define mmDENTIST_DISPCLK_CNTL 0x0124
95 #define regDENTIST_DISPCLK_CNTL 0x0064
96 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
97
98 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
99 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
100 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
101 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
102 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
103 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
104
105 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
106 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
107 // DENTIST_DISPCLK_CNTL
108 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
109 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
110 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
111 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
112 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
113 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
114 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
115 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
116 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L
117 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L
118
119 #define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L
120 #define CLK6_spll_field_8__spll_ssc_en_MASK 0x00002000L
121
122 #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0
123 #undef FN
124 #define FN(reg_name, field_name) \
125 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
126
127 #define REG(reg) \
128 (clk_mgr->regs->reg)
129
130 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
131
132 #define BASE(seg) BASE_INNER(seg)
133
134 #define SR(reg_name)\
135 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 reg ## reg_name
137
138 #define CLK_SR_DCN35(reg_name)\
139 .reg_name = mm ## reg_name
140
141 static const struct clk_mgr_registers clk_mgr_regs_dcn35 = {
142 CLK_REG_LIST_DCN35()
143 };
144
145 static const struct clk_mgr_shift clk_mgr_shift_dcn35 = {
146 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
147 };
148
149 static const struct clk_mgr_mask clk_mgr_mask_dcn35 = {
150 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
151 };
152
153 #define TO_CLK_MGR_DCN35(clk_mgr)\
154 container_of(clk_mgr, struct clk_mgr_dcn35, base)
155
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)156 static int dcn35_get_active_display_cnt_wa(
157 struct dc *dc,
158 struct dc_state *context,
159 int *all_active_disps)
160 {
161 int i, display_count = 0;
162 bool tmds_present = false;
163
164 for (i = 0; i < context->stream_count; i++) {
165 const struct dc_stream_state *stream = context->streams[i];
166
167 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
168 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
169 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
170 tmds_present = true;
171 }
172
173 for (i = 0; i < dc->link_count; i++) {
174 const struct dc_link *link = dc->links[i];
175
176 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
177 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
178 link->link_enc->funcs->is_dig_enabled(link->link_enc))
179 display_count++;
180 }
181 if (all_active_disps != NULL)
182 *all_active_disps = display_count;
183 /* WA for hang on HDMI after display off back on*/
184 if (display_count == 0 && tmds_present)
185 display_count = 1;
186
187 return display_count;
188 }
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)189 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
190 bool safe_to_lower, bool disable)
191 {
192 struct dc *dc = clk_mgr_base->ctx->dc;
193 int i;
194
195 if (dc->ctx->dce_environment == DCE_ENV_DIAG)
196 return;
197
198 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
199 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
200 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
201 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
202 struct dccg *dccg = clk_mgr_internal->dccg;
203 struct pipe_ctx *pipe = safe_to_lower
204 ? &context->res_ctx.pipe_ctx[i]
205 : &dc->current_state->res_ctx.pipe_ctx[i];
206 struct link_encoder *new_pipe_link_enc = new_pipe->link_res.dio_link_enc;
207 struct link_encoder *pipe_link_enc = pipe->link_res.dio_link_enc;
208 bool stream_changed_otg_dig_on = false;
209 bool has_active_hpo = false;
210
211 if (pipe->top_pipe || pipe->prev_odm_pipe)
212 continue;
213
214 if (!dc->config.unify_link_enc_assignment) {
215 if (new_pipe->stream)
216 new_pipe_link_enc = new_pipe->stream->link_enc;
217 if (pipe->stream)
218 pipe_link_enc = pipe->stream->link_enc;
219 }
220
221 stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
222 old_pipe->stream != new_pipe->stream &&
223 old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
224 new_pipe_link_enc && !new_pipe->stream->dpms_off &&
225 new_pipe_link_enc->funcs->is_dig_enabled &&
226 new_pipe_link_enc->funcs->is_dig_enabled(
227 new_pipe_link_enc) &&
228 new_pipe->stream_res.stream_enc &&
229 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
230 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
231
232 if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
233 has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
234 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
235
236 }
237
238 if (!has_active_hpo && !stream_changed_otg_dig_on && pipe->stream &&
239 (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || !pipe_link_enc) &&
240 !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {
241 /* This w/a should not trigger when we have a dig active */
242 if (disable) {
243 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
244 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
245
246 reset_sync_context_for_pipe(dc, context, i);
247 } else {
248 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
249 }
250 }
251 }
252 }
253
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)254 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
255 struct dc_state *context,
256 int ref_dtbclk_khz)
257 {
258 struct dccg *dccg = clk_mgr->dccg;
259 uint32_t tg_mask = 0;
260 int i;
261
262 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
263 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
264 struct dtbclk_dto_params dto_params = {0};
265
266 /* use mask to program DTO once per tg */
267 if (pipe_ctx->stream_res.tg &&
268 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
269 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
270
271 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
272 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
273
274 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
275 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
276 }
277 }
278 }
279
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)280 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
281 struct dc_state *context, bool safe_to_lower)
282 {
283 int i;
284 bool dppclk_active[MAX_PIPES] = {0};
285
286
287 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
288 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
289 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
290
291 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
292
293 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
294 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
295 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
296 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
297 * In this case just continue in loop
298 */
299 continue;
300 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
301 /* The software state is not valid if dpp resource is NULL and
302 * dppclk_khz > 0.
303 */
304 ASSERT(false);
305 continue;
306 }
307
308 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
309
310 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
311 clk_mgr->dccg->funcs->update_dpp_dto(
312 clk_mgr->dccg, dpp_inst, dppclk_khz);
313 dppclk_active[dpp_inst] = true;
314 }
315 if (safe_to_lower)
316 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
317 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
318
319 if (old_dpp && !dppclk_active[old_dpp->inst])
320 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
321 }
322 }
323
get_lowest_dpia_index(const struct dc_link * link)324 static uint8_t get_lowest_dpia_index(const struct dc_link *link)
325 {
326 const struct dc *dc_struct = link->dc;
327 uint8_t idx = 0xFF;
328 int i;
329
330 for (i = 0; i < MAX_PIPES * 2; ++i) {
331 if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
332 continue;
333
334 if (idx > dc_struct->links[i]->link_index)
335 idx = dc_struct->links[i]->link_index;
336 }
337
338 return idx;
339 }
340
dcn35_notify_host_router_bw(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)341 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,
342 bool safe_to_lower)
343 {
344 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
345 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
346 uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
347 int i;
348 for (i = 0; i < context->stream_count; ++i) {
349 const struct dc_stream_state *stream = context->streams[i];
350 const struct dc_link *link = stream->link;
351 uint8_t lowest_dpia_index = 0;
352 unsigned int hr_index = 0;
353
354 if (!link)
355 continue;
356
357 lowest_dpia_index = get_lowest_dpia_index(link);
358 if (link->link_index < lowest_dpia_index)
359 continue;
360
361 hr_index = (link->link_index - lowest_dpia_index) / 2;
362 if (hr_index >= MAX_HOST_ROUTERS_NUM)
363 continue;
364 host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
365 &stream->timing, dc_link_get_highest_encoding_format(link));
366 }
367
368 for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
369 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
370 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) {
371 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i];
372 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);
373 }
374 }
375 }
376
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)377 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
378 struct dc_state *context,
379 bool safe_to_lower)
380 {
381 union dmub_rb_cmd cmd;
382 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
383 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
384 struct dc *dc = clk_mgr_base->ctx->dc;
385 int display_count = 0;
386 bool update_dppclk = false;
387 bool update_dispclk = false;
388 bool dpp_clock_lowered = false;
389 int all_active_disps = 0;
390
391 if (dc->work_arounds.skip_clock_update)
392 return;
393
394 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
395 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
396 new_clocks->ref_dtbclk_khz = 600000;
397
398 /*
399 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
400 * also if safe to lower is false, we just go in the higher state
401 */
402 if (safe_to_lower) {
403 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
404 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
405 dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
406 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
407 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
408 }
409
410 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
411 if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
412 dcn35_smu_set_dtbclk(clk_mgr, false);
413
414 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
415 }
416 /* check that we're not already in lower */
417 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
418 /* if we can go lower, go lower */
419 if (display_count == 0)
420 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
421 }
422 } else {
423 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
424 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
425 dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
426 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
427 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
428 }
429
430 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
431 int actual_dtbclk = 0;
432
433 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
434 dcn35_smu_set_dtbclk(clk_mgr, true);
435
436 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);
437
438 if (actual_dtbclk) {
439 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
440 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
441 }
442 }
443
444 /* check that we're not already in D0 */
445 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
446 union display_idle_optimization_u idle_info = { 0 };
447
448 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
449 /* update power state */
450 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
451 }
452 }
453 if (dc->debug.force_min_dcfclk_mhz > 0)
454 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
455 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
456
457 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
458 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
459 dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
460 }
461
462 if (should_set_clock(safe_to_lower,
463 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
464 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
465 dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
466 }
467
468 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
469 if (new_clocks->dppclk_khz < 100000)
470 new_clocks->dppclk_khz = 100000;
471
472 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
473 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
474 dpp_clock_lowered = true;
475 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
476 update_dppclk = true;
477 }
478
479 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
480 (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
481 int requested_dispclk_khz = new_clocks->dispclk_khz;
482
483 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
484
485 /* Clamp the requested clock to PMFW based on their limit. */
486 if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
487 requested_dispclk_khz = dc->debug.min_disp_clk_khz;
488
489 dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
490 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
491
492 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
493
494 update_dispclk = true;
495 }
496
497 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
498 if (!dc->debug.disable_dtb_ref_clk_switch &&
499 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
500 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
501 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
502 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
503 }
504
505 if (dpp_clock_lowered) {
506 // increase per DPP DTO before lowering global dppclk
507 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
508 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
509 } else {
510 // increase global DPPCLK before lowering per DPP DTO
511 if (update_dppclk || update_dispclk)
512 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
513 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
514 }
515
516 // notify PMFW of bandwidth per DPIA tunnel
517 if (dc->debug.notify_dpia_hr_bw)
518 dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);
519
520 // notify DMCUB of latest clocks
521 memset(&cmd, 0, sizeof(cmd));
522 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
523 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
524 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
525 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
526 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
527 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
528 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
529
530 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
531 }
532
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)533 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
534 {
535 /* get FbMult value */
536 struct fixed31_32 pll_req;
537 unsigned int fbmult_frac_val = 0;
538 unsigned int fbmult_int_val = 0;
539
540 /*
541 * Register value of fbmult is in 8.16 format, we are converting to 314.32
542 * to leverage the fix point operations available in driver
543 */
544
545 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
546 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
547
548 pll_req = dc_fixpt_from_int(fbmult_int_val);
549
550 /*
551 * since fractional part is only 16 bit in register definition but is 32 bit
552 * in our fix point definiton, need to shift left by 16 to obtain correct value
553 */
554 pll_req.value |= fbmult_frac_val << 16;
555
556 /* multiply by REFCLK period */
557 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
558
559 /* integer part is now VCO frequency in kHz */
560 return dc_fixpt_floor(pll_req);
561 }
562
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)563 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
564 {
565 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
566
567 dcn35_smu_enable_pme_wa(clk_mgr);
568 }
569
570
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)571 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
572 struct dc_clocks *b)
573 {
574 if (a->dispclk_khz != b->dispclk_khz)
575 return false;
576 else if (a->dppclk_khz != b->dppclk_khz)
577 return false;
578 else if (a->dcfclk_khz != b->dcfclk_khz)
579 return false;
580 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
581 return false;
582 else if (a->zstate_support != b->zstate_support)
583 return false;
584 else if (a->dtbclk_en != b->dtbclk_en)
585 return false;
586
587 return true;
588 }
589
dcn35_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)590 static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
591 struct clk_mgr_dcn35 *clk_mgr)
592 {
593 }
594
dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)595 static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
596 {
597 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
598
599 uint32_t ssc_enable;
600
601 if (clk_mgr_base->ctx->dce_version == DCN_VERSION_3_51) {
602 ssc_enable = REG_READ(CLK6_spll_field_8) & CLK6_spll_field_8__spll_ssc_en_MASK;
603 } else {
604 ssc_enable = REG_READ(CLK5_spll_field_8) & CLK5_spll_field_8__spll_ssc_en_MASK;
605 }
606
607 return ssc_enable != 0;
608 }
609
init_clk_states(struct clk_mgr * clk_mgr)610 static void init_clk_states(struct clk_mgr *clk_mgr)
611 {
612 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
613
614 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
615
616 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
617 clk_mgr->clks.p_state_change_support = true;
618 clk_mgr->clks.prev_p_state_change_support = true;
619 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
620 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
621 }
622
dcn35_init_clocks(struct clk_mgr * clk_mgr)623 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
624 {
625 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
626
627 init_clk_states(clk_mgr);
628
629 // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
630 if (dcn35_is_spll_ssc_enabled(clk_mgr))
631 clk_mgr->dp_dto_source_clock_in_khz =
632 dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
633 else
634 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
635
636 }
637 static struct clk_bw_params dcn35_bw_params = {
638 .vram_type = Ddr4MemType,
639 .num_channels = 1,
640 .clk_table = {
641 .num_entries = 4,
642 },
643
644 };
645
646 static struct wm_table ddr5_wm_table = {
647 .entries = {
648 {
649 .wm_inst = WM_A,
650 .wm_type = WM_TYPE_PSTATE_CHG,
651 .pstate_latency_us = 11.72,
652 .sr_exit_time_us = 28.0,
653 .sr_enter_plus_exit_time_us = 30.0,
654 .valid = true,
655 },
656 {
657 .wm_inst = WM_B,
658 .wm_type = WM_TYPE_PSTATE_CHG,
659 .pstate_latency_us = 11.72,
660 .sr_exit_time_us = 28.0,
661 .sr_enter_plus_exit_time_us = 30.0,
662 .valid = true,
663 },
664 {
665 .wm_inst = WM_C,
666 .wm_type = WM_TYPE_PSTATE_CHG,
667 .pstate_latency_us = 11.72,
668 .sr_exit_time_us = 28.0,
669 .sr_enter_plus_exit_time_us = 30.0,
670 .valid = true,
671 },
672 {
673 .wm_inst = WM_D,
674 .wm_type = WM_TYPE_PSTATE_CHG,
675 .pstate_latency_us = 11.72,
676 .sr_exit_time_us = 28.0,
677 .sr_enter_plus_exit_time_us = 30.0,
678 .valid = true,
679 },
680 }
681 };
682
683 static struct wm_table lpddr5_wm_table = {
684 .entries = {
685 {
686 .wm_inst = WM_A,
687 .wm_type = WM_TYPE_PSTATE_CHG,
688 .pstate_latency_us = 11.65333,
689 .sr_exit_time_us = 28.0,
690 .sr_enter_plus_exit_time_us = 30.0,
691 .valid = true,
692 },
693 {
694 .wm_inst = WM_B,
695 .wm_type = WM_TYPE_PSTATE_CHG,
696 .pstate_latency_us = 11.65333,
697 .sr_exit_time_us = 28.0,
698 .sr_enter_plus_exit_time_us = 30.0,
699 .valid = true,
700 },
701 {
702 .wm_inst = WM_C,
703 .wm_type = WM_TYPE_PSTATE_CHG,
704 .pstate_latency_us = 11.65333,
705 .sr_exit_time_us = 28.0,
706 .sr_enter_plus_exit_time_us = 30.0,
707 .valid = true,
708 },
709 {
710 .wm_inst = WM_D,
711 .wm_type = WM_TYPE_PSTATE_CHG,
712 .pstate_latency_us = 11.65333,
713 .sr_exit_time_us = 28.0,
714 .sr_enter_plus_exit_time_us = 30.0,
715 .valid = true,
716 },
717 }
718 };
719
720 static DpmClocks_t_dcn35 dummy_clocks;
721 static DpmClocks_t_dcn351 dummy_clocks_dcn351;
722
723 static struct dcn35_watermarks dummy_wms = { 0 };
724
725 static struct dcn35_ss_info_table ss_info_table = {
726 .ss_divider = 1000,
727 .ss_percentage = {0, 0, 375, 375, 375}
728 };
729
dcn35_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)730 static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
731 {
732 uint32_t clock_source = 0;
733
734 clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;
735
736 // If it's DFS mode, clock_source is 0.
737 if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
738 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
739
740 if (clk_mgr->dprefclk_ss_percentage != 0) {
741 clk_mgr->ss_on_dprefclk = true;
742 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
743 }
744 }
745 }
746
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)747 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
748 {
749 int i, num_valid_sets;
750
751 num_valid_sets = 0;
752
753 for (i = 0; i < WM_SET_COUNT; i++) {
754 /* skip empty entries, the smu array has no holes*/
755 if (!bw_params->wm_table.entries[i].valid)
756 continue;
757
758 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
759 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
760 /* We will not select WM based on fclk, so leave it as unconstrained */
761 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
762 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
763
764 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
765 if (i == 0)
766 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
767 else {
768 /* add 1 to make it non-overlapping with next lvl */
769 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
770 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
771 }
772 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
773 bw_params->clk_table.entries[i].dcfclk_mhz;
774
775 } else {
776 /* unconstrained for memory retraining */
777 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
778 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
779
780 /* Modify previous watermark range to cover up to max */
781 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
782 }
783 num_valid_sets++;
784 }
785
786 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
787
788 /* modify the min and max to make sure we cover the whole range*/
789 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
790 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
791 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
792 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
793
794 /* This is for writeback only, does not matter currently as no writeback support*/
795 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
796 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
797 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
798 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
799 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
800 }
801
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)802 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
803 {
804 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
805 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
806 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
807
808 if (!clk_mgr->smu_ver)
809 return;
810
811 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
812 return;
813
814 memset(table, 0, sizeof(*table));
815
816 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
817
818 dcn35_smu_set_dram_addr_high(clk_mgr,
819 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
820 dcn35_smu_set_dram_addr_low(clk_mgr,
821 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
822 dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
823 }
824
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)825 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
826 struct dcn35_smu_dpm_clks *smu_dpm_clks)
827 {
828 DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
829
830 if (!clk_mgr->smu_ver)
831 return;
832
833 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
834 return;
835
836 memset(table, 0, sizeof(*table));
837
838 dcn35_smu_set_dram_addr_high(clk_mgr,
839 smu_dpm_clks->mc_address.high_part);
840 dcn35_smu_set_dram_addr_low(clk_mgr,
841 smu_dpm_clks->mc_address.low_part);
842 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
843 }
844
dcn351_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn351_smu_dpm_clks * smu_dpm_clks)845 static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
846 struct dcn351_smu_dpm_clks *smu_dpm_clks)
847 {
848 DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;
849
850 if (!clk_mgr->smu_ver)
851 return;
852 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
853 return;
854 memset(table, 0, sizeof(*table));
855 dcn35_smu_set_dram_addr_high(clk_mgr,
856 smu_dpm_clks->mc_address.high_part);
857 dcn35_smu_set_dram_addr_low(clk_mgr,
858 smu_dpm_clks->mc_address.low_part);
859 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
860 }
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)861 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
862 {
863 uint32_t max = 0;
864 int i;
865
866 for (i = 0; i < num_clocks; ++i) {
867 if (clocks[i] > max)
868 max = clocks[i];
869 }
870
871 return max;
872 }
873
is_valid_clock_value(uint32_t clock_value)874 static inline bool is_valid_clock_value(uint32_t clock_value)
875 {
876 return clock_value > 1 && clock_value < 100000;
877 }
878
convert_wck_ratio(uint8_t wck_ratio)879 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
880 {
881 switch (wck_ratio) {
882 case WCK_RATIO_1_2:
883 return 2;
884
885 case WCK_RATIO_1_4:
886 return 4;
887 /* Find lowest DPM, FCLK is filled in reverse order*/
888
889 default:
890 break;
891 }
892
893 return 1;
894 }
895
calc_dram_speed_mts(const MemPstateTable_t * entry)896 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
897 {
898 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
899 }
900
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)901 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
902 struct integrated_info *bios_info,
903 DpmClocks_t_dcn35 *clock_table)
904 {
905 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
906 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
907 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
908 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
909 uint32_t num_memps, num_fclk, num_dcfclk;
910 int i;
911
912 /* Determine min/max p-state values. */
913 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
914 clock_table->NumMemPstatesEnabled;
915 for (i = 0; i < num_memps; i++) {
916 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
917
918 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
919 max_dram_speed_mts = dram_speed_mts;
920 max_pstate = i;
921 }
922 }
923
924 min_dram_speed_mts = max_dram_speed_mts;
925 min_pstate = max_pstate;
926
927 for (i = 0; i < num_memps; i++) {
928 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
929
930 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
931 min_dram_speed_mts = dram_speed_mts;
932 min_pstate = i;
933 }
934 }
935
936 /* We expect the table to contain at least one valid P-state entry. */
937 ASSERT(clock_table->NumMemPstatesEnabled &&
938 is_valid_clock_value(max_dram_speed_mts) &&
939 is_valid_clock_value(min_dram_speed_mts));
940
941 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
942 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
943 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
944 max_dispclk = find_max_clk_value(clock_table->DispClocks,
945 clock_table->NumDispClkLevelsEnabled);
946 max_dppclk = find_max_clk_value(clock_table->DppClocks,
947 clock_table->NumDispClkLevelsEnabled);
948 } else {
949 /* Invalid number of entries in the table from PMFW. */
950 ASSERT(0);
951 }
952
953 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
954 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
955
956 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
957 clock_table->NumFclkLevelsEnabled;
958 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
959
960 num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
961 clock_table->NumDcfClkLevelsEnabled;
962 for (i = 0; i < num_dcfclk; i++) {
963 int j;
964
965 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
966 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
967 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
968 break;
969
970 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
971 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
972 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
973
974 /* Now update clocks we do read */
975 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
976 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
977 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
978 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
979 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
980 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
981 bw_params->clk_table.entries[i].wck_ratio =
982 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
983
984 /* Dcfclk and Fclk are tied, but at a different ratio */
985 bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
986 }
987
988 /* Make sure to include at least one entry at highest pstate */
989 if (max_pstate != min_pstate || i == 0) {
990 if (i > MAX_NUM_DPM_LVL - 1)
991 i = MAX_NUM_DPM_LVL - 1;
992
993 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
994 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
995 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
996 bw_params->clk_table.entries[i].dcfclk_mhz =
997 find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
998 bw_params->clk_table.entries[i].socclk_mhz =
999 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
1000 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
1001 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
1002 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
1003 clock_table->MemPstateTable[max_pstate].WckRatio);
1004 i++;
1005 }
1006 bw_params->clk_table.num_entries = i--;
1007
1008 /* Make sure all highest clocks are included*/
1009 bw_params->clk_table.entries[i].socclk_mhz =
1010 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
1011 bw_params->clk_table.entries[i].dispclk_mhz =
1012 find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
1013 bw_params->clk_table.entries[i].dppclk_mhz =
1014 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
1015 bw_params->clk_table.entries[i].fclk_mhz =
1016 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
1017 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
1018 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1019 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1020 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1021 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
1022 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
1023 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
1024 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
1025 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
1026 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
1027
1028 /*
1029 * Set any 0 clocks to max default setting. Not an issue for
1030 * power since we aren't doing switching in such case anyway
1031 */
1032 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
1033 if (!bw_params->clk_table.entries[i].fclk_mhz) {
1034 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1035 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
1036 bw_params->clk_table.entries[i].voltage = def_max.voltage;
1037 }
1038 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
1039 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
1040 if (!bw_params->clk_table.entries[i].socclk_mhz)
1041 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
1042 if (!bw_params->clk_table.entries[i].dispclk_mhz)
1043 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
1044 if (!bw_params->clk_table.entries[i].dppclk_mhz)
1045 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
1046 if (!bw_params->clk_table.entries[i].fclk_mhz)
1047 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
1048 if (!bw_params->clk_table.entries[i].phyclk_mhz)
1049 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1050 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
1051 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1052 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
1053 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1054 }
1055 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
1056 bw_params->vram_type = bios_info->memory_type;
1057 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
1058 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
1059
1060 for (i = 0; i < WM_SET_COUNT; i++) {
1061 bw_params->wm_table.entries[i].wm_inst = i;
1062
1063 if (i >= bw_params->clk_table.num_entries) {
1064 bw_params->wm_table.entries[i].valid = false;
1065 continue;
1066 }
1067
1068 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
1069 bw_params->wm_table.entries[i].valid = true;
1070 }
1071 }
1072
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)1073 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
1074 {
1075 int display_count;
1076 struct dc *dc = clk_mgr_base->ctx->dc;
1077 struct dc_state *context = dc->current_state;
1078
1079 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
1080 display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
1081 /* if we can go lower, go lower */
1082 if (display_count == 0)
1083 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
1084 }
1085 }
1086
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)1087 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
1088 {
1089 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1090
1091 //SMU optimization is performed part of low power state exit.
1092 dcn35_smu_exit_low_power_state(clk_mgr);
1093
1094 }
1095
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)1096 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
1097 {
1098 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1099
1100 return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
1101 }
1102
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)1103 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
1104 {
1105 init_clk_states(clk_mgr);
1106
1107 /* TODO: Implement the functions and remove the ifndef guard */
1108 }
1109
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)1110 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
1111 struct dc_state *context,
1112 bool safe_to_lower)
1113 {
1114 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
1115 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
1116 int fclk_adj = new_clocks->fclk_khz;
1117
1118 /* TODO: remove this after correctly set by DML */
1119 new_clocks->dcfclk_khz = 400000;
1120 new_clocks->socclk_khz = 400000;
1121
1122 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
1123 //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
1124 new_clocks->fclk_khz = 4320000;
1125
1126 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
1127 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
1128 }
1129
1130 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
1131 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1132 }
1133
1134 if (should_set_clock(safe_to_lower,
1135 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
1136 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1137 }
1138
1139 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
1140 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
1141 }
1142
1143 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
1144 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
1145 }
1146
1147 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
1148 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
1149 }
1150
1151 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
1152 clk_mgr->clks.fclk_khz = fclk_adj;
1153 }
1154
1155 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
1156 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
1157 }
1158
1159 /* Both fclk and ref_dppclk run on the same scemi clock.
1160 * So take the higher value since the DPP DTO is typically programmed
1161 * such that max dppclk is 1:1 with ref_dppclk.
1162 */
1163 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
1164 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
1165 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
1166 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
1167
1168 // Both fclk and ref_dppclk run on the same scemi clock.
1169 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
1170
1171 /* TODO: set dtbclk in correct place */
1172 clk_mgr->clks.dtbclk_en = true;
1173 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
1174 dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
1175
1176 dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
1177 }
1178
1179 static struct clk_mgr_funcs dcn35_funcs = {
1180 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1181 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1182 .update_clocks = dcn35_update_clocks,
1183 .init_clocks = dcn35_init_clocks,
1184 .enable_pme_wa = dcn35_enable_pme_wa,
1185 .are_clock_states_equal = dcn35_are_clock_states_equal,
1186 .notify_wm_ranges = dcn35_notify_wm_ranges,
1187 .set_low_power_state = dcn35_set_low_power_state,
1188 .exit_low_power_state = dcn35_exit_low_power_state,
1189 .is_ips_supported = dcn35_is_ips_supported,
1190 };
1191
1192 struct clk_mgr_funcs dcn35_fpga_funcs = {
1193 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1194 .update_clocks = dcn35_update_clocks_fpga,
1195 .init_clocks = dcn35_init_clocks_fpga,
1196 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1197 };
1198
translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks * smu_dpm_clks_a,struct dcn35_smu_dpm_clks * smu_dpm_clks_b)1199 static void translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks *smu_dpm_clks_a,
1200 struct dcn35_smu_dpm_clks *smu_dpm_clks_b)
1201 {
1202 /*translate two structures and only take need clock tables*/
1203 uint8_t i;
1204
1205 if (smu_dpm_clks_a == NULL || smu_dpm_clks_b == NULL ||
1206 smu_dpm_clks_a->dpm_clks == NULL || smu_dpm_clks_b->dpm_clks == NULL)
1207 return;
1208
1209 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++)
1210 smu_dpm_clks_b->dpm_clks->DcfClocks[i] = smu_dpm_clks_a->dpm_clks->DcfClocks[i];
1211
1212 for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
1213 smu_dpm_clks_b->dpm_clks->DispClocks[i] = smu_dpm_clks_a->dpm_clks->DispClocks[i];
1214
1215 for (i = 0; i < NUM_DPPCLK_DPM_LEVELS; i++)
1216 smu_dpm_clks_b->dpm_clks->DppClocks[i] = smu_dpm_clks_a->dpm_clks->DppClocks[i];
1217
1218 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1219 smu_dpm_clks_b->dpm_clks->FclkClocks_Freq[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Freq[i];
1220 smu_dpm_clks_b->dpm_clks->FclkClocks_Voltage[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Voltage[i];
1221 }
1222 for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) {
1223 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].MemClk =
1224 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].MemClk;
1225 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].UClk =
1226 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].UClk;
1227 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].Voltage =
1228 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].Voltage;
1229 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].WckRatio =
1230 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].WckRatio;
1231 }
1232 smu_dpm_clks_b->dpm_clks->MaxGfxClk = smu_dpm_clks_a->dpm_clks->MaxGfxClk;
1233 smu_dpm_clks_b->dpm_clks->MinGfxClk = smu_dpm_clks_a->dpm_clks->MinGfxClk;
1234 smu_dpm_clks_b->dpm_clks->NumDcfClkLevelsEnabled =
1235 smu_dpm_clks_a->dpm_clks->NumDcfClkLevelsEnabled;
1236 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled =
1237 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled;
1238 smu_dpm_clks_b->dpm_clks->NumFclkLevelsEnabled =
1239 smu_dpm_clks_a->dpm_clks->NumFclkLevelsEnabled;
1240 smu_dpm_clks_b->dpm_clks->NumMemPstatesEnabled =
1241 smu_dpm_clks_a->dpm_clks->NumMemPstatesEnabled;
1242 smu_dpm_clks_b->dpm_clks->NumSocClkLevelsEnabled =
1243 smu_dpm_clks_a->dpm_clks->NumSocClkLevelsEnabled;
1244
1245 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
1246 smu_dpm_clks_b->dpm_clks->SocClocks[i] = smu_dpm_clks_a->dpm_clks->SocClocks[i];
1247 smu_dpm_clks_b->dpm_clks->SocVoltage[i] = smu_dpm_clks_a->dpm_clks->SocVoltage[i];
1248 }
1249 }
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1250 void dcn35_clk_mgr_construct(
1251 struct dc_context *ctx,
1252 struct clk_mgr_dcn35 *clk_mgr,
1253 struct pp_smu_funcs *pp_smu,
1254 struct dccg *dccg)
1255 {
1256 struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
1257 struct dcn351_smu_dpm_clks smu_dpm_clks_dcn351 = { 0 };
1258 clk_mgr->base.base.ctx = ctx;
1259 clk_mgr->base.base.funcs = &dcn35_funcs;
1260
1261 clk_mgr->base.pp_smu = pp_smu;
1262
1263 clk_mgr->base.dccg = dccg;
1264 clk_mgr->base.dfs_bypass_disp_clk = 0;
1265
1266 clk_mgr->base.dprefclk_ss_percentage = 0;
1267 clk_mgr->base.dprefclk_ss_divider = 1000;
1268 clk_mgr->base.ss_on_dprefclk = false;
1269 clk_mgr->base.dfs_ref_freq_khz = 48000;
1270 if (ctx->dce_version != DCN_VERSION_3_51) {
1271 clk_mgr->base.regs = &clk_mgr_regs_dcn35;
1272 clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn35;
1273 clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;
1274 }
1275
1276
1277 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1278 clk_mgr->base.base.ctx,
1279 DC_MEM_ALLOC_TYPE_GART,
1280 sizeof(struct dcn35_watermarks),
1281 &clk_mgr->smu_wm_set.mc_address.quad_part);
1282
1283 if (!clk_mgr->smu_wm_set.wm_set) {
1284 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1285 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1286 }
1287 ASSERT(clk_mgr->smu_wm_set.wm_set);
1288
1289 smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1290 clk_mgr->base.base.ctx,
1291 DC_MEM_ALLOC_TYPE_GART,
1292 sizeof(DpmClocks_t_dcn35),
1293 &smu_dpm_clks.mc_address.quad_part);
1294 if (smu_dpm_clks.dpm_clks == NULL) {
1295 smu_dpm_clks.dpm_clks = &dummy_clocks;
1296 smu_dpm_clks.mc_address.quad_part = 0;
1297 }
1298 ASSERT(smu_dpm_clks.dpm_clks);
1299
1300 if (ctx->dce_version == DCN_VERSION_3_51) {
1301 smu_dpm_clks_dcn351.dpm_clks = (DpmClocks_t_dcn351 *)dm_helpers_allocate_gpu_mem(
1302 clk_mgr->base.base.ctx,
1303 DC_MEM_ALLOC_TYPE_GART,
1304 sizeof(DpmClocks_t_dcn351),
1305 &smu_dpm_clks_dcn351.mc_address.quad_part);
1306 if (smu_dpm_clks_dcn351.dpm_clks == NULL) {
1307 smu_dpm_clks_dcn351.dpm_clks = &dummy_clocks_dcn351;
1308 smu_dpm_clks_dcn351.mc_address.quad_part = 0;
1309 }
1310 }
1311
1312 clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1313
1314 if (clk_mgr->base.smu_ver)
1315 clk_mgr->base.smu_present = true;
1316
1317 /* TODO: Check we get what we expect during bringup */
1318 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1319
1320 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
1321 dcn35_bw_params.wm_table = lpddr5_wm_table;
1322 } else {
1323 dcn35_bw_params.wm_table = ddr5_wm_table;
1324 }
1325 /* Saved clocks configured at boot for debug purposes */
1326 dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1327
1328 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1329 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1330
1331 dce_clock_read_ss_info(&clk_mgr->base);
1332 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1333
1334 dcn35_read_ss_info_from_lut(&clk_mgr->base);
1335
1336 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1337
1338 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1339 int i;
1340 if (ctx->dce_version == DCN_VERSION_3_51) {
1341 dcn351_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks_dcn351);
1342 translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);
1343 } else
1344 dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1345 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1346 "NumDispClkLevelsEnabled: %d\n"
1347 "NumSocClkLevelsEnabled: %d\n"
1348 "VcnClkLevelsEnabled: %d\n"
1349 "FClkLevelsEnabled: %d\n"
1350 "NumMemPstatesEnabled: %d\n"
1351 "MinGfxClk: %d\n"
1352 "MaxGfxClk: %d\n",
1353 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1354 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1355 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1356 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1357 smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1358 smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1359 smu_dpm_clks.dpm_clks->MinGfxClk,
1360 smu_dpm_clks.dpm_clks->MaxGfxClk);
1361 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1362 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1363 i,
1364 smu_dpm_clks.dpm_clks->DcfClocks[i]);
1365 }
1366 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1367 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1368 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1369 }
1370 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1371 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1372 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1373 }
1374 for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1375 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1376 i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1377 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1378 i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1379 }
1380 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1381 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1382 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1383
1384 for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1385 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1386 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1387 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1388 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1389 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1390 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1391 }
1392
1393 if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1394 dcn35_clk_mgr_helper_populate_bw_params(
1395 &clk_mgr->base,
1396 ctx->dc_bios->integrated_info,
1397 smu_dpm_clks.dpm_clks);
1398 }
1399 }
1400
1401 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1402 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1403 smu_dpm_clks.dpm_clks);
1404
1405 if (smu_dpm_clks_dcn351.dpm_clks && smu_dpm_clks_dcn351.mc_address.quad_part != 0)
1406 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1407 smu_dpm_clks_dcn351.dpm_clks);
1408
1409 if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1410 bool ips_support = false;
1411
1412 /*avoid call pmfw at init*/
1413 ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1414 if (ips_support) {
1415 ctx->dc->debug.ignore_pg = false;
1416 ctx->dc->debug.disable_dpp_power_gate = false;
1417 ctx->dc->debug.disable_hubp_power_gate = false;
1418 ctx->dc->debug.disable_dsc_power_gate = false;
1419
1420 /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
1421 if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
1422 ctx->dce_version != DCN_VERSION_3_51 &&
1423 ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
1424 ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1425 } else {
1426 /*let's reset the config control flag*/
1427 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1428 }
1429 }
1430 }
1431
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1432 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1433 {
1434 struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1435
1436 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1437 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1438 clk_mgr->smu_wm_set.wm_set);
1439 }
1440