1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10#include <dt-bindings/sound/qcom,q6afe.h> 11#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 12 13#include "monaco.dtsi" 14#include "monaco-pmics.dtsi" 15 16/ { 17 model = "Qualcomm Technologies, Inc. Monaco EVK"; 18 compatible = "qcom,monaco-evk", "qcom,qcs8300"; 19 20 aliases { 21 ethernet0 = ðernet0; 22 i2c1 = &i2c1; 23 serial0 = &uart7; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 dmic: audio-codec-0 { 31 compatible = "dmic-codec"; 32 #sound-dai-cells = <0>; 33 num-channels = <1>; 34 }; 35 36 max98357a: audio-codec-1 { 37 compatible = "maxim,max98357a"; 38 #sound-dai-cells = <0>; 39 }; 40 41 sound { 42 compatible = "qcom,qcs8275-sndcard"; 43 model = "MONACO-EVK"; 44 45 pinctrl-0 = <&hs0_mi2s_active>, <&mi2s1_active>; 46 pinctrl-names = "default"; 47 48 hs0-mi2s-playback-dai-link { 49 link-name = "HS0 MI2S Playback"; 50 51 codec { 52 sound-dai = <&max98357a>; 53 }; 54 55 cpu { 56 sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>; 57 }; 58 59 platform { 60 sound-dai = <&q6apm>; 61 }; 62 }; 63 64 sec-mi2s-capture-dai-link { 65 link-name = "Secondary MI2S Capture"; 66 67 codec { 68 sound-dai = <&dmic>; 69 }; 70 71 cpu { 72 sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; 73 }; 74 75 platform { 76 sound-dai = <&q6apm>; 77 }; 78 }; 79 }; 80}; 81 82&apps_rsc { 83 regulators-0 { 84 compatible = "qcom,pmm8654au-rpmh-regulators"; 85 qcom,pmic-id = "a"; 86 87 vreg_l3a: ldo3 { 88 regulator-name = "vreg_l3a"; 89 regulator-min-microvolt = <1200000>; 90 regulator-max-microvolt = <1200000>; 91 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 92 regulator-allow-set-load; 93 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 94 }; 95 96 vreg_l4a: ldo4 { 97 regulator-name = "vreg_l4a"; 98 regulator-min-microvolt = <880000>; 99 regulator-max-microvolt = <912000>; 100 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 101 regulator-allow-set-load; 102 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 103 }; 104 105 vreg_l5a: ldo5 { 106 regulator-name = "vreg_l5a"; 107 regulator-min-microvolt = <1200000>; 108 regulator-max-microvolt = <1200000>; 109 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 110 regulator-allow-set-load; 111 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 112 }; 113 114 vreg_l6a: ldo6 { 115 regulator-name = "vreg_l6a"; 116 regulator-min-microvolt = <880000>; 117 regulator-max-microvolt = <912000>; 118 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 119 regulator-allow-set-load; 120 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 121 }; 122 123 vreg_l7a: ldo7 { 124 regulator-name = "vreg_l7a"; 125 regulator-min-microvolt = <880000>; 126 regulator-max-microvolt = <912000>; 127 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 128 regulator-allow-set-load; 129 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 130 }; 131 132 vreg_l8a: ldo8 { 133 regulator-name = "vreg_l8a"; 134 regulator-min-microvolt = <2504000>; 135 regulator-max-microvolt = <2960000>; 136 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 137 regulator-allow-set-load; 138 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 139 }; 140 141 vreg_l9a: ldo9 { 142 regulator-name = "vreg_l9a"; 143 regulator-min-microvolt = <2970000>; 144 regulator-max-microvolt = <3072000>; 145 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 146 regulator-allow-set-load; 147 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 148 }; 149 }; 150 151 regulators-1 { 152 compatible = "qcom,pmm8654au-rpmh-regulators"; 153 qcom,pmic-id = "c"; 154 155 vreg_s5c: smps5 { 156 regulator-name = "vreg_s5c"; 157 regulator-min-microvolt = <1104000>; 158 regulator-max-microvolt = <1104000>; 159 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 160 }; 161 162 vreg_l1c: ldo1 { 163 regulator-name = "vreg_l1c"; 164 regulator-min-microvolt = <300000>; 165 regulator-max-microvolt = <512000>; 166 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 167 regulator-allow-set-load; 168 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 169 }; 170 171 vreg_l2c: ldo2 { 172 regulator-name = "vreg_l2c"; 173 regulator-min-microvolt = <900000>; 174 regulator-max-microvolt = <904000>; 175 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 176 regulator-allow-set-load; 177 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 178 }; 179 180 vreg_l4c: ldo4 { 181 regulator-name = "vreg_l4c"; 182 regulator-min-microvolt = <1200000>; 183 regulator-max-microvolt = <1200000>; 184 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 185 regulator-allow-set-load; 186 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 187 }; 188 189 vreg_l7c: ldo7 { 190 regulator-name = "vreg_l7c"; 191 regulator-min-microvolt = <1800000>; 192 regulator-max-microvolt = <1800000>; 193 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 194 regulator-allow-set-load; 195 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 196 }; 197 198 vreg_l8c: ldo8 { 199 regulator-name = "vreg_l8c"; 200 regulator-min-microvolt = <1800000>; 201 regulator-max-microvolt = <1800000>; 202 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 203 regulator-allow-set-load; 204 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 205 }; 206 207 vreg_l9c: ldo9 { 208 regulator-name = "vreg_l9c"; 209 regulator-min-microvolt = <1800000>; 210 regulator-max-microvolt = <1800000>; 211 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 212 regulator-allow-set-load; 213 regulator-allowed-modes = <RPMH_REGULATOR_MODE_HPM>; 214 }; 215 }; 216}; 217 218ðernet0 { 219 phy-mode = "2500base-x"; 220 phy-handle = <&hsgmii_phy0>; 221 222 pinctrl-0 = <ðernet0_default>; 223 pinctrl-names = "default"; 224 225 snps,mtl-rx-config = <&mtl_rx_setup>; 226 snps,mtl-tx-config = <&mtl_tx_setup>; 227 nvmem-cells = <&mac_addr0>; 228 nvmem-cell-names = "mac-address"; 229 230 status = "okay"; 231 232 mdio { 233 compatible = "snps,dwmac-mdio"; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 237 hsgmii_phy0: ethernet-phy@1c { 238 compatible = "ethernet-phy-id004d.d101"; 239 reg = <0x1c>; 240 reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; 241 reset-assert-us = <11000>; 242 reset-deassert-us = <70000>; 243 }; 244 }; 245 246 mtl_rx_setup: rx-queues-config { 247 snps,rx-queues-to-use = <4>; 248 snps,rx-sched-sp; 249 250 queue0 { 251 snps,dcb-algorithm; 252 snps,map-to-dma-channel = <0x0>; 253 snps,route-up; 254 snps,priority = <0x1>; 255 }; 256 257 queue1 { 258 snps,dcb-algorithm; 259 snps,map-to-dma-channel = <0x1>; 260 snps,route-ptp; 261 }; 262 263 queue2 { 264 snps,avb-algorithm; 265 snps,map-to-dma-channel = <0x2>; 266 snps,route-avcp; 267 }; 268 269 queue3 { 270 snps,avb-algorithm; 271 snps,map-to-dma-channel = <0x3>; 272 snps,priority = <0xc>; 273 }; 274 }; 275 276 mtl_tx_setup: tx-queues-config { 277 snps,tx-queues-to-use = <4>; 278 279 queue0 { 280 snps,dcb-algorithm; 281 }; 282 283 queue1 { 284 snps,dcb-algorithm; 285 }; 286 287 queue2 { 288 snps,avb-algorithm; 289 snps,send_slope = <0x1000>; 290 snps,idle_slope = <0x1000>; 291 snps,high_credit = <0x3e800>; 292 snps,low_credit = <0xffc18000>; 293 }; 294 295 queue3 { 296 snps,avb-algorithm; 297 snps,send_slope = <0x1000>; 298 snps,idle_slope = <0x1000>; 299 snps,high_credit = <0x3e800>; 300 snps,low_credit = <0xffc18000>; 301 }; 302 }; 303}; 304 305&gpi_dma0 { 306 status = "okay"; 307}; 308 309&gpi_dma1 { 310 status = "okay"; 311}; 312 313&gpu { 314 status = "okay"; 315}; 316 317&gpu_zap_shader { 318 firmware-name = "qcom/qcs8300/a623_zap.mbn"; 319}; 320 321&i2c1 { 322 pinctrl-0 = <&qup_i2c1_default>; 323 pinctrl-names = "default"; 324 325 status = "okay"; 326 327 fan_controller: fan@18 { 328 compatible = "ti,amc6821"; 329 reg = <0x18>; 330 #pwm-cells = <2>; 331 332 fan { 333 pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; 334 }; 335 }; 336 337 eeprom0: eeprom@50 { 338 compatible = "atmel,24c256"; 339 reg = <0x50>; 340 pagesize = <64>; 341 342 nvmem-layout { 343 compatible = "fixed-layout"; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 347 mac_addr0: mac-addr@0 { 348 reg = <0x0 0x6>; 349 }; 350 }; 351 }; 352}; 353 354&i2c15 { 355 pinctrl-0 = <&qup_i2c15_default>; 356 pinctrl-names = "default"; 357 358 status = "okay"; 359 360 expander0: gpio@38 { 361 compatible = "ti,tca9538"; 362 reg = <0x38>; 363 #gpio-cells = <2>; 364 gpio-controller; 365 }; 366 367 expander1: gpio@39 { 368 compatible = "ti,tca9538"; 369 reg = <0x39>; 370 #gpio-cells = <2>; 371 gpio-controller; 372 }; 373 374 expander2: gpio@3a { 375 compatible = "ti,tca9538"; 376 reg = <0x3a>; 377 #gpio-cells = <2>; 378 gpio-controller; 379 }; 380 381 expander3: gpio@3b { 382 compatible = "ti,tca9538"; 383 reg = <0x3b>; 384 #gpio-cells = <2>; 385 gpio-controller; 386 }; 387 388 expander4: gpio@3c { 389 compatible = "ti,tca9538"; 390 reg = <0x3c>; 391 #gpio-cells = <2>; 392 gpio-controller; 393 }; 394 395 expander5: gpio@3d { 396 compatible = "ti,tca9538"; 397 reg = <0x3d>; 398 #gpio-cells = <2>; 399 gpio-controller; 400 }; 401 402 expander6: gpio@3e { 403 compatible = "ti,tca9538"; 404 reg = <0x3e>; 405 #gpio-cells = <2>; 406 gpio-controller; 407 }; 408}; 409 410&iris { 411 status = "okay"; 412}; 413 414&pcie0 { 415 pinctrl-0 = <&pcie0_default_state>; 416 pinctrl-names = "default"; 417 418 status = "okay"; 419}; 420 421&pcie0_phy { 422 vdda-phy-supply = <&vreg_l6a>; 423 vdda-pll-supply = <&vreg_l5a>; 424 425 status = "okay"; 426}; 427 428&pcie1 { 429 pinctrl-0 = <&pcie1_default_state>; 430 pinctrl-names = "default"; 431 432 status = "okay"; 433}; 434 435&pcie1_phy { 436 vdda-phy-supply = <&vreg_l6a>; 437 vdda-pll-supply = <&vreg_l5a>; 438 439 status = "okay"; 440}; 441 442&pcieport0 { 443 reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; 444 wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; 445}; 446 447&pcieport1 { 448 reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; 449 wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; 450}; 451 452&qupv3_id_0 { 453 firmware-name = "qcom/qcs8300/qupv3fw.elf"; 454 status = "okay"; 455}; 456 457&qupv3_id_1 { 458 firmware-name = "qcom/qcs8300/qupv3fw.elf"; 459 status = "okay"; 460}; 461 462&remoteproc_adsp { 463 firmware-name = "qcom/qcs8300/adsp.mbn"; 464 465 status = "okay"; 466}; 467 468&remoteproc_cdsp { 469 firmware-name = "qcom/qcs8300/cdsp0.mbn"; 470 471 status = "okay"; 472}; 473 474&remoteproc_gpdsp { 475 firmware-name = "qcom/qcs8300/gpdsp0.mbn"; 476 477 status = "okay"; 478}; 479 480&serdes0 { 481 phy-supply = <&vreg_l4a>; 482 483 status = "okay"; 484}; 485 486&spi10 { 487 status = "okay"; 488 489 tpm@0 { 490 compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; 491 reg = <0>; 492 spi-max-frequency = <20000000>; 493 }; 494}; 495 496&tlmm { 497 498 pcie0_default_state: pcie0-default-state { 499 wake-pins { 500 pins = "gpio0"; 501 function = "gpio"; 502 drive-strength = <2>; 503 bias-pull-up; 504 }; 505 506 clkreq-pins { 507 pins = "gpio1"; 508 function = "pcie0_clkreq"; 509 drive-strength = <2>; 510 bias-pull-up; 511 }; 512 513 perst-pins { 514 pins = "gpio2"; 515 function = "gpio"; 516 drive-strength = <2>; 517 bias-pull-up; 518 }; 519 }; 520 521 ethernet0_default: ethernet0-default-state { 522 ethernet0_mdc: ethernet0-mdc-pins { 523 pins = "gpio5"; 524 function = "emac0_mdc"; 525 drive-strength = <16>; 526 bias-pull-up; 527 }; 528 529 ethernet0_mdio: ethernet0-mdio-pins { 530 pins = "gpio6"; 531 function = "emac0_mdio"; 532 drive-strength = <16>; 533 bias-pull-up; 534 }; 535 }; 536 537 qup_i2c1_default: qup-i2c1-state { 538 pins = "gpio19", "gpio20"; 539 function = "qup0_se1"; 540 drive-strength = <2>; 541 bias-pull-up; 542 }; 543 544 pcie1_default_state: pcie1-default-state { 545 wake-pins { 546 pins = "gpio21"; 547 function = "gpio"; 548 drive-strength = <2>; 549 bias-pull-up; 550 }; 551 552 clkreq-pins { 553 pins = "gpio22"; 554 function = "pcie1_clkreq"; 555 drive-strength = <2>; 556 bias-pull-up; 557 }; 558 559 perst-pins { 560 pins = "gpio23"; 561 function = "gpio"; 562 drive-strength = <2>; 563 bias-pull-up; 564 }; 565 }; 566 567 qup_i2c15_default: qup-i2c15-state { 568 pins = "gpio91", "gpio92"; 569 function = "qup1_se7"; 570 drive-strength = <2>; 571 bias-pull-up; 572 }; 573}; 574 575&uart7 { 576 status = "okay"; 577}; 578 579&ufs_mem_hc { 580 reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; 581 vcc-supply = <&vreg_l8a>; 582 vcc-max-microamp = <1100000>; 583 vccq-supply = <&vreg_l4c>; 584 vccq-max-microamp = <1200000>; 585 586 status = "okay"; 587}; 588 589&ufs_mem_phy { 590 vdda-phy-supply = <&vreg_l4a>; 591 vdda-pll-supply = <&vreg_l5a>; 592 593 status = "okay"; 594}; 595 596&usb_1 { 597 dr_mode = "peripheral"; 598 599 status = "okay"; 600}; 601 602&usb_1_hsphy { 603 vdda-pll-supply = <&vreg_l7a>; 604 vdda18-supply = <&vreg_l7c>; 605 vdda33-supply = <&vreg_l9a>; 606 607 status = "okay"; 608}; 609 610&usb_qmpphy { 611 vdda-phy-supply = <&vreg_l7a>; 612 vdda-pll-supply = <&vreg_l5a>; 613 614 status = "okay"; 615}; 616