1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7770, AD7771, AD7779 ADC
4 *
5 * Copyright 2023-2024 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitmap.h>
10 #include <linux/clk.h>
11 #include <linux/crc8.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/math.h>
18 #include <linux/module.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/unaligned.h>
25 #include <linux/units.h>
26
27 #include <linux/iio/iio.h>
28 #include <linux/iio/backend.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/iio/trigger_consumer.h>
34
35 #define AD7779_SPI_READ_CMD BIT(7)
36
37 #define AD7779_DISABLE_SD BIT(7)
38
39 #define AD7779_REG_CH_DISABLE 0x08
40 #define AD7779_REG_CH_SYNC_OFFSET(ch) (0x09 + (ch))
41 #define AD7779_REG_CH_CONFIG(ch) (0x00 + (ch))
42 #define AD7779_REG_GENERAL_USER_CONFIG_1 0x11
43 #define AD7779_REG_GENERAL_USER_CONFIG_2 0x12
44 #define AD7779_REG_GENERAL_USER_CONFIG_3 0x13
45 #define AD7779_REG_DOUT_FORMAT 0x14
46 #define AD7779_REG_ADC_MUX_CONFIG 0x15
47 #define AD7779_REG_GPIO_CONFIG 0x17
48 #define AD7779_REG_BUFFER_CONFIG_1 0x19
49 #define AD7779_REG_GLOBAL_MUX_CONFIG 0x16
50 #define AD7779_REG_BUFFER_CONFIG_2 0x1A
51 #define AD7779_REG_GPIO_DATA 0x18
52 #define AD7779_REG_CH_OFFSET_UPPER_BYTE(ch) (0x1C + (ch) * 6)
53 #define AD7779_REG_CH_OFFSET_LOWER_BYTE(ch) (0x1E + (ch) * 6)
54 #define AD7779_REG_CH_GAIN_UPPER_BYTE(ch) (0x1F + (ch) * 6)
55 #define AD7779_REG_CH_OFFSET_MID_BYTE(ch) (0x1D + (ch) * 6)
56 #define AD7779_REG_CH_GAIN_MID_BYTE(ch) (0x20 + (ch) * 6)
57 #define AD7779_REG_CH_ERR_REG(ch) (0x4C + (ch))
58 #define AD7779_REG_CH0_1_SAT_ERR 0x54
59 #define AD7779_REG_CH_GAIN_LOWER_BYTE(ch) (0x21 + (ch) * 6)
60 #define AD7779_REG_CH2_3_SAT_ERR 0x55
61 #define AD7779_REG_CH4_5_SAT_ERR 0x56
62 #define AD7779_REG_CH6_7_SAT_ERR 0x57
63 #define AD7779_REG_CHX_ERR_REG_EN 0x58
64 #define AD7779_REG_GEN_ERR_REG_1 0x59
65 #define AD7779_REG_GEN_ERR_REG_1_EN 0x5A
66 #define AD7779_REG_GEN_ERR_REG_2 0x5B
67 #define AD7779_REG_GEN_ERR_REG_2_EN 0x5C
68 #define AD7779_REG_STATUS_REG_1 0x5D
69 #define AD7779_REG_STATUS_REG_2 0x5E
70 #define AD7779_REG_STATUS_REG_3 0x5F
71 #define AD7779_REG_SRC_N_MSB 0x60
72 #define AD7779_REG_SRC_N_LSB 0x61
73 #define AD7779_REG_SRC_IF_MSB 0x62
74 #define AD7779_REG_SRC_IF_LSB 0x63
75 #define AD7779_REG_SRC_UPDATE 0x64
76
77 #define AD7779_FILTER_MSK BIT(6)
78 #define AD7779_MOD_POWERMODE_MSK BIT(6)
79 #define AD7779_MOD_PDB_REFOUT_MSK BIT(4)
80 #define AD7779_MOD_SPI_EN_MSK BIT(4)
81 #define AD7779_USRMOD_INIT_MSK GENMASK(6, 4)
82
83 /* AD7779_REG_DOUT_FORMAT */
84 #define AD7779_DOUT_FORMAT_MSK GENMASK(7, 6)
85 #define AD7779_DOUT_HEADER_FORMAT BIT(5)
86 #define AD7779_DCLK_CLK_DIV_MSK GENMASK(3, 1)
87
88 #define AD7779_REFMUX_CTRL_MSK GENMASK(7, 6)
89 #define AD7779_SPI_CRC_EN_MSK BIT(0)
90
91 #define AD7779_MAXCLK_LOWPOWER (4096 * HZ_PER_KHZ)
92 #define AD7779_NUM_CHANNELS 8
93 #define AD7779_RESET_BUF_SIZE 8
94 #define AD7779_CHAN_DATA_SIZE 4
95
96 #define AD7779_LOWPOWER_DIV 512
97 #define AD7779_HIGHPOWER_DIV 2048
98
99 #define AD7779_SINC3_MAXFREQ (16 * HZ_PER_KHZ)
100 #define AD7779_SINC5_MAXFREQ (128 * HZ_PER_KHZ)
101
102 #define AD7779_DEFAULT_SAMPLING_FREQ (8 * HZ_PER_KHZ)
103 #define AD7779_DEFAULT_SAMPLING_2LINE (4 * HZ_PER_KHZ)
104 #define AD7779_DEFAULT_SAMPLING_1LINE (2 * HZ_PER_KHZ)
105
106 #define AD7779_SPIMODE_MAX_SAMP_FREQ (16 * HZ_PER_KHZ)
107
108 #define GAIN_REL 0x555555
109 #define AD7779_FREQ_MSB_MSK GENMASK(15, 8)
110 #define AD7779_FREQ_LSB_MSK GENMASK(7, 0)
111 #define AD7779_UPPER GENMASK(23, 16)
112 #define AD7779_MID GENMASK(15, 8)
113 #define AD7779_LOWER GENMASK(7, 0)
114
115 #define AD7779_REG_MSK GENMASK(6, 0)
116
117 #define AD7779_CRC8_POLY 0x07
118 DECLARE_CRC8_TABLE(ad7779_crc8_table);
119
120 enum ad7779_filter {
121 AD7779_SINC3,
122 AD7779_SINC5,
123 };
124
125 enum ad7779_variant {
126 ad7770,
127 ad7771,
128 ad7779,
129 };
130
131 enum ad7779_power_mode {
132 AD7779_LOW_POWER,
133 AD7779_HIGH_POWER,
134 };
135
136 struct ad7779_chip_info {
137 const char *name;
138 struct iio_chan_spec const *channels;
139 };
140
141 struct ad7779_state {
142 struct spi_device *spi;
143 const struct ad7779_chip_info *chip_info;
144 struct clk *mclk;
145 struct iio_trigger *trig;
146 struct completion completion;
147 unsigned int sampling_freq;
148 enum ad7779_filter filter_enabled;
149 struct iio_backend *back;
150 /*
151 * DMA (thus cache coherency maintenance) requires the
152 * transfer buffers to live in their own cache lines.
153 */
154 struct {
155 u32 chans[8];
156 aligned_s64 timestamp;
157 } data __aligned(IIO_DMA_MINALIGN);
158 u32 spidata_tx[8];
159 u8 reg_rx_buf[3];
160 u8 reg_tx_buf[3];
161 u8 reset_buf[8];
162 };
163
164 static const char * const ad7779_filter_type[] = {
165 [AD7779_SINC3] = "sinc3",
166 [AD7779_SINC5] = "sinc5",
167 };
168
169 static const char * const ad7779_power_supplies[] = {
170 "avdd1", "avdd2", "avdd4",
171 };
172
ad7779_spi_read(struct ad7779_state * st,u8 reg,u8 * rbuf)173 static int ad7779_spi_read(struct ad7779_state *st, u8 reg, u8 *rbuf)
174 {
175 int ret;
176 u8 crc_buf[2];
177 u8 exp_crc;
178 struct spi_transfer t = {
179 .tx_buf = st->reg_tx_buf,
180 .rx_buf = st->reg_rx_buf,
181 };
182
183 st->reg_tx_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg);
184 st->reg_tx_buf[1] = 0;
185
186 if (reg == AD7779_REG_GEN_ERR_REG_1_EN) {
187 t.len = 2;
188 } else {
189 t.len = 3;
190 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf,
191 t.len - 1, 0);
192 }
193
194 ret = spi_sync_transfer(st->spi, &t, 1);
195 if (ret)
196 return ret;
197
198 crc_buf[0] = AD7779_SPI_READ_CMD | FIELD_GET(AD7779_REG_MSK, reg);
199 crc_buf[1] = st->reg_rx_buf[1];
200 exp_crc = crc8(ad7779_crc8_table, crc_buf, ARRAY_SIZE(crc_buf), 0);
201 if (reg != AD7779_REG_GEN_ERR_REG_1_EN && exp_crc != st->reg_rx_buf[2]) {
202 dev_err(&st->spi->dev, "Bad CRC %x, expected %x",
203 st->reg_rx_buf[2], exp_crc);
204 return -EINVAL;
205 }
206 *rbuf = st->reg_rx_buf[1];
207
208 return 0;
209 }
210
ad7779_spi_write(struct ad7779_state * st,u8 reg,u8 val)211 static int ad7779_spi_write(struct ad7779_state *st, u8 reg, u8 val)
212 {
213 u8 length = 3;
214
215 st->reg_tx_buf[0] = FIELD_GET(AD7779_REG_MSK, reg);
216 st->reg_tx_buf[1] = val;
217 if (reg == AD7779_REG_GEN_ERR_REG_1_EN)
218 length = 2;
219 else
220 st->reg_tx_buf[2] = crc8(ad7779_crc8_table, st->reg_tx_buf,
221 length - 1, 0);
222
223 return spi_write(st->spi, st->reg_tx_buf, length);
224 }
225
ad7779_spi_write_mask(struct ad7779_state * st,u8 reg,u8 mask,u8 val)226 static int ad7779_spi_write_mask(struct ad7779_state *st, u8 reg, u8 mask,
227 u8 val)
228 {
229 int ret;
230 u8 regval, data;
231
232 ret = ad7779_spi_read(st, reg, &data);
233 if (ret)
234 return ret;
235
236 regval = (data & ~mask) | (val & mask);
237
238 if (regval == data)
239 return 0;
240
241 return ad7779_spi_write(st, reg, regval);
242 }
243
ad7779_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)244 static int ad7779_reg_access(struct iio_dev *indio_dev,
245 unsigned int reg,
246 unsigned int writeval,
247 unsigned int *readval)
248 {
249 struct ad7779_state *st = iio_priv(indio_dev);
250 u8 rval;
251 int ret;
252
253 if (readval) {
254 ret = ad7779_spi_read(st, reg, &rval);
255 *readval = rval;
256 return ret;
257 }
258
259 return ad7779_spi_write(st, reg, writeval);
260 }
261
ad7779_set_sampling_frequency(struct ad7779_state * st,unsigned int sampling_freq)262 static int ad7779_set_sampling_frequency(struct ad7779_state *st,
263 unsigned int sampling_freq)
264 {
265 int ret;
266 unsigned int dec;
267 unsigned int frac;
268 unsigned int div;
269 unsigned int decimal;
270 unsigned int freq_khz;
271
272 if (st->filter_enabled == AD7779_SINC3 &&
273 sampling_freq > AD7779_SINC3_MAXFREQ)
274 return -EINVAL;
275
276 if (st->filter_enabled == AD7779_SINC5 &&
277 sampling_freq > AD7779_SINC5_MAXFREQ)
278 return -EINVAL;
279
280 if (sampling_freq > AD7779_SPIMODE_MAX_SAMP_FREQ)
281 return -EINVAL;
282
283 div = AD7779_HIGHPOWER_DIV;
284
285 freq_khz = sampling_freq / HZ_PER_KHZ;
286 dec = div / freq_khz;
287 frac = div % freq_khz;
288
289 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB,
290 FIELD_GET(AD7779_FREQ_MSB_MSK, dec));
291 if (ret)
292 return ret;
293 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB,
294 FIELD_GET(AD7779_FREQ_LSB_MSK, dec));
295 if (ret)
296 return ret;
297
298 if (frac) {
299 /*
300 * In order to obtain the first three decimals of the decimation
301 * the initial number is multiplied with 10^3 prior to the
302 * division, then the original division result is subtracted and
303 * the number is divided by 10^3.
304 */
305 decimal = ((mult_frac(div, KILO, freq_khz) - dec * KILO) << 16)
306 / KILO;
307 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB,
308 FIELD_GET(AD7779_FREQ_MSB_MSK, decimal));
309 if (ret)
310 return ret;
311 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB,
312 FIELD_GET(AD7779_FREQ_LSB_MSK, decimal));
313 if (ret)
314 return ret;
315 } else {
316 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_MSB,
317 FIELD_GET(AD7779_FREQ_MSB_MSK, 0x0));
318 if (ret)
319 return ret;
320 ret = ad7779_spi_write(st, AD7779_REG_SRC_N_LSB,
321 FIELD_GET(AD7779_FREQ_LSB_MSK, 0x0));
322 if (ret)
323 return ret;
324 }
325 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, BIT(0));
326 if (ret)
327 return ret;
328
329 /* SRC update settling time */
330 fsleep(15);
331
332 ret = ad7779_spi_write(st, AD7779_REG_SRC_UPDATE, 0x0);
333 if (ret)
334 return ret;
335
336 /* SRC update settling time */
337 fsleep(15);
338
339 st->sampling_freq = sampling_freq;
340
341 return 0;
342 }
343
ad7779_get_filter(struct iio_dev * indio_dev,struct iio_chan_spec const * chan)344 static int ad7779_get_filter(struct iio_dev *indio_dev,
345 struct iio_chan_spec const *chan)
346 {
347 struct ad7779_state *st = iio_priv(indio_dev);
348 u8 temp;
349 int ret;
350
351 ret = ad7779_spi_read(st, AD7779_REG_GENERAL_USER_CONFIG_2, &temp);
352 if (ret)
353 return ret;
354
355 return FIELD_GET(AD7779_FILTER_MSK, temp);
356 }
357
ad7779_set_filter(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,unsigned int mode)358 static int ad7779_set_filter(struct iio_dev *indio_dev,
359 struct iio_chan_spec const *chan,
360 unsigned int mode)
361 {
362 struct ad7779_state *st = iio_priv(indio_dev);
363 int ret;
364
365 ret = ad7779_spi_write_mask(st,
366 AD7779_REG_GENERAL_USER_CONFIG_2,
367 AD7779_FILTER_MSK,
368 FIELD_PREP(AD7779_FILTER_MSK, mode));
369 if (ret)
370 return ret;
371
372 ret = ad7779_set_sampling_frequency(st, st->sampling_freq);
373 if (ret)
374 return ret;
375
376 st->filter_enabled = mode;
377
378 return 0;
379 }
380
ad7779_get_calibscale(struct ad7779_state * st,int channel)381 static int ad7779_get_calibscale(struct ad7779_state *st, int channel)
382 {
383 int ret;
384 u8 calibscale[3];
385
386 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel),
387 &calibscale[0]);
388 if (ret)
389 return ret;
390
391 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_MID_BYTE(channel),
392 &calibscale[1]);
393 if (ret)
394 return ret;
395
396 ret = ad7779_spi_read(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel),
397 &calibscale[2]);
398 if (ret)
399 return ret;
400
401 return get_unaligned_be24(calibscale);
402 }
403
ad7779_set_calibscale(struct ad7779_state * st,int channel,int val)404 static int ad7779_set_calibscale(struct ad7779_state *st, int channel, int val)
405 {
406 int ret;
407 unsigned int gain;
408 u8 gain_bytes[3];
409
410 /*
411 * The gain value is relative to 0x555555, which represents a gain of 1
412 */
413 gain = DIV_ROUND_CLOSEST_ULL((u64)val * 5592405LL, MEGA);
414 put_unaligned_be24(gain, gain_bytes);
415 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_UPPER_BYTE(channel),
416 gain_bytes[0]);
417 if (ret)
418 return ret;
419
420 ret = ad7779_spi_write(st, AD7779_REG_CH_GAIN_MID_BYTE(channel),
421 gain_bytes[1]);
422 if (ret)
423 return ret;
424
425 return ad7779_spi_write(st, AD7779_REG_CH_GAIN_LOWER_BYTE(channel),
426 gain_bytes[2]);
427 }
428
ad7779_get_calibbias(struct ad7779_state * st,int channel)429 static int ad7779_get_calibbias(struct ad7779_state *st, int channel)
430 {
431 int ret;
432 u8 calibbias[3];
433
434 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel),
435 &calibbias[0]);
436 if (ret)
437 return ret;
438
439 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel),
440 &calibbias[1]);
441 if (ret)
442 return ret;
443
444 ret = ad7779_spi_read(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel),
445 &calibbias[2]);
446 if (ret)
447 return ret;
448
449 return get_unaligned_be24(calibbias);
450 }
451
ad7779_set_calibbias(struct ad7779_state * st,int channel,int val)452 static int ad7779_set_calibbias(struct ad7779_state *st, int channel, int val)
453 {
454 int ret;
455 u8 calibbias[3];
456
457 put_unaligned_be24(val, calibbias);
458 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_UPPER_BYTE(channel),
459 calibbias[0]);
460 if (ret)
461 return ret;
462
463 ret = ad7779_spi_write(st, AD7779_REG_CH_OFFSET_MID_BYTE(channel),
464 calibbias[1]);
465 if (ret)
466 return ret;
467
468 return ad7779_spi_write(st, AD7779_REG_CH_OFFSET_LOWER_BYTE(channel),
469 calibbias[2]);
470 }
471
__ad7779_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)472 static int __ad7779_read_raw(struct iio_dev *indio_dev,
473 struct iio_chan_spec const *chan, int *val,
474 int *val2, long mask)
475 {
476 struct ad7779_state *st = iio_priv(indio_dev);
477 int ret;
478
479 switch (mask) {
480 case IIO_CHAN_INFO_CALIBSCALE:
481 ret = ad7779_get_calibscale(st, chan->channel);
482 if (ret < 0)
483 return ret;
484 *val = ret;
485 *val2 = GAIN_REL;
486 return IIO_VAL_FRACTIONAL;
487 case IIO_CHAN_INFO_CALIBBIAS:
488 ret = ad7779_get_calibbias(st, chan->channel);
489 if (ret < 0)
490 return ret;
491 *val = ret;
492 return IIO_VAL_INT;
493 case IIO_CHAN_INFO_SAMP_FREQ:
494 *val = st->sampling_freq;
495 if (*val < 0)
496 return -EINVAL;
497 return IIO_VAL_INT;
498 default:
499 return -EINVAL;
500 }
501 }
502
ad7779_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)503 static int ad7779_read_raw(struct iio_dev *indio_dev,
504 struct iio_chan_spec const *chan, int *val,
505 int *val2, long mask)
506 {
507 int ret;
508
509 if (!iio_device_claim_direct(indio_dev))
510 return -EBUSY;
511
512 ret = __ad7779_read_raw(indio_dev, chan, val, val2, mask);
513 iio_device_release_direct(indio_dev);
514 return ret;
515 }
516
__ad7779_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)517 static int __ad7779_write_raw(struct iio_dev *indio_dev,
518 struct iio_chan_spec const *chan,
519 int val, int val2,
520 long mask)
521 {
522 struct ad7779_state *st = iio_priv(indio_dev);
523
524 switch (mask) {
525 case IIO_CHAN_INFO_CALIBSCALE:
526 return ad7779_set_calibscale(st, chan->channel, val2);
527 case IIO_CHAN_INFO_CALIBBIAS:
528 return ad7779_set_calibbias(st, chan->channel, val);
529 case IIO_CHAN_INFO_SAMP_FREQ:
530 return ad7779_set_sampling_frequency(st, val);
531 default:
532 return -EINVAL;
533 }
534 }
535
ad7779_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)536 static int ad7779_write_raw(struct iio_dev *indio_dev,
537 struct iio_chan_spec const *chan, int val, int val2,
538 long mask)
539 {
540 int ret;
541
542 if (!iio_device_claim_direct(indio_dev))
543 return -EBUSY;
544
545 ret = __ad7779_write_raw(indio_dev, chan, val, val2, mask);
546 iio_device_release_direct(indio_dev);
547 return ret;
548 }
549
ad7779_buffer_preenable(struct iio_dev * indio_dev)550 static int ad7779_buffer_preenable(struct iio_dev *indio_dev)
551 {
552 int ret;
553 struct ad7779_state *st = iio_priv(indio_dev);
554
555 ret = ad7779_spi_write_mask(st,
556 AD7779_REG_GENERAL_USER_CONFIG_3,
557 AD7779_MOD_SPI_EN_MSK,
558 FIELD_PREP(AD7779_MOD_SPI_EN_MSK, 1));
559 if (ret)
560 return ret;
561
562 /*
563 * DRDY output cannot be disabled at device level therefore we mask
564 * the irq at host end.
565 */
566 enable_irq(st->spi->irq);
567
568 return 0;
569 }
570
ad7779_buffer_postdisable(struct iio_dev * indio_dev)571 static int ad7779_buffer_postdisable(struct iio_dev *indio_dev)
572 {
573 struct ad7779_state *st = iio_priv(indio_dev);
574
575 disable_irq(st->spi->irq);
576
577 return ad7779_spi_write(st, AD7779_REG_GENERAL_USER_CONFIG_3,
578 AD7779_DISABLE_SD);
579 }
580
ad7779_trigger_handler(int irq,void * p)581 static irqreturn_t ad7779_trigger_handler(int irq, void *p)
582 {
583 struct iio_poll_func *pf = p;
584 struct iio_dev *indio_dev = pf->indio_dev;
585 struct ad7779_state *st = iio_priv(indio_dev);
586 int ret;
587 struct spi_transfer t = {
588 .rx_buf = st->data.chans,
589 .tx_buf = st->spidata_tx,
590 .len = AD7779_NUM_CHANNELS * AD7779_CHAN_DATA_SIZE,
591 };
592
593 st->spidata_tx[0] = AD7779_SPI_READ_CMD;
594 ret = spi_sync_transfer(st->spi, &t, 1);
595 if (ret) {
596 dev_err(&st->spi->dev, "SPI transfer error in IRQ handler");
597 goto exit_handler;
598 }
599
600 iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data),
601 pf->timestamp);
602
603 exit_handler:
604 iio_trigger_notify_done(indio_dev->trig);
605 return IRQ_HANDLED;
606 }
607
ad7779_reset(struct iio_dev * indio_dev,struct gpio_desc * reset_gpio)608 static int ad7779_reset(struct iio_dev *indio_dev, struct gpio_desc *reset_gpio)
609 {
610 struct ad7779_state *st = iio_priv(indio_dev);
611 int ret;
612 struct spi_transfer t = {
613 .tx_buf = st->reset_buf,
614 .len = 8,
615 };
616
617 if (reset_gpio) {
618 gpiod_set_value(reset_gpio, 1);
619 /* Delay for reset to occur is 225 microseconds */
620 fsleep(230);
621 ret = 0;
622 } else {
623 memset(st->reset_buf, 0xff, sizeof(st->reset_buf));
624 ret = spi_sync_transfer(st->spi, &t, 1);
625 if (ret)
626 return ret;
627 }
628
629 /* Delay for reset to occur is 225 microseconds */
630 fsleep(230);
631
632 return ret;
633 }
634
ad7779_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)635 static int ad7779_update_scan_mode(struct iio_dev *indio_dev,
636 const unsigned long *scan_mask)
637 {
638 struct ad7779_state *st = iio_priv(indio_dev);
639 unsigned int c;
640 int ret;
641
642 for (c = 0; c < AD7779_NUM_CHANNELS; c++) {
643 if (test_bit(c, scan_mask))
644 ret = iio_backend_chan_enable(st->back, c);
645 else
646 ret = iio_backend_chan_disable(st->back, c);
647 if (ret)
648 return ret;
649 }
650
651 return 0;
652 }
653
654 static const struct iio_info ad7779_info = {
655 .read_raw = ad7779_read_raw,
656 .write_raw = ad7779_write_raw,
657 .debugfs_reg_access = &ad7779_reg_access,
658 };
659
660 static const struct iio_info ad7779_info_data = {
661 .read_raw = ad7779_read_raw,
662 .write_raw = ad7779_write_raw,
663 .debugfs_reg_access = &ad7779_reg_access,
664 .update_scan_mode = &ad7779_update_scan_mode,
665 };
666
667 static const struct iio_enum ad7779_filter_enum = {
668 .items = ad7779_filter_type,
669 .num_items = ARRAY_SIZE(ad7779_filter_type),
670 .get = ad7779_get_filter,
671 .set = ad7779_set_filter,
672 };
673
674 static const struct iio_chan_spec_ext_info ad7779_ext_filter[] = {
675 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7779_filter_enum),
676 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL,
677 &ad7779_filter_enum),
678 { }
679 };
680
681 #define AD777x_CHAN_S(index, _ext_info) \
682 { \
683 .type = IIO_VOLTAGE, \
684 .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
685 BIT(IIO_CHAN_INFO_CALIBBIAS), \
686 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
687 .address = (index), \
688 .indexed = 1, \
689 .channel = (index), \
690 .scan_index = (index), \
691 .ext_info = (_ext_info), \
692 .scan_type = { \
693 .sign = 's', \
694 .realbits = 24, \
695 .storagebits = 32, \
696 .endianness = IIO_BE, \
697 }, \
698 }
699
700 #define AD777x_CHAN_NO_FILTER_S(index) \
701 AD777x_CHAN_S(index, NULL)
702
703 #define AD777x_CHAN_FILTER_S(index) \
704 AD777x_CHAN_S(index, ad7779_ext_filter)
705 static const struct iio_chan_spec ad7779_channels[] = {
706 AD777x_CHAN_NO_FILTER_S(0),
707 AD777x_CHAN_NO_FILTER_S(1),
708 AD777x_CHAN_NO_FILTER_S(2),
709 AD777x_CHAN_NO_FILTER_S(3),
710 AD777x_CHAN_NO_FILTER_S(4),
711 AD777x_CHAN_NO_FILTER_S(5),
712 AD777x_CHAN_NO_FILTER_S(6),
713 AD777x_CHAN_NO_FILTER_S(7),
714 IIO_CHAN_SOFT_TIMESTAMP(8),
715 };
716
717 static const struct iio_chan_spec ad7779_channels_filter[] = {
718 AD777x_CHAN_FILTER_S(0),
719 AD777x_CHAN_FILTER_S(1),
720 AD777x_CHAN_FILTER_S(2),
721 AD777x_CHAN_FILTER_S(3),
722 AD777x_CHAN_FILTER_S(4),
723 AD777x_CHAN_FILTER_S(5),
724 AD777x_CHAN_FILTER_S(6),
725 AD777x_CHAN_FILTER_S(7),
726 IIO_CHAN_SOFT_TIMESTAMP(8),
727 };
728
729 static const struct iio_buffer_setup_ops ad7779_buffer_setup_ops = {
730 .preenable = ad7779_buffer_preenable,
731 .postdisable = ad7779_buffer_postdisable,
732 };
733
734 static const struct iio_trigger_ops ad7779_trigger_ops = {
735 .validate_device = iio_trigger_validate_own_device,
736 };
737
ad7779_conf(struct ad7779_state * st,struct gpio_desc * start_gpio)738 static int ad7779_conf(struct ad7779_state *st, struct gpio_desc *start_gpio)
739 {
740 int ret;
741
742 ret = ad7779_spi_write_mask(st, AD7779_REG_GEN_ERR_REG_1_EN,
743 AD7779_SPI_CRC_EN_MSK,
744 FIELD_PREP(AD7779_SPI_CRC_EN_MSK, 1));
745 if (ret)
746 return ret;
747
748 ret = ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1,
749 AD7779_USRMOD_INIT_MSK,
750 FIELD_PREP(AD7779_USRMOD_INIT_MSK, 5));
751 if (ret)
752 return ret;
753
754 ret = ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT,
755 AD7779_DCLK_CLK_DIV_MSK,
756 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 1));
757 if (ret)
758 return ret;
759
760 ret = ad7779_spi_write_mask(st, AD7779_REG_ADC_MUX_CONFIG,
761 AD7779_REFMUX_CTRL_MSK,
762 FIELD_PREP(AD7779_REFMUX_CTRL_MSK, 1));
763 if (ret)
764 return ret;
765
766 ret = ad7779_set_sampling_frequency(st, AD7779_DEFAULT_SAMPLING_FREQ);
767 if (ret)
768 return ret;
769
770 gpiod_set_value(start_gpio, 0);
771 /* Start setup time */
772 fsleep(15);
773 gpiod_set_value(start_gpio, 1);
774 /* Start setup time */
775 fsleep(15);
776 gpiod_set_value(start_gpio, 0);
777 /* Start setup time */
778 fsleep(15);
779
780 return 0;
781 }
782
ad7779_set_data_lines(struct iio_dev * indio_dev,u32 num_lanes)783 static int ad7779_set_data_lines(struct iio_dev *indio_dev, u32 num_lanes)
784 {
785 struct ad7779_state *st = iio_priv(indio_dev);
786 int ret;
787
788 if (num_lanes != 1 && num_lanes != 2 && num_lanes != 4)
789 return -EINVAL;
790
791 ret = ad7779_set_sampling_frequency(st, num_lanes * AD7779_DEFAULT_SAMPLING_1LINE);
792 if (ret)
793 return ret;
794
795 ret = iio_backend_num_lanes_set(st->back, num_lanes);
796 if (ret)
797 return ret;
798
799 return ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT,
800 AD7779_DOUT_FORMAT_MSK,
801 FIELD_PREP(AD7779_DOUT_FORMAT_MSK, 2 - ilog2(num_lanes)));
802 }
803
ad7779_setup_channels(struct iio_dev * indio_dev,const struct ad7779_state * st)804 static int ad7779_setup_channels(struct iio_dev *indio_dev, const struct ad7779_state *st)
805 {
806 struct iio_chan_spec *channels;
807 struct device *dev = &st->spi->dev;
808
809 channels = devm_kmemdup_array(dev, st->chip_info->channels,
810 ARRAY_SIZE(ad7779_channels),
811 sizeof(*channels), GFP_KERNEL);
812 if (!channels)
813 return -ENOMEM;
814
815 for (unsigned int i = 0; i < ARRAY_SIZE(ad7779_channels); i++)
816 channels[i].scan_type.endianness = IIO_CPU;
817
818 indio_dev->channels = channels;
819 indio_dev->num_channels = ARRAY_SIZE(ad7779_channels);
820
821 return 0;
822 }
823
ad7779_setup_without_backend(struct ad7779_state * st,struct iio_dev * indio_dev)824 static int ad7779_setup_without_backend(struct ad7779_state *st, struct iio_dev *indio_dev)
825 {
826 int ret;
827 struct device *dev = &st->spi->dev;
828
829 indio_dev->info = &ad7779_info;
830 indio_dev->channels = st->chip_info->channels;
831 indio_dev->num_channels = ARRAY_SIZE(ad7779_channels);
832
833 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
834 iio_device_id(indio_dev));
835 if (!st->trig)
836 return -ENOMEM;
837
838 st->trig->ops = &ad7779_trigger_ops;
839
840 iio_trigger_set_drvdata(st->trig, st);
841
842 ret = devm_request_irq(dev, st->spi->irq, iio_trigger_generic_data_rdy_poll,
843 IRQF_NO_THREAD | IRQF_NO_AUTOEN, indio_dev->name,
844 st->trig);
845 if (ret)
846 return dev_err_probe(dev, ret, "request IRQ %d failed\n",
847 st->spi->irq);
848
849 ret = devm_iio_trigger_register(dev, st->trig);
850 if (ret)
851 return ret;
852
853 indio_dev->trig = iio_trigger_get(st->trig);
854
855 init_completion(&st->completion);
856
857 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
858 &iio_pollfunc_store_time,
859 &ad7779_trigger_handler,
860 &ad7779_buffer_setup_ops);
861 if (ret)
862 return ret;
863
864 return ad7779_spi_write_mask(st, AD7779_REG_DOUT_FORMAT,
865 AD7779_DCLK_CLK_DIV_MSK,
866 FIELD_PREP(AD7779_DCLK_CLK_DIV_MSK, 7));
867 }
868
ad7779_setup_backend(struct ad7779_state * st,struct iio_dev * indio_dev)869 static int ad7779_setup_backend(struct ad7779_state *st, struct iio_dev *indio_dev)
870 {
871 struct device *dev = &st->spi->dev;
872 int ret;
873 u32 num_lanes;
874
875 indio_dev->info = &ad7779_info_data;
876
877 ret = ad7779_setup_channels(indio_dev, st);
878 if (ret)
879 return ret;
880
881 st->back = devm_iio_backend_get(dev, NULL);
882 if (IS_ERR(st->back))
883 return dev_err_probe(dev, PTR_ERR(st->back),
884 "failed to get iio backend");
885
886 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
887 if (ret)
888 return ret;
889
890 ret = devm_iio_backend_enable(dev, st->back);
891 if (ret)
892 return ret;
893
894 num_lanes = 4;
895 ret = device_property_read_u32(dev, "adi,num-lanes", &num_lanes);
896 if (ret && ret != -EINVAL)
897 return ret;
898
899 return ad7779_set_data_lines(indio_dev, num_lanes);
900 }
901
ad7779_probe(struct spi_device * spi)902 static int ad7779_probe(struct spi_device *spi)
903 {
904 struct iio_dev *indio_dev;
905 struct ad7779_state *st;
906 struct gpio_desc *reset_gpio, *start_gpio;
907 struct device *dev = &spi->dev;
908 int ret = -EINVAL;
909
910 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
911 if (!indio_dev)
912 return -ENOMEM;
913
914 st = iio_priv(indio_dev);
915
916 ret = devm_regulator_bulk_get_enable(dev,
917 ARRAY_SIZE(ad7779_power_supplies),
918 ad7779_power_supplies);
919 if (ret)
920 return dev_err_probe(dev, ret,
921 "failed to get and enable supplies\n");
922
923 st->mclk = devm_clk_get_enabled(dev, "mclk");
924 if (IS_ERR(st->mclk))
925 return PTR_ERR(st->mclk);
926
927 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
928 if (IS_ERR(reset_gpio))
929 return PTR_ERR(reset_gpio);
930
931 start_gpio = devm_gpiod_get(dev, "start", GPIOD_OUT_HIGH);
932 if (IS_ERR(start_gpio))
933 return PTR_ERR(start_gpio);
934
935 crc8_populate_msb(ad7779_crc8_table, AD7779_CRC8_POLY);
936 st->spi = spi;
937
938 st->chip_info = spi_get_device_match_data(spi);
939 if (!st->chip_info)
940 return -ENODEV;
941
942 ret = ad7779_reset(indio_dev, reset_gpio);
943 if (ret)
944 return ret;
945
946 ret = ad7779_conf(st, start_gpio);
947 if (ret)
948 return ret;
949
950 indio_dev->name = st->chip_info->name;
951 indio_dev->modes = INDIO_DIRECT_MODE;
952
953 if (device_property_present(dev, "io-backends"))
954 ret = ad7779_setup_backend(st, indio_dev);
955 else
956 ret = ad7779_setup_without_backend(st, indio_dev);
957 if (ret)
958 return ret;
959
960 return devm_iio_device_register(dev, indio_dev);
961 }
962
ad7779_suspend(struct device * dev)963 static int ad7779_suspend(struct device *dev)
964 {
965 struct iio_dev *indio_dev = dev_get_drvdata(dev);
966 struct ad7779_state *st = iio_priv(indio_dev);
967
968 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1,
969 AD7779_MOD_POWERMODE_MSK,
970 FIELD_PREP(AD7779_MOD_POWERMODE_MSK,
971 AD7779_LOW_POWER));
972 }
973
ad7779_resume(struct device * dev)974 static int ad7779_resume(struct device *dev)
975 {
976 struct iio_dev *indio_dev = dev_get_drvdata(dev);
977 struct ad7779_state *st = iio_priv(indio_dev);
978
979 return ad7779_spi_write_mask(st, AD7779_REG_GENERAL_USER_CONFIG_1,
980 AD7779_MOD_POWERMODE_MSK,
981 FIELD_PREP(AD7779_MOD_POWERMODE_MSK,
982 AD7779_HIGH_POWER));
983 }
984
985 static DEFINE_SIMPLE_DEV_PM_OPS(ad7779_pm_ops, ad7779_suspend, ad7779_resume);
986
987 static const struct ad7779_chip_info ad7770_chip_info = {
988 .name = "ad7770",
989 .channels = ad7779_channels,
990 };
991
992 static const struct ad7779_chip_info ad7771_chip_info = {
993 .name = "ad7771",
994 .channels = ad7779_channels_filter,
995 };
996
997 static const struct ad7779_chip_info ad7779_chip_info = {
998 .name = "ad7779",
999 .channels = ad7779_channels,
1000 };
1001
1002 static const struct spi_device_id ad7779_id[] = {
1003 {
1004 .name = "ad7770",
1005 .driver_data = (kernel_ulong_t)&ad7770_chip_info,
1006 },
1007 {
1008 .name = "ad7771",
1009 .driver_data = (kernel_ulong_t)&ad7771_chip_info,
1010 },
1011 {
1012 .name = "ad7779",
1013 .driver_data = (kernel_ulong_t)&ad7779_chip_info,
1014 },
1015 { }
1016 };
1017 MODULE_DEVICE_TABLE(spi, ad7779_id);
1018
1019 static const struct of_device_id ad7779_of_table[] = {
1020 {
1021 .compatible = "adi,ad7770",
1022 .data = &ad7770_chip_info,
1023 },
1024 {
1025 .compatible = "adi,ad7771",
1026 .data = &ad7771_chip_info,
1027 },
1028 {
1029 .compatible = "adi,ad7779",
1030 .data = &ad7779_chip_info,
1031 },
1032 { }
1033 };
1034 MODULE_DEVICE_TABLE(of, ad7779_of_table);
1035
1036 static struct spi_driver ad7779_driver = {
1037 .driver = {
1038 .name = "ad7779",
1039 .pm = pm_sleep_ptr(&ad7779_pm_ops),
1040 .of_match_table = ad7779_of_table,
1041 },
1042 .probe = ad7779_probe,
1043 .id_table = ad7779_id,
1044 };
1045 module_spi_driver(ad7779_driver);
1046
1047 MODULE_AUTHOR("Ramona Alexandra Nechita <ramona.nechita@analog.com>");
1048 MODULE_DESCRIPTION("Analog Devices AD7779 ADC");
1049 MODULE_LICENSE("GPL");
1050 MODULE_IMPORT_NS("IIO_BACKEND");
1051