1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Low-level exception handling code 4 * 5 * Copyright (C) 2012 ARM Ltd. 6 * Authors: Catalin Marinas <catalin.marinas@arm.com> 7 * Will Deacon <will.deacon@arm.com> 8 */ 9 10#include <linux/arm-smccc.h> 11#include <linux/init.h> 12#include <linux/linkage.h> 13 14#include <asm/alternative.h> 15#include <asm/assembler.h> 16#include <asm/asm-offsets.h> 17#include <asm/asm_pointer_auth.h> 18#include <asm/bug.h> 19#include <asm/cpufeature.h> 20#include <asm/errno.h> 21#include <asm/esr.h> 22#include <asm/irq.h> 23#include <asm/memory.h> 24#include <asm/mmu.h> 25#include <asm/processor.h> 26#include <asm/ptrace.h> 27#include <asm/scs.h> 28#include <asm/stacktrace/frame.h> 29#include <asm/thread_info.h> 30#include <asm/asm-uaccess.h> 31#include <asm/unistd.h> 32 33 .macro clear_gp_regs 34 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29 35 mov x\n, xzr 36 .endr 37 .endm 38 39 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req 40 .align 7 41.Lventry_start\@: 42 .if \el == 0 43 /* 44 * This must be the first instruction of the EL0 vector entries. It is 45 * skipped by the trampoline vectors, to trigger the cleanup. 46 */ 47 b .Lskip_tramp_vectors_cleanup\@ 48 .if \regsize == 64 49 mrs x30, tpidrro_el0 50 msr tpidrro_el0, xzr 51 .else 52 mov x30, xzr 53 .endif 54.Lskip_tramp_vectors_cleanup\@: 55 .endif 56 57 sub sp, sp, #PT_REGS_SIZE 58 /* 59 * Test whether the SP has overflowed, without corrupting a GPR. 60 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT) 61 * should always be zero. 62 */ 63 add sp, sp, x0 // sp' = sp + x0 64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp 65 tbnz x0, #THREAD_SHIFT, 0f 66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0 67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp 68 b el\el\ht\()_\regsize\()_\label 69 700: 71 /* 72 * Either we've just detected an overflow, or we've taken an exception 73 * while on the overflow stack. Either way, we won't return to 74 * userspace, and can clobber EL0 registers to free up GPRs. 75 */ 76 77 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */ 78 msr tpidr_el0, x0 79 80 /* Recover the original x0 value and stash it in tpidrro_el0 */ 81 sub x0, sp, x0 82 msr tpidrro_el0, x0 83 84 /* Switch to the overflow stack */ 85 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0 86 87 /* 88 * Check whether we were already on the overflow stack. This may happen 89 * after panic() re-enables interrupts. 90 */ 91 mrs x0, tpidr_el0 // sp of interrupted context 92 sub x0, sp, x0 // delta with top of overflow stack 93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range? 94 b.ne __bad_stack // no? -> bad stack pointer 95 96 /* We were already on the overflow stack. Restore sp/x0 and carry on. */ 97 sub sp, sp, x0 98 mrs x0, tpidrro_el0 99 b el\el\ht\()_\regsize\()_\label 100.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? 101 .endm 102 103 .macro tramp_alias, dst, sym 104 .set .Lalias\@, TRAMP_VALIAS + \sym - .entry.tramp.text 105 movz \dst, :abs_g2_s:.Lalias\@ 106 movk \dst, :abs_g1_nc:.Lalias\@ 107 movk \dst, :abs_g0_nc:.Lalias\@ 108 .endm 109 110 /* 111 * This macro corrupts x0-x3. It is the caller's duty to save/restore 112 * them if required. 113 */ 114 .macro apply_ssbd, state, tmp1, tmp2 115alternative_cb ARM64_ALWAYS_SYSTEM, spectre_v4_patch_fw_mitigation_enable 116 b .L__asm_ssbd_skip\@ // Patched to NOP 117alternative_cb_end 118 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1 119 cbz \tmp2, .L__asm_ssbd_skip\@ 120 ldr \tmp2, [tsk, #TSK_TI_FLAGS] 121 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@ 122 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2 123 mov w1, #\state 124alternative_cb ARM64_ALWAYS_SYSTEM, smccc_patch_fw_mitigation_conduit 125 nop // Patched to SMC/HVC #0 126alternative_cb_end 127.L__asm_ssbd_skip\@: 128 .endm 129 130 /* Check for MTE asynchronous tag check faults */ 131 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr 132#ifdef CONFIG_ARM64_MTE 133 .arch_extension lse 134alternative_if_not ARM64_MTE 135 b 1f 136alternative_else_nop_endif 137 /* 138 * Asynchronous tag check faults are only possible in ASYNC (2) or 139 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is 140 * set, so skip the check if it is unset. 141 */ 142 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 143 mrs_s \tmp, SYS_TFSRE0_EL1 144 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f 145 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ 146 mov \tmp, #_TIF_MTE_ASYNC_FAULT 147 add \ti_flags, tsk, #TSK_TI_FLAGS 148 stset \tmp, [\ti_flags] 1491: 150#endif 151 .endm 152 153 /* Clear the MTE asynchronous tag check faults */ 154 .macro clear_mte_async_tcf thread_sctlr 155#ifdef CONFIG_ARM64_MTE 156alternative_if ARM64_MTE 157 /* See comment in check_mte_async_tcf above. */ 158 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f 159 dsb ish 160 msr_s SYS_TFSRE0_EL1, xzr 1611: 162alternative_else_nop_endif 163#endif 164 .endm 165 166 .macro mte_set_gcr, mte_ctrl, tmp 167#ifdef CONFIG_ARM64_MTE 168 ubfx \tmp, \mte_ctrl, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16 169 orr \tmp, \tmp, #SYS_GCR_EL1_RRND 170 msr_s SYS_GCR_EL1, \tmp 171#endif 172 .endm 173 174 .macro mte_set_kernel_gcr, tmp, tmp2 175#ifdef CONFIG_KASAN_HW_TAGS 176alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 177 b 1f 178alternative_cb_end 179 mov \tmp, KERNEL_GCR_EL1 180 msr_s SYS_GCR_EL1, \tmp 1811: 182#endif 183 .endm 184 185 .macro mte_set_user_gcr, tsk, tmp, tmp2 186#ifdef CONFIG_KASAN_HW_TAGS 187alternative_cb ARM64_ALWAYS_SYSTEM, kasan_hw_tags_enable 188 b 1f 189alternative_cb_end 190 ldr \tmp, [\tsk, #THREAD_MTE_CTRL] 191 192 mte_set_gcr \tmp, \tmp2 1931: 194#endif 195 .endm 196 197 .macro kernel_entry, el, regsize = 64 198 .if \el == 0 199 alternative_insn nop, SET_PSTATE_DIT(1), ARM64_HAS_DIT 200 .endif 201 .if \regsize == 32 202 mov w0, w0 // zero upper 32 bits of x0 203 .endif 204 stp x0, x1, [sp, #16 * 0] 205 stp x2, x3, [sp, #16 * 1] 206 stp x4, x5, [sp, #16 * 2] 207 stp x6, x7, [sp, #16 * 3] 208 stp x8, x9, [sp, #16 * 4] 209 stp x10, x11, [sp, #16 * 5] 210 stp x12, x13, [sp, #16 * 6] 211 stp x14, x15, [sp, #16 * 7] 212 stp x16, x17, [sp, #16 * 8] 213 stp x18, x19, [sp, #16 * 9] 214 stp x20, x21, [sp, #16 * 10] 215 stp x22, x23, [sp, #16 * 11] 216 stp x24, x25, [sp, #16 * 12] 217 stp x26, x27, [sp, #16 * 13] 218 stp x28, x29, [sp, #16 * 14] 219 220 .if \el == 0 221 clear_gp_regs 222 mrs x21, sp_el0 223 ldr_this_cpu tsk, __entry_task, x20 224 msr sp_el0, tsk 225 226 /* 227 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions 228 * when scheduling. 229 */ 230 ldr x19, [tsk, #TSK_TI_FLAGS] 231 disable_step_tsk x19, x20 232 233 /* Check for asynchronous tag check faults in user space */ 234 ldr x0, [tsk, THREAD_SCTLR_USER] 235 check_mte_async_tcf x22, x23, x0 236 237#ifdef CONFIG_ARM64_PTR_AUTH 238alternative_if ARM64_HAS_ADDRESS_AUTH 239 /* 240 * Enable IA for in-kernel PAC if the task had it disabled. Although 241 * this could be implemented with an unconditional MRS which would avoid 242 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76. 243 * 244 * Install the kernel IA key only if IA was enabled in the task. If IA 245 * was disabled on kernel exit then we would have left the kernel IA 246 * installed so there is no need to install it again. 247 */ 248 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 249 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23 250 b 2f 2511: 252 mrs x0, sctlr_el1 253 orr x0, x0, SCTLR_ELx_ENIA 254 msr sctlr_el1, x0 2552: 256alternative_else_nop_endif 257#endif 258 259 apply_ssbd 1, x22, x23 260 261 mte_set_kernel_gcr x22, x23 262 263 /* 264 * Any non-self-synchronizing system register updates required for 265 * kernel entry should be placed before this point. 266 */ 267alternative_if ARM64_MTE 268 isb 269 b 1f 270alternative_else_nop_endif 271alternative_if ARM64_HAS_ADDRESS_AUTH 272 isb 273alternative_else_nop_endif 2741: 275 276 scs_load_current_base 277 .else 278 add x21, sp, #PT_REGS_SIZE 279 get_current_task tsk 280 .endif /* \el == 0 */ 281 mrs x22, elr_el1 282 mrs x23, spsr_el1 283 stp lr, x21, [sp, #S_LR] 284 285 /* 286 * Create a metadata frame record. The unwinder will use this to 287 * identify and unwind exception boundaries. 288 */ 289 stp xzr, xzr, [sp, #S_STACKFRAME] 290 .if \el == 0 291 mov x0, #FRAME_META_TYPE_FINAL 292 .else 293 mov x0, #FRAME_META_TYPE_PT_REGS 294 .endif 295 str x0, [sp, #S_STACKFRAME_TYPE] 296 add x29, sp, #S_STACKFRAME 297 298#ifdef CONFIG_ARM64_SW_TTBR0_PAN 299alternative_if_not ARM64_HAS_PAN 300 bl __swpan_entry_el\el 301alternative_else_nop_endif 302#endif 303 304 stp x22, x23, [sp, #S_PC] 305 306 /* Not in a syscall by default (el0_svc overwrites for real syscall) */ 307 .if \el == 0 308 mov w21, #NO_SYSCALL 309 str w21, [sp, #S_SYSCALLNO] 310 .endif 311 312#ifdef CONFIG_ARM64_PSEUDO_NMI 313alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 314 b .Lskip_pmr_save\@ 315alternative_else_nop_endif 316 317 mrs_s x20, SYS_ICC_PMR_EL1 318 str w20, [sp, #S_PMR] 319 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET 320 msr_s SYS_ICC_PMR_EL1, x20 321 322.Lskip_pmr_save\@: 323#endif 324 325 /* 326 * Registers that may be useful after this macro is invoked: 327 * 328 * x20 - ICC_PMR_EL1 329 * x21 - aborted SP 330 * x22 - aborted PC 331 * x23 - aborted PSTATE 332 */ 333 .endm 334 335 .macro kernel_exit, el 336 .if \el != 0 337 disable_daif 338 .endif 339 340#ifdef CONFIG_ARM64_PSEUDO_NMI 341alternative_if_not ARM64_HAS_GIC_PRIO_MASKING 342 b .Lskip_pmr_restore\@ 343alternative_else_nop_endif 344 345 ldr w20, [sp, #S_PMR] 346 msr_s SYS_ICC_PMR_EL1, x20 347 348 /* Ensure priority change is seen by redistributor */ 349alternative_if_not ARM64_HAS_GIC_PRIO_RELAXED_SYNC 350 dsb sy 351alternative_else_nop_endif 352 353.Lskip_pmr_restore\@: 354#endif 355 356 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR 357 358#ifdef CONFIG_ARM64_SW_TTBR0_PAN 359alternative_if_not ARM64_HAS_PAN 360 bl __swpan_exit_el\el 361alternative_else_nop_endif 362#endif 363 364 .if \el == 0 365 ldr x23, [sp, #S_SP] // load return stack pointer 366 msr sp_el0, x23 367 tst x22, #PSR_MODE32_BIT // native task? 368 b.eq 3f 369 370#ifdef CONFIG_ARM64_ERRATUM_845719 371alternative_if ARM64_WORKAROUND_845719 372#ifdef CONFIG_PID_IN_CONTEXTIDR 373 mrs x29, contextidr_el1 374 msr contextidr_el1, x29 375#else 376 msr contextidr_el1, xzr 377#endif 378alternative_else_nop_endif 379#endif 3803: 381 /* Ignore asynchronous tag check faults in the uaccess routines */ 382 ldr x0, [tsk, THREAD_SCTLR_USER] 383 clear_mte_async_tcf x0 384 385#ifdef CONFIG_ARM64_PTR_AUTH 386alternative_if ARM64_HAS_ADDRESS_AUTH 387 /* 388 * IA was enabled for in-kernel PAC. Disable it now if needed, or 389 * alternatively install the user's IA. All other per-task keys and 390 * SCTLR bits were updated on task switch. 391 * 392 * No kernel C function calls after this. 393 */ 394 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f 395 __ptrauth_keys_install_user tsk, x0, x1, x2 396 b 2f 3971: 398 mrs x0, sctlr_el1 399 bic x0, x0, SCTLR_ELx_ENIA 400 msr sctlr_el1, x0 4012: 402alternative_else_nop_endif 403#endif 404 405 mte_set_user_gcr tsk, x0, x1 406 407 apply_ssbd 0, x0, x1 408 .endif 409 410 msr elr_el1, x21 // set up the return data 411 msr spsr_el1, x22 412 ldp x0, x1, [sp, #16 * 0] 413 ldp x2, x3, [sp, #16 * 1] 414 ldp x4, x5, [sp, #16 * 2] 415 ldp x6, x7, [sp, #16 * 3] 416 ldp x8, x9, [sp, #16 * 4] 417 ldp x10, x11, [sp, #16 * 5] 418 ldp x12, x13, [sp, #16 * 6] 419 ldp x14, x15, [sp, #16 * 7] 420 ldp x16, x17, [sp, #16 * 8] 421 ldp x18, x19, [sp, #16 * 9] 422 ldp x20, x21, [sp, #16 * 10] 423 ldp x22, x23, [sp, #16 * 11] 424 ldp x24, x25, [sp, #16 * 12] 425 ldp x26, x27, [sp, #16 * 13] 426 ldp x28, x29, [sp, #16 * 14] 427 428 .if \el == 0 429#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 430 alternative_insn "b .L_skip_tramp_exit_\@", nop, ARM64_UNMAP_KERNEL_AT_EL0 431 432 msr far_el1, x29 433 434 ldr_this_cpu x30, this_cpu_vector, x29 435 tramp_alias x29, tramp_exit 436 msr vbar_el1, x30 // install vector table 437 ldr lr, [sp, #S_LR] // restore x30 438 add sp, sp, #PT_REGS_SIZE // restore sp 439 br x29 440 441.L_skip_tramp_exit_\@: 442#endif 443 .endif 444 445 ldr lr, [sp, #S_LR] 446 add sp, sp, #PT_REGS_SIZE // restore sp 447 448 .if \el == 0 449 /* This must be after the last explicit memory access */ 450alternative_if ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 451 tlbi vale1, xzr 452 dsb nsh 453alternative_else_nop_endif 454 .else 455 /* Ensure any device/NC reads complete */ 456 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412 457 .endif 458 459 eret 460 sb 461 .endm 462 463#ifdef CONFIG_ARM64_SW_TTBR0_PAN 464 /* 465 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from 466 * EL0, there is no need to check the state of TTBR0_EL1 since 467 * accesses are always enabled. 468 * Note that the meaning of this bit differs from the ARMv8.1 PAN 469 * feature as all TTBR0_EL1 accesses are disabled, not just those to 470 * user mappings. 471 */ 472SYM_CODE_START_LOCAL(__swpan_entry_el1) 473 mrs x21, ttbr0_el1 474 tst x21, #TTBRx_EL1_ASID_MASK // Check for the reserved ASID 475 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR 476 b.eq 1f // TTBR0 access already disabled 477 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR 478SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL) 479 __uaccess_ttbr0_disable x21 4801: ret 481SYM_CODE_END(__swpan_entry_el1) 482 483 /* 484 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR 485 * PAN bit checking. 486 */ 487SYM_CODE_START_LOCAL(__swpan_exit_el1) 488 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set 489 __uaccess_ttbr0_enable x0, x1 4901: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit 491 ret 492SYM_CODE_END(__swpan_exit_el1) 493 494SYM_CODE_START_LOCAL(__swpan_exit_el0) 495 __uaccess_ttbr0_enable x0, x1 496 /* 497 * Enable errata workarounds only if returning to user. The only 498 * workaround currently required for TTBR0_EL1 changes are for the 499 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache 500 * corruption). 501 */ 502 b post_ttbr_update_workaround 503SYM_CODE_END(__swpan_exit_el0) 504#endif 505 506/* GPRs used by entry code */ 507tsk .req x28 // current thread_info 508 509 .text 510 511/* 512 * Exception vectors. 513 */ 514 .pushsection ".entry.text", "ax" 515 516 .align 11 517SYM_CODE_START(vectors) 518 kernel_ventry 1, t, 64, sync // Synchronous EL1t 519 kernel_ventry 1, t, 64, irq // IRQ EL1t 520 kernel_ventry 1, t, 64, fiq // FIQ EL1t 521 kernel_ventry 1, t, 64, error // Error EL1t 522 523 kernel_ventry 1, h, 64, sync // Synchronous EL1h 524 kernel_ventry 1, h, 64, irq // IRQ EL1h 525 kernel_ventry 1, h, 64, fiq // FIQ EL1h 526 kernel_ventry 1, h, 64, error // Error EL1h 527 528 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0 529 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0 530 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0 531 kernel_ventry 0, t, 64, error // Error 64-bit EL0 532 533 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0 534 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0 535 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0 536 kernel_ventry 0, t, 32, error // Error 32-bit EL0 537SYM_CODE_END(vectors) 538 539SYM_CODE_START_LOCAL(__bad_stack) 540 /* 541 * We detected an overflow in kernel_ventry, which switched to the 542 * overflow stack. Stash the exception regs, and head to our overflow 543 * handler. 544 */ 545 546 /* Restore the original x0 value */ 547 mrs x0, tpidrro_el0 548 549 /* 550 * Store the original GPRs to the new stack. The orginal SP (minus 551 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry. 552 */ 553 sub sp, sp, #PT_REGS_SIZE 554 kernel_entry 1 555 mrs x0, tpidr_el0 556 add x0, x0, #PT_REGS_SIZE 557 str x0, [sp, #S_SP] 558 559 /* Stash the regs for handle_bad_stack */ 560 mov x0, sp 561 562 /* Time to die */ 563 bl handle_bad_stack 564 ASM_BUG() 565SYM_CODE_END(__bad_stack) 566 567 568 .macro entry_handler el:req, ht:req, regsize:req, label:req 569SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label) 570 kernel_entry \el, \regsize 571 mov x0, sp 572 bl el\el\ht\()_\regsize\()_\label\()_handler 573 .if \el == 0 574 b ret_to_user 575 .else 576 b ret_to_kernel 577 .endif 578SYM_CODE_END(el\el\ht\()_\regsize\()_\label) 579 .endm 580 581/* 582 * Early exception handlers 583 */ 584 entry_handler 1, t, 64, sync 585 entry_handler 1, t, 64, irq 586 entry_handler 1, t, 64, fiq 587 entry_handler 1, t, 64, error 588 589 entry_handler 1, h, 64, sync 590 entry_handler 1, h, 64, irq 591 entry_handler 1, h, 64, fiq 592 entry_handler 1, h, 64, error 593 594 entry_handler 0, t, 64, sync 595 entry_handler 0, t, 64, irq 596 entry_handler 0, t, 64, fiq 597 entry_handler 0, t, 64, error 598 599 entry_handler 0, t, 32, sync 600 entry_handler 0, t, 32, irq 601 entry_handler 0, t, 32, fiq 602 entry_handler 0, t, 32, error 603 604SYM_CODE_START_LOCAL(ret_to_kernel) 605 kernel_exit 1 606SYM_CODE_END(ret_to_kernel) 607 608SYM_CODE_START_LOCAL(ret_to_user) 609 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step 610 enable_step_tsk x19, x2 611#ifdef CONFIG_KSTACK_ERASE 612 bl stackleak_erase_on_task_stack 613#endif 614 kernel_exit 0 615SYM_CODE_END(ret_to_user) 616 617 .popsection // .entry.text 618 619 // Move from tramp_pg_dir to swapper_pg_dir 620 .macro tramp_map_kernel, tmp 621 mrs \tmp, ttbr1_el1 622 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 623 bic \tmp, \tmp, #USER_ASID_FLAG 624 msr ttbr1_el1, \tmp 625#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 626alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 627 /* ASID already in \tmp[63:48] */ 628 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) 629 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) 630 /* 2MB boundary containing the vectors, so we nobble the walk cache */ 631 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12) 632 isb 633 tlbi vae1, \tmp 634 dsb nsh 635alternative_else_nop_endif 636#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ 637 .endm 638 639 // Move from swapper_pg_dir to tramp_pg_dir 640 .macro tramp_unmap_kernel, tmp 641 mrs \tmp, ttbr1_el1 642 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET 643 orr \tmp, \tmp, #USER_ASID_FLAG 644 msr ttbr1_el1, \tmp 645 /* 646 * We avoid running the post_ttbr_update_workaround here because 647 * it's only needed by Cavium ThunderX, which requires KPTI to be 648 * disabled. 649 */ 650 .endm 651 652 .macro tramp_data_read_var dst, var 653#ifdef CONFIG_RELOCATABLE 654 ldr \dst, .L__tramp_data_\var 655 .ifndef .L__tramp_data_\var 656 .pushsection ".entry.tramp.rodata", "a", %progbits 657 .align 3 658.L__tramp_data_\var: 659 .quad \var 660 .popsection 661 .endif 662#else 663 /* 664 * As !RELOCATABLE implies !RANDOMIZE_BASE the address is always a 665 * compile time constant (and hence not secret and not worth hiding). 666 * 667 * As statically allocated kernel code and data always live in the top 668 * 47 bits of the address space we can sign-extend bit 47 and avoid an 669 * instruction to load the upper 16 bits (which must be 0xFFFF). 670 */ 671 movz \dst, :abs_g2_s:\var 672 movk \dst, :abs_g1_nc:\var 673 movk \dst, :abs_g0_nc:\var 674#endif 675 .endm 676 677#define BHB_MITIGATION_NONE 0 678#define BHB_MITIGATION_LOOP 1 679#define BHB_MITIGATION_FW 2 680#define BHB_MITIGATION_INSN 3 681 682 .macro tramp_ventry, vector_start, regsize, kpti, bhb 683 .align 7 6841: 685 .if \regsize == 64 686 msr tpidrro_el0, x30 // Restored in kernel_ventry 687 .endif 688 689 .if \bhb == BHB_MITIGATION_LOOP 690 /* 691 * This sequence must appear before the first indirect branch. i.e. the 692 * ret out of tramp_ventry. It appears here because x30 is free. 693 */ 694 __mitigate_spectre_bhb_loop x30 695 .endif // \bhb == BHB_MITIGATION_LOOP 696 697 .if \bhb == BHB_MITIGATION_INSN 698 clearbhb 699 isb 700 .endif // \bhb == BHB_MITIGATION_INSN 701 702 .if \kpti == 1 703 /* 704 * Defend against branch aliasing attacks by pushing a dummy 705 * entry onto the return stack and using a RET instruction to 706 * enter the full-fat kernel vectors. 707 */ 708 bl 2f 709 b . 7102: 711 tramp_map_kernel x30 712alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 713 tramp_data_read_var x30, vectors 714alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 715 prfm plil1strm, [x30, #(1b - \vector_start)] 716alternative_else_nop_endif 717 718 msr vbar_el1, x30 719 isb 720 .else 721 adr_l x30, vectors 722 .endif // \kpti == 1 723 724 .if \bhb == BHB_MITIGATION_FW 725 /* 726 * The firmware sequence must appear before the first indirect branch. 727 * i.e. the ret out of tramp_ventry. But it also needs the stack to be 728 * mapped to save/restore the registers the SMC clobbers. 729 */ 730 __mitigate_spectre_bhb_fw 731 .endif // \bhb == BHB_MITIGATION_FW 732 733 add x30, x30, #(1b - \vector_start + 4) 734 ret 735.org 1b + 128 // Did we overflow the ventry slot? 736 .endm 737 738 .macro generate_tramp_vector, kpti, bhb 739.Lvector_start\@: 740 .space 0x400 741 742 .rept 4 743 tramp_ventry .Lvector_start\@, 64, \kpti, \bhb 744 .endr 745 .rept 4 746 tramp_ventry .Lvector_start\@, 32, \kpti, \bhb 747 .endr 748 .endm 749 750#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 751/* 752 * Exception vectors trampoline. 753 * The order must match __bp_harden_el1_vectors and the 754 * arm64_bp_harden_el1_vectors enum. 755 */ 756 .pushsection ".entry.tramp.text", "ax" 757 .align 11 758SYM_CODE_START_LOCAL_NOALIGN(tramp_vectors) 759#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 760 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP 761 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW 762 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN 763#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 764 generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE 765SYM_CODE_END(tramp_vectors) 766 767SYM_CODE_START_LOCAL(tramp_exit) 768 tramp_unmap_kernel x29 769 mrs x29, far_el1 // restore x29 770 eret 771 sb 772SYM_CODE_END(tramp_exit) 773 .popsection // .entry.tramp.text 774#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 775 776/* 777 * Exception vectors for spectre mitigations on entry from EL1 when 778 * kpti is not in use. 779 */ 780 .macro generate_el1_vector, bhb 781.Lvector_start\@: 782 kernel_ventry 1, t, 64, sync // Synchronous EL1t 783 kernel_ventry 1, t, 64, irq // IRQ EL1t 784 kernel_ventry 1, t, 64, fiq // FIQ EL1h 785 kernel_ventry 1, t, 64, error // Error EL1t 786 787 kernel_ventry 1, h, 64, sync // Synchronous EL1h 788 kernel_ventry 1, h, 64, irq // IRQ EL1h 789 kernel_ventry 1, h, 64, fiq // FIQ EL1h 790 kernel_ventry 1, h, 64, error // Error EL1h 791 792 .rept 4 793 tramp_ventry .Lvector_start\@, 64, 0, \bhb 794 .endr 795 .rept 4 796 tramp_ventry .Lvector_start\@, 32, 0, \bhb 797 .endr 798 .endm 799 800/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ 801 .pushsection ".entry.text", "ax" 802 .align 11 803SYM_CODE_START(__bp_harden_el1_vectors) 804#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY 805 generate_el1_vector bhb=BHB_MITIGATION_LOOP 806 generate_el1_vector bhb=BHB_MITIGATION_FW 807 generate_el1_vector bhb=BHB_MITIGATION_INSN 808#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ 809SYM_CODE_END(__bp_harden_el1_vectors) 810 .popsection 811 812 813/* 814 * Register switch for AArch64. The callee-saved registers need to be saved 815 * and restored. On entry: 816 * x0 = previous task_struct (must be preserved across the switch) 817 * x1 = next task_struct 818 * Previous and next are guaranteed not to be the same. 819 * 820 */ 821SYM_FUNC_START(cpu_switch_to) 822 save_and_disable_daif x11 823 mov x10, #THREAD_CPU_CONTEXT 824 add x8, x0, x10 825 mov x9, sp 826 stp x19, x20, [x8], #16 // store callee-saved registers 827 stp x21, x22, [x8], #16 828 stp x23, x24, [x8], #16 829 stp x25, x26, [x8], #16 830 stp x27, x28, [x8], #16 831 stp x29, x9, [x8], #16 832 str lr, [x8] 833 add x8, x1, x10 834 ldp x19, x20, [x8], #16 // restore callee-saved registers 835 ldp x21, x22, [x8], #16 836 ldp x23, x24, [x8], #16 837 ldp x25, x26, [x8], #16 838 ldp x27, x28, [x8], #16 839 ldp x29, x9, [x8], #16 840 ldr lr, [x8] 841 mov sp, x9 842 msr sp_el0, x1 843 ptrauth_keys_install_kernel x1, x8, x9, x10 844 scs_save x0 845 scs_load_current 846 restore_irq x11 847 ret 848SYM_FUNC_END(cpu_switch_to) 849NOKPROBE(cpu_switch_to) 850 851/* 852 * This is how we return from a fork. 853 */ 854SYM_CODE_START(ret_from_fork) 855 bl schedule_tail 856 cbz x19, 1f // not a kernel thread 857 mov x0, x20 858 blr x19 8591: get_current_task tsk 860 mov x0, sp 861 bl asm_exit_to_user_mode 862 b ret_to_user 863SYM_CODE_END(ret_from_fork) 864NOKPROBE(ret_from_fork) 865 866/* 867 * void call_on_irq_stack(struct pt_regs *regs, 868 * void (*func)(struct pt_regs *)); 869 * 870 * Calls func(regs) using this CPU's irq stack and shadow irq stack. 871 */ 872SYM_FUNC_START(call_on_irq_stack) 873 save_and_disable_daif x9 874#ifdef CONFIG_SHADOW_CALL_STACK 875 get_current_task x16 876 scs_save x16 877 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17 878#endif 879 880 /* Create a frame record to save our LR and SP (implicit in FP) */ 881 stp x29, x30, [sp, #-16]! 882 mov x29, sp 883 884 ldr_this_cpu x16, irq_stack_ptr, x17 885 886 /* Move to the new stack and call the function there */ 887 add sp, x16, #IRQ_STACK_SIZE 888 restore_irq x9 889 blr x1 890 891 save_and_disable_daif x9 892 /* 893 * Restore the SP from the FP, and restore the FP and LR from the frame 894 * record. 895 */ 896 mov sp, x29 897 ldp x29, x30, [sp], #16 898 scs_load_current 899 restore_irq x9 900 ret 901SYM_FUNC_END(call_on_irq_stack) 902NOKPROBE(call_on_irq_stack) 903 904#ifdef CONFIG_ARM_SDE_INTERFACE 905 906#include <asm/sdei.h> 907#include <uapi/linux/arm_sdei.h> 908 909.macro sdei_handler_exit exit_mode 910 /* On success, this call never returns... */ 911 cmp \exit_mode, #SDEI_EXIT_SMC 912 b.ne 99f 913 smc #0 914 b . 91599: hvc #0 916 b . 917.endm 918 919#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 920/* 921 * The regular SDEI entry point may have been unmapped along with the rest of 922 * the kernel. This trampoline restores the kernel mapping to make the x1 memory 923 * argument accessible. 924 * 925 * This clobbers x4, __sdei_handler() will restore this from firmware's 926 * copy. 927 */ 928.pushsection ".entry.tramp.text", "ax" 929SYM_CODE_START(__sdei_asm_entry_trampoline) 930 mrs x4, ttbr1_el1 931 tbz x4, #USER_ASID_BIT, 1f 932 933 tramp_map_kernel tmp=x4 934 isb 935 mov x4, xzr 936 937 /* 938 * Remember whether to unmap the kernel on exit. 939 */ 9401: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 941 tramp_data_read_var x4, __sdei_asm_handler 942 br x4 943SYM_CODE_END(__sdei_asm_entry_trampoline) 944NOKPROBE(__sdei_asm_entry_trampoline) 945 946/* 947 * Make the exit call and restore the original ttbr1_el1 948 * 949 * x0 & x1: setup for the exit API call 950 * x2: exit_mode 951 * x4: struct sdei_registered_event argument from registration time. 952 */ 953SYM_CODE_START(__sdei_asm_exit_trampoline) 954 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)] 955 cbnz x4, 1f 956 957 tramp_unmap_kernel tmp=x4 958 9591: sdei_handler_exit exit_mode=x2 960SYM_CODE_END(__sdei_asm_exit_trampoline) 961NOKPROBE(__sdei_asm_exit_trampoline) 962.popsection // .entry.tramp.text 963#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ 964 965/* 966 * Software Delegated Exception entry point. 967 * 968 * x0: Event number 969 * x1: struct sdei_registered_event argument from registration time. 970 * x2: interrupted PC 971 * x3: interrupted PSTATE 972 * x4: maybe clobbered by the trampoline 973 * 974 * Firmware has preserved x0->x17 for us, we must save/restore the rest to 975 * follow SMC-CC. We save (or retrieve) all the registers as the handler may 976 * want them. 977 */ 978SYM_CODE_START(__sdei_asm_handler) 979 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC] 980 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2] 981 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3] 982 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4] 983 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5] 984 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6] 985 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7] 986 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8] 987 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9] 988 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10] 989 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11] 990 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12] 991 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13] 992 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14] 993 mov x4, sp 994 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR] 995 996 mov x19, x1 997 998 /* Store the registered-event for crash_smp_send_stop() */ 999 ldrb w4, [x19, #SDEI_EVENT_PRIORITY] 1000 cbnz w4, 1f 1001 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 1002 b 2f 10031: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10042: str x19, [x5] 1005 1006 /* 1007 * entry.S may have been using sp as a scratch register, find whether 1008 * this is a normal or critical event and switch to the appropriate 1009 * stack for this CPU. 1010 */ 1011 cbnz w4, 1f 1012 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6 1013 b 2f 10141: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6 10152: mov x6, #SDEI_STACK_SIZE 1016 add x5, x5, x6 1017 mov sp, x5 1018 1019#ifdef CONFIG_SHADOW_CALL_STACK 1020 /* Use a separate shadow call stack for normal and critical events */ 1021 cbnz w4, 3f 1022 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6 1023 b 4f 10243: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6 10254: 1026#endif 1027 1028 /* 1029 * We may have interrupted userspace, or a guest, or exit-from or 1030 * return-to either of these. We can't trust sp_el0, restore it. 1031 */ 1032 mrs x28, sp_el0 1033 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1 1034 msr sp_el0, x0 1035 1036 /* If we interrupted the kernel point to the previous stack/frame. */ 1037 and x0, x3, #0xc 1038 mrs x1, CurrentEL 1039 cmp x0, x1 1040 csel x29, x29, xzr, eq // fp, or zero 1041 csel x4, x2, xzr, eq // elr, or zero 1042 1043 stp x29, x4, [sp, #-16]! 1044 mov x29, sp 1045 1046 add x0, x19, #SDEI_EVENT_INTREGS 1047 mov x1, x19 1048 bl __sdei_handler 1049 1050 msr sp_el0, x28 1051 /* restore regs >x17 that we clobbered */ 1052 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline 1053 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14] 1054 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9] 1055 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR] 1056 mov sp, x1 1057 1058 mov x1, x0 // address to complete_and_resume 1059 /* x0 = (x0 <= SDEI_EV_FAILED) ? 1060 * EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME 1061 */ 1062 cmp x0, #SDEI_EV_FAILED 1063 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE 1064 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1065 csel x0, x2, x3, ls 1066 1067 ldr_l x2, sdei_exit_mode 1068 1069 /* Clear the registered-event seen by crash_smp_send_stop() */ 1070 ldrb w3, [x4, #SDEI_EVENT_PRIORITY] 1071 cbnz w3, 1f 1072 adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6 1073 b 2f 10741: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6 10752: str xzr, [x5] 1076 1077alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 1078 sdei_handler_exit exit_mode=x2 1079alternative_else_nop_endif 1080 1081#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 1082 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline 1083 br x5 1084#endif 1085SYM_CODE_END(__sdei_asm_handler) 1086NOKPROBE(__sdei_asm_handler) 1087 1088SYM_CODE_START(__sdei_handler_abort) 1089 mov_q x0, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME 1090 adr x1, 1f 1091 ldr_l x2, sdei_exit_mode 1092 sdei_handler_exit exit_mode=x2 1093 // exit the handler and jump to the next instruction. 1094 // Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx. 10951: ret 1096SYM_CODE_END(__sdei_handler_abort) 1097NOKPROBE(__sdei_handler_abort) 1098#endif /* CONFIG_ARM_SDE_INTERFACE */ 1099