1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024-2025 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx94-clock.h" 12#include "imx94-pinfunc.h" 13#include "imx94-power.h" 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 osc_24m: clock-24m { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "osc_24m"; 25 }; 26 27 dummy: clock-dummy { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <0>; 31 clock-output-names = "dummy"; 32 }; 33 34 clk_ext1: clock-ext1 { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <133000000>; 38 clock-output-names = "clk_ext1"; 39 }; 40 41 sai1_mclk: clock-sai1-mclk1 { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 clock-output-names = "sai1_mclk"; 46 }; 47 48 sai2_mclk: clock-sai2-mclk1 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 clock-output-names = "sai2_mclk"; 53 }; 54 55 sai3_mclk: clock-sai3-mclk1 { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 clock-output-names = "sai3_mclk"; 60 }; 61 62 sai4_mclk: clock-sai4-mclk1 { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 clock-output-names = "sai4_mclk"; 67 }; 68 69 firmware { 70 scmi { 71 compatible = "arm,scmi"; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 75 shmem = <&scmi_buf0>, <&scmi_buf1>; 76 arm,max-rx-timeout-ms = <5000>; 77 78 scmi_devpd: protocol@11 { 79 reg = <0x11>; 80 #power-domain-cells = <1>; 81 }; 82 83 scmi_sys_power: protocol@12 { 84 reg = <0x12>; 85 }; 86 87 scmi_perf: protocol@13 { 88 reg = <0x13>; 89 #power-domain-cells = <1>; 90 }; 91 92 scmi_clk: protocol@14 { 93 reg = <0x14>; 94 #clock-cells = <1>; 95 }; 96 97 scmi_iomuxc: protocol@19 { 98 reg = <0x19>; 99 }; 100 101 scmi_bbm: protocol@81 { 102 reg = <0x81>; 103 }; 104 105 scmi_misc: protocol@84 { 106 reg = <0x84>; 107 }; 108 }; 109 }; 110 111 mqs1: mqs1 { 112 compatible = "fsl,imx943-aonmix-mqs"; 113 status = "disabled"; 114 }; 115 116 mqs2: mqs2 { 117 compatible = "fsl,imx943-wakeupmix-mqs"; 118 status = "disabled"; 119 }; 120 121 pmu { 122 compatible = "arm,cortex-a55-pmu"; 123 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 psci { 127 compatible = "arm,psci-1.0"; 128 method = "smc"; 129 }; 130 131 timer { 132 compatible = "arm,armv8-timer"; 133 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 134 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 136 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 137 clock-frequency = <24000000>; 138 interrupt-parent = <&gic>; 139 arm,no-tick-in-suspend; 140 }; 141 142 gic: interrupt-controller@48000000 { 143 compatible = "arm,gic-v3"; 144 reg = <0 0x48000000 0 0x10000>, 145 <0 0x48060000 0 0xc0000>; 146 ranges; 147 #interrupt-cells = <3>; 148 interrupt-controller; 149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <2>; 151 #size-cells = <2>; 152 dma-noncoherent; 153 interrupt-parent = <&gic>; 154 155 its: msi-controller@48040000 { 156 compatible = "arm,gic-v3-its"; 157 reg = <0 0x48040000 0 0x20000>; 158 #msi-cells = <1>; 159 dma-noncoherent; 160 msi-controller; 161 }; 162 }; 163 164 soc { 165 compatible = "simple-bus"; 166 ranges; 167 #address-cells = <2>; 168 #size-cells = <2>; 169 170 aips2: bus@42000000 { 171 compatible = "fsl,aips-bus", "simple-bus"; 172 reg = <0x0 0x42000000 0x0 0x800000>; 173 ranges = <0x42000000 0x0 0x42000000 0x8000000>; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 177 edma2: dma-controller@42000000 { 178 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; 179 reg = <0x42000000 0x210000>; 180 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 181 clock-names = "dma"; 182 #dma-cells = <3>; 183 dma-channels = <64>; 184 interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>, 185 <&a55_irqsteer 2>, <&a55_irqsteer 3>, 186 <&a55_irqsteer 4>, <&a55_irqsteer 5>, 187 <&a55_irqsteer 6>, <&a55_irqsteer 7>, 188 <&a55_irqsteer 8>, <&a55_irqsteer 9>, 189 <&a55_irqsteer 10>, <&a55_irqsteer 11>, 190 <&a55_irqsteer 12>, <&a55_irqsteer 13>, 191 <&a55_irqsteer 14>, <&a55_irqsteer 15>, 192 <&a55_irqsteer 16>, <&a55_irqsteer 17>, 193 <&a55_irqsteer 18>, <&a55_irqsteer 19>, 194 <&a55_irqsteer 20>, <&a55_irqsteer 21>, 195 <&a55_irqsteer 22>, <&a55_irqsteer 23>, 196 <&a55_irqsteer 24>, <&a55_irqsteer 25>, 197 <&a55_irqsteer 26>, <&a55_irqsteer 27>, 198 <&a55_irqsteer 28>, <&a55_irqsteer 29>, 199 <&a55_irqsteer 30>, <&a55_irqsteer 31>, 200 <&a55_irqsteer 64>, <&a55_irqsteer 65>, 201 <&a55_irqsteer 66>, <&a55_irqsteer 67>, 202 <&a55_irqsteer 68>, <&a55_irqsteer 69>, 203 <&a55_irqsteer 70>, <&a55_irqsteer 71>, 204 <&a55_irqsteer 72>, <&a55_irqsteer 73>, 205 <&a55_irqsteer 74>, <&a55_irqsteer 75>, 206 <&a55_irqsteer 76>, <&a55_irqsteer 77>, 207 <&a55_irqsteer 78>, <&a55_irqsteer 79>, 208 <&a55_irqsteer 80>, <&a55_irqsteer 81>, 209 <&a55_irqsteer 82>, <&a55_irqsteer 83>, 210 <&a55_irqsteer 84>, <&a55_irqsteer 85>, 211 <&a55_irqsteer 86>, <&a55_irqsteer 87>, 212 <&a55_irqsteer 88>, <&a55_irqsteer 89>, 213 <&a55_irqsteer 90>, <&a55_irqsteer 91>, 214 <&a55_irqsteer 92>, <&a55_irqsteer 93>, 215 <&a55_irqsteer 94>, <&a55_irqsteer 95>; 216 }; 217 218 mu10: mailbox@42430000 { 219 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 220 reg = <0x42430000 0x10000>; 221 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 223 #mbox-cells = <2>; 224 status = "disabled"; 225 }; 226 227 i3c2: i3c@42520000 { 228 compatible = "silvaco,i3c-master-v1"; 229 reg = <0x42520000 0x10000>; 230 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <3>; 232 #size-cells = <0>; 233 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 234 <&scmi_clk IMX94_CLK_I3C2SLOW>, 235 <&dummy>; 236 clock-names = "pclk", "fast_clk", "slow_clk"; 237 status = "disabled"; 238 }; 239 240 lpi2c3: i2c@42530000 { 241 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 242 reg = <0x42530000 0x10000>; 243 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 clocks = <&scmi_clk IMX94_CLK_LPI2C3>, 247 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 248 clock-names = "per", "ipg"; 249 dmas = <&edma2 5 0 0>, <&edma2 6 0 FSL_EDMA_RX>; 250 dma-names = "tx", "rx"; 251 status = "disabled"; 252 }; 253 254 lpi2c4: i2c@42540000 { 255 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 256 reg = <0x42540000 0x10000>; 257 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 clocks = <&scmi_clk IMX94_CLK_LPI2C4>, 261 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 262 clock-names = "per", "ipg"; 263 dmas = <&edma4 4 0 0>, <&edma4 5 0 FSL_EDMA_RX>; 264 dma-names = "tx", "rx"; 265 status = "disabled"; 266 }; 267 268 lpspi3: spi@42550000 { 269 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 270 reg = <0x42550000 0x10000>; 271 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 clocks = <&scmi_clk IMX94_CLK_LPSPI3>, 275 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 276 clock-names = "per", "ipg"; 277 dmas = <&edma2 7 0 0>, <&edma2 8 0 FSL_EDMA_RX>; 278 dma-names = "tx", "rx"; 279 status = "disabled"; 280 }; 281 282 lpspi4: spi@42560000 { 283 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 284 reg = <0x42560000 0x10000>; 285 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 clocks = <&scmi_clk IMX94_CLK_LPSPI4>, 289 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 290 clock-names = "per", "ipg"; 291 dmas = <&edma4 6 0 0>, <&edma4 7 0 FSL_EDMA_RX>; 292 dma-names = "tx", "rx"; 293 status = "disabled"; 294 }; 295 296 lpuart3: serial@42570000 { 297 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 298 "fsl,imx7ulp-lpuart"; 299 reg = <0x42570000 0x1000>; 300 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&scmi_clk IMX94_CLK_LPUART3>; 302 clock-names = "ipg"; 303 dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 9 0 0>; 304 dma-names = "rx", "tx"; 305 status = "disabled"; 306 }; 307 308 lpuart4: serial@42580000 { 309 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 310 "fsl,imx7ulp-lpuart"; 311 reg = <0x42580000 0x1000>; 312 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&scmi_clk IMX94_CLK_LPUART4>; 314 clock-names = "ipg"; 315 dmas = <&edma4 10 0 FSL_EDMA_RX>, <&edma4 9 0 0>; 316 dma-names = "rx", "tx"; 317 status = "disabled"; 318 }; 319 320 lpuart5: serial@42590000 { 321 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 322 "fsl,imx7ulp-lpuart"; 323 reg = <0x42590000 0x1000>; 324 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&scmi_clk IMX94_CLK_LPUART5>; 326 clock-names = "ipg"; 327 dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 11 0 0>; 328 dma-names = "rx", "tx"; 329 status = "disabled"; 330 }; 331 332 lpuart6: serial@425a0000 { 333 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 334 "fsl,imx7ulp-lpuart"; 335 reg = <0x425a0000 0x1000>; 336 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&scmi_clk IMX94_CLK_LPUART6>; 338 clock-names = "ipg"; 339 dmas = <&edma4 12 0 FSL_EDMA_RX>, <&edma4 11 0 0>; 340 dma-names = "rx", "tx"; 341 status = "disabled"; 342 }; 343 344 flexcan2: can@425b0000 { 345 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 346 reg = <0x425b0000 0x10000>; 347 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 349 <&scmi_clk IMX94_CLK_CAN2>; 350 clock-names = "ipg", "per"; 351 assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>; 352 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 353 assigned-clock-rates = <80000000>; 354 fsl,clk-source = /bits/ 8 <0>; 355 status = "disabled"; 356 }; 357 358 flexcan3: can@425e0000 { 359 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 360 reg = <0x425e0000 0x10000>; 361 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 363 <&scmi_clk IMX94_CLK_CAN3>; 364 clock-names = "ipg", "per"; 365 assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>; 366 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 367 assigned-clock-rates = <80000000>; 368 fsl,clk-source = /bits/ 8 <0>; 369 status = "disabled"; 370 }; 371 372 flexcan4: can@425f0000 { 373 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 374 reg = <0x425f0000 0x10000>; 375 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 377 <&scmi_clk IMX94_CLK_CAN4>; 378 clock-names = "ipg", "per"; 379 assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>; 380 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 381 assigned-clock-rates = <80000000>; 382 fsl,clk-source = /bits/ 8 <0>; 383 status = "disabled"; 384 }; 385 386 flexcan5: can@42600000 { 387 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 388 reg = <0x42600000 0x10000>; 389 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 391 <&scmi_clk IMX94_CLK_CAN5>; 392 clock-names = "ipg", "per"; 393 assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>; 394 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 395 assigned-clock-rates = <80000000>; 396 fsl,clk-source = /bits/ 8 <0>; 397 status = "disabled"; 398 }; 399 400 sai2: sai@42650000 { 401 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 402 reg = <0x42650000 0x10000>; 403 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 405 <&scmi_clk IMX94_CLK_SAI2>, <&dummy>, <&dummy>; 406 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 407 dmas = <&edma2 30 0 FSL_EDMA_RX>, <&edma2 29 0 0>; 408 dma-names = "rx", "tx"; 409 #sound-dai-cells = <0>; 410 status = "disabled"; 411 }; 412 413 sai3: sai@42660000 { 414 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 415 reg = <0x42660000 0x10000>; 416 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 418 <&scmi_clk IMX94_CLK_SAI3>, <&dummy>, <&dummy>; 419 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 420 dmas = <&edma2 32 0 FSL_EDMA_RX>, <&edma2 31 0 0>; 421 dma-names = "rx", "tx"; 422 #sound-dai-cells = <0>; 423 status = "disabled"; 424 }; 425 426 sai4: sai@42670000 { 427 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 428 reg = <0x42670000 0x10000>; 429 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 431 <&scmi_clk IMX94_CLK_SAI4>, <&dummy>, <&dummy>; 432 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 433 dmas = <&edma2 36 0 FSL_EDMA_RX>, <&edma2 35 0 0>; 434 dma-names = "rx", "tx"; 435 #sound-dai-cells = <0>; 436 status = "disabled"; 437 }; 438 439 lpuart7: serial@42690000 { 440 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 441 "fsl,imx7ulp-lpuart"; 442 reg = <0x42690000 0x1000>; 443 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&scmi_clk IMX94_CLK_LPUART7>; 445 clock-names = "ipg"; 446 dmas = <&edma2 46 0 FSL_EDMA_RX>, <&edma2 45 0 0>; 447 dma-names = "rx", "tx"; 448 status = "disabled"; 449 }; 450 451 lpuart8: serial@426a0000 { 452 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 453 "fsl,imx7ulp-lpuart"; 454 reg = <0x426a0000 0x1000>; 455 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&scmi_clk IMX94_CLK_LPUART8>; 457 clock-names = "ipg"; 458 dmas = <&edma4 39 0 FSL_EDMA_RX>, <&edma4 38 0 0>; 459 dma-names = "rx", "tx"; 460 status = "disabled"; 461 }; 462 463 lpi2c5: i2c@426b0000 { 464 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 465 reg = <0x426b0000 0x10000>; 466 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 clocks = <&scmi_clk IMX94_CLK_LPI2C5>, 470 <&scmi_clk IMX94_CLK_BUSAON>; 471 clock-names = "per", "ipg"; 472 dmas = <&edma2 37 0 0>, <&edma2 38 0 FSL_EDMA_RX>; 473 dma-names = "tx", "rx"; 474 status = "disabled"; 475 }; 476 477 lpi2c6: i2c@426c0000 { 478 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 479 reg = <0x426c0000 0x10000>; 480 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 clocks = <&scmi_clk IMX94_CLK_LPI2C6>, 484 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 485 clock-names = "per", "ipg"; 486 dmas = <&edma4 30 0 0>, <&edma4 31 0 FSL_EDMA_RX>; 487 dma-names = "tx", "rx"; 488 status = "disabled"; 489 }; 490 491 lpi2c7: i2c@426d0000 { 492 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 493 reg = <0x426d0000 0x10000>; 494 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 clocks = <&scmi_clk IMX94_CLK_LPI2C7>, 498 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 499 clock-names = "per", "ipg"; 500 dmas = <&edma2 39 0 0>, <&edma2 40 0 FSL_EDMA_RX>; 501 dma-names = "tx", "rx"; 502 status = "disabled"; 503 }; 504 505 lpi2c8: i2c@426e0000 { 506 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 507 reg = <0x426e0000 0x10000>; 508 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 clocks = <&scmi_clk IMX94_CLK_LPI2C8>, 512 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 513 clock-names = "per", "ipg"; 514 dmas = <&edma4 32 0 0>, <&edma4 33 0 FSL_EDMA_RX>; 515 dma-names = "tx", "rx"; 516 status = "disabled"; 517 }; 518 519 lpspi5: spi@426f0000 { 520 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 521 reg = <0x426f0000 0x10000>; 522 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 clocks = <&scmi_clk IMX94_CLK_LPSPI5>, 526 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 527 clock-names = "per", "ipg"; 528 dmas = <&edma2 41 0 0>, <&edma2 42 0 FSL_EDMA_RX>; 529 dma-names = "tx", "rx"; 530 status = "disabled"; 531 }; 532 533 lpspi6: spi@42700000 { 534 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 535 reg = <0x42700000 0x10000>; 536 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 clocks = <&scmi_clk IMX94_CLK_LPSPI6>, 540 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 541 clock-names = "per", "ipg"; 542 dmas = <&edma4 34 0 0>, <&edma4 35 0 FSL_EDMA_RX>; 543 dma-names = "tx", "rx"; 544 status = "disabled"; 545 }; 546 547 lpspi7: spi@42710000 { 548 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 549 reg = <0x42710000 0x10000>; 550 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 clocks = <&scmi_clk IMX94_CLK_LPSPI7>, 554 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 555 clock-names = "per", "ipg"; 556 dmas = <&edma2 43 0 0>, <&edma2 44 0 FSL_EDMA_RX>; 557 dma-names = "tx", "rx"; 558 status = "disabled"; 559 }; 560 561 lpspi8: spi@42720000 { 562 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 563 reg = <0x42720000 0x10000>; 564 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 clocks = <&scmi_clk IMX94_CLK_LPSPI8>, 568 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 569 clock-names = "per", "ipg"; 570 dmas = <&edma4 36 0 0>, <&edma4 37 0 FSL_EDMA_RX>; 571 dma-names = "tx", "rx"; 572 status = "disabled"; 573 }; 574 575 mu11: mailbox@42730000 { 576 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 577 reg = <0x42730000 0x10000>; 578 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 580 #mbox-cells = <2>; 581 status = "disabled"; 582 }; 583 584 edma4: dma-controller@42df0000 { 585 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; 586 reg = <0x42df0000 0x210000>; 587 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 588 clock-names = "dma"; 589 #dma-cells = <3>; 590 dma-channels = <64>; 591 interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>, 592 <&a55_irqsteer 130>, <&a55_irqsteer 131>, 593 <&a55_irqsteer 132>, <&a55_irqsteer 133>, 594 <&a55_irqsteer 134>, <&a55_irqsteer 135>, 595 <&a55_irqsteer 136>, <&a55_irqsteer 137>, 596 <&a55_irqsteer 138>, <&a55_irqsteer 139>, 597 <&a55_irqsteer 140>, <&a55_irqsteer 141>, 598 <&a55_irqsteer 142>, <&a55_irqsteer 143>, 599 <&a55_irqsteer 144>, <&a55_irqsteer 145>, 600 <&a55_irqsteer 146>, <&a55_irqsteer 147>, 601 <&a55_irqsteer 148>, <&a55_irqsteer 149>, 602 <&a55_irqsteer 150>, <&a55_irqsteer 151>, 603 <&a55_irqsteer 152>, <&a55_irqsteer 153>, 604 <&a55_irqsteer 154>, <&a55_irqsteer 155>, 605 <&a55_irqsteer 156>, <&a55_irqsteer 157>, 606 <&a55_irqsteer 158>, <&a55_irqsteer 159>, 607 <&a55_irqsteer 192>, <&a55_irqsteer 193>, 608 <&a55_irqsteer 194>, <&a55_irqsteer 195>, 609 <&a55_irqsteer 196>, <&a55_irqsteer 197>, 610 <&a55_irqsteer 198>, <&a55_irqsteer 199>, 611 <&a55_irqsteer 200>, <&a55_irqsteer 201>, 612 <&a55_irqsteer 202>, <&a55_irqsteer 203>, 613 <&a55_irqsteer 204>, <&a55_irqsteer 205>, 614 <&a55_irqsteer 206>, <&a55_irqsteer 207>, 615 <&a55_irqsteer 208>, <&a55_irqsteer 209>, 616 <&a55_irqsteer 210>, <&a55_irqsteer 211>, 617 <&a55_irqsteer 212>, <&a55_irqsteer 213>, 618 <&a55_irqsteer 214>, <&a55_irqsteer 215>, 619 <&a55_irqsteer 216>, <&a55_irqsteer 217>, 620 <&a55_irqsteer 218>, <&a55_irqsteer 219>, 621 <&a55_irqsteer 220>, <&a55_irqsteer 221>, 622 <&a55_irqsteer 222>, <&a55_irqsteer 223>; 623 }; 624 }; 625 626 aips3: bus@42800000 { 627 compatible = "fsl,aips-bus", "simple-bus"; 628 reg = <0 0x42800000 0 0x800000>; 629 ranges = <0x42800000 0x0 0x42800000 0x800000>, 630 <0x28000000 0x0 0x28000000 0x1000000>; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 634 usdhc1: mmc@42850000 { 635 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 636 reg = <0x42850000 0x10000>; 637 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 639 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 640 <&scmi_clk IMX94_CLK_USDHC1>; 641 clock-names = "ipg", "ahb", "per"; 642 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>; 643 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 644 assigned-clock-rates = <400000000>; 645 bus-width = <8>; 646 fsl,tuning-start-tap = <1>; 647 fsl,tuning-step = <2>; 648 status = "disabled"; 649 }; 650 651 usdhc2: mmc@42860000 { 652 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 653 reg = <0x42860000 0x10000>; 654 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 656 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 657 <&scmi_clk IMX94_CLK_USDHC2>; 658 clock-names = "ipg", "ahb", "per"; 659 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>; 660 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 661 assigned-clock-rates = <200000000>; 662 bus-width = <4>; 663 fsl,tuning-start-tap = <1>; 664 fsl,tuning-step = <2>; 665 status = "disabled"; 666 }; 667 668 usdhc3: mmc@42880000 { 669 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 670 reg = <0x42880000 0x10000>; 671 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 673 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 674 <&scmi_clk IMX94_CLK_USDHC3>; 675 clock-names = "ipg", "ahb", "per"; 676 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>; 677 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 678 assigned-clock-rates = <200000000>; 679 bus-width = <4>; 680 fsl,tuning-start-tap = <1>; 681 fsl,tuning-step = <2>; 682 status = "disabled"; 683 }; 684 685 lpuart9: serial@42a50000 { 686 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 687 "fsl,imx7ulp-lpuart"; 688 reg = <0x42a50000 0x1000>; 689 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&scmi_clk IMX94_CLK_LPUART10>; 691 clock-names = "ipg"; 692 dmas = <&edma2 51 0 FSL_EDMA_RX>, <&edma2 50 0 0>; 693 dma-names = "rx", "tx"; 694 status = "disabled"; 695 }; 696 697 lpuart10: serial@42a60000 { 698 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 699 "fsl,imx7ulp-lpuart"; 700 reg = <0x42a60000 0x1000>; 701 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&scmi_clk IMX94_CLK_LPUART10>; 703 clock-names = "ipg"; 704 dmas = <&edma4 47 0 FSL_EDMA_RX>, <&edma4 46 0 0>; 705 dma-names = "rx", "tx"; 706 status = "disabled"; 707 }; 708 709 lpuart11: serial@42a70000 { 710 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 711 "fsl,imx7ulp-lpuart"; 712 reg = <0x42a70000 0x1000>; 713 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&scmi_clk IMX94_CLK_LPUART11>; 715 clock-names = "ipg"; 716 dmas = <&edma2 53 0 FSL_EDMA_RX>, <&edma2 52 0 0>; 717 dma-names = "rx", "tx"; 718 status = "disabled"; 719 }; 720 721 lpuart12: serial@42a80000 { 722 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 723 "fsl,imx7ulp-lpuart"; 724 reg = <0x42a80000 0x1000>; 725 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&scmi_clk IMX94_CLK_LPUART12>; 727 clock-names = "ipg"; 728 dmas = <&edma4 49 0 FSL_EDMA_RX>, <&edma4 48 0 0>; 729 dma-names = "rx", "tx"; 730 status = "disabled"; 731 }; 732 733 mu12: mailbox@42ac0000 { 734 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 735 reg = <0x42ac0000 0x10000>; 736 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 738 #mbox-cells = <2>; 739 status = "disabled"; 740 }; 741 742 mu13: mailbox@42ae0000 { 743 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 744 reg = <0x42ae0000 0x10000>; 745 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 747 #mbox-cells = <2>; 748 status = "disabled"; 749 }; 750 751 mu14: mailbox@42b00000 { 752 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 753 reg = <0x42b00000 0x10000>; 754 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 756 #mbox-cells = <2>; 757 status = "disabled"; 758 }; 759 760 mu15: mailbox@42b20000 { 761 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 762 reg = <0x42b20000 0x10000>; 763 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 765 #mbox-cells = <2>; 766 status = "disabled"; 767 }; 768 769 mu16: mailbox@42b40000 { 770 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 771 reg = <0x42b40000 0x10000>; 772 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 774 #mbox-cells = <2>; 775 status = "disabled"; 776 }; 777 778 mu17: mailbox@42b60000 { 779 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 780 reg = <0x42b60000 0x10000>; 781 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 783 #mbox-cells = <2>; 784 status = "disabled"; 785 }; 786 }; 787 788 gpio2: gpio@43810000 { 789 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 790 reg = <0x0 0x43810000 0x0 0x1000>; 791 #interrupt-cells = <2>; 792 interrupt-controller; 793 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 795 #gpio-cells = <2>; 796 gpio-controller; 797 gpio-ranges = <&scmi_iomuxc 0 4 32>; 798 ngpios = <32>; 799 }; 800 801 gpio3: gpio@43820000 { 802 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 803 reg = <0x0 0x43820000 0x0 0x1000>; 804 #interrupt-cells = <2>; 805 interrupt-controller; 806 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 808 #gpio-cells = <2>; 809 gpio-controller; 810 gpio-ranges = <&scmi_iomuxc 0 36 26>; 811 ngpios = <26>; 812 }; 813 814 gpio4: gpio@43840000 { 815 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 816 reg = <0x0 0x43840000 0x0 0x1000>; 817 #interrupt-cells = <2>; 818 interrupt-controller; 819 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 821 #gpio-cells = <2>; 822 gpio-controller; 823 gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>, 824 <&scmi_iomuxc 8 140 12>, <&scmi_iomuxc 20 164 12>; 825 ngpios = <32>; 826 }; 827 828 gpio5: gpio@43850000 { 829 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 830 reg = <0x0 0x43850000 0x0 0x1000>; 831 #interrupt-cells = <2>; 832 interrupt-controller; 833 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 835 #gpio-cells = <2>; 836 gpio-controller; 837 gpio-ranges = <&scmi_iomuxc 0 108 32>; 838 ngpios = <32>; 839 }; 840 841 gpio6: gpio@43860000 { 842 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 843 reg = <0x0 0x43860000 0x0 0x1000>; 844 #interrupt-cells = <2>; 845 interrupt-controller; 846 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 848 #gpio-cells = <2>; 849 gpio-controller; 850 gpio-ranges = <&scmi_iomuxc 0 66 32>; 851 ngpios = <32>; 852 }; 853 854 gpio7: gpio@43870000 { 855 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 856 reg = <0x0 0x43870000 0x0 0x1000>; 857 #interrupt-cells = <2>; 858 interrupt-controller; 859 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 861 #gpio-cells = <2>; 862 gpio-controller; 863 gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>; 864 gpio-reserved-ranges = <10 6>; 865 ngpios = <28>; 866 }; 867 868 aips1: bus@44000000 { 869 compatible = "fsl,aips-bus", "simple-bus"; 870 reg = <0x0 0x44000000 0x0 0x800000>; 871 ranges = <0x44000000 0x0 0x44000000 0x800000>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 875 edma1: dma-controller@44000000 { 876 compatible = "fsl,imx94-edma3", "fsl,imx93-edma3"; 877 reg = <0x44000000 0x210000>; 878 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 912 clock-names = "dma"; 913 #dma-cells = <3>; 914 dma-channels = <32>; 915 }; 916 917 mu1: mailbox@44220000 { 918 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 919 reg = <0x44220000 0x10000>; 920 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 922 #mbox-cells = <2>; 923 status = "disabled"; 924 }; 925 926 system_counter: timer@44290000 { 927 compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer"; 928 reg = <0x44290000 0x30000>; 929 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&osc_24m>; 931 clock-names = "per"; 932 nxp,no-divider; 933 }; 934 935 tpm1: pwm@44310000 { 936 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; 937 reg = <0x44310000 0x1000>; 938 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 939 #pwm-cells = <3>; 940 status = "disabled"; 941 }; 942 943 tpm2: pwm@44320000 { 944 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; 945 reg = <0x44320000 0x1000>; 946 clocks = <&scmi_clk IMX94_CLK_TPM2>; 947 #pwm-cells = <3>; 948 status = "disabled"; 949 }; 950 951 i3c1: i3c@44330000 { 952 compatible = "silvaco,i3c-master-v1"; 953 reg = <0x44330000 0x10000>; 954 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 955 #address-cells = <3>; 956 #size-cells = <0>; 957 clocks = <&scmi_clk IMX94_CLK_BUSAON>, 958 <&scmi_clk IMX94_CLK_I3C1SLOW>, 959 <&dummy>; 960 clock-names = "pclk", "fast_clk", "slow_clk"; 961 status = "disabled"; 962 }; 963 964 lpi2c1: i2c@44340000 { 965 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 966 reg = <0x44340000 0x10000>; 967 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 clocks = <&scmi_clk IMX94_CLK_LPI2C1>, 971 <&scmi_clk IMX94_CLK_BUSAON>; 972 clock-names = "per", "ipg"; 973 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX>; 974 dma-names = "tx", "rx"; 975 status = "disabled"; 976 }; 977 978 lpi2c2: i2c@44350000 { 979 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 980 reg = <0x44350000 0x10000>; 981 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 clocks = <&scmi_clk IMX94_CLK_LPI2C2>, 985 <&scmi_clk IMX94_CLK_BUSAON>; 986 clock-names = "per", "ipg"; 987 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX>; 988 dma-names = "tx", "rx"; 989 status = "disabled"; 990 }; 991 992 lpspi1: spi@44360000 { 993 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 994 reg = <0x44360000 0x10000>; 995 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 clocks = <&scmi_clk IMX94_CLK_LPSPI2>, 999 <&scmi_clk IMX94_CLK_BUSAON>; 1000 clock-names = "per", "ipg"; 1001 dmas = <&edma1 16 0 0>, <&edma1 17 0 FSL_EDMA_RX>; 1002 dma-names = "tx", "rx"; 1003 status = "disabled"; 1004 }; 1005 1006 lpspi2: spi@44370000 { 1007 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 1008 reg = <0x44370000 0x10000>; 1009 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1010 #address-cells = <1>; 1011 #size-cells = <0>; 1012 clocks = <&scmi_clk IMX94_CLK_LPSPI2>, 1013 <&scmi_clk IMX94_CLK_BUSAON>; 1014 clock-names = "per", "ipg"; 1015 dmas = <&edma1 18 0 0>, <&edma1 19 0 FSL_EDMA_RX>; 1016 dma-names = "tx", "rx"; 1017 status = "disabled"; 1018 }; 1019 1020 lpuart1: serial@44380000 { 1021 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 1022 "fsl,imx7ulp-lpuart"; 1023 reg = <0x44380000 0x1000>; 1024 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&scmi_clk IMX94_CLK_LPUART1>; 1026 clock-names = "ipg"; 1027 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1028 dma-names = "rx", "tx"; 1029 status = "disabled"; 1030 }; 1031 1032 lpuart2: serial@44390000 { 1033 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 1034 "fsl,imx7ulp-lpuart"; 1035 reg = <0x44390000 0x1000>; 1036 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&scmi_clk IMX94_CLK_LPUART2>; 1038 clock-names = "ipg"; 1039 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1040 dma-names = "rx", "tx"; 1041 status = "disabled"; 1042 }; 1043 1044 flexcan1: can@443a0000 { 1045 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 1046 reg = <0x443a0000 0x10000>; 1047 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&scmi_clk IMX94_CLK_BUSAON>, 1049 <&scmi_clk IMX94_CLK_CAN1>; 1050 clock-names = "ipg", "per"; 1051 assigned-clocks = <&scmi_clk IMX94_CLK_CAN1>; 1052 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 1053 assigned-clock-rates = <80000000>; 1054 fsl,clk-source = /bits/ 8 <0>; 1055 status = "disabled"; 1056 }; 1057 1058 sai1: sai@443b0000 { 1059 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 1060 reg = <0x443b0000 0x10000>; 1061 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&scmi_clk IMX94_CLK_BUSAON>, <&dummy>, 1063 <&scmi_clk IMX94_CLK_SAI1>, <&dummy>, 1064 <&dummy>, <&dummy>; 1065 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1066 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1067 dma-names = "rx", "tx"; 1068 #sound-dai-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 micfil: micfil@44520000 { 1073 compatible = "fsl,imx943-micfil"; 1074 reg = <0x44520000 0x10000>; 1075 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1079 clocks = <&scmi_clk IMX94_CLK_BUSAON>, 1080 <&scmi_clk IMX94_CLK_PDM>, 1081 <&scmi_clk IMX94_CLK_AUDIOPLL1>, 1082 <&scmi_clk IMX94_CLK_AUDIOPLL2>, 1083 <&dummy>; 1084 clock-names = "ipg_clk", "ipg_clk_app", 1085 "pll8k", "pll11k", "clkext3"; 1086 dmas = <&edma1 6 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>; 1087 dma-names = "rx"; 1088 #sound-dai-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 adc1: adc@44530000 { 1093 compatible = "nxp,imx94-adc", "nxp,imx93-adc"; 1094 reg = <0x44530000 0x10000>; 1095 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&scmi_clk IMX94_CLK_ADC>; 1099 clock-names = "ipg"; 1100 #io-channel-cells = <1>; 1101 status = "disabled"; 1102 }; 1103 1104 mu2: mailbox@445b0000 { 1105 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1106 reg = <0x445b0000 0x1000>; 1107 ranges; 1108 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 1109 #address-cells = <1>; 1110 #size-cells = <1>; 1111 #mbox-cells = <2>; 1112 1113 sram0: sram@445b1000 { 1114 compatible = "mmio-sram"; 1115 reg = <0x445b1000 0x400>; 1116 ranges = <0x0 0x445b1000 0x400>; 1117 #address-cells = <1>; 1118 #size-cells = <1>; 1119 1120 scmi_buf0: scmi-sram-section@0 { 1121 compatible = "arm,scmi-shmem"; 1122 reg = <0x0 0x80>; 1123 }; 1124 1125 scmi_buf1: scmi-sram-section@80 { 1126 compatible = "arm,scmi-shmem"; 1127 reg = <0x80 0x80>; 1128 }; 1129 }; 1130 }; 1131 1132 mu3: mailbox@445d0000 { 1133 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1134 reg = <0x445d0000 0x10000>; 1135 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1136 #mbox-cells = <2>; 1137 status = "disabled"; 1138 }; 1139 1140 mu4: mailbox@445f0000 { 1141 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1142 reg = <0x445f0000 0x10000>; 1143 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1144 #mbox-cells = <2>; 1145 status = "disabled"; 1146 }; 1147 1148 mu6: mailbox@44630000 { 1149 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1150 reg = <0x44630000 0x10000>; 1151 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1152 #mbox-cells = <2>; 1153 status = "disabled"; 1154 }; 1155 1156 a55_irqsteer: interrupt-controller@446a0000 { 1157 compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer"; 1158 reg = <0x446a0000 0x1000>; 1159 #interrupt-cells = <1>; 1160 interrupt-controller; 1161 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1167 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 1168 clock-names = "ipg"; 1169 fsl,channel = <0>; 1170 fsl,num-irqs = <960>; 1171 }; 1172 }; 1173 1174 aips4: bus@49000000 { 1175 compatible = "fsl,aips-bus", "simple-bus"; 1176 reg = <0x0 0x49000000 0x0 0x800000>; 1177 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1178 #address-cells = <1>; 1179 #size-cells = <1>; 1180 1181 wdog3: watchdog@49220000 { 1182 compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; 1183 reg = <0x49220000 0x10000>; 1184 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 1186 timeout-sec = <40>; 1187 fsl,ext-reset-output; 1188 status = "disabled"; 1189 }; 1190 }; 1191 }; 1192}; 1193