1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Based on Ocelot Linux port, which is
4 * Copyright 2001 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * Copyright 2003 ICT CAS
8 * Author: Michael Guo <guoyi@ict.ac.cn>
9 *
10 * Copyright (C) 2007 Lemote Inc. & Institute of Computing Technology
11 * Author: Fuxin Zhang, zhangfx@lemote.com
12 *
13 * Copyright (C) 2009 Lemote Inc.
14 * Author: Wu Zhangjin, wuzhangjin@gmail.com
15 */
16
17 #include <linux/dma-map-ops.h>
18 #include <linux/export.h>
19 #include <linux/libfdt.h>
20 #include <linux/minmax.h>
21 #include <linux/pci_ids.h>
22 #include <linux/serial_core.h>
23 #include <linux/string_choices.h>
24 #include <asm/bootinfo.h>
25 #include <loongson.h>
26 #include <boot_param.h>
27 #include <builtin_dtbs.h>
28 #include <workarounds.h>
29
30 #define HOST_BRIDGE_CONFIG_ADDR ((void __iomem *)TO_UNCAC(0x1a000000))
31
32 u32 cpu_clock_freq;
33 EXPORT_SYMBOL(cpu_clock_freq);
34 struct efi_memory_map_loongson *loongson_memmap;
35 struct loongson_system_configuration loongson_sysconf;
36
37 struct board_devices *eboard;
38 struct interface_info *einter;
39 struct loongson_special_attribute *especial;
40
41 u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
42 u64 loongson_chiptemp[MAX_PACKAGES];
43 u64 loongson_freqctrl[MAX_PACKAGES];
44
45 unsigned long long smp_group[4];
46
get_system_type(void)47 const char *get_system_type(void)
48 {
49 return "Generic Loongson64 System";
50 }
51
52
prom_dtb_init_env(void)53 void __init prom_dtb_init_env(void)
54 {
55 if ((fw_arg2 < CKSEG0 || fw_arg2 > CKSEG1)
56 && (fw_arg2 < XKPHYS || fw_arg2 > XKSEG))
57
58 loongson_fdt_blob = __dtb_loongson64_2core_2k1000_begin;
59 else
60 loongson_fdt_blob = (void *)fw_arg2;
61 }
62
lefi_fixup_fdt_serial(void * fdt,u64 uart_addr,u32 uart_clk)63 static int __init lefi_fixup_fdt_serial(void *fdt, u64 uart_addr, u32 uart_clk)
64 {
65 int node, len, depth = -1;
66 const fdt64_t *reg;
67 fdt32_t *clk;
68
69 for (node = fdt_next_node(fdt, -1, &depth);
70 node >= 0 && depth >= 0;
71 node = fdt_next_node(fdt, node, &depth)) {
72 reg = fdt_getprop(fdt, node, "reg", &len);
73 if (!reg || len <= 8 || fdt64_ld(reg) != uart_addr)
74 continue;
75
76 clk = fdt_getprop_w(fdt, node, "clock-frequency", &len);
77 if (!clk) {
78 pr_warn("UART 0x%llx misses clock-frequency property\n",
79 uart_addr);
80 return -ENOENT;
81 } else if (len != 4) {
82 pr_warn("UART 0x%llx has invalid clock-frequency property\n",
83 uart_addr);
84 return -EINVAL;
85 }
86
87 fdt32_st(clk, uart_clk);
88
89 return 0;
90 }
91
92 return -ENODEV;
93 }
94
lefi_fixup_fdt(struct system_loongson * system)95 static void __init lefi_fixup_fdt(struct system_loongson *system)
96 {
97 static unsigned char fdt_buf[16 << 10] __initdata;
98 struct uart_device *uartdev;
99 bool is_loongson64g;
100 u64 uart_base;
101 int ret, i;
102
103 ret = fdt_open_into(loongson_fdt_blob, fdt_buf, sizeof(fdt_buf));
104 if (ret) {
105 pr_err("Failed to open FDT to fix up\n");
106 return;
107 }
108
109 is_loongson64g = (read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G;
110
111 for (i = 0; i < min(system->nr_uarts, MAX_UARTS); i++) {
112 uartdev = &system->uarts[i];
113
114 /*
115 * Some firmware does not set nr_uarts properly and passes empty
116 * items. Ignore them silently.
117 */
118 if (uartdev->uart_base == 0)
119 continue;
120
121 /* Our DT only works with UPIO_MEM. */
122 if (uartdev->iotype != UPIO_MEM) {
123 pr_warn("Ignore UART 0x%llx with iotype %u passed by firmware\n",
124 uartdev->uart_base, uartdev->iotype);
125 continue;
126 }
127
128 ret = lefi_fixup_fdt_serial(fdt_buf, uartdev->uart_base,
129 uartdev->uartclk);
130 /*
131 * LOONGSON64G's CPU serials are mapped to two different
132 * addresses, one full-featured but differs from
133 * previous generations, one fully compatible with them.
134 *
135 * It's unspecified that which mapping should uart_base refer
136 * to, thus we should try fixing up with both.
137 */
138 if (ret == -ENODEV && is_loongson64g) {
139 switch (uartdev->uart_base) {
140 case 0x1fe00100:
141 uart_base = 0x1fe001e0;
142 break;
143 case 0x1fe00110:
144 uart_base = 0x1fe001e8;
145 break;
146 case 0x1fe001e0:
147 uart_base = 0x1fe00100;
148 break;
149 case 0x1fe001e8:
150 uart_base = 0x1fe00110;
151 break;
152 default:
153 pr_err("Unexpected UART address 0x%llx passed by firmware\n",
154 uartdev->uart_base);
155 ret = -EINVAL;
156 goto err_fixup;
157 }
158
159 ret = lefi_fixup_fdt_serial(fdt_buf, uart_base,
160 uartdev->uartclk);
161 }
162
163 err_fixup:
164 if (ret)
165 pr_err("Couldn't fix up FDT node for UART 0x%llx\n",
166 uartdev->uart_base);
167 }
168
169 loongson_fdt_blob = fdt_buf;
170 }
171
prom_lefi_init_env(void)172 void __init prom_lefi_init_env(void)
173 {
174 struct boot_params *boot_p;
175 struct loongson_params *loongson_p;
176 struct system_loongson *esys;
177 struct efi_cpuinfo_loongson *ecpu;
178 struct irq_source_routing_table *eirq_source;
179 u32 id;
180 u16 vendor;
181
182 /* firmware arguments are initialized in head.S */
183 boot_p = (struct boot_params *)fw_arg2;
184 loongson_p = &(boot_p->efi.smbios.lp);
185
186 esys = (struct system_loongson *)
187 ((u64)loongson_p + loongson_p->system_offset);
188 ecpu = (struct efi_cpuinfo_loongson *)
189 ((u64)loongson_p + loongson_p->cpu_offset);
190 eboard = (struct board_devices *)
191 ((u64)loongson_p + loongson_p->boarddev_table_offset);
192 einter = (struct interface_info *)
193 ((u64)loongson_p + loongson_p->interface_offset);
194 especial = (struct loongson_special_attribute *)
195 ((u64)loongson_p + loongson_p->special_offset);
196 eirq_source = (struct irq_source_routing_table *)
197 ((u64)loongson_p + loongson_p->irq_offset);
198 loongson_memmap = (struct efi_memory_map_loongson *)
199 ((u64)loongson_p + loongson_p->memory_offset);
200
201 cpu_clock_freq = ecpu->cpu_clock_freq;
202 loongson_sysconf.cputype = ecpu->cputype;
203 switch (ecpu->cputype) {
204 case Legacy_2K:
205 case Loongson_2K:
206 smp_group[0] = 0x900000001fe11000;
207 loongson_sysconf.cores_per_node = 2;
208 loongson_sysconf.cores_per_package = 2;
209 break;
210 case Legacy_3A:
211 case Loongson_3A:
212 loongson_sysconf.cores_per_node = 4;
213 loongson_sysconf.cores_per_package = 4;
214 smp_group[0] = 0x900000003ff01000;
215 smp_group[1] = 0x900010003ff01000;
216 smp_group[2] = 0x900020003ff01000;
217 smp_group[3] = 0x900030003ff01000;
218 loongson_chipcfg[0] = 0x900000001fe00180;
219 loongson_chipcfg[1] = 0x900010001fe00180;
220 loongson_chipcfg[2] = 0x900020001fe00180;
221 loongson_chipcfg[3] = 0x900030001fe00180;
222 loongson_chiptemp[0] = 0x900000001fe0019c;
223 loongson_chiptemp[1] = 0x900010001fe0019c;
224 loongson_chiptemp[2] = 0x900020001fe0019c;
225 loongson_chiptemp[3] = 0x900030001fe0019c;
226 loongson_freqctrl[0] = 0x900000001fe001d0;
227 loongson_freqctrl[1] = 0x900010001fe001d0;
228 loongson_freqctrl[2] = 0x900020001fe001d0;
229 loongson_freqctrl[3] = 0x900030001fe001d0;
230 loongson_sysconf.workarounds = WORKAROUND_CPUFREQ;
231 break;
232 case Legacy_3B:
233 case Loongson_3B:
234 loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
235 loongson_sysconf.cores_per_package = 8;
236 smp_group[0] = 0x900000003ff01000;
237 smp_group[1] = 0x900010003ff05000;
238 smp_group[2] = 0x900020003ff09000;
239 smp_group[3] = 0x900030003ff0d000;
240 loongson_chipcfg[0] = 0x900000001fe00180;
241 loongson_chipcfg[1] = 0x900020001fe00180;
242 loongson_chipcfg[2] = 0x900040001fe00180;
243 loongson_chipcfg[3] = 0x900060001fe00180;
244 loongson_chiptemp[0] = 0x900000001fe0019c;
245 loongson_chiptemp[1] = 0x900020001fe0019c;
246 loongson_chiptemp[2] = 0x900040001fe0019c;
247 loongson_chiptemp[3] = 0x900060001fe0019c;
248 loongson_freqctrl[0] = 0x900000001fe001d0;
249 loongson_freqctrl[1] = 0x900020001fe001d0;
250 loongson_freqctrl[2] = 0x900040001fe001d0;
251 loongson_freqctrl[3] = 0x900060001fe001d0;
252 loongson_sysconf.workarounds = WORKAROUND_CPUHOTPLUG;
253 break;
254 default:
255 loongson_sysconf.cores_per_node = 1;
256 loongson_sysconf.cores_per_package = 1;
257 loongson_chipcfg[0] = 0x900000001fe00180;
258 }
259
260 loongson_sysconf.nr_cpus = ecpu->nr_cpus;
261 loongson_sysconf.boot_cpu_id = ecpu->cpu_startup_core_id;
262 loongson_sysconf.reserved_cpus_mask = ecpu->reserved_cores_mask;
263 if (ecpu->nr_cpus > NR_CPUS || ecpu->nr_cpus == 0)
264 loongson_sysconf.nr_cpus = NR_CPUS;
265 loongson_sysconf.nr_nodes = (loongson_sysconf.nr_cpus +
266 loongson_sysconf.cores_per_node - 1) /
267 loongson_sysconf.cores_per_node;
268
269 loongson_sysconf.dma_mask_bits = eirq_source->dma_mask_bits;
270 if (loongson_sysconf.dma_mask_bits < 32 ||
271 loongson_sysconf.dma_mask_bits > 64) {
272 loongson_sysconf.dma_mask_bits = 32;
273 dma_default_coherent = true;
274 } else {
275 dma_default_coherent = !eirq_source->dma_noncoherent;
276 }
277
278 pr_info("Firmware: Coherent DMA: %s\n", str_on_off(dma_default_coherent));
279
280 loongson_sysconf.restart_addr = boot_p->reset_system.ResetWarm;
281 loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
282 loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;
283
284 loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
285 pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
286 loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
287 loongson_sysconf.vgabios_addr);
288
289 loongson_sysconf.workarounds |= esys->workarounds;
290
291 pr_info("CpuClock = %u\n", cpu_clock_freq);
292
293 /* Read the ID of PCI host bridge to detect bridge type */
294 id = readl(HOST_BRIDGE_CONFIG_ADDR);
295 vendor = id & 0xffff;
296
297 switch (vendor) {
298 case PCI_VENDOR_ID_LOONGSON:
299 pr_info("The bridge chip is LS7A\n");
300 loongson_sysconf.bridgetype = LS7A;
301 loongson_sysconf.early_config = ls7a_early_config;
302 break;
303 case PCI_VENDOR_ID_AMD:
304 case PCI_VENDOR_ID_ATI:
305 pr_info("The bridge chip is RS780E or SR5690\n");
306 loongson_sysconf.bridgetype = RS780E;
307 loongson_sysconf.early_config = rs780e_early_config;
308 break;
309 default:
310 pr_info("The bridge chip is VIRTUAL\n");
311 loongson_sysconf.bridgetype = VIRTUAL;
312 loongson_sysconf.early_config = virtual_early_config;
313 loongson_fdt_blob = __dtb_loongson64v_4core_virtio_begin;
314 break;
315 }
316
317 if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
318 switch (read_c0_prid() & PRID_REV_MASK) {
319 case PRID_REV_LOONGSON3A_R1:
320 case PRID_REV_LOONGSON3A_R2_0:
321 case PRID_REV_LOONGSON3A_R2_1:
322 case PRID_REV_LOONGSON3A_R3_0:
323 case PRID_REV_LOONGSON3A_R3_1:
324 switch (loongson_sysconf.bridgetype) {
325 case LS7A:
326 loongson_fdt_blob = __dtb_loongson64c_4core_ls7a_begin;
327 break;
328 case RS780E:
329 loongson_fdt_blob = __dtb_loongson64c_4core_rs780e_begin;
330 break;
331 default:
332 break;
333 }
334 break;
335 case PRID_REV_LOONGSON3B_R1:
336 case PRID_REV_LOONGSON3B_R2:
337 if (loongson_sysconf.bridgetype == RS780E)
338 loongson_fdt_blob = __dtb_loongson64c_8core_rs780e_begin;
339 break;
340 default:
341 break;
342 }
343 } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) {
344 loongson_fdt_blob = __dtb_loongson64_2core_2k1000_begin;
345 } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
346 if (loongson_sysconf.bridgetype == LS7A)
347 loongson_fdt_blob = __dtb_loongson64g_4core_ls7a_begin;
348 }
349
350 if (!loongson_fdt_blob)
351 pr_err("Failed to determine built-in Loongson64 dtb\n");
352 else
353 lefi_fixup_fdt(esys);
354 }
355