1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <drm/display/drm_dsc_helper.h>
27
28 #include "reg_helper.h"
29 #include "dcn20_dsc.h"
30 #include "dsc/dscc_types.h"
31 #include "dsc/rc_calc.h"
32
33 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
34
35 static const struct dsc_funcs dcn20_dsc_funcs = {
36 .dsc_get_enc_caps = dsc2_get_enc_caps,
37 .dsc_read_state = dsc2_read_state,
38 .dsc_validate_stream = dsc2_validate_stream,
39 .dsc_set_config = dsc2_set_config,
40 .dsc_get_packed_pps = dsc2_get_packed_pps,
41 .dsc_enable = dsc2_enable,
42 .dsc_disable = dsc2_disable,
43 .dsc_disconnect = dsc2_disconnect,
44 .dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,
45 };
46
47 /* Macro definitios for REG_SET macros*/
48 #define CTX \
49 dsc20->base.ctx
50
51 #define REG(reg)\
52 dsc20->dsc_regs->reg
53
54 #undef FN
55 #define FN(reg_name, field_name) \
56 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name
57 #define DC_LOGGER \
58 dsc->ctx->logger
59
60 /* API functions (external or via structure->function_pointer) */
61
dsc2_construct(struct dcn20_dsc * dsc,struct dc_context * ctx,int inst,const struct dcn20_dsc_registers * dsc_regs,const struct dcn20_dsc_shift * dsc_shift,const struct dcn20_dsc_mask * dsc_mask)62 void dsc2_construct(struct dcn20_dsc *dsc,
63 struct dc_context *ctx,
64 int inst,
65 const struct dcn20_dsc_registers *dsc_regs,
66 const struct dcn20_dsc_shift *dsc_shift,
67 const struct dcn20_dsc_mask *dsc_mask)
68 {
69 dsc->base.ctx = ctx;
70 dsc->base.inst = inst;
71 dsc->base.funcs = &dcn20_dsc_funcs;
72
73 dsc->dsc_regs = dsc_regs;
74 dsc->dsc_shift = dsc_shift;
75 dsc->dsc_mask = dsc_mask;
76
77 dsc->max_image_width = 5184;
78 }
79
80
81 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188
82 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200
83
84 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput
85 * can be doubled, tripled etc. by using additional DSC engines.
86 */
dsc2_get_enc_caps(struct dsc_enc_caps * dsc_enc_caps,int pixel_clock_100Hz)87 void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
88 {
89 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */
90
91 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;
92 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;
93 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;
94 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;
95
96 dsc_enc_caps->lb_bit_depth = 13;
97 dsc_enc_caps->is_block_pred_supported = true;
98
99 dsc_enc_caps->color_formats.bits.RGB = 1;
100 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
101 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
102 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
103 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
104
105 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;
106 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;
107 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;
108
109 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it.
110 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices.
111 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always
112 * be sufficient to process the input pixel rate fed into a single DSC engine.
113 */
114 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;
115
116 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our
117 * throughput and number of slices, but also introduces a lower limit of 2 slices
118 */
119 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) {
120 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;
121 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;
122 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;
123 }
124
125 /* For pixel clock bigger than a single-pipe limit needing four engines ODM 4:1, which then quardruples our
126 * throughput and number of slices
127 */
128 if (pixel_clock_100Hz > DCN20_MAX_PIXEL_CLOCK_Mhz*10000*2) {
129 dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;
130 dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;
131 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4;
132 }
133
134 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */
135 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */
136 }
137
138
139 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
140 * into a dcn_dsc_state struct.
141 */
dsc2_read_state(struct display_stream_compressor * dsc,struct dcn_dsc_state * s)142 void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
143 {
144 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
145
146 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en);
147 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width);
148 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bits_per_pixel);
149 REG_GET(DSCC_PPS_CONFIG3, SLICE_HEIGHT, &s->dsc_slice_height);
150 REG_GET(DSCC_PPS_CONFIG1, CHUNK_SIZE, &s->dsc_chunk_size);
151 REG_GET(DSCC_PPS_CONFIG2, PIC_WIDTH, &s->dsc_pic_width);
152 REG_GET(DSCC_PPS_CONFIG2, PIC_HEIGHT, &s->dsc_pic_height);
153 REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
154 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
155 DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
156 }
157
158
dsc2_validate_stream(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg)159 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
160 {
161 struct dsc_optc_config dsc_optc_cfg;
162 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
163
164 if (dsc_cfg->pic_width > dsc20->max_image_width)
165 return false;
166
167 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg);
168 }
169
170
dsc_config_log(struct display_stream_compressor * dsc,const struct dsc_config * config)171 void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)
172 {
173 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h);
174 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v);
175 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)",
176 config->dc_dsc_cfg.bits_per_pixel,
177 config->dc_dsc_cfg.bits_per_pixel / 16,
178 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16);
179 DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
180 }
181
dsc2_set_config(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,struct dsc_optc_config * dsc_optc_cfg)182 void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
183 struct dsc_optc_config *dsc_optc_cfg)
184 {
185 bool is_config_ok;
186 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
187
188 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
189 dsc_config_log(dsc, dsc_cfg);
190 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg);
191 ASSERT(is_config_ok);
192 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
193 dsc_log_pps(dsc, &dsc20->reg_vals.pps);
194 dsc_write_to_registers(dsc, &dsc20->reg_vals);
195 }
196
197
dsc2_get_packed_pps(struct display_stream_compressor * dsc,const struct dsc_config * dsc_cfg,uint8_t * dsc_packed_pps)198 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)
199 {
200 bool is_config_ok;
201 struct dsc_reg_values dsc_reg_vals;
202 struct dsc_optc_config dsc_optc_cfg;
203
204 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals));
205 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg));
206
207 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:");
208 dsc_config_log(dsc, dsc_cfg);
209 DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
210 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg);
211 ASSERT(is_config_ok);
212 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps);
213 dsc_log_pps(dsc, &dsc_reg_vals.pps);
214
215 return is_config_ok;
216 }
217
218
dsc2_enable(struct display_stream_compressor * dsc,int opp_pipe)219 void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
220 {
221 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
222 int dsc_clock_en;
223 int dsc_fw_config;
224 int enabled_opp_pipe;
225
226 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
227
228 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
229 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
230 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
231 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
232 ASSERT(0);
233 }
234
235 REG_UPDATE(DSC_TOP_CONTROL,
236 DSC_CLOCK_EN, 1);
237
238 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
239 DSCRM_DSC_FORWARD_EN, 1,
240 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
241 }
242
243
dsc2_disable(struct display_stream_compressor * dsc)244 void dsc2_disable(struct display_stream_compressor *dsc)
245 {
246 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
247 int dsc_clock_en;
248
249 DC_LOG_DSC("disable DSC %d", dsc->inst);
250
251 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
252 if (!dsc_clock_en) {
253 DC_LOG_DSC("DSC %d already disabled!", dsc->inst);
254 }
255
256 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
257 DSCRM_DSC_FORWARD_EN, 0);
258
259 REG_UPDATE(DSC_TOP_CONTROL,
260 DSC_CLOCK_EN, 0);
261 }
262
dsc2_wait_disconnect_pending_clear(struct display_stream_compressor * dsc)263 void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
264 {
265 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
266
267 REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000);
268 }
269
dsc2_disconnect(struct display_stream_compressor * dsc)270 void dsc2_disconnect(struct display_stream_compressor *dsc)
271 {
272 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
273
274 DC_LOG_DSC("disconnect DSC %d", dsc->inst);
275
276 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG,
277 DSCRM_DSC_FORWARD_EN, 0);
278 }
279
280 /* This module's internal functions */
dsc_log_pps(struct display_stream_compressor * dsc,struct drm_dsc_config * pps)281 void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps)
282 {
283 int i;
284 int bits_per_pixel = pps->bits_per_pixel;
285
286 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
287 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor);
288 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component);
289 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth);
290 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable);
291 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
292 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
293 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
294 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16);
295 DC_LOG_DSC("\tpic_height %d", pps->pic_height);
296 DC_LOG_DSC("\tpic_width %d", pps->pic_width);
297 DC_LOG_DSC("\tslice_height %d", pps->slice_height);
298 DC_LOG_DSC("\tslice_width %d", pps->slice_width);
299 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
300 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay);
301 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay);
302 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value);
303 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval);
304 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval);
305 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset);
306 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset);
307 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
308 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
309 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset);
310 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp);
311 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp);
312 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */
313 DC_LOG_DSC("\tnative_420 %d", pps->native_420);
314 DC_LOG_DSC("\tnative_422 %d", pps->native_422);
315 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset);
316 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset);
317 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj);
318 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size);
319 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor);
320 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
321 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
322 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high);
323 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low);
324
325 for (i = 0; i < NUM_BUF_RANGES - 1; i++)
326 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]);
327
328 for (i = 0; i < NUM_BUF_RANGES; i++) {
329 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp);
330 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp);
331 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
332 }
333 }
334
dsc_override_rc_params(struct rc_params * rc,const struct dc_dsc_rc_params_override * override)335 void dsc_override_rc_params(struct rc_params *rc, const struct dc_dsc_rc_params_override *override)
336 {
337 uint8_t i;
338
339 rc->rc_model_size = override->rc_model_size;
340 for (i = 0; i < DC_DSC_RC_BUF_THRESH_SIZE; i++)
341 rc->rc_buf_thresh[i] = override->rc_buf_thresh[i];
342 for (i = 0; i < DC_DSC_QP_SET_SIZE; i++) {
343 rc->qp_min[i] = override->rc_minqp[i];
344 rc->qp_max[i] = override->rc_maxqp[i];
345 rc->ofs[i] = override->rc_offset[i];
346 }
347
348 rc->rc_tgt_offset_hi = override->rc_tgt_offset_hi;
349 rc->rc_tgt_offset_lo = override->rc_tgt_offset_lo;
350 rc->rc_edge_factor = override->rc_edge_factor;
351 rc->rc_quant_incr_limit0 = override->rc_quant_incr_limit0;
352 rc->rc_quant_incr_limit1 = override->rc_quant_incr_limit1;
353
354 rc->initial_fullness_offset = override->initial_fullness_offset;
355 rc->initial_xmit_delay = override->initial_delay;
356
357 rc->flatness_min_qp = override->flatness_min_qp;
358 rc->flatness_max_qp = override->flatness_max_qp;
359 rc->flatness_det_thresh = override->flatness_det_thresh;
360 }
361
dsc_prepare_config(const struct dsc_config * dsc_cfg,struct dsc_reg_values * dsc_reg_vals,struct dsc_optc_config * dsc_optc_cfg)362 bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,
363 struct dsc_optc_config *dsc_optc_cfg)
364 {
365 struct dsc_parameters dsc_params;
366 struct rc_params rc;
367
368 /* Validate input parameters */
369 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h);
370 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v);
371 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2);
372 ASSERT(dsc_cfg->pic_width);
373 ASSERT(dsc_cfg->pic_height);
374 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 &&
375 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) ||
376 (dsc_cfg->dc_dsc_cfg.version_minor == 2 &&
377 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
378 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0)));
379 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375
380
381 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h ||
382 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) ||
383 !dsc_cfg->pic_width || !dsc_cfg->pic_height ||
384 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range:
385 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) ||
386 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range:
387 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) ||
388 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) ||
389 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) {
390 dm_output_to_console("%s: Invalid parameters\n", __func__);
391 return false;
392 }
393
394 dsc_init_reg_values(dsc_reg_vals);
395
396 /* Copy input config */
397 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
398 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
399 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
400 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
401 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
402 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
403 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
404 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
405 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
406 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
407 dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;
408
409 // TODO: in addition to validating slice height (pic height must be divisible by slice height),
410 // see what happens when the same condition doesn't apply for slice_width/pic_width.
411 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
412 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
413
414 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
415 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
416 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
417 return false;
418 }
419
420 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
421 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
422 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
423 else
424 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
425
426 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
427 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
428 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420);
429 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422);
430
431 calc_rc_params(&rc, &dsc_reg_vals->pps);
432
433 if (dsc_cfg->dc_dsc_cfg.rc_params_ovrd)
434 dsc_override_rc_params(&rc, dsc_cfg->dc_dsc_cfg.rc_params_ovrd);
435
436 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &rc, &dsc_params)) {
437 dm_output_to_console("%s: DSC config failed\n", __func__);
438 return false;
439 }
440
441 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params);
442
443 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel;
444 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width;
445 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ||
446 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 ||
447 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422;
448
449 return true;
450 }
451
452
dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc,bool is_ycbcr422_simple)453 enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple)
454 {
455 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
456
457 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */
458
459 switch (dc_pix_enc) {
460 case PIXEL_ENCODING_RGB:
461 dsc_pix_fmt = DSC_PIXFMT_RGB;
462 break;
463 case PIXEL_ENCODING_YCBCR422:
464 if (is_ycbcr422_simple)
465 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422;
466 else
467 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422;
468 break;
469 case PIXEL_ENCODING_YCBCR444:
470 dsc_pix_fmt = DSC_PIXFMT_YCBCR444;
471 break;
472 case PIXEL_ENCODING_YCBCR420:
473 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420;
474 break;
475 default:
476 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN;
477 break;
478 }
479
480 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN);
481 return dsc_pix_fmt;
482 }
483
484
dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)485 enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth)
486 {
487 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN;
488
489 switch (dc_color_depth) {
490 case COLOR_DEPTH_888:
491 bpc = DSC_BPC_8;
492 break;
493 case COLOR_DEPTH_101010:
494 bpc = DSC_BPC_10;
495 break;
496 case COLOR_DEPTH_121212:
497 bpc = DSC_BPC_12;
498 break;
499 default:
500 bpc = DSC_BPC_UNKNOWN;
501 break;
502 }
503
504 return bpc;
505 }
506
507
dsc_init_reg_values(struct dsc_reg_values * reg_vals)508 void dsc_init_reg_values(struct dsc_reg_values *reg_vals)
509 {
510 int i;
511
512 memset(reg_vals, 0, sizeof(struct dsc_reg_values));
513
514 /* Non-PPS values */
515 reg_vals->dsc_clock_enable = 1;
516 reg_vals->dsc_clock_gating_disable = 0;
517 reg_vals->underflow_recovery_en = 0;
518 reg_vals->underflow_occurred_int_en = 0;
519 reg_vals->underflow_occurred_status = 0;
520 reg_vals->ich_reset_at_eol = 0;
521 reg_vals->alternate_ich_encoding_en = 0;
522 reg_vals->rc_buffer_model_size = 0;
523 /*reg_vals->disable_ich = 0;*/
524 reg_vals->dsc_dbg_en = 0;
525
526 for (i = 0; i < 4; i++)
527 reg_vals->rc_buffer_model_overflow_int_en[i] = 0;
528
529 /* PPS values */
530 reg_vals->pps.dsc_version_minor = 2;
531 reg_vals->pps.dsc_version_major = 1;
532 reg_vals->pps.line_buf_depth = 9;
533 reg_vals->pps.bits_per_component = 8;
534 reg_vals->pps.block_pred_enable = 1;
535 reg_vals->pps.slice_chunk_size = 0;
536 reg_vals->pps.pic_width = 0;
537 reg_vals->pps.pic_height = 0;
538 reg_vals->pps.slice_width = 0;
539 reg_vals->pps.slice_height = 0;
540 reg_vals->pps.initial_xmit_delay = 170;
541 reg_vals->pps.initial_dec_delay = 0;
542 reg_vals->pps.initial_scale_value = 0;
543 reg_vals->pps.scale_increment_interval = 0;
544 reg_vals->pps.scale_decrement_interval = 0;
545 reg_vals->pps.nfl_bpg_offset = 0;
546 reg_vals->pps.slice_bpg_offset = 0;
547 reg_vals->pps.nsl_bpg_offset = 0;
548 reg_vals->pps.initial_offset = 6144;
549 reg_vals->pps.final_offset = 0;
550 reg_vals->pps.flatness_min_qp = 3;
551 reg_vals->pps.flatness_max_qp = 12;
552 reg_vals->pps.rc_model_size = 8192;
553 reg_vals->pps.rc_edge_factor = 6;
554 reg_vals->pps.rc_quant_incr_limit0 = 11;
555 reg_vals->pps.rc_quant_incr_limit1 = 11;
556 reg_vals->pps.rc_tgt_offset_low = 3;
557 reg_vals->pps.rc_tgt_offset_high = 3;
558 }
559
560 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params.
561 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn
562 * affects non-PPS register values.
563 */
dsc_update_from_dsc_parameters(struct dsc_reg_values * reg_vals,const struct dsc_parameters * dsc_params)564 void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)
565 {
566 int i;
567
568 reg_vals->pps = dsc_params->pps;
569
570 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs.
571 for (i = 0; i < NUM_BUF_RANGES - 1; i++)
572 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6;
573
574 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size;
575 }
576
dsc_write_to_registers(struct display_stream_compressor * dsc,const struct dsc_reg_values * reg_vals)577 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)
578 {
579 uint32_t temp_int;
580 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
581
582 REG_SET(DSC_DEBUG_CONTROL, 0,
583 DSC_DBG_EN, reg_vals->dsc_dbg_en);
584
585 // dsccif registers
586 REG_SET_5(DSCCIF_CONFIG0, 0,
587 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en,
588 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en,
589 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status,
590 INPUT_PIXEL_FORMAT, reg_vals->pixel_format,
591 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
592
593 REG_SET_2(DSCCIF_CONFIG1, 0,
594 PIC_WIDTH, reg_vals->pps.pic_width,
595 PIC_HEIGHT, reg_vals->pps.pic_height);
596
597 // dscc registers
598 if (dsc20->dsc_mask->ICH_RESET_AT_END_OF_LINE == 0) {
599 REG_SET_3(DSCC_CONFIG0, 0,
600 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1,
601 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en,
602 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1);
603 } else {
604 REG_SET_4(DSCC_CONFIG0, 0, ICH_RESET_AT_END_OF_LINE,
605 reg_vals->ich_reset_at_eol, NUMBER_OF_SLICES_PER_LINE,
606 reg_vals->num_slices_h - 1, ALTERNATE_ICH_ENCODING_EN,
607 reg_vals->alternate_ich_encoding_en, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION,
608 reg_vals->num_slices_v - 1);
609 }
610
611 REG_SET(DSCC_CONFIG1, 0,
612 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size);
613 /*REG_SET_2(DSCC_CONFIG1, 0,
614 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size,
615 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/
616
617 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0,
618 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0],
619 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1],
620 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2],
621 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]);
622
623 REG_SET_3(DSCC_PPS_CONFIG0, 0,
624 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor,
625 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth,
626 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component);
627
628 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
629 temp_int = reg_vals->bpp_x32;
630 else
631 temp_int = reg_vals->bpp_x32 >> 1;
632
633 REG_SET_7(DSCC_PPS_CONFIG1, 0,
634 BITS_PER_PIXEL, temp_int,
635 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422,
636 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB,
637 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable,
638 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422,
639 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420,
640 CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
641
642 REG_SET_2(DSCC_PPS_CONFIG2, 0,
643 PIC_WIDTH, reg_vals->pps.pic_width,
644 PIC_HEIGHT, reg_vals->pps.pic_height);
645
646 REG_SET_2(DSCC_PPS_CONFIG3, 0,
647 SLICE_WIDTH, reg_vals->pps.slice_width,
648 SLICE_HEIGHT, reg_vals->pps.slice_height);
649
650 REG_SET(DSCC_PPS_CONFIG4, 0,
651 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay);
652
653 REG_SET_2(DSCC_PPS_CONFIG5, 0,
654 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value,
655 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval);
656
657 REG_SET_3(DSCC_PPS_CONFIG6, 0,
658 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval,
659 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset,
660 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset);
661
662 REG_SET_2(DSCC_PPS_CONFIG7, 0,
663 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset,
664 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
665
666 REG_SET_2(DSCC_PPS_CONFIG8, 0,
667 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset,
668 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj);
669
670 REG_SET_2(DSCC_PPS_CONFIG9, 0,
671 INITIAL_OFFSET, reg_vals->pps.initial_offset,
672 FINAL_OFFSET, reg_vals->pps.final_offset);
673
674 REG_SET_3(DSCC_PPS_CONFIG10, 0,
675 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp,
676 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp,
677 RC_MODEL_SIZE, reg_vals->pps.rc_model_size);
678
679 REG_SET_5(DSCC_PPS_CONFIG11, 0,
680 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor,
681 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
682 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
683 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low,
684 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high);
685
686 REG_SET_4(DSCC_PPS_CONFIG12, 0,
687 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0],
688 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1],
689 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2],
690 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]);
691
692 REG_SET_4(DSCC_PPS_CONFIG13, 0,
693 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4],
694 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5],
695 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6],
696 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]);
697
698 REG_SET_4(DSCC_PPS_CONFIG14, 0,
699 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8],
700 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9],
701 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10],
702 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]);
703
704 REG_SET_5(DSCC_PPS_CONFIG15, 0,
705 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12],
706 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13],
707 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp,
708 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp,
709 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
710
711 REG_SET_6(DSCC_PPS_CONFIG16, 0,
712 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp,
713 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp,
714 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
715 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp,
716 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp,
717 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
718
719 REG_SET_6(DSCC_PPS_CONFIG17, 0,
720 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp,
721 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp,
722 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
723 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp,
724 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp,
725 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
726
727 REG_SET_6(DSCC_PPS_CONFIG18, 0,
728 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp,
729 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp,
730 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
731 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp,
732 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp,
733 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
734
735 REG_SET_6(DSCC_PPS_CONFIG19, 0,
736 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp,
737 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp,
738 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
739 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp,
740 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp,
741 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
742
743 REG_SET_6(DSCC_PPS_CONFIG20, 0,
744 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp,
745 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp,
746 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
747 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp,
748 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp,
749 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
750
751 REG_SET_6(DSCC_PPS_CONFIG21, 0,
752 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp,
753 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp,
754 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
755 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp,
756 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp,
757 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
758
759 REG_SET_6(DSCC_PPS_CONFIG22, 0,
760 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp,
761 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp,
762 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
763 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp,
764 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp,
765 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
766
767 }
768