1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 status = "fail"; 317 }; 318 319 dmic_codec: dmic-codec { 320 compatible = "dmic-codec"; 321 num-channels = <2>; 322 wakeup-delay-ms = <50>; 323 }; 324 325 sound: mt8195-sound { 326 mediatek,platform = <&afe>; 327 status = "disabled"; 328 }; 329 330 clk13m: fixed-factor-clock-13m { 331 compatible = "fixed-factor-clock"; 332 #clock-cells = <0>; 333 clocks = <&clk26m>; 334 clock-div = <2>; 335 clock-mult = <1>; 336 clock-output-names = "clk13m"; 337 }; 338 339 clk26m: oscillator-26m { 340 compatible = "fixed-clock"; 341 #clock-cells = <0>; 342 clock-frequency = <26000000>; 343 clock-output-names = "clk26m"; 344 }; 345 346 clk32k: oscillator-32k { 347 compatible = "fixed-clock"; 348 #clock-cells = <0>; 349 clock-frequency = <32768>; 350 clock-output-names = "clk32k"; 351 }; 352 353 performance: performance-controller@11bc10 { 354 compatible = "mediatek,cpufreq-hw"; 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 356 #performance-domain-cells = <1>; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-390000000 { 364 opp-hz = /bits/ 64 <390000000>; 365 opp-microvolt = <625000>; 366 }; 367 opp-410000000 { 368 opp-hz = /bits/ 64 <410000000>; 369 opp-microvolt = <631250>; 370 }; 371 opp-431000000 { 372 opp-hz = /bits/ 64 <431000000>; 373 opp-microvolt = <631250>; 374 }; 375 opp-473000000 { 376 opp-hz = /bits/ 64 <473000000>; 377 opp-microvolt = <637500>; 378 }; 379 opp-515000000 { 380 opp-hz = /bits/ 64 <515000000>; 381 opp-microvolt = <637500>; 382 }; 383 opp-556000000 { 384 opp-hz = /bits/ 64 <556000000>; 385 opp-microvolt = <643750>; 386 }; 387 opp-598000000 { 388 opp-hz = /bits/ 64 <598000000>; 389 opp-microvolt = <650000>; 390 }; 391 opp-640000000 { 392 opp-hz = /bits/ 64 <640000000>; 393 opp-microvolt = <650000>; 394 }; 395 opp-670000000 { 396 opp-hz = /bits/ 64 <670000000>; 397 opp-microvolt = <662500>; 398 }; 399 opp-700000000 { 400 opp-hz = /bits/ 64 <700000000>; 401 opp-microvolt = <675000>; 402 }; 403 opp-730000000 { 404 opp-hz = /bits/ 64 <730000000>; 405 opp-microvolt = <687500>; 406 }; 407 opp-760000000 { 408 opp-hz = /bits/ 64 <760000000>; 409 opp-microvolt = <700000>; 410 }; 411 opp-790000000 { 412 opp-hz = /bits/ 64 <790000000>; 413 opp-microvolt = <712500>; 414 }; 415 opp-820000000 { 416 opp-hz = /bits/ 64 <820000000>; 417 opp-microvolt = <725000>; 418 }; 419 opp-850000000 { 420 opp-hz = /bits/ 64 <850000000>; 421 opp-microvolt = <737500>; 422 }; 423 opp-880000000 { 424 opp-hz = /bits/ 64 <880000000>; 425 opp-microvolt = <750000>; 426 }; 427 }; 428 429 pmu-a55 { 430 compatible = "arm,cortex-a55-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 433 }; 434 435 pmu-a78 { 436 compatible = "arm,cortex-a78-pmu"; 437 interrupt-parent = <&gic>; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 }; 445 446 timer: timer { 447 compatible = "arm,armv8-timer"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 453 }; 454 455 soc { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 compatible = "simple-bus"; 459 ranges; 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 461 462 gic: interrupt-controller@c000000 { 463 compatible = "arm,gic-v3"; 464 #interrupt-cells = <4>; 465 #redistributor-regions = <1>; 466 interrupt-parent = <&gic>; 467 interrupt-controller; 468 reg = <0 0x0c000000 0 0x40000>, 469 <0 0x0c040000 0 0x200000>; 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 479 }; 480 }; 481 }; 482 483 topckgen: syscon@10000000 { 484 compatible = "mediatek,mt8195-topckgen", "syscon"; 485 reg = <0 0x10000000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 infracfg_ao: syscon@10001000 { 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon"; 491 reg = <0 0x10001000 0 0x1000>; 492 #clock-cells = <1>; 493 #reset-cells = <1>; 494 }; 495 496 pericfg: syscon@10003000 { 497 compatible = "mediatek,mt8195-pericfg", "syscon"; 498 reg = <0 0x10003000 0 0x1000>; 499 #clock-cells = <1>; 500 }; 501 502 pio: pinctrl@10005000 { 503 compatible = "mediatek,mt8195-pinctrl"; 504 reg = <0 0x10005000 0 0x1000>, 505 <0 0x11d10000 0 0x1000>, 506 <0 0x11d30000 0 0x1000>, 507 <0 0x11d40000 0 0x1000>, 508 <0 0x11e20000 0 0x1000>, 509 <0 0x11eb0000 0 0x1000>, 510 <0 0x11f40000 0 0x1000>, 511 <0 0x1000b000 0 0x1000>; 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 513 "iocfg_br", "iocfg_lm", "iocfg_rb", 514 "iocfg_tl", "eint"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pio 0 0 144>; 518 interrupt-controller; 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 520 #interrupt-cells = <2>; 521 }; 522 523 scpsys: syscon@10006000 { 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 525 reg = <0 0x10006000 0 0x1000>; 526 527 /* System Power Manager */ 528 spm: power-controller { 529 compatible = "mediatek,mt8195-power-controller"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 /* power domain of the SoC */ 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 536 reg = <MT8195_POWER_DOMAIN_MFG0>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 #power-domain-cells = <1>; 540 541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { 542 reg = <MT8195_POWER_DOMAIN_MFG1>; 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 544 <&topckgen CLK_TOP_MFG_CORE_TMP>; 545 clock-names = "mfg", "alt"; 546 mediatek,infracfg = <&infracfg_ao>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 #power-domain-cells = <1>; 550 551 power-domain@MT8195_POWER_DOMAIN_MFG2 { 552 reg = <MT8195_POWER_DOMAIN_MFG2>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@MT8195_POWER_DOMAIN_MFG3 { 557 reg = <MT8195_POWER_DOMAIN_MFG3>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_MFG4 { 562 reg = <MT8195_POWER_DOMAIN_MFG4>; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8195_POWER_DOMAIN_MFG5 { 567 reg = <MT8195_POWER_DOMAIN_MFG5>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_MFG6 { 572 reg = <MT8195_POWER_DOMAIN_MFG6>; 573 #power-domain-cells = <0>; 574 }; 575 }; 576 }; 577 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 580 clocks = <&topckgen CLK_TOP_VPP>, 581 <&topckgen CLK_TOP_CAM>, 582 <&topckgen CLK_TOP_CCU>, 583 <&topckgen CLK_TOP_IMG>, 584 <&topckgen CLK_TOP_VENC>, 585 <&topckgen CLK_TOP_VDEC>, 586 <&topckgen CLK_TOP_WPE_VPP>, 587 <&topckgen CLK_TOP_CFG_VPP0>, 588 <&vppsys0 CLK_VPP0_SMI_COMMON>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 593 <&vppsys0 CLK_VPP0_GALS_INFRA>, 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 597 <&vppsys0 CLK_VPP0_SMI_REORDER>, 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 602 <&vppsys0 CLK_VPP0_SMI_RSI>, 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 612 "vppsys0-12", "vppsys0-13", "vppsys0-14", 613 "vppsys0-15", "vppsys0-16", "vppsys0-17", 614 "vppsys0-18"; 615 mediatek,infracfg = <&infracfg_ao>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 621 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 622 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 623 <&vdosys0 CLK_VDO0_SMI_GALS>, 624 <&vdosys0 CLK_VDO0_SMI_COMMON>, 625 <&vdosys0 CLK_VDO0_SMI_EMI>, 626 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 627 <&vdosys0 CLK_VDO0_SMI_LARB>, 628 <&vdosys0 CLK_VDO0_SMI_RSI>; 629 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 630 "vdosys0-2", "vdosys0-3", 631 "vdosys0-4", "vdosys0-5"; 632 mediatek,infracfg = <&infracfg_ao>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 #power-domain-cells = <1>; 636 637 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 638 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 639 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 640 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 641 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 642 clock-names = "vppsys1", "vppsys1-0", 643 "vppsys1-1"; 644 mediatek,infracfg = <&infracfg_ao>; 645 #power-domain-cells = <0>; 646 }; 647 648 power-domain@MT8195_POWER_DOMAIN_WPESYS { 649 reg = <MT8195_POWER_DOMAIN_WPESYS>; 650 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 651 <&wpesys CLK_WPE_SMI_LARB8>, 652 <&wpesys CLK_WPE_SMI_LARB7_P>, 653 <&wpesys CLK_WPE_SMI_LARB8_P>; 654 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 655 "wepsys-3"; 656 mediatek,infracfg = <&infracfg_ao>; 657 #power-domain-cells = <0>; 658 }; 659 660 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 661 reg = <MT8195_POWER_DOMAIN_VDEC0>; 662 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 663 clock-names = "vdec0-0"; 664 mediatek,infracfg = <&infracfg_ao>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 #power-domain-cells = <0>; 668 669 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 670 reg = <MT8195_POWER_DOMAIN_VDEC1>; 671 clocks = <&vdecsys CLK_VDEC_LARB1>; 672 clock-names = "vdec1-0"; 673 mediatek,infracfg = <&infracfg_ao>; 674 #power-domain-cells = <0>; 675 }; 676 677 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 678 reg = <MT8195_POWER_DOMAIN_VDEC2>; 679 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 680 clock-names = "vdec2-0"; 681 mediatek,infracfg = <&infracfg_ao>; 682 #power-domain-cells = <0>; 683 }; 684 }; 685 686 power-domain@MT8195_POWER_DOMAIN_VENC { 687 reg = <MT8195_POWER_DOMAIN_VENC>; 688 clocks = <&vencsys CLK_VENC_LARB>; 689 clock-names = "venc0-larb"; 690 mediatek,infracfg = <&infracfg_ao>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 #power-domain-cells = <0>; 694 695 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 696 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 697 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>; 698 clock-names = "venc1-larb"; 699 mediatek,infracfg = <&infracfg_ao>; 700 #power-domain-cells = <0>; 701 }; 702 }; 703 704 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 705 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 706 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 707 <&vdosys1 CLK_VDO1_SMI_LARB2>, 708 <&vdosys1 CLK_VDO1_SMI_LARB3>, 709 <&vdosys1 CLK_VDO1_GALS>; 710 clock-names = "vdosys1", "vdosys1-0", 711 "vdosys1-1", "vdosys1-2"; 712 mediatek,infracfg = <&infracfg_ao>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 #power-domain-cells = <1>; 716 717 power-domain@MT8195_POWER_DOMAIN_DP_TX { 718 reg = <MT8195_POWER_DOMAIN_DP_TX>; 719 mediatek,infracfg = <&infracfg_ao>; 720 #power-domain-cells = <0>; 721 }; 722 723 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 724 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 725 mediatek,infracfg = <&infracfg_ao>; 726 #power-domain-cells = <0>; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 730 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 731 clocks = <&topckgen CLK_TOP_HDMI_APB>; 732 clock-names = "hdmi_tx"; 733 #power-domain-cells = <0>; 734 }; 735 }; 736 737 power-domain@MT8195_POWER_DOMAIN_IMG { 738 reg = <MT8195_POWER_DOMAIN_IMG>; 739 clocks = <&imgsys CLK_IMG_LARB9>, 740 <&imgsys CLK_IMG_GALS>; 741 clock-names = "img-0", "img-1"; 742 mediatek,infracfg = <&infracfg_ao>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 #power-domain-cells = <1>; 746 747 power-domain@MT8195_POWER_DOMAIN_DIP { 748 reg = <MT8195_POWER_DOMAIN_DIP>; 749 #power-domain-cells = <0>; 750 }; 751 752 power-domain@MT8195_POWER_DOMAIN_IPE { 753 reg = <MT8195_POWER_DOMAIN_IPE>; 754 clocks = <&topckgen CLK_TOP_IPE>, 755 <&imgsys CLK_IMG_IPE>, 756 <&ipesys CLK_IPE_SMI_LARB12>; 757 clock-names = "ipe", "ipe-0", "ipe-1"; 758 mediatek,infracfg = <&infracfg_ao>; 759 #power-domain-cells = <0>; 760 }; 761 }; 762 763 power-domain@MT8195_POWER_DOMAIN_CAM { 764 reg = <MT8195_POWER_DOMAIN_CAM>; 765 clocks = <&camsys CLK_CAM_LARB13>, 766 <&camsys CLK_CAM_LARB14>, 767 <&camsys CLK_CAM_CAM2MM0_GALS>, 768 <&camsys CLK_CAM_CAM2MM1_GALS>, 769 <&camsys CLK_CAM_CAM2SYS_GALS>; 770 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 771 "cam-4"; 772 mediatek,infracfg = <&infracfg_ao>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 #power-domain-cells = <1>; 776 777 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 778 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 779 #power-domain-cells = <0>; 780 }; 781 782 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 783 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 784 #power-domain-cells = <0>; 785 }; 786 787 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 788 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 789 #power-domain-cells = <0>; 790 }; 791 }; 792 }; 793 }; 794 795 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 796 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 797 mediatek,infracfg = <&infracfg_ao>; 798 #power-domain-cells = <0>; 799 }; 800 801 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 802 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 803 mediatek,infracfg = <&infracfg_ao>; 804 #power-domain-cells = <0>; 805 }; 806 807 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 808 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 809 #power-domain-cells = <0>; 810 }; 811 812 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 813 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 814 #power-domain-cells = <0>; 815 }; 816 817 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 818 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 819 clocks = <&topckgen CLK_TOP_SENINF>, 820 <&topckgen CLK_TOP_SENINF2>; 821 clock-names = "csi_rx_top", "csi_rx_top1"; 822 #power-domain-cells = <0>; 823 }; 824 825 power-domain@MT8195_POWER_DOMAIN_ETHER { 826 reg = <MT8195_POWER_DOMAIN_ETHER>; 827 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 828 clock-names = "ether"; 829 #power-domain-cells = <0>; 830 }; 831 832 power-domain@MT8195_POWER_DOMAIN_ADSP { 833 reg = <MT8195_POWER_DOMAIN_ADSP>; 834 clocks = <&topckgen CLK_TOP_ADSP>, 835 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 836 clock-names = "adsp", "adsp1"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 mediatek,infracfg = <&infracfg_ao>; 840 #power-domain-cells = <1>; 841 842 power-domain@MT8195_POWER_DOMAIN_AUDIO { 843 reg = <MT8195_POWER_DOMAIN_AUDIO>; 844 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 845 <&topckgen CLK_TOP_AUD_INTBUS>, 846 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 847 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 848 clock-names = "audio", "audio1", "audio2", 849 "audio3"; 850 mediatek,infracfg = <&infracfg_ao>; 851 #power-domain-cells = <0>; 852 }; 853 }; 854 }; 855 }; 856 857 watchdog: watchdog@10007000 { 858 compatible = "mediatek,mt8195-wdt"; 859 mediatek,disable-extrst; 860 reg = <0 0x10007000 0 0x100>; 861 #reset-cells = <1>; 862 }; 863 864 apmixedsys: syscon@1000c000 { 865 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 866 reg = <0 0x1000c000 0 0x1000>; 867 #clock-cells = <1>; 868 }; 869 870 systimer: timer@10017000 { 871 compatible = "mediatek,mt8195-timer", 872 "mediatek,mt6765-timer"; 873 reg = <0 0x10017000 0 0x1000>; 874 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&clk13m>; 876 }; 877 878 pwrap: pwrap@10024000 { 879 compatible = "mediatek,mt8195-pwrap", "syscon"; 880 reg = <0 0x10024000 0 0x1000>; 881 reg-names = "pwrap"; 882 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 883 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 884 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 885 clock-names = "spi", "wrap"; 886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 888 }; 889 890 spmi: spmi@10027000 { 891 compatible = "mediatek,mt8195-spmi"; 892 reg = <0 0x10027000 0 0x000e00>, 893 <0 0x10029000 0 0x000100>; 894 reg-names = "pmif", "spmimst"; 895 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 896 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 897 <&topckgen CLK_TOP_SPMI_M_MST>; 898 clock-names = "pmif_sys_ck", 899 "pmif_tmr_ck", 900 "spmimst_clk_mux"; 901 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 902 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 903 }; 904 905 iommu_infra: infra-iommu@10315000 { 906 compatible = "mediatek,mt8195-iommu-infra"; 907 reg = <0 0x10315000 0 0x5000>; 908 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 909 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 910 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 911 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 912 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 913 #iommu-cells = <1>; 914 }; 915 916 gce0: mailbox@10320000 { 917 compatible = "mediatek,mt8195-gce"; 918 reg = <0 0x10320000 0 0x4000>; 919 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 920 #mbox-cells = <2>; 921 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 922 }; 923 924 gce1: mailbox@10330000 { 925 compatible = "mediatek,mt8195-gce"; 926 reg = <0 0x10330000 0 0x4000>; 927 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 928 #mbox-cells = <2>; 929 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 930 }; 931 932 scp: scp@10500000 { 933 compatible = "mediatek,mt8195-scp"; 934 reg = <0 0x10500000 0 0x100000>, 935 <0 0x10720000 0 0xe0000>, 936 <0 0x10700000 0 0x8000>; 937 reg-names = "sram", "cfg", "l1tcm"; 938 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 939 status = "disabled"; 940 }; 941 942 scp_adsp: clock-controller@10720000 { 943 compatible = "mediatek,mt8195-scp_adsp"; 944 reg = <0 0x10720000 0 0x1000>; 945 #clock-cells = <1>; 946 }; 947 948 adsp: dsp@10803000 { 949 compatible = "mediatek,mt8195-dsp"; 950 reg = <0 0x10803000 0 0x1000>, 951 <0 0x10840000 0 0x40000>; 952 reg-names = "cfg", "sram"; 953 clocks = <&topckgen CLK_TOP_ADSP>, 954 <&clk26m>, 955 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 956 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 957 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 958 <&topckgen CLK_TOP_AUDIO_H>; 959 clock-names = "adsp_sel", 960 "clk26m_ck", 961 "audio_local_bus", 962 "mainpll_d7_d2", 963 "scp_adsp_audiodsp", 964 "audio_h"; 965 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 966 mbox-names = "rx", "tx"; 967 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 968 status = "disabled"; 969 }; 970 971 adsp_mailbox0: mailbox@10816000 { 972 compatible = "mediatek,mt8195-adsp-mbox"; 973 #mbox-cells = <0>; 974 reg = <0 0x10816000 0 0x1000>; 975 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 976 }; 977 978 adsp_mailbox1: mailbox@10817000 { 979 compatible = "mediatek,mt8195-adsp-mbox"; 980 #mbox-cells = <0>; 981 reg = <0 0x10817000 0 0x1000>; 982 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 983 }; 984 985 afe: mt8195-afe-pcm@10890000 { 986 compatible = "mediatek,mt8195-audio"; 987 reg = <0 0x10890000 0 0x10000>; 988 mediatek,topckgen = <&topckgen>; 989 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 990 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 991 resets = <&watchdog 14>; 992 reset-names = "audiosys"; 993 clocks = <&clk26m>, 994 <&apmixedsys CLK_APMIXED_APLL1>, 995 <&apmixedsys CLK_APMIXED_APLL2>, 996 <&topckgen CLK_TOP_APLL12_DIV0>, 997 <&topckgen CLK_TOP_APLL12_DIV1>, 998 <&topckgen CLK_TOP_APLL12_DIV2>, 999 <&topckgen CLK_TOP_APLL12_DIV3>, 1000 <&topckgen CLK_TOP_APLL12_DIV9>, 1001 <&topckgen CLK_TOP_A1SYS_HP>, 1002 <&topckgen CLK_TOP_AUD_INTBUS>, 1003 <&topckgen CLK_TOP_AUDIO_H>, 1004 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1005 <&topckgen CLK_TOP_DPTX_MCK>, 1006 <&topckgen CLK_TOP_I2SO1_MCK>, 1007 <&topckgen CLK_TOP_I2SO2_MCK>, 1008 <&topckgen CLK_TOP_I2SI1_MCK>, 1009 <&topckgen CLK_TOP_I2SI2_MCK>, 1010 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1011 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1012 clock-names = "clk26m", 1013 "apll1_ck", 1014 "apll2_ck", 1015 "apll12_div0", 1016 "apll12_div1", 1017 "apll12_div2", 1018 "apll12_div3", 1019 "apll12_div9", 1020 "a1sys_hp_sel", 1021 "aud_intbus_sel", 1022 "audio_h_sel", 1023 "audio_local_bus_sel", 1024 "dptx_m_sel", 1025 "i2so1_m_sel", 1026 "i2so2_m_sel", 1027 "i2si1_m_sel", 1028 "i2si2_m_sel", 1029 "infra_ao_audio_26m_b", 1030 "scp_adsp_audiodsp"; 1031 status = "disabled"; 1032 }; 1033 1034 uart0: serial@11001100 { 1035 compatible = "mediatek,mt8195-uart", 1036 "mediatek,mt6577-uart"; 1037 reg = <0 0x11001100 0 0x100>; 1038 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1039 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1040 clock-names = "baud", "bus"; 1041 status = "disabled"; 1042 }; 1043 1044 uart1: serial@11001200 { 1045 compatible = "mediatek,mt8195-uart", 1046 "mediatek,mt6577-uart"; 1047 reg = <0 0x11001200 0 0x100>; 1048 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1049 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1050 clock-names = "baud", "bus"; 1051 status = "disabled"; 1052 }; 1053 1054 uart2: serial@11001300 { 1055 compatible = "mediatek,mt8195-uart", 1056 "mediatek,mt6577-uart"; 1057 reg = <0 0x11001300 0 0x100>; 1058 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1059 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1060 clock-names = "baud", "bus"; 1061 status = "disabled"; 1062 }; 1063 1064 uart3: serial@11001400 { 1065 compatible = "mediatek,mt8195-uart", 1066 "mediatek,mt6577-uart"; 1067 reg = <0 0x11001400 0 0x100>; 1068 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1069 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1070 clock-names = "baud", "bus"; 1071 status = "disabled"; 1072 }; 1073 1074 uart4: serial@11001500 { 1075 compatible = "mediatek,mt8195-uart", 1076 "mediatek,mt6577-uart"; 1077 reg = <0 0x11001500 0 0x100>; 1078 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1079 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1080 clock-names = "baud", "bus"; 1081 status = "disabled"; 1082 }; 1083 1084 uart5: serial@11001600 { 1085 compatible = "mediatek,mt8195-uart", 1086 "mediatek,mt6577-uart"; 1087 reg = <0 0x11001600 0 0x100>; 1088 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1089 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1090 clock-names = "baud", "bus"; 1091 status = "disabled"; 1092 }; 1093 1094 auxadc: auxadc@11002000 { 1095 compatible = "mediatek,mt8195-auxadc", 1096 "mediatek,mt8173-auxadc"; 1097 reg = <0 0x11002000 0 0x1000>; 1098 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1099 clock-names = "main"; 1100 #io-channel-cells = <1>; 1101 status = "disabled"; 1102 }; 1103 1104 pericfg_ao: syscon@11003000 { 1105 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1106 reg = <0 0x11003000 0 0x1000>; 1107 #clock-cells = <1>; 1108 }; 1109 1110 spi0: spi@1100a000 { 1111 compatible = "mediatek,mt8195-spi", 1112 "mediatek,mt6765-spi"; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 reg = <0 0x1100a000 0 0x1000>; 1116 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1117 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1118 <&topckgen CLK_TOP_SPI>, 1119 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1120 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1121 status = "disabled"; 1122 }; 1123 1124 lvts_ap: thermal-sensor@1100b000 { 1125 compatible = "mediatek,mt8195-lvts-ap"; 1126 reg = <0 0x1100b000 0 0xc00>; 1127 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1128 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1129 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1130 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1131 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1132 #thermal-sensor-cells = <1>; 1133 }; 1134 1135 svs: svs@1100bc00 { 1136 compatible = "mediatek,mt8195-svs"; 1137 reg = <0 0x1100bc00 0 0x400>; 1138 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>; 1139 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1140 clock-names = "main"; 1141 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; 1142 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 1143 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; 1144 reset-names = "svs_rst"; 1145 }; 1146 1147 disp_pwm0: pwm@1100e000 { 1148 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1149 reg = <0 0x1100e000 0 0x1000>; 1150 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1152 #pwm-cells = <2>; 1153 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1154 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1155 clock-names = "main", "mm"; 1156 status = "disabled"; 1157 }; 1158 1159 disp_pwm1: pwm@1100f000 { 1160 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1161 reg = <0 0x1100f000 0 0x1000>; 1162 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1163 #pwm-cells = <2>; 1164 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1165 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1166 clock-names = "main", "mm"; 1167 status = "disabled"; 1168 }; 1169 1170 spi1: spi@11010000 { 1171 compatible = "mediatek,mt8195-spi", 1172 "mediatek,mt6765-spi"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 reg = <0 0x11010000 0 0x1000>; 1176 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1177 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1178 <&topckgen CLK_TOP_SPI>, 1179 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1180 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1181 status = "disabled"; 1182 }; 1183 1184 spi2: spi@11012000 { 1185 compatible = "mediatek,mt8195-spi", 1186 "mediatek,mt6765-spi"; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 reg = <0 0x11012000 0 0x1000>; 1190 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1191 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1192 <&topckgen CLK_TOP_SPI>, 1193 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1194 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1195 status = "disabled"; 1196 }; 1197 1198 spi3: spi@11013000 { 1199 compatible = "mediatek,mt8195-spi", 1200 "mediatek,mt6765-spi"; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 reg = <0 0x11013000 0 0x1000>; 1204 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1206 <&topckgen CLK_TOP_SPI>, 1207 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1208 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1209 status = "disabled"; 1210 }; 1211 1212 spi4: spi@11018000 { 1213 compatible = "mediatek,mt8195-spi", 1214 "mediatek,mt6765-spi"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 reg = <0 0x11018000 0 0x1000>; 1218 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1219 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1220 <&topckgen CLK_TOP_SPI>, 1221 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1222 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1223 status = "disabled"; 1224 }; 1225 1226 spi5: spi@11019000 { 1227 compatible = "mediatek,mt8195-spi", 1228 "mediatek,mt6765-spi"; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 reg = <0 0x11019000 0 0x1000>; 1232 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1233 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1234 <&topckgen CLK_TOP_SPI>, 1235 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1236 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1237 status = "disabled"; 1238 }; 1239 1240 spis0: spi@1101d000 { 1241 compatible = "mediatek,mt8195-spi-slave"; 1242 reg = <0 0x1101d000 0 0x1000>; 1243 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1244 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1245 clock-names = "spi"; 1246 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1247 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1248 status = "disabled"; 1249 }; 1250 1251 spis1: spi@1101e000 { 1252 compatible = "mediatek,mt8195-spi-slave"; 1253 reg = <0 0x1101e000 0 0x1000>; 1254 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1255 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1256 clock-names = "spi"; 1257 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1258 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1259 status = "disabled"; 1260 }; 1261 1262 eth: ethernet@11021000 { 1263 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1264 reg = <0 0x11021000 0 0x4000>; 1265 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1266 interrupt-names = "macirq"; 1267 clock-names = "axi", 1268 "apb", 1269 "mac_main", 1270 "ptp_ref", 1271 "rmii_internal", 1272 "mac_cg"; 1273 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1274 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1275 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1276 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1277 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1278 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1279 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1280 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1281 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1282 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1283 <&topckgen CLK_TOP_ETHPLL_D8>, 1284 <&topckgen CLK_TOP_ETHPLL_D10>; 1285 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1286 mediatek,pericfg = <&infracfg_ao>; 1287 snps,axi-config = <&stmmac_axi_setup>; 1288 snps,mtl-rx-config = <&mtl_rx_setup>; 1289 snps,mtl-tx-config = <&mtl_tx_setup>; 1290 snps,txpbl = <16>; 1291 snps,rxpbl = <16>; 1292 snps,clk-csr = <0>; 1293 status = "disabled"; 1294 1295 mdio { 1296 compatible = "snps,dwmac-mdio"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 }; 1300 1301 stmmac_axi_setup: stmmac-axi-config { 1302 snps,wr_osr_lmt = <0x7>; 1303 snps,rd_osr_lmt = <0x7>; 1304 snps,blen = <0 0 0 0 16 8 4>; 1305 }; 1306 1307 mtl_rx_setup: rx-queues-config { 1308 snps,rx-queues-to-use = <4>; 1309 snps,rx-sched-sp; 1310 queue0 { 1311 snps,dcb-algorithm; 1312 snps,map-to-dma-channel = <0x0>; 1313 }; 1314 queue1 { 1315 snps,dcb-algorithm; 1316 snps,map-to-dma-channel = <0x0>; 1317 }; 1318 queue2 { 1319 snps,dcb-algorithm; 1320 snps,map-to-dma-channel = <0x0>; 1321 }; 1322 queue3 { 1323 snps,dcb-algorithm; 1324 snps,map-to-dma-channel = <0x0>; 1325 }; 1326 }; 1327 1328 mtl_tx_setup: tx-queues-config { 1329 snps,tx-queues-to-use = <4>; 1330 snps,tx-sched-wrr; 1331 queue0 { 1332 snps,weight = <0x10>; 1333 snps,dcb-algorithm; 1334 snps,priority = <0x0>; 1335 }; 1336 queue1 { 1337 snps,weight = <0x11>; 1338 snps,dcb-algorithm; 1339 snps,priority = <0x1>; 1340 }; 1341 queue2 { 1342 snps,weight = <0x12>; 1343 snps,dcb-algorithm; 1344 snps,priority = <0x2>; 1345 }; 1346 queue3 { 1347 snps,weight = <0x13>; 1348 snps,dcb-algorithm; 1349 snps,priority = <0x3>; 1350 }; 1351 }; 1352 }; 1353 1354 ssusb0: usb@11201000 { 1355 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1356 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1357 reg-names = "mac", "ippc"; 1358 ranges = <0 0 0 0x11200000 0 0x3f00>; 1359 #address-cells = <2>; 1360 #size-cells = <2>; 1361 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1362 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1363 <&topckgen CLK_TOP_SSUSB_REF>, 1364 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1365 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1366 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 1367 wakeup-source; 1368 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1369 status = "disabled"; 1370 1371 xhci0: usb@0 { 1372 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1373 reg = <0 0 0 0x1000>; 1374 reg-names = "mac"; 1375 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1376 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1377 <&topckgen CLK_TOP_SSUSB_XHCI>; 1378 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1379 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1380 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1381 <&topckgen CLK_TOP_SSUSB_REF>, 1382 <&apmixedsys CLK_APMIXED_USB1PLL>, 1383 <&clk26m>, 1384 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1385 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1386 status = "disabled"; 1387 }; 1388 }; 1389 1390 mmc0: mmc@11230000 { 1391 compatible = "mediatek,mt8195-mmc", 1392 "mediatek,mt8183-mmc"; 1393 reg = <0 0x11230000 0 0x10000>, 1394 <0 0x11f50000 0 0x1000>; 1395 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1397 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1398 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1399 clock-names = "source", "hclk", "source_cg"; 1400 status = "disabled"; 1401 }; 1402 1403 mmc1: mmc@11240000 { 1404 compatible = "mediatek,mt8195-mmc", 1405 "mediatek,mt8183-mmc"; 1406 reg = <0 0x11240000 0 0x1000>, 1407 <0 0x11c70000 0 0x1000>; 1408 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1409 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1410 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1411 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1412 clock-names = "source", "hclk", "source_cg"; 1413 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1414 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1415 status = "disabled"; 1416 }; 1417 1418 mmc2: mmc@11250000 { 1419 compatible = "mediatek,mt8195-mmc", 1420 "mediatek,mt8183-mmc"; 1421 reg = <0 0x11250000 0 0x1000>, 1422 <0 0x11e60000 0 0x1000>; 1423 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1424 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1425 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1426 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1427 clock-names = "source", "hclk", "source_cg"; 1428 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1429 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1430 status = "disabled"; 1431 }; 1432 1433 ufshci: ufshci@11270000 { 1434 compatible = "mediatek,mt8195-ufshci"; 1435 reg = <0 0x11270000 0 0x2300>; 1436 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>; 1437 phys = <&ufsphy>; 1438 clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>, 1439 <&infracfg_ao CLK_INFRA_AO_AES>, 1440 <&infracfg_ao CLK_INFRA_AO_UFS_TICK>, 1441 <&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>, 1442 <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>, 1443 <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>, 1444 <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>, 1445 <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>; 1446 clock-names = "ufs", "ufs_aes", "ufs_tick", 1447 "unipro_sysclk", "unipro_tick", 1448 "unipro_mp_bclk", "ufs_tx_symbol", 1449 "ufs_mem_sub"; 1450 freq-table-hz = <0 0>, <0 0>, <0 0>, 1451 <0 0>, <0 0>, <0 0>, 1452 <0 0>, <0 0>; 1453 1454 mediatek,ufs-disable-mcq; 1455 status = "disabled"; 1456 }; 1457 1458 lvts_mcu: thermal-sensor@11278000 { 1459 compatible = "mediatek,mt8195-lvts-mcu"; 1460 reg = <0 0x11278000 0 0x1000>; 1461 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1462 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1463 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1464 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1465 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1466 #thermal-sensor-cells = <1>; 1467 }; 1468 1469 xhci1: usb@11290000 { 1470 compatible = "mediatek,mt8195-xhci", 1471 "mediatek,mtk-xhci"; 1472 reg = <0 0x11290000 0 0x1000>, 1473 <0 0x11293e00 0 0x0100>; 1474 reg-names = "mac", "ippc"; 1475 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1476 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1477 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1478 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1479 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1480 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1481 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1482 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1483 <&apmixedsys CLK_APMIXED_USB1PLL>, 1484 <&clk26m>, 1485 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1486 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1487 "xhci_ck"; 1488 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1489 wakeup-source; 1490 status = "disabled"; 1491 }; 1492 1493 ssusb2: usb@112a1000 { 1494 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1495 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; 1496 reg-names = "mac", "ippc"; 1497 ranges = <0 0 0 0x112a0000 0 0x3f00>; 1498 #address-cells = <2>; 1499 #size-cells = <2>; 1500 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1501 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; 1502 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1503 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1504 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1505 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1506 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1507 phys = <&u2port2 PHY_TYPE_USB2>; 1508 wakeup-source; 1509 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1510 status = "disabled"; 1511 1512 xhci2: usb@0 { 1513 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1514 reg = <0 0 0 0x1000>; 1515 reg-names = "mac"; 1516 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1517 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1518 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1519 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1520 clock-names = "sys_ck"; 1521 status = "disabled"; 1522 }; 1523 }; 1524 1525 ssusb3: usb@112b1000 { 1526 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1527 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; 1528 reg-names = "mac", "ippc"; 1529 ranges = <0 0 0 0x112b0000 0 0x3f00>; 1530 #address-cells = <2>; 1531 #size-cells = <2>; 1532 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1533 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; 1534 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1535 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1536 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1537 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1538 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1539 phys = <&u2port3 PHY_TYPE_USB2>; 1540 wakeup-source; 1541 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1542 status = "disabled"; 1543 1544 xhci3: usb@0 { 1545 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1546 reg = <0 0 0 0x1000>; 1547 reg-names = "mac"; 1548 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1549 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1550 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1551 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1552 clock-names = "sys_ck"; 1553 status = "disabled"; 1554 }; 1555 }; 1556 1557 pcie0: pcie@112f0000 { 1558 compatible = "mediatek,mt8195-pcie", 1559 "mediatek,mt8192-pcie"; 1560 device_type = "pci"; 1561 #address-cells = <3>; 1562 #size-cells = <2>; 1563 reg = <0 0x112f0000 0 0x4000>; 1564 reg-names = "pcie-mac"; 1565 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1566 bus-range = <0x00 0xff>; 1567 ranges = <0x81000000 0 0x20000000 1568 0x0 0x20000000 0 0x200000>, 1569 <0x82000000 0 0x20200000 1570 0x0 0x20200000 0 0x3e00000>; 1571 1572 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1573 iommu-map-mask = <0x0>; 1574 1575 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1576 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1577 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1578 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1579 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1580 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1581 clock-names = "pl_250m", "tl_26m", "tl_96m", 1582 "tl_32k", "peri_26m", "peri_mem"; 1583 assigned-clocks = <&topckgen CLK_TOP_TL>; 1584 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1585 1586 phys = <&pciephy>; 1587 phy-names = "pcie-phy"; 1588 1589 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1590 1591 resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; 1592 reset-names = "mac"; 1593 1594 #interrupt-cells = <1>; 1595 interrupt-map-mask = <0 0 0 7>; 1596 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1597 <0 0 0 2 &pcie_intc0 1>, 1598 <0 0 0 3 &pcie_intc0 2>, 1599 <0 0 0 4 &pcie_intc0 3>; 1600 status = "disabled"; 1601 1602 pcie_intc0: interrupt-controller { 1603 interrupt-controller; 1604 #address-cells = <0>; 1605 #interrupt-cells = <1>; 1606 }; 1607 }; 1608 1609 pcie1: pcie@112f8000 { 1610 compatible = "mediatek,mt8195-pcie", 1611 "mediatek,mt8192-pcie"; 1612 device_type = "pci"; 1613 #address-cells = <3>; 1614 #size-cells = <2>; 1615 reg = <0 0x112f8000 0 0x4000>; 1616 reg-names = "pcie-mac"; 1617 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1618 bus-range = <0x00 0xff>; 1619 ranges = <0x81000000 0 0x24000000 1620 0x0 0x24000000 0 0x200000>, 1621 <0x82000000 0 0x24200000 1622 0x0 0x24200000 0 0x3e00000>; 1623 1624 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1625 iommu-map-mask = <0x0>; 1626 1627 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1628 <&clk26m>, 1629 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1630 <&clk26m>, 1631 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1632 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1633 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1634 clock-names = "pl_250m", "tl_26m", "tl_96m", 1635 "tl_32k", "peri_26m", "peri_mem"; 1636 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1637 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1638 1639 phys = <&u3port1 PHY_TYPE_PCIE>; 1640 phy-names = "pcie-phy"; 1641 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1642 1643 #interrupt-cells = <1>; 1644 interrupt-map-mask = <0 0 0 7>; 1645 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1646 <0 0 0 2 &pcie_intc1 1>, 1647 <0 0 0 3 &pcie_intc1 2>, 1648 <0 0 0 4 &pcie_intc1 3>; 1649 status = "disabled"; 1650 1651 pcie_intc1: interrupt-controller { 1652 interrupt-controller; 1653 #address-cells = <0>; 1654 #interrupt-cells = <1>; 1655 }; 1656 }; 1657 1658 nor_flash: spi@1132c000 { 1659 compatible = "mediatek,mt8195-nor", 1660 "mediatek,mt8173-nor"; 1661 reg = <0 0x1132c000 0 0x1000>; 1662 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1663 clocks = <&topckgen CLK_TOP_SPINOR>, 1664 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1665 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1666 clock-names = "spi", "sf", "axi"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 efuse: efuse@11c10000 { 1673 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1674 reg = <0 0x11c10000 0 0x1000>; 1675 #address-cells = <1>; 1676 #size-cells = <1>; 1677 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1678 reg = <0x184 0x1>; 1679 bits = <0 5>; 1680 }; 1681 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1682 reg = <0x184 0x2>; 1683 bits = <5 5>; 1684 }; 1685 u3_intr_p0: usb3-intr@185 { 1686 reg = <0x185 0x1>; 1687 bits = <2 6>; 1688 }; 1689 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1690 reg = <0x186 0x1>; 1691 bits = <0 5>; 1692 }; 1693 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1694 reg = <0x186 0x2>; 1695 bits = <5 5>; 1696 }; 1697 comb_intr_p1: usb3-intr@187 { 1698 reg = <0x187 0x1>; 1699 bits = <2 6>; 1700 }; 1701 u2_intr_p0: usb2-intr-p0@188,1 { 1702 reg = <0x188 0x1>; 1703 bits = <0 5>; 1704 }; 1705 u2_intr_p1: usb2-intr-p1@188,2 { 1706 reg = <0x188 0x2>; 1707 bits = <5 5>; 1708 }; 1709 u2_intr_p2: usb2-intr-p2@189,1 { 1710 reg = <0x189 0x1>; 1711 bits = <2 5>; 1712 }; 1713 u2_intr_p3: usb2-intr-p3@189,2 { 1714 reg = <0x189 0x2>; 1715 bits = <7 5>; 1716 }; 1717 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1718 reg = <0x190 0x1>; 1719 bits = <0 4>; 1720 }; 1721 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1722 reg = <0x190 0x1>; 1723 bits = <4 4>; 1724 }; 1725 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1726 reg = <0x191 0x1>; 1727 bits = <0 4>; 1728 }; 1729 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1730 reg = <0x191 0x1>; 1731 bits = <4 4>; 1732 }; 1733 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1734 reg = <0x192 0x1>; 1735 bits = <0 4>; 1736 }; 1737 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1738 reg = <0x192 0x1>; 1739 bits = <4 4>; 1740 }; 1741 pciephy_glb_intr: pciephy-glb-intr@193 { 1742 reg = <0x193 0x1>; 1743 bits = <0 4>; 1744 }; 1745 dp_calibration: dp-data@1ac { 1746 reg = <0x1ac 0x10>; 1747 }; 1748 lvts_efuse_data1: lvts1-calib@1bc { 1749 reg = <0x1bc 0x14>; 1750 }; 1751 lvts_efuse_data2: lvts2-calib@1d0 { 1752 reg = <0x1d0 0x38>; 1753 }; 1754 svs_calib_data: svs-calib@580 { 1755 reg = <0x580 0x64>; 1756 }; 1757 socinfo-data1@7a0 { 1758 reg = <0x7a0 0x4>; 1759 }; 1760 }; 1761 1762 u3phy2: t-phy@11c40000 { 1763 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1764 #address-cells = <1>; 1765 #size-cells = <1>; 1766 ranges = <0 0 0x11c40000 0x700>; 1767 status = "disabled"; 1768 1769 u2port2: usb-phy@0 { 1770 reg = <0x0 0x700>; 1771 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1772 clock-names = "ref"; 1773 #phy-cells = <1>; 1774 }; 1775 }; 1776 1777 u3phy3: t-phy@11c50000 { 1778 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1779 #address-cells = <1>; 1780 #size-cells = <1>; 1781 ranges = <0 0 0x11c50000 0x700>; 1782 status = "disabled"; 1783 1784 u2port3: usb-phy@0 { 1785 reg = <0x0 0x700>; 1786 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1787 clock-names = "ref"; 1788 #phy-cells = <1>; 1789 }; 1790 }; 1791 1792 mipi_tx0: dsi-phy@11c80000 { 1793 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1794 reg = <0 0x11c80000 0 0x1000>; 1795 clocks = <&clk26m>; 1796 clock-output-names = "mipi_tx0_pll"; 1797 #clock-cells = <0>; 1798 #phy-cells = <0>; 1799 status = "disabled"; 1800 }; 1801 1802 mipi_tx1: dsi-phy@11c90000 { 1803 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1804 reg = <0 0x11c90000 0 0x1000>; 1805 clocks = <&clk26m>; 1806 clock-output-names = "mipi_tx1_pll"; 1807 #clock-cells = <0>; 1808 #phy-cells = <0>; 1809 status = "disabled"; 1810 }; 1811 1812 i2c5: i2c@11d00000 { 1813 compatible = "mediatek,mt8195-i2c", 1814 "mediatek,mt8192-i2c"; 1815 reg = <0 0x11d00000 0 0x1000>, 1816 <0 0x10220580 0 0x80>; 1817 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1818 clock-div = <1>; 1819 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1820 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1821 clock-names = "main", "dma"; 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 status = "disabled"; 1825 }; 1826 1827 i2c6: i2c@11d01000 { 1828 compatible = "mediatek,mt8195-i2c", 1829 "mediatek,mt8192-i2c"; 1830 reg = <0 0x11d01000 0 0x1000>, 1831 <0 0x10220600 0 0x80>; 1832 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1833 clock-div = <1>; 1834 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1835 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1836 clock-names = "main", "dma"; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 status = "disabled"; 1840 }; 1841 1842 i2c7: i2c@11d02000 { 1843 compatible = "mediatek,mt8195-i2c", 1844 "mediatek,mt8192-i2c"; 1845 reg = <0 0x11d02000 0 0x1000>, 1846 <0 0x10220680 0 0x80>; 1847 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1848 clock-div = <1>; 1849 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1850 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1851 clock-names = "main", "dma"; 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 status = "disabled"; 1855 }; 1856 1857 imp_iic_wrap_s: clock-controller@11d03000 { 1858 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1859 reg = <0 0x11d03000 0 0x1000>; 1860 #clock-cells = <1>; 1861 }; 1862 1863 i2c0: i2c@11e00000 { 1864 compatible = "mediatek,mt8195-i2c", 1865 "mediatek,mt8192-i2c"; 1866 reg = <0 0x11e00000 0 0x1000>, 1867 <0 0x10220080 0 0x80>; 1868 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1869 clock-div = <1>; 1870 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1871 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1872 clock-names = "main", "dma"; 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 status = "disabled"; 1876 }; 1877 1878 i2c1: i2c@11e01000 { 1879 compatible = "mediatek,mt8195-i2c", 1880 "mediatek,mt8192-i2c"; 1881 reg = <0 0x11e01000 0 0x1000>, 1882 <0 0x10220200 0 0x80>; 1883 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1884 clock-div = <1>; 1885 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1886 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1887 clock-names = "main", "dma"; 1888 #address-cells = <1>; 1889 #size-cells = <0>; 1890 status = "disabled"; 1891 }; 1892 1893 i2c2: i2c@11e02000 { 1894 compatible = "mediatek,mt8195-i2c", 1895 "mediatek,mt8192-i2c"; 1896 reg = <0 0x11e02000 0 0x1000>, 1897 <0 0x10220380 0 0x80>; 1898 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1899 clock-div = <1>; 1900 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1901 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1902 clock-names = "main", "dma"; 1903 #address-cells = <1>; 1904 #size-cells = <0>; 1905 status = "disabled"; 1906 }; 1907 1908 i2c3: i2c@11e03000 { 1909 compatible = "mediatek,mt8195-i2c", 1910 "mediatek,mt8192-i2c"; 1911 reg = <0 0x11e03000 0 0x1000>, 1912 <0 0x10220480 0 0x80>; 1913 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1914 clock-div = <1>; 1915 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1916 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1917 clock-names = "main", "dma"; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 status = "disabled"; 1921 }; 1922 1923 i2c4: i2c@11e04000 { 1924 compatible = "mediatek,mt8195-i2c", 1925 "mediatek,mt8192-i2c"; 1926 reg = <0 0x11e04000 0 0x1000>, 1927 <0 0x10220500 0 0x80>; 1928 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1929 clock-div = <1>; 1930 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1931 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1932 clock-names = "main", "dma"; 1933 #address-cells = <1>; 1934 #size-cells = <0>; 1935 status = "disabled"; 1936 }; 1937 1938 imp_iic_wrap_w: clock-controller@11e05000 { 1939 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1940 reg = <0 0x11e05000 0 0x1000>; 1941 #clock-cells = <1>; 1942 }; 1943 1944 u3phy1: t-phy@11e30000 { 1945 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1946 #address-cells = <1>; 1947 #size-cells = <1>; 1948 ranges = <0 0 0x11e30000 0xe00>; 1949 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1950 status = "disabled"; 1951 1952 u2port1: usb-phy@0 { 1953 reg = <0x0 0x700>; 1954 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1955 <&clk26m>; 1956 clock-names = "ref", "da_ref"; 1957 #phy-cells = <1>; 1958 }; 1959 1960 u3port1: usb-phy@700 { 1961 reg = <0x700 0x700>; 1962 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1963 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1964 clock-names = "ref", "da_ref"; 1965 nvmem-cells = <&comb_intr_p1>, 1966 <&comb_rx_imp_p1>, 1967 <&comb_tx_imp_p1>; 1968 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1969 #phy-cells = <1>; 1970 }; 1971 }; 1972 1973 u3phy0: t-phy@11e40000 { 1974 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1975 #address-cells = <1>; 1976 #size-cells = <1>; 1977 ranges = <0 0 0x11e40000 0xe00>; 1978 status = "disabled"; 1979 1980 u2port0: usb-phy@0 { 1981 reg = <0x0 0x700>; 1982 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1983 <&clk26m>; 1984 clock-names = "ref", "da_ref"; 1985 #phy-cells = <1>; 1986 }; 1987 1988 u3port0: usb-phy@700 { 1989 reg = <0x700 0x700>; 1990 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1991 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1992 clock-names = "ref", "da_ref"; 1993 nvmem-cells = <&u3_intr_p0>, 1994 <&u3_rx_imp_p0>, 1995 <&u3_tx_imp_p0>; 1996 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1997 #phy-cells = <1>; 1998 }; 1999 }; 2000 2001 pciephy: phy@11e80000 { 2002 compatible = "mediatek,mt8195-pcie-phy"; 2003 reg = <0 0x11e80000 0 0x10000>; 2004 reg-names = "sif"; 2005 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 2006 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 2007 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 2008 <&pciephy_rx_ln1>; 2009 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 2010 "tx_ln0_nmos", "rx_ln0", 2011 "tx_ln1_pmos", "tx_ln1_nmos", 2012 "rx_ln1"; 2013 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 2014 #phy-cells = <0>; 2015 status = "disabled"; 2016 }; 2017 2018 ufsphy: ufs-phy@11fa0000 { 2019 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 2020 reg = <0 0x11fa0000 0 0xc000>; 2021 clocks = <&clk26m>, <&clk26m>; 2022 clock-names = "unipro", "mp"; 2023 #phy-cells = <0>; 2024 status = "disabled"; 2025 }; 2026 2027 gpu: gpu@13000000 { 2028 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 2029 "arm,mali-valhall-jm"; 2030 reg = <0 0x13000000 0 0x4000>; 2031 2032 clocks = <&mfgcfg CLK_MFG_BG3D>; 2033 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 2034 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 2035 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 2036 interrupt-names = "job", "mmu", "gpu"; 2037 operating-points-v2 = <&gpu_opp_table>; 2038 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 2039 <&spm MT8195_POWER_DOMAIN_MFG3>, 2040 <&spm MT8195_POWER_DOMAIN_MFG4>, 2041 <&spm MT8195_POWER_DOMAIN_MFG5>, 2042 <&spm MT8195_POWER_DOMAIN_MFG6>; 2043 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 2044 status = "disabled"; 2045 }; 2046 2047 mfgcfg: clock-controller@13fbf000 { 2048 compatible = "mediatek,mt8195-mfgcfg"; 2049 reg = <0 0x13fbf000 0 0x1000>; 2050 #clock-cells = <1>; 2051 }; 2052 2053 vppsys0: syscon@14000000 { 2054 compatible = "mediatek,mt8195-vppsys0", "syscon"; 2055 reg = <0 0x14000000 0 0x1000>; 2056 #clock-cells = <1>; 2057 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; 2058 }; 2059 2060 dma-controller@14001000 { 2061 compatible = "mediatek,mt8195-mdp3-rdma"; 2062 reg = <0 0x14001000 0 0x1000>; 2063 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 2064 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 2065 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 2066 mediatek,scp = <&scp>; 2067 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2068 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; 2069 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 2070 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, 2071 <&gce1 13 CMDQ_THR_PRIO_1>, 2072 <&gce1 14 CMDQ_THR_PRIO_1>, 2073 <&gce1 21 CMDQ_THR_PRIO_1>, 2074 <&gce1 22 CMDQ_THR_PRIO_1>; 2075 #dma-cells = <1>; 2076 }; 2077 2078 display@14002000 { 2079 compatible = "mediatek,mt8195-mdp3-fg"; 2080 reg = <0 0x14002000 0 0x1000>; 2081 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2082 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2083 }; 2084 2085 display@14003000 { 2086 compatible = "mediatek,mt8195-mdp3-stitch"; 2087 reg = <0 0x14003000 0 0x1000>; 2088 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; 2089 clocks = <&vppsys0 CLK_VPP0_STITCH>; 2090 }; 2091 2092 display@14004000 { 2093 compatible = "mediatek,mt8195-mdp3-hdr"; 2094 reg = <0 0x14004000 0 0x1000>; 2095 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2096 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2097 }; 2098 2099 display@14005000 { 2100 compatible = "mediatek,mt8195-mdp3-aal"; 2101 reg = <0 0x14005000 0 0x1000>; 2102 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2103 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2104 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2105 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2106 }; 2107 2108 display@14006000 { 2109 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2110 reg = <0 0x14006000 0 0x1000>; 2111 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2112 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2113 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2114 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2115 }; 2116 2117 display@14007000 { 2118 compatible = "mediatek,mt8195-mdp3-tdshp"; 2119 reg = <0 0x14007000 0 0x1000>; 2120 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2121 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2122 }; 2123 2124 display@14008000 { 2125 compatible = "mediatek,mt8195-mdp3-color"; 2126 reg = <0 0x14008000 0 0x1000>; 2127 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2128 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2129 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2130 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2131 }; 2132 2133 display@14009000 { 2134 compatible = "mediatek,mt8195-mdp3-ovl"; 2135 reg = <0 0x14009000 0 0x1000>; 2136 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2137 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2138 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2139 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2140 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>; 2141 }; 2142 2143 display@1400a000 { 2144 compatible = "mediatek,mt8195-mdp3-padding"; 2145 reg = <0 0x1400a000 0 0x1000>; 2146 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2147 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2148 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2149 }; 2150 2151 display@1400b000 { 2152 compatible = "mediatek,mt8195-mdp3-tcc"; 2153 reg = <0 0x1400b000 0 0x1000>; 2154 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2155 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2156 }; 2157 2158 dma-controller@1400c000 { 2159 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2160 reg = <0 0x1400c000 0 0x1000>; 2161 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2162 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2163 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2164 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2165 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; 2166 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2167 #dma-cells = <1>; 2168 }; 2169 2170 mutex@1400f000 { 2171 compatible = "mediatek,mt8195-vpp-mutex"; 2172 reg = <0 0x1400f000 0 0x1000>; 2173 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2174 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2175 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2176 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2177 }; 2178 2179 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 2180 compatible = "mediatek,mt8195-smi-sub-common"; 2181 reg = <0 0x14010000 0 0x1000>; 2182 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2183 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2184 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2185 clock-names = "apb", "smi", "gals0"; 2186 mediatek,smi = <&smi_common_vpp>; 2187 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2188 }; 2189 2190 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 2191 compatible = "mediatek,mt8195-smi-sub-common"; 2192 reg = <0 0x14011000 0 0x1000>; 2193 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2194 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2195 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 2196 clock-names = "apb", "smi", "gals0"; 2197 mediatek,smi = <&smi_common_vpp>; 2198 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2199 }; 2200 2201 smi_common_vpp: smi@14012000 { 2202 compatible = "mediatek,mt8195-smi-common-vpp"; 2203 reg = <0 0x14012000 0 0x1000>; 2204 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2205 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2206 <&vppsys0 CLK_VPP0_SMI_RSI>, 2207 <&vppsys0 CLK_VPP0_SMI_RSI>; 2208 clock-names = "apb", "smi", "gals0", "gals1"; 2209 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2210 }; 2211 2212 larb4: larb@14013000 { 2213 compatible = "mediatek,mt8195-smi-larb"; 2214 reg = <0 0x14013000 0 0x1000>; 2215 mediatek,larb-id = <4>; 2216 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2217 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2218 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2219 clock-names = "apb", "smi"; 2220 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2221 }; 2222 2223 iommu_vpp: iommu@14018000 { 2224 compatible = "mediatek,mt8195-iommu-vpp"; 2225 reg = <0 0x14018000 0 0x1000>; 2226 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2227 &larb12 &larb14 &larb16 &larb18 2228 &larb20 &larb22 &larb23 &larb26 2229 &larb27>; 2230 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2231 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2232 clock-names = "bclk"; 2233 #iommu-cells = <1>; 2234 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2235 }; 2236 2237 wpesys: clock-controller@14e00000 { 2238 compatible = "mediatek,mt8195-wpesys"; 2239 reg = <0 0x14e00000 0 0x1000>; 2240 #clock-cells = <1>; 2241 }; 2242 2243 wpesys_vpp0: clock-controller@14e02000 { 2244 compatible = "mediatek,mt8195-wpesys_vpp0"; 2245 reg = <0 0x14e02000 0 0x1000>; 2246 #clock-cells = <1>; 2247 }; 2248 2249 wpesys_vpp1: clock-controller@14e03000 { 2250 compatible = "mediatek,mt8195-wpesys_vpp1"; 2251 reg = <0 0x14e03000 0 0x1000>; 2252 #clock-cells = <1>; 2253 }; 2254 2255 larb7: larb@14e04000 { 2256 compatible = "mediatek,mt8195-smi-larb"; 2257 reg = <0 0x14e04000 0 0x1000>; 2258 mediatek,larb-id = <7>; 2259 mediatek,smi = <&smi_common_vdo>; 2260 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2261 <&wpesys CLK_WPE_SMI_LARB7>; 2262 clock-names = "apb", "smi"; 2263 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2264 }; 2265 2266 larb8: larb@14e05000 { 2267 compatible = "mediatek,mt8195-smi-larb"; 2268 reg = <0 0x14e05000 0 0x1000>; 2269 mediatek,larb-id = <8>; 2270 mediatek,smi = <&smi_common_vpp>; 2271 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2272 <&wpesys CLK_WPE_SMI_LARB8>, 2273 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2274 clock-names = "apb", "smi", "gals"; 2275 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2276 }; 2277 2278 vppsys1: syscon@14f00000 { 2279 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2280 reg = <0 0x14f00000 0 0x1000>; 2281 #clock-cells = <1>; 2282 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; 2283 }; 2284 2285 mutex@14f01000 { 2286 compatible = "mediatek,mt8195-vpp-mutex"; 2287 reg = <0 0x14f01000 0 0x1000>; 2288 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2289 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2290 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2291 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2292 }; 2293 2294 larb5: larb@14f02000 { 2295 compatible = "mediatek,mt8195-smi-larb"; 2296 reg = <0 0x14f02000 0 0x1000>; 2297 mediatek,larb-id = <5>; 2298 mediatek,smi = <&smi_common_vdo>; 2299 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2300 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2301 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2302 clock-names = "apb", "smi", "gals"; 2303 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2304 }; 2305 2306 larb6: larb@14f03000 { 2307 compatible = "mediatek,mt8195-smi-larb"; 2308 reg = <0 0x14f03000 0 0x1000>; 2309 mediatek,larb-id = <6>; 2310 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2311 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2312 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2313 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2314 clock-names = "apb", "smi", "gals"; 2315 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2316 }; 2317 2318 display@14f06000 { 2319 compatible = "mediatek,mt8195-mdp3-split"; 2320 reg = <0 0x14f06000 0 0x1000>; 2321 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; 2322 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, 2323 <&vppsys1 CLK_VPP1_HDMI_META>, 2324 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 2325 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2326 }; 2327 2328 display@14f07000 { 2329 compatible = "mediatek,mt8195-mdp3-tcc"; 2330 reg = <0 0x14f07000 0 0x1000>; 2331 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; 2332 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; 2333 }; 2334 2335 dma-controller@14f08000 { 2336 compatible = "mediatek,mt8195-mdp3-rdma"; 2337 reg = <0 0x14f08000 0 0x1000>; 2338 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; 2339 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>, 2340 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>; 2341 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; 2342 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; 2343 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2344 #dma-cells = <1>; 2345 }; 2346 2347 dma-controller@14f09000 { 2348 compatible = "mediatek,mt8195-mdp3-rdma"; 2349 reg = <0 0x14f09000 0 0x1000>; 2350 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2351 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2352 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2353 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2354 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; 2355 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2356 #dma-cells = <1>; 2357 }; 2358 2359 dma-controller@14f0a000 { 2360 compatible = "mediatek,mt8195-mdp3-rdma"; 2361 reg = <0 0x14f0a000 0 0x1000>; 2362 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2363 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2364 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2365 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2366 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; 2367 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2368 #dma-cells = <1>; 2369 }; 2370 2371 display@14f0b000 { 2372 compatible = "mediatek,mt8195-mdp3-fg"; 2373 reg = <0 0x14f0b000 0 0x1000>; 2374 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; 2375 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; 2376 }; 2377 2378 display@14f0c000 { 2379 compatible = "mediatek,mt8195-mdp3-fg"; 2380 reg = <0 0x14f0c000 0 0x1000>; 2381 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2382 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2383 }; 2384 2385 display@14f0d000 { 2386 compatible = "mediatek,mt8195-mdp3-fg"; 2387 reg = <0 0x14f0d000 0 0x1000>; 2388 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2389 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2390 }; 2391 2392 display@14f0e000 { 2393 compatible = "mediatek,mt8195-mdp3-hdr"; 2394 reg = <0 0x14f0e000 0 0x1000>; 2395 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; 2396 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; 2397 }; 2398 2399 display@14f0f000 { 2400 compatible = "mediatek,mt8195-mdp3-hdr"; 2401 reg = <0 0x14f0f000 0 0x1000>; 2402 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2403 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2404 }; 2405 2406 display@14f10000 { 2407 compatible = "mediatek,mt8195-mdp3-hdr"; 2408 reg = <0 0x14f10000 0 0x1000>; 2409 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2410 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2411 }; 2412 2413 display@14f11000 { 2414 compatible = "mediatek,mt8195-mdp3-aal"; 2415 reg = <0 0x14f11000 0 0x1000>; 2416 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>; 2417 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; 2418 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; 2419 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2420 }; 2421 2422 display@14f12000 { 2423 compatible = "mediatek,mt8195-mdp3-aal"; 2424 reg = <0 0x14f12000 0 0x1000>; 2425 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2426 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2427 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2428 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2429 }; 2430 2431 display@14f13000 { 2432 compatible = "mediatek,mt8195-mdp3-aal"; 2433 reg = <0 0x14f13000 0 0x1000>; 2434 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2435 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2436 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2437 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2438 }; 2439 2440 display@14f14000 { 2441 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2442 reg = <0 0x14f14000 0 0x1000>; 2443 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; 2444 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>, 2445 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>; 2446 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; 2447 }; 2448 2449 display@14f15000 { 2450 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2451 reg = <0 0x14f15000 0 0x1000>; 2452 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2453 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2454 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2455 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2456 }; 2457 2458 display@14f16000 { 2459 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2460 reg = <0 0x14f16000 0 0x1000>; 2461 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2462 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2463 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2464 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2465 }; 2466 2467 display@14f17000 { 2468 compatible = "mediatek,mt8195-mdp3-tdshp"; 2469 reg = <0 0x14f17000 0 0x1000>; 2470 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; 2471 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; 2472 }; 2473 2474 display@14f18000 { 2475 compatible = "mediatek,mt8195-mdp3-tdshp"; 2476 reg = <0 0x14f18000 0 0x1000>; 2477 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2478 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2479 }; 2480 2481 display@14f19000 { 2482 compatible = "mediatek,mt8195-mdp3-tdshp"; 2483 reg = <0 0x14f19000 0 0x1000>; 2484 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2485 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2486 }; 2487 2488 display@14f1a000 { 2489 compatible = "mediatek,mt8195-mdp3-merge"; 2490 reg = <0 0x14f1a000 0 0x1000>; 2491 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2492 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2493 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2494 }; 2495 2496 display@14f1b000 { 2497 compatible = "mediatek,mt8195-mdp3-merge"; 2498 reg = <0 0x14f1b000 0 0x1000>; 2499 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2500 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2501 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2502 }; 2503 2504 display@14f1c000 { 2505 compatible = "mediatek,mt8195-mdp3-color"; 2506 reg = <0 0x14f1c000 0 0x1000>; 2507 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>; 2508 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; 2509 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; 2510 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2511 }; 2512 2513 display@14f1d000 { 2514 compatible = "mediatek,mt8195-mdp3-color"; 2515 reg = <0 0x14f1d000 0 0x1000>; 2516 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2517 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2518 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2519 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2520 }; 2521 2522 display@14f1e000 { 2523 compatible = "mediatek,mt8195-mdp3-color"; 2524 reg = <0 0x14f1e000 0 0x1000>; 2525 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2526 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2527 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2528 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2529 }; 2530 2531 display@14f1f000 { 2532 compatible = "mediatek,mt8195-mdp3-ovl"; 2533 reg = <0 0x14f1f000 0 0x1000>; 2534 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>; 2535 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; 2536 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; 2537 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2538 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; 2539 }; 2540 2541 display@14f20000 { 2542 compatible = "mediatek,mt8195-mdp3-padding"; 2543 reg = <0 0x14f20000 0 0x1000>; 2544 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; 2545 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; 2546 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2547 }; 2548 2549 display@14f21000 { 2550 compatible = "mediatek,mt8195-mdp3-padding"; 2551 reg = <0 0x14f21000 0 0x1000>; 2552 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2553 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2554 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2555 }; 2556 2557 display@14f22000 { 2558 compatible = "mediatek,mt8195-mdp3-padding"; 2559 reg = <0 0x14f22000 0 0x1000>; 2560 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2561 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2562 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2563 }; 2564 2565 dma-controller@14f23000 { 2566 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2567 reg = <0 0x14f23000 0 0x1000>; 2568 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; 2569 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>, 2570 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>; 2571 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; 2572 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; 2573 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2574 #dma-cells = <1>; 2575 }; 2576 2577 dma-controller@14f24000 { 2578 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2579 reg = <0 0x14f24000 0 0x1000>; 2580 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2581 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2582 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2583 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2584 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; 2585 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2586 #dma-cells = <1>; 2587 }; 2588 2589 dma-controller@14f25000 { 2590 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2591 reg = <0 0x14f25000 0 0x1000>; 2592 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2593 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2594 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2595 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2596 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; 2597 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2598 #dma-cells = <1>; 2599 }; 2600 2601 imgsys: clock-controller@15000000 { 2602 compatible = "mediatek,mt8195-imgsys"; 2603 reg = <0 0x15000000 0 0x1000>; 2604 #clock-cells = <1>; 2605 }; 2606 2607 larb9: larb@15001000 { 2608 compatible = "mediatek,mt8195-smi-larb"; 2609 reg = <0 0x15001000 0 0x1000>; 2610 mediatek,larb-id = <9>; 2611 mediatek,smi = <&smi_sub_common_img1_3x1>; 2612 clocks = <&imgsys CLK_IMG_LARB9>, 2613 <&imgsys CLK_IMG_LARB9>, 2614 <&imgsys CLK_IMG_GALS>; 2615 clock-names = "apb", "smi", "gals"; 2616 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2617 }; 2618 2619 smi_sub_common_img0_3x1: smi@15002000 { 2620 compatible = "mediatek,mt8195-smi-sub-common"; 2621 reg = <0 0x15002000 0 0x1000>; 2622 clocks = <&imgsys CLK_IMG_IPE>, 2623 <&imgsys CLK_IMG_IPE>, 2624 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2625 clock-names = "apb", "smi", "gals0"; 2626 mediatek,smi = <&smi_common_vpp>; 2627 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2628 }; 2629 2630 smi_sub_common_img1_3x1: smi@15003000 { 2631 compatible = "mediatek,mt8195-smi-sub-common"; 2632 reg = <0 0x15003000 0 0x1000>; 2633 clocks = <&imgsys CLK_IMG_LARB9>, 2634 <&imgsys CLK_IMG_LARB9>, 2635 <&imgsys CLK_IMG_GALS>; 2636 clock-names = "apb", "smi", "gals0"; 2637 mediatek,smi = <&smi_common_vdo>; 2638 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2639 }; 2640 2641 imgsys1_dip_top: clock-controller@15110000 { 2642 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2643 reg = <0 0x15110000 0 0x1000>; 2644 #clock-cells = <1>; 2645 }; 2646 2647 larb10: larb@15120000 { 2648 compatible = "mediatek,mt8195-smi-larb"; 2649 reg = <0 0x15120000 0 0x1000>; 2650 mediatek,larb-id = <10>; 2651 mediatek,smi = <&smi_sub_common_img1_3x1>; 2652 clocks = <&imgsys CLK_IMG_DIP0>, 2653 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2654 clock-names = "apb", "smi"; 2655 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2656 }; 2657 2658 imgsys1_dip_nr: clock-controller@15130000 { 2659 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2660 reg = <0 0x15130000 0 0x1000>; 2661 #clock-cells = <1>; 2662 }; 2663 2664 imgsys1_wpe: clock-controller@15220000 { 2665 compatible = "mediatek,mt8195-imgsys1_wpe"; 2666 reg = <0 0x15220000 0 0x1000>; 2667 #clock-cells = <1>; 2668 }; 2669 2670 larb11: larb@15230000 { 2671 compatible = "mediatek,mt8195-smi-larb"; 2672 reg = <0 0x15230000 0 0x1000>; 2673 mediatek,larb-id = <11>; 2674 mediatek,smi = <&smi_sub_common_img1_3x1>; 2675 clocks = <&imgsys CLK_IMG_WPE0>, 2676 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2677 clock-names = "apb", "smi"; 2678 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2679 }; 2680 2681 ipesys: clock-controller@15330000 { 2682 compatible = "mediatek,mt8195-ipesys"; 2683 reg = <0 0x15330000 0 0x1000>; 2684 #clock-cells = <1>; 2685 }; 2686 2687 larb12: larb@15340000 { 2688 compatible = "mediatek,mt8195-smi-larb"; 2689 reg = <0 0x15340000 0 0x1000>; 2690 mediatek,larb-id = <12>; 2691 mediatek,smi = <&smi_sub_common_img0_3x1>; 2692 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2693 <&ipesys CLK_IPE_SMI_LARB12>; 2694 clock-names = "apb", "smi"; 2695 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2696 }; 2697 2698 camsys: clock-controller@16000000 { 2699 compatible = "mediatek,mt8195-camsys"; 2700 reg = <0 0x16000000 0 0x1000>; 2701 #clock-cells = <1>; 2702 }; 2703 2704 larb13: larb@16001000 { 2705 compatible = "mediatek,mt8195-smi-larb"; 2706 reg = <0 0x16001000 0 0x1000>; 2707 mediatek,larb-id = <13>; 2708 mediatek,smi = <&smi_sub_common_cam_4x1>; 2709 clocks = <&camsys CLK_CAM_LARB13>, 2710 <&camsys CLK_CAM_LARB13>, 2711 <&camsys CLK_CAM_CAM2MM0_GALS>; 2712 clock-names = "apb", "smi", "gals"; 2713 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2714 }; 2715 2716 larb14: larb@16002000 { 2717 compatible = "mediatek,mt8195-smi-larb"; 2718 reg = <0 0x16002000 0 0x1000>; 2719 mediatek,larb-id = <14>; 2720 mediatek,smi = <&smi_sub_common_cam_7x1>; 2721 clocks = <&camsys CLK_CAM_LARB14>, 2722 <&camsys CLK_CAM_LARB14>; 2723 clock-names = "apb", "smi"; 2724 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2725 }; 2726 2727 smi_sub_common_cam_4x1: smi@16004000 { 2728 compatible = "mediatek,mt8195-smi-sub-common"; 2729 reg = <0 0x16004000 0 0x1000>; 2730 clocks = <&camsys CLK_CAM_LARB13>, 2731 <&camsys CLK_CAM_LARB13>, 2732 <&camsys CLK_CAM_CAM2MM0_GALS>; 2733 clock-names = "apb", "smi", "gals0"; 2734 mediatek,smi = <&smi_common_vdo>; 2735 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2736 }; 2737 2738 smi_sub_common_cam_7x1: smi@16005000 { 2739 compatible = "mediatek,mt8195-smi-sub-common"; 2740 reg = <0 0x16005000 0 0x1000>; 2741 clocks = <&camsys CLK_CAM_LARB14>, 2742 <&camsys CLK_CAM_CAM2MM1_GALS>, 2743 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2744 clock-names = "apb", "smi", "gals0"; 2745 mediatek,smi = <&smi_common_vpp>; 2746 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2747 }; 2748 2749 larb16: larb@16012000 { 2750 compatible = "mediatek,mt8195-smi-larb"; 2751 reg = <0 0x16012000 0 0x1000>; 2752 mediatek,larb-id = <16>; 2753 mediatek,smi = <&smi_sub_common_cam_7x1>; 2754 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2755 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2756 clock-names = "apb", "smi"; 2757 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2758 }; 2759 2760 larb17: larb@16013000 { 2761 compatible = "mediatek,mt8195-smi-larb"; 2762 reg = <0 0x16013000 0 0x1000>; 2763 mediatek,larb-id = <17>; 2764 mediatek,smi = <&smi_sub_common_cam_4x1>; 2765 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2766 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2767 clock-names = "apb", "smi"; 2768 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2769 }; 2770 2771 larb27: larb@16014000 { 2772 compatible = "mediatek,mt8195-smi-larb"; 2773 reg = <0 0x16014000 0 0x1000>; 2774 mediatek,larb-id = <27>; 2775 mediatek,smi = <&smi_sub_common_cam_7x1>; 2776 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2777 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2778 clock-names = "apb", "smi"; 2779 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2780 }; 2781 2782 larb28: larb@16015000 { 2783 compatible = "mediatek,mt8195-smi-larb"; 2784 reg = <0 0x16015000 0 0x1000>; 2785 mediatek,larb-id = <28>; 2786 mediatek,smi = <&smi_sub_common_cam_4x1>; 2787 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2788 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2789 clock-names = "apb", "smi"; 2790 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2791 }; 2792 2793 camsys_rawa: clock-controller@1604f000 { 2794 compatible = "mediatek,mt8195-camsys_rawa"; 2795 reg = <0 0x1604f000 0 0x1000>; 2796 #clock-cells = <1>; 2797 }; 2798 2799 camsys_yuva: clock-controller@1606f000 { 2800 compatible = "mediatek,mt8195-camsys_yuva"; 2801 reg = <0 0x1606f000 0 0x1000>; 2802 #clock-cells = <1>; 2803 }; 2804 2805 camsys_rawb: clock-controller@1608f000 { 2806 compatible = "mediatek,mt8195-camsys_rawb"; 2807 reg = <0 0x1608f000 0 0x1000>; 2808 #clock-cells = <1>; 2809 }; 2810 2811 camsys_yuvb: clock-controller@160af000 { 2812 compatible = "mediatek,mt8195-camsys_yuvb"; 2813 reg = <0 0x160af000 0 0x1000>; 2814 #clock-cells = <1>; 2815 }; 2816 2817 camsys_mraw: clock-controller@16140000 { 2818 compatible = "mediatek,mt8195-camsys_mraw"; 2819 reg = <0 0x16140000 0 0x1000>; 2820 #clock-cells = <1>; 2821 }; 2822 2823 larb25: larb@16141000 { 2824 compatible = "mediatek,mt8195-smi-larb"; 2825 reg = <0 0x16141000 0 0x1000>; 2826 mediatek,larb-id = <25>; 2827 mediatek,smi = <&smi_sub_common_cam_4x1>; 2828 clocks = <&camsys CLK_CAM_LARB13>, 2829 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2830 <&camsys CLK_CAM_CAM2MM0_GALS>; 2831 clock-names = "apb", "smi", "gals"; 2832 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2833 }; 2834 2835 larb26: larb@16142000 { 2836 compatible = "mediatek,mt8195-smi-larb"; 2837 reg = <0 0x16142000 0 0x1000>; 2838 mediatek,larb-id = <26>; 2839 mediatek,smi = <&smi_sub_common_cam_7x1>; 2840 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2841 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2842 clock-names = "apb", "smi"; 2843 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2844 2845 }; 2846 2847 ccusys: clock-controller@17200000 { 2848 compatible = "mediatek,mt8195-ccusys"; 2849 reg = <0 0x17200000 0 0x1000>; 2850 #clock-cells = <1>; 2851 }; 2852 2853 larb18: larb@17201000 { 2854 compatible = "mediatek,mt8195-smi-larb"; 2855 reg = <0 0x17201000 0 0x1000>; 2856 mediatek,larb-id = <18>; 2857 mediatek,smi = <&smi_sub_common_cam_7x1>; 2858 clocks = <&ccusys CLK_CCU_LARB18>, 2859 <&ccusys CLK_CCU_LARB18>; 2860 clock-names = "apb", "smi"; 2861 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2862 }; 2863 2864 video-codec@18000000 { 2865 compatible = "mediatek,mt8195-vcodec-dec"; 2866 mediatek,scp = <&scp>; 2867 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2868 #address-cells = <2>; 2869 #size-cells = <2>; 2870 reg = <0 0x18000000 0 0x1000>, 2871 <0 0x18004000 0 0x1000>; 2872 ranges = <0 0 0 0x18000000 0 0x26000>; 2873 2874 video-codec@2000 { 2875 compatible = "mediatek,mtk-vcodec-lat-soc"; 2876 reg = <0 0x2000 0 0x800>; 2877 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2878 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2879 clocks = <&topckgen CLK_TOP_VDEC>, 2880 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2881 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2882 <&topckgen CLK_TOP_UNIVPLL_D4>; 2883 clock-names = "sel", "vdec", "lat", "top"; 2884 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2885 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2886 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2887 }; 2888 2889 video-codec@10000 { 2890 compatible = "mediatek,mtk-vcodec-lat"; 2891 reg = <0 0x10000 0 0x800>; 2892 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2893 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2894 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2895 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2896 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2897 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2898 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2899 clocks = <&topckgen CLK_TOP_VDEC>, 2900 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2901 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2902 <&topckgen CLK_TOP_UNIVPLL_D4>; 2903 clock-names = "sel", "vdec", "lat", "top"; 2904 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2905 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2906 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2907 }; 2908 2909 video-codec@25000 { 2910 compatible = "mediatek,mtk-vcodec-core"; 2911 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2912 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2913 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2914 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2915 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2916 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2917 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2918 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2919 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2920 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2921 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2922 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2923 clocks = <&topckgen CLK_TOP_VDEC>, 2924 <&vdecsys CLK_VDEC_VDEC>, 2925 <&vdecsys CLK_VDEC_LAT>, 2926 <&topckgen CLK_TOP_UNIVPLL_D4>; 2927 clock-names = "sel", "vdec", "lat", "top"; 2928 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2929 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2930 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2931 }; 2932 }; 2933 2934 larb24: larb@1800d000 { 2935 compatible = "mediatek,mt8195-smi-larb"; 2936 reg = <0 0x1800d000 0 0x1000>; 2937 mediatek,larb-id = <24>; 2938 mediatek,smi = <&smi_common_vdo>; 2939 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2940 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2941 clock-names = "apb", "smi"; 2942 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2943 }; 2944 2945 larb23: larb@1800e000 { 2946 compatible = "mediatek,mt8195-smi-larb"; 2947 reg = <0 0x1800e000 0 0x1000>; 2948 mediatek,larb-id = <23>; 2949 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2950 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2951 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2952 clock-names = "apb", "smi"; 2953 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2954 }; 2955 2956 vdecsys_soc: clock-controller@1800f000 { 2957 compatible = "mediatek,mt8195-vdecsys_soc"; 2958 reg = <0 0x1800f000 0 0x1000>; 2959 #clock-cells = <1>; 2960 }; 2961 2962 larb21: larb@1802e000 { 2963 compatible = "mediatek,mt8195-smi-larb"; 2964 reg = <0 0x1802e000 0 0x1000>; 2965 mediatek,larb-id = <21>; 2966 mediatek,smi = <&smi_common_vdo>; 2967 clocks = <&vdecsys CLK_VDEC_LARB1>, 2968 <&vdecsys CLK_VDEC_LARB1>; 2969 clock-names = "apb", "smi"; 2970 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2971 }; 2972 2973 vdecsys: clock-controller@1802f000 { 2974 compatible = "mediatek,mt8195-vdecsys"; 2975 reg = <0 0x1802f000 0 0x1000>; 2976 #clock-cells = <1>; 2977 }; 2978 2979 larb22: larb@1803e000 { 2980 compatible = "mediatek,mt8195-smi-larb"; 2981 reg = <0 0x1803e000 0 0x1000>; 2982 mediatek,larb-id = <22>; 2983 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2984 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2985 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2986 clock-names = "apb", "smi"; 2987 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2988 }; 2989 2990 vdecsys_core1: clock-controller@1803f000 { 2991 compatible = "mediatek,mt8195-vdecsys_core1"; 2992 reg = <0 0x1803f000 0 0x1000>; 2993 #clock-cells = <1>; 2994 }; 2995 2996 apusys_pll: clock-controller@190f3000 { 2997 compatible = "mediatek,mt8195-apusys_pll"; 2998 reg = <0 0x190f3000 0 0x1000>; 2999 #clock-cells = <1>; 3000 }; 3001 3002 vencsys: clock-controller@1a000000 { 3003 compatible = "mediatek,mt8195-vencsys"; 3004 reg = <0 0x1a000000 0 0x1000>; 3005 #clock-cells = <1>; 3006 }; 3007 3008 larb19: larb@1a010000 { 3009 compatible = "mediatek,mt8195-smi-larb"; 3010 reg = <0 0x1a010000 0 0x1000>; 3011 mediatek,larb-id = <19>; 3012 mediatek,smi = <&smi_common_vdo>; 3013 clocks = <&vencsys CLK_VENC_VENC>, 3014 <&vencsys CLK_VENC_GALS>; 3015 clock-names = "apb", "smi"; 3016 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3017 }; 3018 3019 venc: video-codec@1a020000 { 3020 compatible = "mediatek,mt8195-vcodec-enc"; 3021 reg = <0 0x1a020000 0 0x10000>; 3022 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 3023 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 3024 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 3025 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 3026 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 3027 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 3028 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 3029 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 3030 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 3031 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 3032 mediatek,scp = <&scp>; 3033 clocks = <&vencsys CLK_VENC_VENC>; 3034 clock-names = "venc_sel"; 3035 assigned-clocks = <&topckgen CLK_TOP_VENC>; 3036 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 3037 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3038 #address-cells = <2>; 3039 #size-cells = <2>; 3040 }; 3041 3042 jpgdec-master { 3043 compatible = "mediatek,mt8195-jpgdec"; 3044 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3045 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3046 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3047 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3048 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3049 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3050 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3051 #address-cells = <2>; 3052 #size-cells = <2>; 3053 ranges; 3054 3055 jpgdec@1a040000 { 3056 compatible = "mediatek,mt8195-jpgdec-hw"; 3057 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */ 3058 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3059 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3060 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3061 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3062 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3063 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3064 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 3065 clocks = <&vencsys CLK_VENC_JPGDEC>; 3066 clock-names = "jpgdec"; 3067 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 3068 }; 3069 3070 jpgdec@1a050000 { 3071 compatible = "mediatek,mt8195-jpgdec-hw"; 3072 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */ 3073 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3074 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3075 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3076 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3077 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3078 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3079 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 3080 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 3081 clock-names = "jpgdec"; 3082 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3083 }; 3084 3085 jpgdec@1b040000 { 3086 compatible = "mediatek,mt8195-jpgdec-hw"; 3087 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */ 3088 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 3089 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 3090 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 3091 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 3092 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 3093 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 3094 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 3095 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 3096 clock-names = "jpgdec"; 3097 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 3098 }; 3099 }; 3100 3101 vencsys_core1: clock-controller@1b000000 { 3102 compatible = "mediatek,mt8195-vencsys_core1"; 3103 reg = <0 0x1b000000 0 0x1000>; 3104 #clock-cells = <1>; 3105 }; 3106 3107 vdosys0: syscon@1c01a000 { 3108 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 3109 reg = <0 0x1c01a000 0 0x1000>; 3110 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3111 #clock-cells = <1>; 3112 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 3113 }; 3114 3115 3116 jpgenc-master { 3117 compatible = "mediatek,mt8195-jpgenc"; 3118 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3119 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3120 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3121 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3122 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3123 #address-cells = <2>; 3124 #size-cells = <2>; 3125 ranges; 3126 3127 jpgenc@1a030000 { 3128 compatible = "mediatek,mt8195-jpgenc-hw"; 3129 reg = <0 0x1a030000 0 0x10000>; 3130 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 3131 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 3132 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 3133 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 3134 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 3135 clocks = <&vencsys CLK_VENC_JPGENC>; 3136 clock-names = "jpgenc"; 3137 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3138 }; 3139 3140 jpgenc@1b030000 { 3141 compatible = "mediatek,mt8195-jpgenc-hw"; 3142 reg = <0 0x1b030000 0 0x10000>; 3143 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3144 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3145 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3146 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3147 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 3148 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 3149 clock-names = "jpgenc"; 3150 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3151 }; 3152 }; 3153 3154 larb20: larb@1b010000 { 3155 compatible = "mediatek,mt8195-smi-larb"; 3156 reg = <0 0x1b010000 0 0x1000>; 3157 mediatek,larb-id = <20>; 3158 mediatek,smi = <&smi_common_vpp>; 3159 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, 3160 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 3161 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3162 clock-names = "apb", "smi", "gals"; 3163 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3164 }; 3165 3166 ovl0: ovl@1c000000 { 3167 compatible = "mediatek,mt8195-disp-ovl"; 3168 reg = <0 0x1c000000 0 0x1000>; 3169 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 3170 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3171 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 3172 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 3173 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 3174 3175 ports { 3176 #address-cells = <1>; 3177 #size-cells = <0>; 3178 3179 port@0 { 3180 reg = <0>; 3181 ovl0_in: endpoint { }; 3182 }; 3183 3184 port@1 { 3185 reg = <1>; 3186 ovl0_out: endpoint { 3187 remote-endpoint = <&rdma0_in>; 3188 }; 3189 }; 3190 }; 3191 }; 3192 3193 rdma0: rdma@1c002000 { 3194 compatible = "mediatek,mt8195-disp-rdma"; 3195 reg = <0 0x1c002000 0 0x1000>; 3196 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 3197 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3198 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 3199 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 3200 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 3201 3202 ports { 3203 #address-cells = <1>; 3204 #size-cells = <0>; 3205 3206 port@0 { 3207 reg = <0>; 3208 rdma0_in: endpoint { 3209 remote-endpoint = <&ovl0_out>; 3210 }; 3211 }; 3212 3213 port@1 { 3214 reg = <1>; 3215 rdma0_out: endpoint { 3216 remote-endpoint = <&color0_in>; 3217 }; 3218 }; 3219 }; 3220 }; 3221 3222 color0: color@1c003000 { 3223 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 3224 reg = <0 0x1c003000 0 0x1000>; 3225 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 3226 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3227 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 3228 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 3229 3230 ports { 3231 #address-cells = <1>; 3232 #size-cells = <0>; 3233 3234 port@0 { 3235 reg = <0>; 3236 color0_in: endpoint { 3237 remote-endpoint = <&rdma0_out>; 3238 }; 3239 }; 3240 3241 port@1 { 3242 reg = <1>; 3243 color0_out: endpoint { 3244 remote-endpoint = <&ccorr0_in>; 3245 }; 3246 }; 3247 }; 3248 }; 3249 3250 ccorr0: ccorr@1c004000 { 3251 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 3252 reg = <0 0x1c004000 0 0x1000>; 3253 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 3254 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3255 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 3256 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 3257 3258 ports { 3259 #address-cells = <1>; 3260 #size-cells = <0>; 3261 3262 port@0 { 3263 reg = <0>; 3264 ccorr0_in: endpoint { 3265 remote-endpoint = <&color0_out>; 3266 }; 3267 }; 3268 3269 port@1 { 3270 reg = <1>; 3271 ccorr0_out: endpoint { 3272 remote-endpoint = <&aal0_in>; 3273 }; 3274 }; 3275 }; 3276 }; 3277 3278 aal0: aal@1c005000 { 3279 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 3280 reg = <0 0x1c005000 0 0x1000>; 3281 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 3282 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3283 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 3284 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 3285 3286 ports { 3287 #address-cells = <1>; 3288 #size-cells = <0>; 3289 3290 port@0 { 3291 reg = <0>; 3292 aal0_in: endpoint { 3293 remote-endpoint = <&ccorr0_out>; 3294 }; 3295 }; 3296 3297 port@1 { 3298 reg = <1>; 3299 aal0_out: endpoint { 3300 remote-endpoint = <&gamma0_in>; 3301 }; 3302 }; 3303 }; 3304 }; 3305 3306 gamma0: gamma@1c006000 { 3307 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 3308 reg = <0 0x1c006000 0 0x1000>; 3309 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3310 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3311 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3312 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3313 3314 ports { 3315 #address-cells = <1>; 3316 #size-cells = <0>; 3317 3318 port@0 { 3319 reg = <0>; 3320 gamma0_in: endpoint { 3321 remote-endpoint = <&aal0_out>; 3322 }; 3323 }; 3324 3325 port@1 { 3326 reg = <1>; 3327 gamma0_out: endpoint { 3328 remote-endpoint = <&dither0_in>; 3329 }; 3330 }; 3331 }; 3332 }; 3333 3334 dither0: dither@1c007000 { 3335 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 3336 reg = <0 0x1c007000 0 0x1000>; 3337 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3338 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3339 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3340 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3341 3342 ports { 3343 #address-cells = <1>; 3344 #size-cells = <0>; 3345 3346 port@0 { 3347 reg = <0>; 3348 dither0_in: endpoint { 3349 remote-endpoint = <&gamma0_out>; 3350 }; 3351 }; 3352 3353 port@1 { 3354 reg = <1>; 3355 dither0_out: endpoint { }; 3356 }; 3357 }; 3358 }; 3359 3360 dsi0: dsi@1c008000 { 3361 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3362 reg = <0 0x1c008000 0 0x1000>; 3363 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3364 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3365 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3366 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3367 <&mipi_tx0>; 3368 clock-names = "engine", "digital", "hs"; 3369 phys = <&mipi_tx0>; 3370 phy-names = "dphy"; 3371 status = "disabled"; 3372 }; 3373 3374 dsc0: dsc@1c009000 { 3375 compatible = "mediatek,mt8195-disp-dsc"; 3376 reg = <0 0x1c009000 0 0x1000>; 3377 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3378 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3379 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3380 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3381 }; 3382 3383 dsi1: dsi@1c012000 { 3384 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3385 reg = <0 0x1c012000 0 0x1000>; 3386 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3387 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3388 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3389 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3390 <&mipi_tx1>; 3391 clock-names = "engine", "digital", "hs"; 3392 phys = <&mipi_tx1>; 3393 phy-names = "dphy"; 3394 status = "disabled"; 3395 }; 3396 3397 merge0: merge@1c014000 { 3398 compatible = "mediatek,mt8195-disp-merge"; 3399 reg = <0 0x1c014000 0 0x1000>; 3400 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3401 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3402 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 3403 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3404 }; 3405 3406 dp_intf0: dp-intf@1c015000 { 3407 compatible = "mediatek,mt8195-dp-intf"; 3408 reg = <0 0x1c015000 0 0x1000>; 3409 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3410 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3411 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3412 <&vdosys0 CLK_VDO0_DP_INTF0>, 3413 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3414 clock-names = "pixel", "engine", "pll"; 3415 status = "disabled"; 3416 }; 3417 3418 mutex: mutex@1c016000 { 3419 compatible = "mediatek,mt8195-disp-mutex"; 3420 reg = <0 0x1c016000 0 0x1000>; 3421 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3422 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3423 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3424 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 3425 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3426 }; 3427 3428 larb0: larb@1c018000 { 3429 compatible = "mediatek,mt8195-smi-larb"; 3430 reg = <0 0x1c018000 0 0x1000>; 3431 mediatek,larb-id = <0>; 3432 mediatek,smi = <&smi_common_vdo>; 3433 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3434 <&vdosys0 CLK_VDO0_SMI_LARB>, 3435 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 3436 clock-names = "apb", "smi", "gals"; 3437 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3438 }; 3439 3440 larb1: larb@1c019000 { 3441 compatible = "mediatek,mt8195-smi-larb"; 3442 reg = <0 0x1c019000 0 0x1000>; 3443 mediatek,larb-id = <1>; 3444 mediatek,smi = <&smi_common_vpp>; 3445 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3446 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 3447 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 3448 clock-names = "apb", "smi", "gals"; 3449 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3450 }; 3451 3452 vdosys1: syscon@1c100000 { 3453 compatible = "mediatek,mt8195-vdosys1", "syscon"; 3454 reg = <0 0x1c100000 0 0x1000>; 3455 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3456 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 3457 #clock-cells = <1>; 3458 #reset-cells = <1>; 3459 }; 3460 3461 smi_common_vdo: smi@1c01b000 { 3462 compatible = "mediatek,mt8195-smi-common-vdo"; 3463 reg = <0 0x1c01b000 0 0x1000>; 3464 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3465 <&vdosys0 CLK_VDO0_SMI_EMI>, 3466 <&vdosys0 CLK_VDO0_SMI_RSI>, 3467 <&vdosys0 CLK_VDO0_SMI_GALS>; 3468 clock-names = "apb", "smi", "gals0", "gals1"; 3469 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3470 3471 }; 3472 3473 iommu_vdo: iommu@1c01f000 { 3474 compatible = "mediatek,mt8195-iommu-vdo"; 3475 reg = <0 0x1c01f000 0 0x1000>; 3476 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 3477 &larb10 &larb11 &larb13 &larb17 3478 &larb19 &larb21 &larb24 &larb25 3479 &larb28>; 3480 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 3481 #iommu-cells = <1>; 3482 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3483 clock-names = "bclk"; 3484 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3485 }; 3486 3487 mutex1: mutex@1c101000 { 3488 compatible = "mediatek,mt8195-disp-mutex"; 3489 reg = <0 0x1c101000 0 0x1000>; 3490 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3491 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3492 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3493 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 3494 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3495 }; 3496 3497 larb2: larb@1c102000 { 3498 compatible = "mediatek,mt8195-smi-larb"; 3499 reg = <0 0x1c102000 0 0x1000>; 3500 mediatek,larb-id = <2>; 3501 mediatek,smi = <&smi_common_vdo>; 3502 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3503 <&vdosys1 CLK_VDO1_SMI_LARB2>, 3504 <&vdosys1 CLK_VDO1_GALS>; 3505 clock-names = "apb", "smi", "gals"; 3506 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3507 }; 3508 3509 larb3: larb@1c103000 { 3510 compatible = "mediatek,mt8195-smi-larb"; 3511 reg = <0 0x1c103000 0 0x1000>; 3512 mediatek,larb-id = <3>; 3513 mediatek,smi = <&smi_common_vpp>; 3514 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3515 <&vdosys1 CLK_VDO1_GALS>, 3516 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3517 clock-names = "apb", "smi", "gals"; 3518 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3519 }; 3520 3521 vdo1_rdma0: dma-controller@1c104000 { 3522 compatible = "mediatek,mt8195-vdo1-rdma"; 3523 reg = <0 0x1c104000 0 0x1000>; 3524 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3525 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3526 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3527 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 3528 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3529 #dma-cells = <1>; 3530 }; 3531 3532 vdo1_rdma1: dma-controller@1c105000 { 3533 compatible = "mediatek,mt8195-vdo1-rdma"; 3534 reg = <0 0x1c105000 0 0x1000>; 3535 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3536 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3537 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3538 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 3539 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3540 #dma-cells = <1>; 3541 }; 3542 3543 vdo1_rdma2: dma-controller@1c106000 { 3544 compatible = "mediatek,mt8195-vdo1-rdma"; 3545 reg = <0 0x1c106000 0 0x1000>; 3546 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3547 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3548 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3549 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 3550 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3551 #dma-cells = <1>; 3552 }; 3553 3554 vdo1_rdma3: dma-controller@1c107000 { 3555 compatible = "mediatek,mt8195-vdo1-rdma"; 3556 reg = <0 0x1c107000 0 0x1000>; 3557 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3558 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3559 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3560 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 3561 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3562 #dma-cells = <1>; 3563 }; 3564 3565 vdo1_rdma4: dma-controller@1c108000 { 3566 compatible = "mediatek,mt8195-vdo1-rdma"; 3567 reg = <0 0x1c108000 0 0x1000>; 3568 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3569 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3570 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3571 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 3572 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3573 #dma-cells = <1>; 3574 }; 3575 3576 vdo1_rdma5: dma-controller@1c109000 { 3577 compatible = "mediatek,mt8195-vdo1-rdma"; 3578 reg = <0 0x1c109000 0 0x1000>; 3579 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3580 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3581 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3582 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 3583 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3584 #dma-cells = <1>; 3585 }; 3586 3587 vdo1_rdma6: dma-controller@1c10a000 { 3588 compatible = "mediatek,mt8195-vdo1-rdma"; 3589 reg = <0 0x1c10a000 0 0x1000>; 3590 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3591 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3592 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3593 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 3594 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3595 #dma-cells = <1>; 3596 }; 3597 3598 vdo1_rdma7: dma-controller@1c10b000 { 3599 compatible = "mediatek,mt8195-vdo1-rdma"; 3600 reg = <0 0x1c10b000 0 0x1000>; 3601 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3602 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3603 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3604 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 3605 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3606 #dma-cells = <1>; 3607 }; 3608 3609 merge1: vpp-merge@1c10c000 { 3610 compatible = "mediatek,mt8195-disp-merge"; 3611 reg = <0 0x1c10c000 0 0x1000>; 3612 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3613 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3614 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3615 clock-names = "merge","merge_async"; 3616 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3617 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3618 mediatek,merge-mute; 3619 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 3620 }; 3621 3622 merge2: vpp-merge@1c10d000 { 3623 compatible = "mediatek,mt8195-disp-merge"; 3624 reg = <0 0x1c10d000 0 0x1000>; 3625 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3626 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3627 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3628 clock-names = "merge","merge_async"; 3629 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3630 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3631 mediatek,merge-mute; 3632 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 3633 }; 3634 3635 merge3: vpp-merge@1c10e000 { 3636 compatible = "mediatek,mt8195-disp-merge"; 3637 reg = <0 0x1c10e000 0 0x1000>; 3638 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3639 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3640 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3641 clock-names = "merge","merge_async"; 3642 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3643 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3644 mediatek,merge-mute; 3645 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3646 }; 3647 3648 merge4: vpp-merge@1c10f000 { 3649 compatible = "mediatek,mt8195-disp-merge"; 3650 reg = <0 0x1c10f000 0 0x1000>; 3651 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3652 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3653 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3654 clock-names = "merge","merge_async"; 3655 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3656 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3657 mediatek,merge-mute; 3658 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3659 }; 3660 3661 merge5: vpp-merge@1c110000 { 3662 compatible = "mediatek,mt8195-disp-merge"; 3663 reg = <0 0x1c110000 0 0x1000>; 3664 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3665 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3666 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3667 clock-names = "merge","merge_async"; 3668 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3669 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3670 mediatek,merge-fifo-en; 3671 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3672 }; 3673 3674 dp_intf1: dp-intf@1c113000 { 3675 compatible = "mediatek,mt8195-dp-intf"; 3676 reg = <0 0x1c113000 0 0x1000>; 3677 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3678 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3679 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3680 <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3681 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3682 clock-names = "pixel", "engine", "pll"; 3683 status = "disabled"; 3684 }; 3685 3686 ethdr0: hdr-engine@1c114000 { 3687 compatible = "mediatek,mt8195-disp-ethdr"; 3688 reg = <0 0x1c114000 0 0x1000>, 3689 <0 0x1c115000 0 0x1000>, 3690 <0 0x1c117000 0 0x1000>, 3691 <0 0x1c119000 0 0x1000>, 3692 <0 0x1c11a000 0 0x1000>, 3693 <0 0x1c11b000 0 0x1000>, 3694 <0 0x1c11c000 0 0x1000>; 3695 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3696 "vdo_be", "adl_ds"; 3697 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3698 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3699 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3700 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3701 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3702 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3703 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3704 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3705 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3706 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3707 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3708 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3709 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3710 <&vdosys1 CLK_VDO1_26M_SLOW>, 3711 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3712 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3713 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3714 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3715 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3716 <&topckgen CLK_TOP_ETHDR>; 3717 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3718 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3719 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3720 "ethdr_top"; 3721 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3722 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3723 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3724 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3725 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3726 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3727 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3728 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3729 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3730 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3731 "gfx_fe1_async", "vdo_be_async"; 3732 }; 3733 3734 edp_tx: edp-tx@1c500000 { 3735 compatible = "mediatek,mt8195-edp-tx"; 3736 reg = <0 0x1c500000 0 0x8000>; 3737 nvmem-cells = <&dp_calibration>; 3738 nvmem-cell-names = "dp_calibration_data"; 3739 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3740 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3741 max-linkrate-mhz = <8100>; 3742 status = "disabled"; 3743 }; 3744 3745 dp_tx: dp-tx@1c600000 { 3746 compatible = "mediatek,mt8195-dp-tx"; 3747 reg = <0 0x1c600000 0 0x8000>; 3748 nvmem-cells = <&dp_calibration>; 3749 nvmem-cell-names = "dp_calibration_data"; 3750 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3751 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3752 max-linkrate-mhz = <8100>; 3753 status = "disabled"; 3754 }; 3755 }; 3756 3757 thermal_zones: thermal-zones { 3758 cpu0-thermal { 3759 polling-delay = <1000>; 3760 polling-delay-passive = <250>; 3761 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3762 3763 trips { 3764 cpu0_alert: trip-alert { 3765 temperature = <85000>; 3766 hysteresis = <2000>; 3767 type = "passive"; 3768 }; 3769 3770 cpu0_crit: trip-crit { 3771 temperature = <100000>; 3772 hysteresis = <2000>; 3773 type = "critical"; 3774 }; 3775 }; 3776 3777 cooling-maps { 3778 map0 { 3779 trip = <&cpu0_alert>; 3780 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3783 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3784 }; 3785 }; 3786 }; 3787 3788 cpu1-thermal { 3789 polling-delay = <1000>; 3790 polling-delay-passive = <250>; 3791 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3792 3793 trips { 3794 cpu1_alert: trip-alert { 3795 temperature = <85000>; 3796 hysteresis = <2000>; 3797 type = "passive"; 3798 }; 3799 3800 cpu1_crit: trip-crit { 3801 temperature = <100000>; 3802 hysteresis = <2000>; 3803 type = "critical"; 3804 }; 3805 }; 3806 3807 cooling-maps { 3808 map0 { 3809 trip = <&cpu1_alert>; 3810 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3814 }; 3815 }; 3816 }; 3817 3818 cpu2-thermal { 3819 polling-delay = <1000>; 3820 polling-delay-passive = <250>; 3821 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3822 3823 trips { 3824 cpu2_alert: trip-alert { 3825 temperature = <85000>; 3826 hysteresis = <2000>; 3827 type = "passive"; 3828 }; 3829 3830 cpu2_crit: trip-crit { 3831 temperature = <100000>; 3832 hysteresis = <2000>; 3833 type = "critical"; 3834 }; 3835 }; 3836 3837 cooling-maps { 3838 map0 { 3839 trip = <&cpu2_alert>; 3840 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3841 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3844 }; 3845 }; 3846 }; 3847 3848 cpu3-thermal { 3849 polling-delay = <1000>; 3850 polling-delay-passive = <250>; 3851 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3852 3853 trips { 3854 cpu3_alert: trip-alert { 3855 temperature = <85000>; 3856 hysteresis = <2000>; 3857 type = "passive"; 3858 }; 3859 3860 cpu3_crit: trip-crit { 3861 temperature = <100000>; 3862 hysteresis = <2000>; 3863 type = "critical"; 3864 }; 3865 }; 3866 3867 cooling-maps { 3868 map0 { 3869 trip = <&cpu3_alert>; 3870 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3874 }; 3875 }; 3876 }; 3877 3878 cpu4-thermal { 3879 polling-delay = <1000>; 3880 polling-delay-passive = <250>; 3881 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3882 3883 trips { 3884 cpu4_alert: trip-alert { 3885 temperature = <85000>; 3886 hysteresis = <2000>; 3887 type = "passive"; 3888 }; 3889 3890 cpu4_crit: trip-crit { 3891 temperature = <100000>; 3892 hysteresis = <2000>; 3893 type = "critical"; 3894 }; 3895 }; 3896 3897 cooling-maps { 3898 map0 { 3899 trip = <&cpu4_alert>; 3900 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3904 }; 3905 }; 3906 }; 3907 3908 cpu5-thermal { 3909 polling-delay = <1000>; 3910 polling-delay-passive = <250>; 3911 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3912 3913 trips { 3914 cpu5_alert: trip-alert { 3915 temperature = <85000>; 3916 hysteresis = <2000>; 3917 type = "passive"; 3918 }; 3919 3920 cpu5_crit: trip-crit { 3921 temperature = <100000>; 3922 hysteresis = <2000>; 3923 type = "critical"; 3924 }; 3925 }; 3926 3927 cooling-maps { 3928 map0 { 3929 trip = <&cpu5_alert>; 3930 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3933 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3934 }; 3935 }; 3936 }; 3937 3938 cpu6-thermal { 3939 polling-delay = <1000>; 3940 polling-delay-passive = <250>; 3941 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3942 3943 trips { 3944 cpu6_alert: trip-alert { 3945 temperature = <85000>; 3946 hysteresis = <2000>; 3947 type = "passive"; 3948 }; 3949 3950 cpu6_crit: trip-crit { 3951 temperature = <100000>; 3952 hysteresis = <2000>; 3953 type = "critical"; 3954 }; 3955 }; 3956 3957 cooling-maps { 3958 map0 { 3959 trip = <&cpu6_alert>; 3960 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3964 }; 3965 }; 3966 }; 3967 3968 cpu7-thermal { 3969 polling-delay = <1000>; 3970 polling-delay-passive = <250>; 3971 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3972 3973 trips { 3974 cpu7_alert: trip-alert { 3975 temperature = <85000>; 3976 hysteresis = <2000>; 3977 type = "passive"; 3978 }; 3979 3980 cpu7_crit: trip-crit { 3981 temperature = <100000>; 3982 hysteresis = <2000>; 3983 type = "critical"; 3984 }; 3985 }; 3986 3987 cooling-maps { 3988 map0 { 3989 trip = <&cpu7_alert>; 3990 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3992 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3993 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3994 }; 3995 }; 3996 }; 3997 3998 vpu0-thermal { 3999 polling-delay = <1000>; 4000 polling-delay-passive = <250>; 4001 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 4002 4003 trips { 4004 vpu0_alert: trip-alert { 4005 temperature = <85000>; 4006 hysteresis = <2000>; 4007 type = "passive"; 4008 }; 4009 4010 vpu0_crit: trip-crit { 4011 temperature = <100000>; 4012 hysteresis = <2000>; 4013 type = "critical"; 4014 }; 4015 }; 4016 }; 4017 4018 vpu1-thermal { 4019 polling-delay = <1000>; 4020 polling-delay-passive = <250>; 4021 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 4022 4023 trips { 4024 vpu1_alert: trip-alert { 4025 temperature = <85000>; 4026 hysteresis = <2000>; 4027 type = "passive"; 4028 }; 4029 4030 vpu1_crit: trip-crit { 4031 temperature = <100000>; 4032 hysteresis = <2000>; 4033 type = "critical"; 4034 }; 4035 }; 4036 }; 4037 4038 gpu-thermal { 4039 polling-delay = <1000>; 4040 polling-delay-passive = <250>; 4041 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 4042 4043 trips { 4044 gpu0_alert: trip-alert { 4045 temperature = <85000>; 4046 hysteresis = <2000>; 4047 type = "passive"; 4048 }; 4049 4050 gpu0_crit: trip-crit { 4051 temperature = <100000>; 4052 hysteresis = <2000>; 4053 type = "critical"; 4054 }; 4055 }; 4056 }; 4057 4058 gpu1-thermal { 4059 polling-delay = <1000>; 4060 polling-delay-passive = <250>; 4061 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 4062 4063 trips { 4064 gpu1_alert: trip-alert { 4065 temperature = <85000>; 4066 hysteresis = <2000>; 4067 type = "passive"; 4068 }; 4069 4070 gpu1_crit: trip-crit { 4071 temperature = <100000>; 4072 hysteresis = <2000>; 4073 type = "critical"; 4074 }; 4075 }; 4076 }; 4077 4078 vdec-thermal { 4079 polling-delay = <1000>; 4080 polling-delay-passive = <250>; 4081 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 4082 4083 trips { 4084 vdec_alert: trip-alert { 4085 temperature = <85000>; 4086 hysteresis = <2000>; 4087 type = "passive"; 4088 }; 4089 4090 vdec_crit: trip-crit { 4091 temperature = <100000>; 4092 hysteresis = <2000>; 4093 type = "critical"; 4094 }; 4095 }; 4096 }; 4097 4098 img-thermal { 4099 polling-delay = <1000>; 4100 polling-delay-passive = <250>; 4101 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 4102 4103 trips { 4104 img_alert: trip-alert { 4105 temperature = <85000>; 4106 hysteresis = <2000>; 4107 type = "passive"; 4108 }; 4109 4110 img_crit: trip-crit { 4111 temperature = <100000>; 4112 hysteresis = <2000>; 4113 type = "critical"; 4114 }; 4115 }; 4116 }; 4117 4118 infra-thermal { 4119 polling-delay = <1000>; 4120 polling-delay-passive = <250>; 4121 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 4122 4123 trips { 4124 infra_alert: trip-alert { 4125 temperature = <85000>; 4126 hysteresis = <2000>; 4127 type = "passive"; 4128 }; 4129 4130 infra_crit: trip-crit { 4131 temperature = <100000>; 4132 hysteresis = <2000>; 4133 type = "critical"; 4134 }; 4135 }; 4136 }; 4137 4138 cam0-thermal { 4139 polling-delay = <1000>; 4140 polling-delay-passive = <250>; 4141 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 4142 4143 trips { 4144 cam0_alert: trip-alert { 4145 temperature = <85000>; 4146 hysteresis = <2000>; 4147 type = "passive"; 4148 }; 4149 4150 cam0_crit: trip-crit { 4151 temperature = <100000>; 4152 hysteresis = <2000>; 4153 type = "critical"; 4154 }; 4155 }; 4156 }; 4157 4158 cam1-thermal { 4159 polling-delay = <1000>; 4160 polling-delay-passive = <250>; 4161 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 4162 4163 trips { 4164 cam1_alert: trip-alert { 4165 temperature = <85000>; 4166 hysteresis = <2000>; 4167 type = "passive"; 4168 }; 4169 4170 cam1_crit: trip-crit { 4171 temperature = <100000>; 4172 hysteresis = <2000>; 4173 type = "critical"; 4174 }; 4175 }; 4176 }; 4177 }; 4178}; 4179