1 // SPDX-License-Identifier: GPL-2.0-or-later
2 // Copyright (c) 2024 Hisilicon Limited.
3
4 #include <linux/io.h>
5 #include <linux/iopoll.h>
6 #include <linux/minmax.h>
7 #include <drm/drm_device.h>
8 #include <drm/drm_print.h>
9 #include "dp_comm.h"
10 #include "dp_reg.h"
11 #include "dp_hw.h"
12
13 #define HIBMC_AUX_CMD_REQ_LEN GENMASK(7, 4)
14 #define HIBMC_AUX_CMD_ADDR GENMASK(27, 8)
15 #define HIBMC_AUX_CMD_I2C_ADDR_ONLY BIT(28)
16 #define HIBMC_BYTES_IN_U32 4
17 #define HIBMC_AUX_I2C_WRITE_SUCCESS 0x1
18 #define HIBMC_DP_MIN_PULSE_NUM 0x9
19 #define BITS_IN_U8 8
20
hibmc_dp_aux_reset(struct hibmc_dp_dev * dp)21 static inline void hibmc_dp_aux_reset(struct hibmc_dp_dev *dp)
22 {
23 hibmc_dp_reg_write_field(dp, HIBMC_DP_DPTX_RST_CTRL, HIBMC_DP_CFG_AUX_RST_N, 0x0);
24 usleep_range(10, 15);
25 hibmc_dp_reg_write_field(dp, HIBMC_DP_DPTX_RST_CTRL, HIBMC_DP_CFG_AUX_RST_N, 0x1);
26 }
27
hibmc_dp_aux_read_data(struct hibmc_dp_dev * dp,u8 * buf,u8 size)28 static void hibmc_dp_aux_read_data(struct hibmc_dp_dev *dp, u8 *buf, u8 size)
29 {
30 u32 reg_num;
31 u32 value;
32 u32 num;
33 u8 i, j;
34
35 reg_num = DIV_ROUND_UP(size, HIBMC_BYTES_IN_U32);
36 for (i = 0; i < reg_num; i++) {
37 /* number of bytes read from a single register */
38 num = min(size - i * HIBMC_BYTES_IN_U32, HIBMC_BYTES_IN_U32);
39 value = readl(dp->base + HIBMC_DP_AUX_RD_DATA0 + i * HIBMC_BYTES_IN_U32);
40 /* convert the 32-bit value of the register to the buffer. */
41 for (j = 0; j < num; j++)
42 buf[i * HIBMC_BYTES_IN_U32 + j] = value >> (j * BITS_IN_U8);
43 }
44 }
45
hibmc_dp_aux_write_data(struct hibmc_dp_dev * dp,u8 * buf,u8 size)46 static void hibmc_dp_aux_write_data(struct hibmc_dp_dev *dp, u8 *buf, u8 size)
47 {
48 u32 reg_num;
49 u32 value;
50 u32 num;
51 u8 i, j;
52
53 reg_num = DIV_ROUND_UP(size, HIBMC_BYTES_IN_U32);
54 for (i = 0; i < reg_num; i++) {
55 /* number of bytes written to a single register */
56 num = min_t(u8, size - i * HIBMC_BYTES_IN_U32, HIBMC_BYTES_IN_U32);
57 value = 0;
58 /* obtain the 32-bit value written to a single register. */
59 for (j = 0; j < num; j++)
60 value |= buf[i * HIBMC_BYTES_IN_U32 + j] << (j * BITS_IN_U8);
61 /* writing data to a single register */
62 writel(value, dp->base + HIBMC_DP_AUX_WR_DATA0 + i * HIBMC_BYTES_IN_U32);
63 }
64 }
65
hibmc_dp_aux_build_cmd(const struct drm_dp_aux_msg * msg)66 static u32 hibmc_dp_aux_build_cmd(const struct drm_dp_aux_msg *msg)
67 {
68 u32 aux_cmd = msg->request;
69
70 if (msg->size)
71 aux_cmd |= FIELD_PREP(HIBMC_AUX_CMD_REQ_LEN, (msg->size - 1));
72 else
73 aux_cmd |= FIELD_PREP(HIBMC_AUX_CMD_I2C_ADDR_ONLY, 1);
74
75 aux_cmd |= FIELD_PREP(HIBMC_AUX_CMD_ADDR, msg->address);
76
77 return aux_cmd;
78 }
79
80 /* ret >= 0, ret is size; ret < 0, ret is err code */
hibmc_dp_aux_parse_xfer(struct hibmc_dp_dev * dp,struct drm_dp_aux_msg * msg)81 static int hibmc_dp_aux_parse_xfer(struct hibmc_dp_dev *dp, struct drm_dp_aux_msg *msg)
82 {
83 u32 buf_data_cnt;
84 u32 aux_status;
85
86 aux_status = readl(dp->base + HIBMC_DP_AUX_STATUS);
87 msg->reply = FIELD_GET(HIBMC_DP_CFG_AUX_STATUS, aux_status);
88
89 if (aux_status & HIBMC_DP_CFG_AUX_TIMEOUT)
90 return -ETIMEDOUT;
91
92 /* only address */
93 if (!msg->size)
94 return 0;
95
96 if (msg->reply != DP_AUX_NATIVE_REPLY_ACK)
97 return -EIO;
98
99 buf_data_cnt = FIELD_GET(HIBMC_DP_CFG_AUX_READY_DATA_BYTE, aux_status);
100
101 switch (msg->request) {
102 case DP_AUX_NATIVE_WRITE:
103 return msg->size;
104 case DP_AUX_I2C_WRITE | DP_AUX_I2C_MOT:
105 if (buf_data_cnt == HIBMC_AUX_I2C_WRITE_SUCCESS)
106 return msg->size;
107 else
108 return FIELD_GET(HIBMC_DP_CFG_AUX, aux_status);
109 case DP_AUX_NATIVE_READ:
110 case DP_AUX_I2C_READ | DP_AUX_I2C_MOT:
111 buf_data_cnt--;
112 if (buf_data_cnt != msg->size) {
113 /* only the successful part of data is read */
114 return -EBUSY;
115 }
116
117 /* all data is successfully read */
118 hibmc_dp_aux_read_data(dp, msg->buffer, msg->size);
119 return msg->size;
120 default:
121 return -EINVAL;
122 }
123 }
124
125 /* ret >= 0 ,ret is size; ret < 0, ret is err code */
hibmc_dp_aux_xfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)126 static ssize_t hibmc_dp_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
127 {
128 struct hibmc_dp *dp_priv = container_of(aux, struct hibmc_dp, aux);
129 struct hibmc_dp_dev *dp = dp_priv->dp_dev;
130 u32 aux_cmd;
131 int ret;
132 u32 val; /* val will be assigned at the beginning of readl_poll_timeout function */
133
134 writel(0, dp->base + HIBMC_DP_AUX_WR_DATA0);
135 writel(0, dp->base + HIBMC_DP_AUX_WR_DATA1);
136 writel(0, dp->base + HIBMC_DP_AUX_WR_DATA2);
137 writel(0, dp->base + HIBMC_DP_AUX_WR_DATA3);
138
139 hibmc_dp_aux_write_data(dp, msg->buffer, msg->size);
140
141 aux_cmd = hibmc_dp_aux_build_cmd(msg);
142 writel(aux_cmd, dp->base + HIBMC_DP_AUX_CMD_ADDR);
143
144 /* enable aux transfer */
145 hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_REQ, 0x1);
146 ret = readl_poll_timeout(dp->base + HIBMC_DP_AUX_REQ, val,
147 !(val & HIBMC_DP_CFG_AUX_REQ), 50, 5000);
148 if (ret) {
149 hibmc_dp_aux_reset(dp);
150 return ret;
151 }
152
153 return hibmc_dp_aux_parse_xfer(dp, msg);
154 }
155
hibmc_dp_aux_init(struct hibmc_dp * dp)156 void hibmc_dp_aux_init(struct hibmc_dp *dp)
157 {
158 hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_SEL, 0x0);
159 hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIMEOUT, 0x1);
160 hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE_NUM,
161 HIBMC_DP_MIN_PULSE_NUM);
162
163 dp->aux.transfer = hibmc_dp_aux_xfer;
164 dp->aux.name = "HIBMC DRM dp aux";
165 dp->aux.drm_dev = dp->drm_dev;
166 drm_dp_aux_init(&dp->aux);
167 dp->dp_dev->aux = &dp->aux;
168 }
169