1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 gpu_opp_table: opp-table-1 { 109 compatible = "operating-points-v2"; 110 111 opp-630000000 { 112 opp-hz = /bits/ 64 <630000000>; 113 opp-microvolt = <800000>; 114 }; 115 116 opp-315000000 { 117 opp-hz = /bits/ 64 <315000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-157500000 { 122 opp-hz = /bits/ 64 <157500000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-78750000 { 127 opp-hz = /bits/ 64 <78750000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-19687500 { 132 opp-hz = /bits/ 64 <19687500>; 133 opp-microvolt = <800000>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0", "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 qextal_clk: qextal-clk { 143 compatible = "fixed-clock"; 144 #clock-cells = <0>; 145 /* This value must be overridden by the board */ 146 clock-frequency = <0>; 147 }; 148 149 rtxin_clk: rtxin-clk { 150 compatible = "fixed-clock"; 151 #clock-cells = <0>; 152 /* This value must be overridden by the board */ 153 clock-frequency = <0>; 154 }; 155 156 soc: soc { 157 compatible = "simple-bus"; 158 interrupt-parent = <&gic>; 159 #address-cells = <2>; 160 #size-cells = <2>; 161 ranges; 162 163 icu: interrupt-controller@10400000 { 164 compatible = "renesas,r9a09g057-icu"; 165 reg = <0 0x10400000 0 0x10000>; 166 #interrupt-cells = <2>; 167 #address-cells = <0>; 168 interrupt-controller; 169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "nmi", 228 "port_irq0", "port_irq1", "port_irq2", 229 "port_irq3", "port_irq4", "port_irq5", 230 "port_irq6", "port_irq7", "port_irq8", 231 "port_irq9", "port_irq10", "port_irq11", 232 "port_irq12", "port_irq13", "port_irq14", 233 "port_irq15", 234 "tint0", "tint1", "tint2", "tint3", 235 "tint4", "tint5", "tint6", "tint7", 236 "tint8", "tint9", "tint10", "tint11", 237 "tint12", "tint13", "tint14", "tint15", 238 "tint16", "tint17", "tint18", "tint19", 239 "tint20", "tint21", "tint22", "tint23", 240 "tint24", "tint25", "tint26", "tint27", 241 "tint28", "tint29", "tint30", "tint31", 242 "int-ca55-0", "int-ca55-1", 243 "int-ca55-2", "int-ca55-3", 244 "icu-error-ca55", 245 "gpt-u0-gtciada", "gpt-u0-gtciadb", 246 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 247 clocks = <&cpg CPG_MOD 0x5>; 248 power-domains = <&cpg>; 249 resets = <&cpg 0x36>; 250 }; 251 252 pinctrl: pinctrl@10410000 { 253 compatible = "renesas,r9a09g057-pinctrl"; 254 reg = <0 0x10410000 0 0x10000>; 255 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 gpio-ranges = <&pinctrl 0 0 96>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 interrupt-parent = <&icu>; 262 power-domains = <&cpg>; 263 resets = <&cpg 0xa5>, <&cpg 0xa6>; 264 }; 265 266 cpg: clock-controller@10420000 { 267 compatible = "renesas,r9a09g057-cpg"; 268 reg = <0 0x10420000 0 0x10000>; 269 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 270 clock-names = "audio_extal", "rtxin", "qextal"; 271 #clock-cells = <2>; 272 #reset-cells = <1>; 273 #power-domain-cells = <0>; 274 }; 275 276 sys: system-controller@10430000 { 277 compatible = "renesas,r9a09g057-sys"; 278 reg = <0 0x10430000 0 0x10000>; 279 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 280 resets = <&cpg 0x30>; 281 }; 282 283 xspi: spi@11030000 { 284 compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; 285 reg = <0 0x11030000 0 0x10000>, 286 <0 0x20000000 0 0x10000000>; 287 reg-names = "regs", "dirmap"; 288 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 290 interrupt-names = "pulse", "err_pulse"; 291 clocks = <&cpg CPG_MOD 0x9f>, 292 <&cpg CPG_MOD 0xa0>, 293 <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>, 294 <&cpg CPG_MOD 0xa1>; 295 clock-names = "ahb", "axi", "spi", "spix2"; 296 resets = <&cpg 0xa3>, <&cpg 0xa4>; 297 reset-names = "hresetn", "aresetn"; 298 power-domains = <&cpg>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 dmac0: dma-controller@11400000 { 305 compatible = "renesas,r9a09g057-dmac"; 306 reg = <0 0x11400000 0 0x10000>; 307 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 324 interrupt-names = "error", 325 "ch0", "ch1", "ch2", "ch3", 326 "ch4", "ch5", "ch6", "ch7", 327 "ch8", "ch9", "ch10", "ch11", 328 "ch12", "ch13", "ch14", "ch15"; 329 clocks = <&cpg CPG_MOD 0x0>; 330 power-domains = <&cpg>; 331 resets = <&cpg 0x31>; 332 #dma-cells = <1>; 333 dma-channels = <16>; 334 renesas,icu = <&icu 4>; 335 }; 336 337 dmac1: dma-controller@14830000 { 338 compatible = "renesas,r9a09g057-dmac"; 339 reg = <0 0x14830000 0 0x10000>; 340 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 341 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 342 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 357 interrupt-names = "error", 358 "ch0", "ch1", "ch2", "ch3", 359 "ch4", "ch5", "ch6", "ch7", 360 "ch8", "ch9", "ch10", "ch11", 361 "ch12", "ch13", "ch14", "ch15"; 362 clocks = <&cpg CPG_MOD 0x1>; 363 power-domains = <&cpg>; 364 resets = <&cpg 0x32>; 365 #dma-cells = <1>; 366 dma-channels = <16>; 367 renesas,icu = <&icu 0>; 368 }; 369 370 dmac2: dma-controller@14840000 { 371 compatible = "renesas,r9a09g057-dmac"; 372 reg = <0 0x14840000 0 0x10000>; 373 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 374 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 375 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 380 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 390 interrupt-names = "error", 391 "ch0", "ch1", "ch2", "ch3", 392 "ch4", "ch5", "ch6", "ch7", 393 "ch8", "ch9", "ch10", "ch11", 394 "ch12", "ch13", "ch14", "ch15"; 395 clocks = <&cpg CPG_MOD 0x2>; 396 power-domains = <&cpg>; 397 resets = <&cpg 0x33>; 398 #dma-cells = <1>; 399 dma-channels = <16>; 400 renesas,icu = <&icu 1>; 401 }; 402 403 dmac3: dma-controller@12000000 { 404 compatible = "renesas,r9a09g057-dmac"; 405 reg = <0 0x12000000 0 0x10000>; 406 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 407 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 408 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 423 interrupt-names = "error", 424 "ch0", "ch1", "ch2", "ch3", 425 "ch4", "ch5", "ch6", "ch7", 426 "ch8", "ch9", "ch10", "ch11", 427 "ch12", "ch13", "ch14", "ch15"; 428 clocks = <&cpg CPG_MOD 0x3>; 429 power-domains = <&cpg>; 430 resets = <&cpg 0x34>; 431 #dma-cells = <1>; 432 dma-channels = <16>; 433 renesas,icu = <&icu 2>; 434 }; 435 436 dmac4: dma-controller@12010000 { 437 compatible = "renesas,r9a09g057-dmac"; 438 reg = <0 0x12010000 0 0x10000>; 439 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 440 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 441 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 456 interrupt-names = "error", 457 "ch0", "ch1", "ch2", "ch3", 458 "ch4", "ch5", "ch6", "ch7", 459 "ch8", "ch9", "ch10", "ch11", 460 "ch12", "ch13", "ch14", "ch15"; 461 clocks = <&cpg CPG_MOD 0x4>; 462 power-domains = <&cpg>; 463 resets = <&cpg 0x35>; 464 #dma-cells = <1>; 465 dma-channels = <16>; 466 renesas,icu = <&icu 3>; 467 }; 468 469 ostm0: timer@11800000 { 470 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 471 reg = <0x0 0x11800000 0x0 0x1000>; 472 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 473 clocks = <&cpg CPG_MOD 0x43>; 474 resets = <&cpg 0x6d>; 475 power-domains = <&cpg>; 476 status = "disabled"; 477 }; 478 479 ostm1: timer@11801000 { 480 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 481 reg = <0x0 0x11801000 0x0 0x1000>; 482 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 483 clocks = <&cpg CPG_MOD 0x44>; 484 resets = <&cpg 0x6e>; 485 power-domains = <&cpg>; 486 status = "disabled"; 487 }; 488 489 ostm2: timer@14000000 { 490 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 491 reg = <0x0 0x14000000 0x0 0x1000>; 492 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 493 clocks = <&cpg CPG_MOD 0x45>; 494 resets = <&cpg 0x6f>; 495 power-domains = <&cpg>; 496 status = "disabled"; 497 }; 498 499 ostm3: timer@14001000 { 500 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 501 reg = <0x0 0x14001000 0x0 0x1000>; 502 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 503 clocks = <&cpg CPG_MOD 0x46>; 504 resets = <&cpg 0x70>; 505 power-domains = <&cpg>; 506 status = "disabled"; 507 }; 508 509 ostm4: timer@12c00000 { 510 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 511 reg = <0x0 0x12c00000 0x0 0x1000>; 512 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 513 clocks = <&cpg CPG_MOD 0x47>; 514 resets = <&cpg 0x71>; 515 power-domains = <&cpg>; 516 status = "disabled"; 517 }; 518 519 ostm5: timer@12c01000 { 520 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 521 reg = <0x0 0x12c01000 0x0 0x1000>; 522 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 523 clocks = <&cpg CPG_MOD 0x48>; 524 resets = <&cpg 0x72>; 525 power-domains = <&cpg>; 526 status = "disabled"; 527 }; 528 529 ostm6: timer@12c02000 { 530 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 531 reg = <0x0 0x12c02000 0x0 0x1000>; 532 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 533 clocks = <&cpg CPG_MOD 0x49>; 534 resets = <&cpg 0x73>; 535 power-domains = <&cpg>; 536 status = "disabled"; 537 }; 538 539 ostm7: timer@12c03000 { 540 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 541 reg = <0x0 0x12c03000 0x0 0x1000>; 542 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 543 clocks = <&cpg CPG_MOD 0x4a>; 544 resets = <&cpg 0x74>; 545 power-domains = <&cpg>; 546 status = "disabled"; 547 }; 548 549 wdt0: watchdog@11c00400 { 550 compatible = "renesas,r9a09g057-wdt"; 551 reg = <0 0x11c00400 0 0x400>; 552 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 553 clock-names = "pclk", "oscclk"; 554 resets = <&cpg 0x75>; 555 power-domains = <&cpg>; 556 status = "disabled"; 557 }; 558 559 wdt1: watchdog@14400000 { 560 compatible = "renesas,r9a09g057-wdt"; 561 reg = <0 0x14400000 0 0x400>; 562 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 563 clock-names = "pclk", "oscclk"; 564 resets = <&cpg 0x76>; 565 power-domains = <&cpg>; 566 status = "disabled"; 567 }; 568 569 wdt2: watchdog@13000000 { 570 compatible = "renesas,r9a09g057-wdt"; 571 reg = <0 0x13000000 0 0x400>; 572 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 573 clock-names = "pclk", "oscclk"; 574 resets = <&cpg 0x77>; 575 power-domains = <&cpg>; 576 status = "disabled"; 577 }; 578 579 wdt3: watchdog@13000400 { 580 compatible = "renesas,r9a09g057-wdt"; 581 reg = <0 0x13000400 0 0x400>; 582 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 583 clock-names = "pclk", "oscclk"; 584 resets = <&cpg 0x78>; 585 power-domains = <&cpg>; 586 status = "disabled"; 587 }; 588 589 scif: serial@11c01400 { 590 compatible = "renesas,scif-r9a09g057"; 591 reg = <0 0x11c01400 0 0x400>; 592 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 600 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 601 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 602 "tei", "tei-dri", "rxi-edge", "txi-edge"; 603 clocks = <&cpg CPG_MOD 0x8f>; 604 clock-names = "fck"; 605 power-domains = <&cpg>; 606 resets = <&cpg 0x95>; 607 status = "disabled"; 608 }; 609 610 i2c0: i2c@14400400 { 611 compatible = "renesas,riic-r9a09g057"; 612 reg = <0 0x14400400 0 0x400>; 613 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 615 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 616 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "tei", "ri", "ti", "spi", "sti", 622 "naki", "ali", "tmoi"; 623 clocks = <&cpg CPG_MOD 0x94>; 624 resets = <&cpg 0x98>; 625 power-domains = <&cpg>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 i2c1: i2c@14400800 { 632 compatible = "renesas,riic-r9a09g057"; 633 reg = <0 0x14400800 0 0x400>; 634 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 636 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 637 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 642 interrupt-names = "tei", "ri", "ti", "spi", "sti", 643 "naki", "ali", "tmoi"; 644 clocks = <&cpg CPG_MOD 0x95>; 645 resets = <&cpg 0x99>; 646 power-domains = <&cpg>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 i2c2: i2c@14400c00 { 653 compatible = "renesas,riic-r9a09g057"; 654 reg = <0 0x14400c00 0 0x400>; 655 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 657 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 658 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 663 interrupt-names = "tei", "ri", "ti", "spi", "sti", 664 "naki", "ali", "tmoi"; 665 clocks = <&cpg CPG_MOD 0x96>; 666 resets = <&cpg 0x9a>; 667 power-domains = <&cpg>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 status = "disabled"; 671 }; 672 673 i2c3: i2c@14401000 { 674 compatible = "renesas,riic-r9a09g057"; 675 reg = <0 0x14401000 0 0x400>; 676 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 678 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 679 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 684 interrupt-names = "tei", "ri", "ti", "spi", "sti", 685 "naki", "ali", "tmoi"; 686 clocks = <&cpg CPG_MOD 0x97>; 687 resets = <&cpg 0x9b>; 688 power-domains = <&cpg>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 i2c4: i2c@14401400 { 695 compatible = "renesas,riic-r9a09g057"; 696 reg = <0 0x14401400 0 0x400>; 697 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 699 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 700 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-names = "tei", "ri", "ti", "spi", "sti", 706 "naki", "ali", "tmoi"; 707 clocks = <&cpg CPG_MOD 0x98>; 708 resets = <&cpg 0x9c>; 709 power-domains = <&cpg>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 i2c5: i2c@14401800 { 716 compatible = "renesas,riic-r9a09g057"; 717 reg = <0 0x14401800 0 0x400>; 718 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 720 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 721 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 726 interrupt-names = "tei", "ri", "ti", "spi", "sti", 727 "naki", "ali", "tmoi"; 728 clocks = <&cpg CPG_MOD 0x99>; 729 resets = <&cpg 0x9d>; 730 power-domains = <&cpg>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 i2c6: i2c@14401c00 { 737 compatible = "renesas,riic-r9a09g057"; 738 reg = <0 0x14401c00 0 0x400>; 739 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 741 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 742 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 747 interrupt-names = "tei", "ri", "ti", "spi", "sti", 748 "naki", "ali", "tmoi"; 749 clocks = <&cpg CPG_MOD 0x9a>; 750 resets = <&cpg 0x9e>; 751 power-domains = <&cpg>; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 757 i2c7: i2c@14402000 { 758 compatible = "renesas,riic-r9a09g057"; 759 reg = <0 0x14402000 0 0x400>; 760 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 762 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 763 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-names = "tei", "ri", "ti", "spi", "sti", 769 "naki", "ali", "tmoi"; 770 clocks = <&cpg CPG_MOD 0x9b>; 771 resets = <&cpg 0x9f>; 772 power-domains = <&cpg>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 i2c8: i2c@11c01000 { 779 compatible = "renesas,riic-r9a09g057"; 780 reg = <0 0x11c01000 0 0x400>; 781 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 783 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 784 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 789 interrupt-names = "tei", "ri", "ti", "spi", "sti", 790 "naki", "ali", "tmoi"; 791 clocks = <&cpg CPG_MOD 0x93>; 792 resets = <&cpg 0xa0>; 793 power-domains = <&cpg>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 status = "disabled"; 797 }; 798 799 gpu: gpu@14850000 { 800 compatible = "renesas,r9a09g057-mali", 801 "arm,mali-bifrost"; 802 reg = <0x0 0x14850000 0x0 0x10000>; 803 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 807 interrupt-names = "job", "mmu", "gpu", "event"; 808 clocks = <&cpg CPG_MOD 0xf0>, 809 <&cpg CPG_MOD 0xf1>, 810 <&cpg CPG_MOD 0xf2>; 811 clock-names = "gpu", "bus", "bus_ace"; 812 power-domains = <&cpg>; 813 resets = <&cpg 0xdd>, 814 <&cpg 0xde>, 815 <&cpg 0xdf>; 816 reset-names = "rst", "axi_rst", "ace_rst"; 817 operating-points-v2 = <&gpu_opp_table>; 818 status = "disabled"; 819 }; 820 821 gic: interrupt-controller@14900000 { 822 compatible = "arm,gic-v3"; 823 reg = <0x0 0x14900000 0 0x20000>, 824 <0x0 0x14940000 0 0x80000>; 825 #interrupt-cells = <3>; 826 #address-cells = <0>; 827 interrupt-controller; 828 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 829 }; 830 831 ohci0: usb@15800000 { 832 compatible = "generic-ohci"; 833 reg = <0 0x15800000 0 0x100>; 834 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 836 resets = <&usb20phyrst>, <&cpg 0xac>; 837 phys = <&usb2_phy0 1>; 838 phy-names = "usb"; 839 power-domains = <&cpg>; 840 status = "disabled"; 841 }; 842 843 ohci1: usb@15810000 { 844 compatible = "generic-ohci"; 845 reg = <0 0x15810000 0 0x100>; 846 interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 848 resets = <&usb21phyrst>, <&cpg 0xad>; 849 phys = <&usb2_phy1 1>; 850 phy-names = "usb"; 851 power-domains = <&cpg>; 852 status = "disabled"; 853 }; 854 855 ehci0: usb@15800100 { 856 compatible = "generic-ehci"; 857 reg = <0 0x15800100 0 0x100>; 858 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 860 resets = <&usb20phyrst>, <&cpg 0xac>; 861 phys = <&usb2_phy0 2>; 862 phy-names = "usb"; 863 companion = <&ohci0>; 864 power-domains = <&cpg>; 865 status = "disabled"; 866 }; 867 868 ehci1: usb@15810100 { 869 compatible = "generic-ehci"; 870 reg = <0 0x15810100 0 0x100>; 871 interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 873 resets = <&usb21phyrst>, <&cpg 0xad>; 874 phys = <&usb2_phy1 2>; 875 phy-names = "usb"; 876 companion = <&ohci1>; 877 power-domains = <&cpg>; 878 status = "disabled"; 879 }; 880 881 usb2_phy0: usb-phy@15800200 { 882 compatible = "renesas,usb2-phy-r9a09g057"; 883 reg = <0 0x15800200 0 0x700>; 884 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cpg CPG_MOD 0xb3>, 886 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>; 887 clock-names = "fck", "usb_x1"; 888 resets = <&usb20phyrst>; 889 #phy-cells = <1>; 890 power-domains = <&cpg>; 891 status = "disabled"; 892 }; 893 894 usb2_phy1: usb-phy@15810200 { 895 compatible = "renesas,usb2-phy-r9a09g057"; 896 reg = <0 0x15810200 0 0x700>; 897 interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&cpg CPG_MOD 0xb4>, 899 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>; 900 clock-names = "fck", "usb_x1"; 901 resets = <&usb21phyrst>; 902 #phy-cells = <1>; 903 power-domains = <&cpg>; 904 status = "disabled"; 905 }; 906 907 hsusb: usb@15820000 { 908 compatible = "renesas,usbhs-r9a09g057", 909 "renesas,rzg2l-usbhs"; 910 reg = <0 0x15820000 0 0x10000>; 911 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 916 resets = <&usb20phyrst>, 917 <&cpg 0xae>; 918 phys = <&usb2_phy0 3>; 919 phy-names = "usb"; 920 power-domains = <&cpg>; 921 status = "disabled"; 922 }; 923 924 usb20phyrst: usb20phy-reset@15830000 { 925 compatible = "renesas,r9a09g057-usb2phy-reset"; 926 reg = <0 0x15830000 0 0x10000>; 927 clocks = <&cpg CPG_MOD 0xb6>; 928 resets = <&cpg 0xaf>; 929 power-domains = <&cpg>; 930 #reset-cells = <0>; 931 status = "disabled"; 932 }; 933 934 usb21phyrst: usb21phy-reset@15840000 { 935 compatible = "renesas,r9a09g057-usb2phy-reset"; 936 reg = <0 0x15840000 0 0x10000>; 937 clocks = <&cpg CPG_MOD 0xb7>; 938 resets = <&cpg 0xaf>; 939 power-domains = <&cpg>; 940 #reset-cells = <0>; 941 status = "disabled"; 942 }; 943 944 sdhi0: mmc@15c00000 { 945 compatible = "renesas,sdhi-r9a09g057"; 946 reg = <0x0 0x15c00000 0 0x10000>; 947 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 950 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 951 clock-names = "core", "clkh", "cd", "aclk"; 952 resets = <&cpg 0xa7>; 953 power-domains = <&cpg>; 954 status = "disabled"; 955 956 sdhi0_vqmmc: vqmmc-regulator { 957 regulator-name = "SDHI0-VQMMC"; 958 regulator-min-microvolt = <1800000>; 959 regulator-max-microvolt = <3300000>; 960 status = "disabled"; 961 }; 962 }; 963 964 sdhi1: mmc@15c10000 { 965 compatible = "renesas,sdhi-r9a09g057"; 966 reg = <0x0 0x15c10000 0 0x10000>; 967 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 970 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 971 clock-names = "core", "clkh", "cd", "aclk"; 972 resets = <&cpg 0xa8>; 973 power-domains = <&cpg>; 974 status = "disabled"; 975 976 sdhi1_vqmmc: vqmmc-regulator { 977 regulator-name = "SDHI1-VQMMC"; 978 regulator-min-microvolt = <1800000>; 979 regulator-max-microvolt = <3300000>; 980 status = "disabled"; 981 }; 982 }; 983 984 sdhi2: mmc@15c20000 { 985 compatible = "renesas,sdhi-r9a09g057"; 986 reg = <0x0 0x15c20000 0 0x10000>; 987 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 990 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 991 clock-names = "core", "clkh", "cd", "aclk"; 992 resets = <&cpg 0xa9>; 993 power-domains = <&cpg>; 994 status = "disabled"; 995 996 sdhi2_vqmmc: vqmmc-regulator { 997 regulator-name = "SDHI2-VQMMC"; 998 regulator-min-microvolt = <1800000>; 999 regulator-max-microvolt = <3300000>; 1000 status = "disabled"; 1001 }; 1002 }; 1003 1004 eth0: ethernet@15c30000 { 1005 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1006 "snps,dwmac-5.20"; 1007 reg = <0 0x15c30000 0 0x10000>; 1008 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 1019 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1020 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1021 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1022 "tx-queue-2", "tx-queue-3"; 1023 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1024 <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1025 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1026 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1027 clock-names = "stmmaceth", "pclk", "ptp_ref", 1028 "tx", "rx", "tx-180", "rx-180"; 1029 resets = <&cpg 0xb0>; 1030 power-domains = <&cpg>; 1031 snps,multicast-filter-bins = <256>; 1032 snps,perfect-filter-entries = <128>; 1033 rx-fifo-depth = <8192>; 1034 tx-fifo-depth = <8192>; 1035 snps,fixed-burst; 1036 snps,no-pbl-x8; 1037 snps,force_thresh_dma_mode; 1038 snps,axi-config = <&stmmac_axi_setup>; 1039 snps,mtl-rx-config = <&mtl_rx_setup0>; 1040 snps,mtl-tx-config = <&mtl_tx_setup0>; 1041 snps,txpbl = <32>; 1042 snps,rxpbl = <32>; 1043 status = "disabled"; 1044 1045 mdio0: mdio { 1046 compatible = "snps,dwmac-mdio"; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 }; 1050 1051 mtl_rx_setup0: rx-queues-config { 1052 snps,rx-queues-to-use = <4>; 1053 snps,rx-sched-sp; 1054 1055 queue0 { 1056 snps,dcb-algorithm; 1057 snps,priority = <0x1>; 1058 snps,map-to-dma-channel = <0>; 1059 }; 1060 1061 queue1 { 1062 snps,dcb-algorithm; 1063 snps,priority = <0x2>; 1064 snps,map-to-dma-channel = <1>; 1065 }; 1066 1067 queue2 { 1068 snps,dcb-algorithm; 1069 snps,priority = <0x4>; 1070 snps,map-to-dma-channel = <2>; 1071 }; 1072 1073 queue3 { 1074 snps,dcb-algorithm; 1075 snps,priority = <0x8>; 1076 snps,map-to-dma-channel = <3>; 1077 }; 1078 }; 1079 1080 mtl_tx_setup0: tx-queues-config { 1081 snps,tx-queues-to-use = <4>; 1082 1083 queue0 { 1084 snps,dcb-algorithm; 1085 snps,priority = <0x1>; 1086 }; 1087 1088 queue1 { 1089 snps,dcb-algorithm; 1090 snps,priority = <0x2>; 1091 }; 1092 1093 queue2 { 1094 snps,dcb-algorithm; 1095 snps,priority = <0x4>; 1096 }; 1097 1098 queue3 { 1099 snps,dcb-algorithm; 1100 snps,priority = <0x8>; 1101 }; 1102 }; 1103 }; 1104 1105 eth1: ethernet@15c40000 { 1106 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1107 "snps,dwmac-5.20"; 1108 reg = <0 0x15c40000 0 0x10000>; 1109 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1120 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1121 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1122 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1123 "tx-queue-2", "tx-queue-3"; 1124 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1125 <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1126 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1127 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1128 clock-names = "stmmaceth", "pclk", "ptp_ref", 1129 "tx", "rx", "tx-180", "rx-180"; 1130 resets = <&cpg 0xb1>; 1131 power-domains = <&cpg>; 1132 snps,multicast-filter-bins = <256>; 1133 snps,perfect-filter-entries = <128>; 1134 rx-fifo-depth = <8192>; 1135 tx-fifo-depth = <8192>; 1136 snps,fixed-burst; 1137 snps,no-pbl-x8; 1138 snps,force_thresh_dma_mode; 1139 snps,axi-config = <&stmmac_axi_setup>; 1140 snps,mtl-rx-config = <&mtl_rx_setup1>; 1141 snps,mtl-tx-config = <&mtl_tx_setup1>; 1142 snps,txpbl = <32>; 1143 snps,rxpbl = <32>; 1144 status = "disabled"; 1145 1146 mdio1: mdio { 1147 compatible = "snps,dwmac-mdio"; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 }; 1151 1152 mtl_rx_setup1: rx-queues-config { 1153 snps,rx-queues-to-use = <4>; 1154 snps,rx-sched-sp; 1155 1156 queue0 { 1157 snps,dcb-algorithm; 1158 snps,priority = <0x1>; 1159 snps,map-to-dma-channel = <0>; 1160 }; 1161 1162 queue1 { 1163 snps,dcb-algorithm; 1164 snps,priority = <0x2>; 1165 snps,map-to-dma-channel = <1>; 1166 }; 1167 1168 queue2 { 1169 snps,dcb-algorithm; 1170 snps,priority = <0x4>; 1171 snps,map-to-dma-channel = <2>; 1172 }; 1173 1174 queue3 { 1175 snps,dcb-algorithm; 1176 snps,priority = <0x8>; 1177 snps,map-to-dma-channel = <3>; 1178 }; 1179 }; 1180 1181 mtl_tx_setup1: tx-queues-config { 1182 snps,tx-queues-to-use = <4>; 1183 1184 queue0 { 1185 snps,dcb-algorithm; 1186 snps,priority = <0x1>; 1187 }; 1188 1189 queue1 { 1190 snps,dcb-algorithm; 1191 snps,priority = <0x2>; 1192 }; 1193 1194 queue2 { 1195 snps,dcb-algorithm; 1196 snps,priority = <0x4>; 1197 }; 1198 1199 queue3 { 1200 snps,dcb-algorithm; 1201 snps,priority = <0x8>; 1202 }; 1203 }; 1204 }; 1205 }; 1206 1207 stmmac_axi_setup: stmmac-axi-config { 1208 snps,lpi_en; 1209 snps,wr_osr_lmt = <0xf>; 1210 snps,rd_osr_lmt = <0xf>; 1211 snps,blen = <16 8 4 0 0 0 0>; 1212 }; 1213 1214 timer { 1215 compatible = "arm,armv8-timer"; 1216 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1217 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1218 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1219 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1220 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1221 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1222 }; 1223}; 1224