1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/array_size.h>
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/pci.h>
18 #include <linux/pci-pwrctrl.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23 #include <linux/unaligned.h>
24
25 #include "../pci.h"
26
27 #define TC9563_GPIO_CONFIG 0x801208
28 #define TC9563_RESET_GPIO 0x801210
29
30 #define TC9563_PORT_L0S_DELAY 0x82496c
31 #define TC9563_PORT_L1_DELAY 0x824970
32
33 #define TC9563_EMBEDDED_ETH_DELAY 0x8200d8
34 #define TC9563_ETH_L1_DELAY_MASK GENMASK(27, 18)
35 #define TC9563_ETH_L1_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L1_DELAY_MASK, x)
36 #define TC9563_ETH_L0S_DELAY_MASK GENMASK(17, 13)
37 #define TC9563_ETH_L0S_DELAY_VALUE(x) FIELD_PREP(TC9563_ETH_L0S_DELAY_MASK, x)
38
39 #define TC9563_NFTS_2_5_GT 0x824978
40 #define TC9563_NFTS_5_GT 0x82497c
41
42 #define TC9563_PORT_LANE_ACCESS_ENABLE 0x828000
43
44 #define TC9563_PHY_RATE_CHANGE_OVERRIDE 0x828040
45 #define TC9563_PHY_RATE_CHANGE 0x828050
46
47 #define TC9563_TX_MARGIN 0x828234
48
49 #define TC9563_DFE_ENABLE 0x828a04
50 #define TC9563_DFE_EQ0_MODE 0x828a08
51 #define TC9563_DFE_EQ1_MODE 0x828a0c
52 #define TC9563_DFE_EQ2_MODE 0x828a14
53 #define TC9563_DFE_PD_MASK 0x828254
54
55 #define TC9563_PORT_SELECT 0x82c02c
56 #define TC9563_PORT_ACCESS_ENABLE 0x82c030
57
58 #define TC9563_POWER_CONTROL 0x82b09c
59 #define TC9563_POWER_CONTROL_OVREN 0x82b2c8
60
61 #define TC9563_GPIO_MASK 0xfffffff3
62 #define TC9563_GPIO_DEASSERT_BITS 0xc /* Clear to deassert GPIO */
63
64 #define TC9563_TX_MARGIN_MIN_UA 400000
65
66 /*
67 * From TC9563 PORSYS rev 0.2, figure 1.1 POR boot sequence
68 * wait for 10ms for the internal osc frequency to stabilize.
69 */
70 #define TC9563_OSC_STAB_DELAY_US (10 * USEC_PER_MSEC)
71
72 #define TC9563_L0S_L1_DELAY_UNIT_NS 256 /* Each unit represents 256 ns */
73
74 struct tc9563_pwrctrl_reg_setting {
75 unsigned int offset;
76 unsigned int val;
77 };
78
79 enum tc9563_pwrctrl_ports {
80 TC9563_USP,
81 TC9563_DSP1,
82 TC9563_DSP2,
83 TC9563_DSP3,
84 TC9563_ETHERNET,
85 TC9563_MAX
86 };
87
88 struct tc9563_pwrctrl_cfg {
89 u32 l0s_delay;
90 u32 l1_delay;
91 u32 tx_amp;
92 u8 nfts[2]; /* GEN1 & GEN2 */
93 bool disable_dfe;
94 bool disable_port;
95 };
96
97 #define TC9563_PWRCTL_MAX_SUPPLY 6
98
99 static const char *const tc9563_supply_names[TC9563_PWRCTL_MAX_SUPPLY] = {
100 "vddc",
101 "vdd18",
102 "vdd09",
103 "vddio1",
104 "vddio2",
105 "vddio18",
106 };
107
108 struct tc9563_pwrctrl {
109 struct pci_pwrctrl pwrctrl;
110 struct regulator_bulk_data supplies[TC9563_PWRCTL_MAX_SUPPLY];
111 struct tc9563_pwrctrl_cfg cfg[TC9563_MAX];
112 struct gpio_desc *reset_gpio;
113 struct i2c_adapter *adapter;
114 struct i2c_client *client;
115 };
116
117 /*
118 * downstream port power off sequence, hardcoding the address
119 * as we don't know register names for these register offsets.
120 */
121 static const struct tc9563_pwrctrl_reg_setting common_pwroff_seq[] = {
122 {0x82900c, 0x1},
123 {0x829010, 0x1},
124 {0x829018, 0x0},
125 {0x829020, 0x1},
126 {0x82902c, 0x1},
127 {0x829030, 0x1},
128 {0x82903c, 0x1},
129 {0x829058, 0x0},
130 {0x82905c, 0x1},
131 {0x829060, 0x1},
132 {0x8290cc, 0x1},
133 {0x8290d0, 0x1},
134 {0x8290d8, 0x1},
135 {0x8290e0, 0x1},
136 {0x8290e8, 0x1},
137 {0x8290ec, 0x1},
138 {0x8290f4, 0x1},
139 {0x82910c, 0x1},
140 {0x829110, 0x1},
141 {0x829114, 0x1},
142 };
143
144 static const struct tc9563_pwrctrl_reg_setting dsp1_pwroff_seq[] = {
145 {TC9563_PORT_ACCESS_ENABLE, 0x2},
146 {TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
147 {TC9563_POWER_CONTROL, 0x014f4804},
148 {TC9563_POWER_CONTROL_OVREN, 0x1},
149 {TC9563_PORT_ACCESS_ENABLE, 0x4},
150 };
151
152 static const struct tc9563_pwrctrl_reg_setting dsp2_pwroff_seq[] = {
153 {TC9563_PORT_ACCESS_ENABLE, 0x8},
154 {TC9563_PORT_LANE_ACCESS_ENABLE, 0x1},
155 {TC9563_POWER_CONTROL, 0x014f4804},
156 {TC9563_POWER_CONTROL_OVREN, 0x1},
157 {TC9563_PORT_ACCESS_ENABLE, 0x8},
158 };
159
160 /*
161 * Since all transfers are initiated by the probe, no locks are necessary,
162 * as there are no concurrent calls.
163 */
tc9563_pwrctrl_i2c_write(struct i2c_client * client,u32 reg_addr,u32 reg_val)164 static int tc9563_pwrctrl_i2c_write(struct i2c_client *client,
165 u32 reg_addr, u32 reg_val)
166 {
167 struct i2c_msg msg;
168 u8 msg_buf[7];
169 int ret;
170
171 msg.addr = client->addr;
172 msg.len = 7;
173 msg.flags = 0;
174
175 /* Big Endian for reg addr */
176 put_unaligned_be24(reg_addr, &msg_buf[0]);
177
178 /* Little Endian for reg val */
179 put_unaligned_le32(reg_val, &msg_buf[3]);
180
181 msg.buf = msg_buf;
182 ret = i2c_transfer(client->adapter, &msg, 1);
183 return ret == 1 ? 0 : ret;
184 }
185
tc9563_pwrctrl_i2c_read(struct i2c_client * client,u32 reg_addr,u32 * reg_val)186 static int tc9563_pwrctrl_i2c_read(struct i2c_client *client,
187 u32 reg_addr, u32 *reg_val)
188 {
189 struct i2c_msg msg[2];
190 u8 wr_data[3];
191 u32 rd_data;
192 int ret;
193
194 msg[0].addr = client->addr;
195 msg[0].len = 3;
196 msg[0].flags = 0;
197
198 /* Big Endian for reg addr */
199 put_unaligned_be24(reg_addr, &wr_data[0]);
200
201 msg[0].buf = wr_data;
202
203 msg[1].addr = client->addr;
204 msg[1].len = 4;
205 msg[1].flags = I2C_M_RD;
206
207 msg[1].buf = (u8 *)&rd_data;
208
209 ret = i2c_transfer(client->adapter, &msg[0], 2);
210 if (ret == 2) {
211 *reg_val = get_unaligned_le32(&rd_data);
212 return 0;
213 }
214
215 /* If only one message successfully completed, return -EIO */
216 return ret == 1 ? -EIO : ret;
217 }
218
tc9563_pwrctrl_i2c_bulk_write(struct i2c_client * client,const struct tc9563_pwrctrl_reg_setting * seq,int len)219 static int tc9563_pwrctrl_i2c_bulk_write(struct i2c_client *client,
220 const struct tc9563_pwrctrl_reg_setting *seq,
221 int len)
222 {
223 int ret, i;
224
225 for (i = 0; i < len; i++) {
226 ret = tc9563_pwrctrl_i2c_write(client, seq[i].offset, seq[i].val);
227 if (ret)
228 return ret;
229 }
230
231 return 0;
232 }
233
tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)234 static int tc9563_pwrctrl_disable_port(struct tc9563_pwrctrl *tc9563,
235 enum tc9563_pwrctrl_ports port)
236 {
237 struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
238 const struct tc9563_pwrctrl_reg_setting *seq;
239 int ret, len;
240
241 if (!cfg->disable_port)
242 return 0;
243
244 if (port == TC9563_DSP1) {
245 seq = dsp1_pwroff_seq;
246 len = ARRAY_SIZE(dsp1_pwroff_seq);
247 } else {
248 seq = dsp2_pwroff_seq;
249 len = ARRAY_SIZE(dsp2_pwroff_seq);
250 }
251
252 ret = tc9563_pwrctrl_i2c_bulk_write(tc9563->client, seq, len);
253 if (ret)
254 return ret;
255
256 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, common_pwroff_seq,
257 ARRAY_SIZE(common_pwroff_seq));
258 }
259
tc9563_pwrctrl_set_l0s_l1_entry_delay(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port,bool is_l1,u32 ns)260 static int tc9563_pwrctrl_set_l0s_l1_entry_delay(struct tc9563_pwrctrl *tc9563,
261 enum tc9563_pwrctrl_ports port,
262 bool is_l1, u32 ns)
263 {
264 u32 rd_val, units;
265 int ret;
266
267 if (ns < TC9563_L0S_L1_DELAY_UNIT_NS)
268 return 0;
269
270 /* convert to units of 256ns */
271 units = ns / TC9563_L0S_L1_DELAY_UNIT_NS;
272
273 if (port == TC9563_ETHERNET) {
274 ret = tc9563_pwrctrl_i2c_read(tc9563->client,
275 TC9563_EMBEDDED_ETH_DELAY,
276 &rd_val);
277 if (ret)
278 return ret;
279
280 if (is_l1)
281 rd_val = u32_replace_bits(rd_val, units,
282 TC9563_ETH_L1_DELAY_MASK);
283 else
284 rd_val = u32_replace_bits(rd_val, units,
285 TC9563_ETH_L0S_DELAY_MASK);
286
287 return tc9563_pwrctrl_i2c_write(tc9563->client,
288 TC9563_EMBEDDED_ETH_DELAY,
289 rd_val);
290 }
291
292 ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
293 BIT(port));
294 if (ret)
295 return ret;
296
297 return tc9563_pwrctrl_i2c_write(tc9563->client,
298 is_l1 ? TC9563_PORT_L1_DELAY : TC9563_PORT_L0S_DELAY,
299 units);
300 }
301
tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)302 static int tc9563_pwrctrl_set_tx_amplitude(struct tc9563_pwrctrl *tc9563,
303 enum tc9563_pwrctrl_ports port)
304 {
305 u32 amp = tc9563->cfg[port].tx_amp;
306 int port_access;
307
308 if (amp < TC9563_TX_MARGIN_MIN_UA)
309 return 0;
310
311 /* txmargin = (Amp(uV) - 400000) / 3125 */
312 amp = (amp - TC9563_TX_MARGIN_MIN_UA) / 3125;
313
314 switch (port) {
315 case TC9563_USP:
316 port_access = 0x1;
317 break;
318 case TC9563_DSP1:
319 port_access = 0x2;
320 break;
321 case TC9563_DSP2:
322 port_access = 0x8;
323 break;
324 default:
325 return -EINVAL;
326 }
327
328 struct tc9563_pwrctrl_reg_setting tx_amp_seq[] = {
329 {TC9563_PORT_ACCESS_ENABLE, port_access},
330 {TC9563_PORT_LANE_ACCESS_ENABLE, 0x3},
331 {TC9563_TX_MARGIN, amp},
332 };
333
334 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, tx_amp_seq,
335 ARRAY_SIZE(tx_amp_seq));
336 }
337
tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)338 static int tc9563_pwrctrl_disable_dfe(struct tc9563_pwrctrl *tc9563,
339 enum tc9563_pwrctrl_ports port)
340 {
341 struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
342 int port_access, lane_access = 0x3;
343 u32 phy_rate = 0x21;
344
345 if (!cfg->disable_dfe)
346 return 0;
347
348 switch (port) {
349 case TC9563_USP:
350 phy_rate = 0x1;
351 port_access = 0x1;
352 break;
353 case TC9563_DSP1:
354 port_access = 0x2;
355 break;
356 case TC9563_DSP2:
357 port_access = 0x8;
358 lane_access = 0x1;
359 break;
360 default:
361 return -EINVAL;
362 }
363
364 struct tc9563_pwrctrl_reg_setting disable_dfe_seq[] = {
365 {TC9563_PORT_ACCESS_ENABLE, port_access},
366 {TC9563_PORT_LANE_ACCESS_ENABLE, lane_access},
367 {TC9563_DFE_ENABLE, 0x0},
368 {TC9563_DFE_EQ0_MODE, 0x411},
369 {TC9563_DFE_EQ1_MODE, 0x11},
370 {TC9563_DFE_EQ2_MODE, 0x11},
371 {TC9563_DFE_PD_MASK, 0x7},
372 {TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x10},
373 {TC9563_PHY_RATE_CHANGE, phy_rate},
374 {TC9563_PHY_RATE_CHANGE, 0x0},
375 {TC9563_PHY_RATE_CHANGE_OVERRIDE, 0x0},
376 };
377
378 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, disable_dfe_seq,
379 ARRAY_SIZE(disable_dfe_seq));
380 }
381
tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl * tc9563,enum tc9563_pwrctrl_ports port)382 static int tc9563_pwrctrl_set_nfts(struct tc9563_pwrctrl *tc9563,
383 enum tc9563_pwrctrl_ports port)
384 {
385 u8 *nfts = tc9563->cfg[port].nfts;
386 struct tc9563_pwrctrl_reg_setting nfts_seq[] = {
387 {TC9563_NFTS_2_5_GT, nfts[0]},
388 {TC9563_NFTS_5_GT, nfts[1]},
389 };
390 int ret;
391
392 if (!nfts[0])
393 return 0;
394
395 ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_PORT_SELECT,
396 BIT(port));
397 if (ret)
398 return ret;
399
400 return tc9563_pwrctrl_i2c_bulk_write(tc9563->client, nfts_seq,
401 ARRAY_SIZE(nfts_seq));
402 }
403
tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl * tc9563,bool deassert)404 static int tc9563_pwrctrl_assert_deassert_reset(struct tc9563_pwrctrl *tc9563,
405 bool deassert)
406 {
407 int ret, val;
408
409 ret = tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_GPIO_CONFIG,
410 TC9563_GPIO_MASK);
411 if (ret)
412 return ret;
413
414 val = deassert ? TC9563_GPIO_DEASSERT_BITS : 0;
415
416 return tc9563_pwrctrl_i2c_write(tc9563->client, TC9563_RESET_GPIO, val);
417 }
418
tc9563_pwrctrl_parse_device_dt(struct tc9563_pwrctrl * tc9563,struct device_node * node,enum tc9563_pwrctrl_ports port)419 static int tc9563_pwrctrl_parse_device_dt(struct tc9563_pwrctrl *tc9563,
420 struct device_node *node,
421 enum tc9563_pwrctrl_ports port)
422 {
423 struct tc9563_pwrctrl_cfg *cfg = &tc9563->cfg[port];
424 int ret;
425
426 /* Disable port if the status of the port is disabled. */
427 if (!of_device_is_available(node)) {
428 cfg->disable_port = true;
429 return 0;
430 }
431
432 ret = of_property_read_u32(node, "aspm-l0s-entry-delay-ns", &cfg->l0s_delay);
433 if (ret && ret != -EINVAL)
434 return ret;
435
436 ret = of_property_read_u32(node, "aspm-l1-entry-delay-ns", &cfg->l1_delay);
437 if (ret && ret != -EINVAL)
438 return ret;
439
440 ret = of_property_read_u32(node, "toshiba,tx-amplitude-microvolt", &cfg->tx_amp);
441 if (ret && ret != -EINVAL)
442 return ret;
443
444 ret = of_property_read_u8_array(node, "n-fts", cfg->nfts, ARRAY_SIZE(cfg->nfts));
445 if (ret && ret != -EINVAL)
446 return ret;
447
448 cfg->disable_dfe = of_property_read_bool(node, "toshiba,no-dfe-support");
449
450 return 0;
451 }
452
tc9563_pwrctrl_power_off(struct pci_pwrctrl * pwrctrl)453 static int tc9563_pwrctrl_power_off(struct pci_pwrctrl *pwrctrl)
454 {
455 struct tc9563_pwrctrl *tc9563 = container_of(pwrctrl,
456 struct tc9563_pwrctrl, pwrctrl);
457
458 gpiod_set_value(tc9563->reset_gpio, 1);
459
460 regulator_bulk_disable(ARRAY_SIZE(tc9563->supplies), tc9563->supplies);
461
462 return 0;
463 }
464
tc9563_pwrctrl_power_on(struct pci_pwrctrl * pwrctrl)465 static int tc9563_pwrctrl_power_on(struct pci_pwrctrl *pwrctrl)
466 {
467 struct tc9563_pwrctrl *tc9563 = container_of(pwrctrl,
468 struct tc9563_pwrctrl, pwrctrl);
469 struct device *dev = tc9563->pwrctrl.dev;
470 struct tc9563_pwrctrl_cfg *cfg;
471 int ret, i;
472
473 ret = regulator_bulk_enable(ARRAY_SIZE(tc9563->supplies),
474 tc9563->supplies);
475 if (ret < 0)
476 return dev_err_probe(dev, ret, "cannot enable regulators\n");
477
478 gpiod_set_value(tc9563->reset_gpio, 0);
479
480 fsleep(TC9563_OSC_STAB_DELAY_US);
481
482 ret = tc9563_pwrctrl_assert_deassert_reset(tc9563, false);
483 if (ret)
484 goto power_off;
485
486 for (i = 0; i < TC9563_MAX; i++) {
487 cfg = &tc9563->cfg[i];
488 ret = tc9563_pwrctrl_disable_port(tc9563, i);
489 if (ret) {
490 dev_err(dev, "Disabling port failed\n");
491 goto power_off;
492 }
493
494 ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(tc9563, i, false, cfg->l0s_delay);
495 if (ret) {
496 dev_err(dev, "Setting L0s entry delay failed\n");
497 goto power_off;
498 }
499
500 ret = tc9563_pwrctrl_set_l0s_l1_entry_delay(tc9563, i, true, cfg->l1_delay);
501 if (ret) {
502 dev_err(dev, "Setting L1 entry delay failed\n");
503 goto power_off;
504 }
505
506 ret = tc9563_pwrctrl_set_tx_amplitude(tc9563, i);
507 if (ret) {
508 dev_err(dev, "Setting Tx amplitude failed\n");
509 goto power_off;
510 }
511
512 ret = tc9563_pwrctrl_set_nfts(tc9563, i);
513 if (ret) {
514 dev_err(dev, "Setting N_FTS failed\n");
515 goto power_off;
516 }
517
518 ret = tc9563_pwrctrl_disable_dfe(tc9563, i);
519 if (ret) {
520 dev_err(dev, "Disabling DFE failed\n");
521 goto power_off;
522 }
523 }
524
525 ret = tc9563_pwrctrl_assert_deassert_reset(tc9563, true);
526 if (!ret)
527 return 0;
528
529 power_off:
530 tc9563_pwrctrl_power_off(&tc9563->pwrctrl);
531 return ret;
532 }
533
tc9563_pwrctrl_probe(struct platform_device * pdev)534 static int tc9563_pwrctrl_probe(struct platform_device *pdev)
535 {
536 struct device_node *node = pdev->dev.of_node;
537 struct device *dev = &pdev->dev;
538 enum tc9563_pwrctrl_ports port;
539 struct tc9563_pwrctrl *tc9563;
540 struct device_node *i2c_node;
541 int ret, addr;
542
543 tc9563 = devm_kzalloc(dev, sizeof(*tc9563), GFP_KERNEL);
544 if (!tc9563)
545 return -ENOMEM;
546
547 ret = of_property_read_u32_index(node, "i2c-parent", 1, &addr);
548 if (ret)
549 return dev_err_probe(dev, ret, "Failed to read i2c-parent property\n");
550
551 i2c_node = of_parse_phandle(dev->of_node, "i2c-parent", 0);
552 tc9563->adapter = of_find_i2c_adapter_by_node(i2c_node);
553 of_node_put(i2c_node);
554 if (!tc9563->adapter)
555 return dev_err_probe(dev, -EPROBE_DEFER, "Failed to find I2C adapter\n");
556
557 tc9563->client = i2c_new_dummy_device(tc9563->adapter, addr);
558 if (IS_ERR(tc9563->client)) {
559 dev_err(dev, "Failed to create I2C client\n");
560 put_device(&tc9563->adapter->dev);
561 return PTR_ERR(tc9563->client);
562 }
563
564 for (int i = 0; i < ARRAY_SIZE(tc9563_supply_names); i++)
565 tc9563->supplies[i].supply = tc9563_supply_names[i];
566
567 ret = devm_regulator_bulk_get(dev, TC9563_PWRCTL_MAX_SUPPLY,
568 tc9563->supplies);
569 if (ret) {
570 dev_err_probe(dev, ret, "failed to get supply regulator\n");
571 goto remove_i2c;
572 }
573
574 tc9563->reset_gpio = devm_gpiod_get(dev, "resx", GPIOD_OUT_HIGH);
575 if (IS_ERR(tc9563->reset_gpio)) {
576 ret = dev_err_probe(dev, PTR_ERR(tc9563->reset_gpio), "failed to get resx GPIO\n");
577 goto remove_i2c;
578 }
579
580 pci_pwrctrl_init(&tc9563->pwrctrl, dev);
581
582 port = TC9563_USP;
583 ret = tc9563_pwrctrl_parse_device_dt(tc9563, node, port);
584 if (ret) {
585 dev_err(dev, "failed to parse device tree properties: %d\n", ret);
586 goto remove_i2c;
587 }
588
589 /*
590 * Downstream ports are always children of the upstream port.
591 * The first node represents DSP1, the second node represents DSP2,
592 * and so on.
593 */
594 for_each_child_of_node_scoped(node, child) {
595 port++;
596 ret = tc9563_pwrctrl_parse_device_dt(tc9563, child, port);
597 if (ret)
598 break;
599 /* Embedded ethernet device are under DSP3 */
600 if (port == TC9563_DSP3) {
601 for_each_child_of_node_scoped(child, child1) {
602 port++;
603 ret = tc9563_pwrctrl_parse_device_dt(tc9563,
604 child1, port);
605 if (ret)
606 break;
607 }
608 }
609 }
610 if (ret) {
611 dev_err(dev, "failed to parse device tree properties: %d\n", ret);
612 goto remove_i2c;
613 }
614
615 tc9563->pwrctrl.power_on = tc9563_pwrctrl_power_on;
616 tc9563->pwrctrl.power_off = tc9563_pwrctrl_power_off;
617
618 ret = devm_pci_pwrctrl_device_set_ready(dev, &tc9563->pwrctrl);
619 if (ret)
620 goto power_off;
621
622 return 0;
623
624 power_off:
625 tc9563_pwrctrl_power_off(&tc9563->pwrctrl);
626 remove_i2c:
627 i2c_unregister_device(tc9563->client);
628 put_device(&tc9563->adapter->dev);
629 return ret;
630 }
631
tc9563_pwrctrl_remove(struct platform_device * pdev)632 static void tc9563_pwrctrl_remove(struct platform_device *pdev)
633 {
634 struct pci_pwrctrl *pwrctrl = dev_get_drvdata(&pdev->dev);
635 struct tc9563_pwrctrl *tc9563 = container_of(pwrctrl,
636 struct tc9563_pwrctrl, pwrctrl);
637
638 tc9563_pwrctrl_power_off(&tc9563->pwrctrl);
639 i2c_unregister_device(tc9563->client);
640 put_device(&tc9563->adapter->dev);
641 }
642
643 static const struct of_device_id tc9563_pwrctrl_of_match[] = {
644 { .compatible = "pci1179,0623"},
645 { }
646 };
647 MODULE_DEVICE_TABLE(of, tc9563_pwrctrl_of_match);
648
649 static struct platform_driver tc9563_pwrctrl_driver = {
650 .driver = {
651 .name = "pwrctrl-tc9563",
652 .of_match_table = tc9563_pwrctrl_of_match,
653 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
654 },
655 .probe = tc9563_pwrctrl_probe,
656 .remove = tc9563_pwrctrl_remove,
657 };
658 module_platform_driver(tc9563_pwrctrl_driver);
659
660 MODULE_AUTHOR("Krishna chaitanya chundru <quic_krichai@quicinc.com>");
661 MODULE_DESCRIPTION("TC956x power control driver");
662 MODULE_LICENSE("GPL");
663