1 /*
2 * Nvidia AGPGART routines.
3 * Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
4 * to work in 2.5 by Dave Jones.
5 */
6
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/agp_backend.h>
11 #include <linux/page-flags.h>
12 #include <linux/mm.h>
13 #include <linux/jiffies.h>
14 #include <asm/msr.h>
15 #include "agp.h"
16
17 /* NVIDIA registers */
18 #define NVIDIA_0_APSIZE 0x80
19 #define NVIDIA_1_WBC 0xf0
20 #define NVIDIA_2_GARTCTRL 0xd0
21 #define NVIDIA_2_APBASE 0xd8
22 #define NVIDIA_2_APLIMIT 0xdc
23 #define NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
24 #define NVIDIA_3_APBASE 0x50
25 #define NVIDIA_3_APLIMIT 0x54
26
27
28 static struct _nvidia_private {
29 struct pci_dev *dev_1;
30 struct pci_dev *dev_2;
31 struct pci_dev *dev_3;
32 volatile u32 __iomem *aperture;
33 int num_active_entries;
34 off_t pg_offset;
35 u32 wbc_mask;
36 } nvidia_private;
37
38
nvidia_fetch_size(void)39 static int nvidia_fetch_size(void)
40 {
41 int i;
42 u8 size_value;
43 struct aper_size_info_8 *values;
44
45 pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);
46 size_value &= 0x0f;
47 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
48
49 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
50 if (size_value == values[i].size_value) {
51 agp_bridge->previous_size =
52 agp_bridge->current_size = (void *) (values + i);
53 agp_bridge->aperture_size_idx = i;
54 return values[i].size;
55 }
56 }
57
58 return 0;
59 }
60
61 #define SYSCFG 0xC0010010
62 #define IORR_BASE0 0xC0010016
63 #define IORR_MASK0 0xC0010017
64 #define AMD_K7_NUM_IORR 2
65
nvidia_init_iorr(u32 base,u32 size)66 static int nvidia_init_iorr(u32 base, u32 size)
67 {
68 u32 base_hi, base_lo;
69 u32 mask_hi, mask_lo;
70 u32 sys_hi, sys_lo;
71 u32 iorr_addr, free_iorr_addr;
72
73 /* Find the iorr that is already used for the base */
74 /* If not found, determine the uppermost available iorr */
75 free_iorr_addr = AMD_K7_NUM_IORR;
76 for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
77 rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
78 rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
79
80 if ((base_lo & 0xfffff000) == (base & 0xfffff000))
81 break;
82
83 if ((mask_lo & 0x00000800) == 0)
84 free_iorr_addr = iorr_addr;
85 }
86
87 if (iorr_addr >= AMD_K7_NUM_IORR) {
88 iorr_addr = free_iorr_addr;
89 if (iorr_addr >= AMD_K7_NUM_IORR)
90 return -EINVAL;
91 }
92 base_hi = 0x0;
93 base_lo = (base & ~0xfff) | 0x18;
94 mask_hi = 0xf;
95 mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
96 wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
97 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
98
99 rdmsr(SYSCFG, sys_lo, sys_hi);
100 sys_lo |= 0x00100000;
101 wrmsr(SYSCFG, sys_lo, sys_hi);
102
103 return 0;
104 }
105
nvidia_configure(void)106 static int nvidia_configure(void)
107 {
108 int i, rc, num_dirs;
109 u32 apbase, aplimit;
110 phys_addr_t apbase_phys;
111 struct aper_size_info_8 *current_size;
112 u32 temp;
113
114 current_size = A_SIZE_8(agp_bridge->current_size);
115
116 /* aperture size */
117 pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
118 current_size->size_value);
119
120 /* address to map to */
121 apbase = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
122 agp_bridge->gart_bus_addr = apbase;
123 aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
124 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
125 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
126 pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
127 pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
128 if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
129 return rc;
130
131 /* directory size is 64k */
132 num_dirs = current_size->size / 64;
133 nvidia_private.num_active_entries = current_size->num_entries;
134 nvidia_private.pg_offset = 0;
135 if (num_dirs == 0) {
136 num_dirs = 1;
137 nvidia_private.num_active_entries /= (64 / current_size->size);
138 nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
139 ~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
140 }
141
142 /* attbase */
143 for (i = 0; i < 8; i++) {
144 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
145 (agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
146 }
147
148 /* gtlb control */
149 pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
150 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);
151
152 /* gart control */
153 pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
154 pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
155
156 /* map aperture */
157 apbase_phys = pci_resource_start(agp_bridge->dev, AGP_APERTURE_BAR);
158 nvidia_private.aperture =
159 (volatile u32 __iomem *) ioremap(apbase_phys, 33 * PAGE_SIZE);
160
161 if (!nvidia_private.aperture)
162 return -ENOMEM;
163
164 return 0;
165 }
166
nvidia_cleanup(void)167 static void nvidia_cleanup(void)
168 {
169 struct aper_size_info_8 *previous_size;
170 u32 temp;
171
172 /* gart control */
173 pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
174 pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));
175
176 /* gtlb control */
177 pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
178 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
179
180 /* unmap aperture */
181 iounmap((void __iomem *) nvidia_private.aperture);
182
183 /* restore previous aperture size */
184 previous_size = A_SIZE_8(agp_bridge->previous_size);
185 pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
186 previous_size->size_value);
187
188 /* restore iorr for previous aperture size */
189 nvidia_init_iorr(agp_bridge->gart_bus_addr,
190 previous_size->size * 1024 * 1024);
191 }
192
193
194 /*
195 * Note we can't use the generic routines, even though they are 99% the same.
196 * Aperture sizes <64M still requires a full 64k GART directory, but
197 * only use the portion of the TLB entries that correspond to the apertures
198 * alignment inside the surrounding 64M block.
199 */
200 extern int agp_memory_reserved;
201
nvidia_insert_memory(struct agp_memory * mem,off_t pg_start,int type)202 static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
203 {
204 int i, j;
205 int mask_type;
206
207 mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
208 if (mask_type != 0 || type != mem->type)
209 return -EINVAL;
210
211 if (mem->page_count == 0)
212 return 0;
213
214 if ((pg_start + mem->page_count) >
215 (nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
216 return -EINVAL;
217
218 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
219 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
220 return -EBUSY;
221 }
222
223 if (!mem->is_flushed) {
224 global_cache_flush();
225 mem->is_flushed = true;
226 }
227 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
228 writel(agp_bridge->driver->mask_memory(agp_bridge,
229 page_to_phys(mem->pages[i]), mask_type),
230 agp_bridge->gatt_table+nvidia_private.pg_offset+j);
231 }
232
233 /* PCI Posting. */
234 readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j - 1);
235
236 agp_bridge->driver->tlb_flush(mem);
237 return 0;
238 }
239
240
nvidia_remove_memory(struct agp_memory * mem,off_t pg_start,int type)241 static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
242 {
243 int i;
244
245 int mask_type;
246
247 mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
248 if (mask_type != 0 || type != mem->type)
249 return -EINVAL;
250
251 if (mem->page_count == 0)
252 return 0;
253
254 for (i = pg_start; i < (mem->page_count + pg_start); i++)
255 writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i);
256
257 agp_bridge->driver->tlb_flush(mem);
258 return 0;
259 }
260
261
nvidia_tlbflush(struct agp_memory * mem)262 static void nvidia_tlbflush(struct agp_memory *mem)
263 {
264 unsigned long end;
265 u32 wbc_reg;
266 u32 __maybe_unused temp;
267 int i;
268
269 /* flush chipset */
270 if (nvidia_private.wbc_mask) {
271 pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
272 wbc_reg |= nvidia_private.wbc_mask;
273 pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
274
275 end = jiffies + 3*HZ;
276 do {
277 pci_read_config_dword(nvidia_private.dev_1,
278 NVIDIA_1_WBC, &wbc_reg);
279 if (time_before_eq(end, jiffies)) {
280 printk(KERN_ERR PFX
281 "TLB flush took more than 3 seconds.\n");
282 }
283 } while (wbc_reg & nvidia_private.wbc_mask);
284 }
285
286 /* flush TLB entries */
287 for (i = 0; i < 32 + 1; i++)
288 temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
289 for (i = 0; i < 32 + 1; i++)
290 temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
291 }
292
293
294 static const struct aper_size_info_8 nvidia_generic_sizes[5] =
295 {
296 {512, 131072, 7, 0},
297 {256, 65536, 6, 8},
298 {128, 32768, 5, 12},
299 {64, 16384, 4, 14},
300 /* The 32M mode still requires a 64k gatt */
301 {32, 16384, 4, 15}
302 };
303
304
305 static const struct gatt_mask nvidia_generic_masks[] =
306 {
307 { .mask = 1, .type = 0}
308 };
309
310
311 static const struct agp_bridge_driver nvidia_driver = {
312 .owner = THIS_MODULE,
313 .aperture_sizes = nvidia_generic_sizes,
314 .size_type = U8_APER_SIZE,
315 .num_aperture_sizes = 5,
316 .needs_scratch_page = true,
317 .configure = nvidia_configure,
318 .fetch_size = nvidia_fetch_size,
319 .cleanup = nvidia_cleanup,
320 .tlb_flush = nvidia_tlbflush,
321 .mask_memory = agp_generic_mask_memory,
322 .masks = nvidia_generic_masks,
323 .agp_enable = agp_generic_enable,
324 .cache_flush = global_cache_flush,
325 .create_gatt_table = agp_generic_create_gatt_table,
326 .free_gatt_table = agp_generic_free_gatt_table,
327 .insert_memory = nvidia_insert_memory,
328 .remove_memory = nvidia_remove_memory,
329 .alloc_by_type = agp_generic_alloc_by_type,
330 .free_by_type = agp_generic_free_by_type,
331 .agp_alloc_page = agp_generic_alloc_page,
332 .agp_alloc_pages = agp_generic_alloc_pages,
333 .agp_destroy_page = agp_generic_destroy_page,
334 .agp_destroy_pages = agp_generic_destroy_pages,
335 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
336 };
337
agp_nvidia_probe(struct pci_dev * pdev,const struct pci_device_id * ent)338 static int agp_nvidia_probe(struct pci_dev *pdev,
339 const struct pci_device_id *ent)
340 {
341 struct agp_bridge_data *bridge;
342 u8 cap_ptr;
343
344 nvidia_private.dev_1 =
345 pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
346 (unsigned int)pdev->bus->number,
347 PCI_DEVFN(0, 1));
348 nvidia_private.dev_2 =
349 pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
350 (unsigned int)pdev->bus->number,
351 PCI_DEVFN(0, 2));
352 nvidia_private.dev_3 =
353 pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
354 (unsigned int)pdev->bus->number,
355 PCI_DEVFN(30, 0));
356
357 if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
358 printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
359 "chipset, but could not find the secondary devices.\n");
360 return -ENODEV;
361 }
362
363 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
364 if (!cap_ptr)
365 return -ENODEV;
366
367 switch (pdev->device) {
368 case PCI_DEVICE_ID_NVIDIA_NFORCE:
369 printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n");
370 nvidia_private.wbc_mask = 0x00010000;
371 break;
372 case PCI_DEVICE_ID_NVIDIA_NFORCE2:
373 printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n");
374 nvidia_private.wbc_mask = 0x80000000;
375 break;
376 default:
377 printk(KERN_ERR PFX "Unsupported NVIDIA chipset (device id: %04x)\n",
378 pdev->device);
379 return -ENODEV;
380 }
381
382 bridge = agp_alloc_bridge();
383 if (!bridge)
384 return -ENOMEM;
385
386 bridge->driver = &nvidia_driver;
387 bridge->dev_private_data = &nvidia_private;
388 bridge->dev = pdev;
389 bridge->capndx = cap_ptr;
390
391 /* Fill in the mode register */
392 pci_read_config_dword(pdev,
393 bridge->capndx+PCI_AGP_STATUS,
394 &bridge->mode);
395
396 pci_set_drvdata(pdev, bridge);
397 return agp_add_bridge(bridge);
398 }
399
agp_nvidia_remove(struct pci_dev * pdev)400 static void agp_nvidia_remove(struct pci_dev *pdev)
401 {
402 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
403
404 agp_remove_bridge(bridge);
405 agp_put_bridge(bridge);
406 }
407
agp_nvidia_resume(struct device * dev)408 static int agp_nvidia_resume(struct device *dev)
409 {
410 /* reconfigure AGP hardware again */
411 nvidia_configure();
412
413 return 0;
414 }
415
416 static const struct pci_device_id agp_nvidia_pci_table[] = {
417 {
418 .class = (PCI_CLASS_BRIDGE_HOST << 8),
419 .class_mask = ~0,
420 .vendor = PCI_VENDOR_ID_NVIDIA,
421 .device = PCI_DEVICE_ID_NVIDIA_NFORCE,
422 .subvendor = PCI_ANY_ID,
423 .subdevice = PCI_ANY_ID,
424 },
425 {
426 .class = (PCI_CLASS_BRIDGE_HOST << 8),
427 .class_mask = ~0,
428 .vendor = PCI_VENDOR_ID_NVIDIA,
429 .device = PCI_DEVICE_ID_NVIDIA_NFORCE2,
430 .subvendor = PCI_ANY_ID,
431 .subdevice = PCI_ANY_ID,
432 },
433 { }
434 };
435
436 MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table);
437
438 static DEFINE_SIMPLE_DEV_PM_OPS(agp_nvidia_pm_ops, NULL, agp_nvidia_resume);
439
440 static struct pci_driver agp_nvidia_pci_driver = {
441 .name = "agpgart-nvidia",
442 .id_table = agp_nvidia_pci_table,
443 .probe = agp_nvidia_probe,
444 .remove = agp_nvidia_remove,
445 .driver.pm = &agp_nvidia_pm_ops,
446 };
447
agp_nvidia_init(void)448 static int __init agp_nvidia_init(void)
449 {
450 if (agp_off)
451 return -EINVAL;
452 return pci_register_driver(&agp_nvidia_pci_driver);
453 }
454
agp_nvidia_cleanup(void)455 static void __exit agp_nvidia_cleanup(void)
456 {
457 pci_unregister_driver(&agp_nvidia_pci_driver);
458 pci_dev_put(nvidia_private.dev_1);
459 pci_dev_put(nvidia_private.dev_2);
460 pci_dev_put(nvidia_private.dev_3);
461 }
462
463 module_init(agp_nvidia_init);
464 module_exit(agp_nvidia_cleanup);
465
466 MODULE_DESCRIPTION("Nvidia AGPGART routines");
467 MODULE_LICENSE("GPL and additional rights");
468 MODULE_AUTHOR("NVIDIA Corporation");
469
470