1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #ifndef ATH12K_QMI_H
8 #define ATH12K_QMI_H
9
10 #include <linux/mutex.h>
11 #include <linux/soc/qcom/qmi.h>
12
13 #define ATH12K_HOST_VERSION_STRING "WIN"
14 #define ATH12K_QMI_WLANFW_TIMEOUT_MS 10000
15 #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64
16 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000
17 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128
18 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45
19 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01
20 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02
21 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1
22
23 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07
24 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332 0x2
25 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32
26 #define ATH12K_QMI_RESP_LEN_MAX 8192
27 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52
28 #define ATH12K_QMI_CALDB_SIZE 0x480000
29 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20
30 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3
31 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4
32 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0
33
34 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035
35 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037
36 #define QMI_WLFW_FW_READY_IND_V01 0x0038
37
38 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144
39 #define ATH12K_FIRMWARE_MODE_OFF 4
40
41 #define ATH12K_BOARD_ID_DEFAULT 0xFF
42
43 struct ath12k_base;
44 struct ath12k_hw_group;
45
46 enum ath12k_qmi_file_type {
47 ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0,
48 ATH12K_QMI_FILE_TYPE_CALDATA = 2,
49 ATH12K_QMI_FILE_TYPE_EEPROM = 3,
50 ATH12K_QMI_MAX_FILE_TYPE = 4,
51 };
52
53 enum ath12k_qmi_bdf_type {
54 ATH12K_QMI_BDF_TYPE_BIN = 0,
55 ATH12K_QMI_BDF_TYPE_ELF = 1,
56 ATH12K_QMI_BDF_TYPE_REGDB = 4,
57 ATH12K_QMI_BDF_TYPE_CALIBRATION = 5,
58 };
59
60 enum ath12k_qmi_event_type {
61 ATH12K_QMI_EVENT_SERVER_ARRIVE,
62 ATH12K_QMI_EVENT_SERVER_EXIT,
63 ATH12K_QMI_EVENT_REQUEST_MEM,
64 ATH12K_QMI_EVENT_FW_MEM_READY,
65 ATH12K_QMI_EVENT_FW_READY,
66 ATH12K_QMI_EVENT_REGISTER_DRIVER,
67 ATH12K_QMI_EVENT_UNREGISTER_DRIVER,
68 ATH12K_QMI_EVENT_RECOVERY,
69 ATH12K_QMI_EVENT_FORCE_FW_ASSERT,
70 ATH12K_QMI_EVENT_POWER_UP,
71 ATH12K_QMI_EVENT_POWER_DOWN,
72 ATH12K_QMI_EVENT_HOST_CAP,
73 ATH12K_QMI_EVENT_MAX,
74 };
75
76 struct ath12k_qmi_driver_event {
77 struct list_head list;
78 enum ath12k_qmi_event_type type;
79 void *data;
80 };
81
82 struct ath12k_qmi_ce_cfg {
83 const struct ce_pipe_config *tgt_ce;
84 int tgt_ce_len;
85 const struct service_to_pipe *svc_to_ce_map;
86 int svc_to_ce_map_len;
87 const u8 *shadow_reg;
88 int shadow_reg_len;
89 u32 *shadow_reg_v3;
90 int shadow_reg_v3_len;
91 };
92
93 struct ath12k_qmi_event_msg {
94 struct list_head list;
95 enum ath12k_qmi_event_type type;
96 };
97
98 struct target_mem_chunk {
99 u32 size;
100 u32 type;
101 u32 prev_size;
102 u32 prev_type;
103 dma_addr_t paddr;
104 union {
105 void __iomem *ioaddr;
106 void *addr;
107 } v;
108 };
109
110 struct target_info {
111 u32 chip_id;
112 u32 chip_family;
113 u32 board_id;
114 u32 soc_id;
115 u32 fw_version;
116 u32 eeprom_caldata;
117 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
118 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
119 char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH];
120 };
121
122 struct m3_mem_region {
123 /* total memory allocated */
124 u32 total_size;
125 /* actual memory being used */
126 u32 size;
127 dma_addr_t paddr;
128 void *vaddr;
129 };
130
131 struct dev_mem_info {
132 u64 start;
133 u64 size;
134 };
135
136 struct ath12k_qmi {
137 struct ath12k_base *ab;
138 struct qmi_handle handle;
139 struct sockaddr_qrtr sq;
140 struct work_struct event_work;
141 struct workqueue_struct *event_wq;
142 struct list_head event_list;
143 spinlock_t event_lock; /* spinlock for qmi event list */
144 struct ath12k_qmi_ce_cfg ce_cfg;
145 struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
146 u32 mem_seg_count;
147 u32 target_mem_mode;
148 bool target_mem_delayed;
149 u8 cal_done;
150
151 /* protected with struct ath12k_qmi::event_lock */
152 bool block_event;
153
154 u8 num_radios;
155 struct target_info target;
156 struct m3_mem_region m3_mem;
157 struct m3_mem_region aux_uc_mem;
158 unsigned int service_ins_id;
159 struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
160 };
161
162 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261
163 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034
164 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7
165 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034
166 #define QMI_WLFW_MAX_NUM_GPIO_V01 32
167 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64
168 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3
169
170 struct qmi_wlanfw_host_ddr_range {
171 u64 start;
172 u64 size;
173 };
174
175 enum ath12k_qmi_target_mem {
176 HOST_DDR_REGION_TYPE = 0x1,
177 BDF_MEM_REGION_TYPE = 0x2,
178 M3_DUMP_REGION_TYPE = 0x3,
179 CALDB_MEM_REGION_TYPE = 0x4,
180 MLO_GLOBAL_MEM_REGION_TYPE = 0x8,
181 PAGEABLE_MEM_REGION_TYPE = 0x9,
182 LPASS_SHARED_V01_REGION_TYPE = 0xb,
183 };
184
185 enum qmi_wlanfw_host_build_type {
186 WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
187 QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0,
188 QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1,
189 QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2,
190 WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
191 };
192
193 #define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
194 #define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
195
196 struct wlfw_host_mlo_chip_info_s_v01 {
197 u8 chip_id;
198 u8 num_local_links;
199 u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
200 u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
201 };
202
203 enum ath12k_qmi_cnss_feature {
204 CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
205 CNSS_QDSS_CFG_MISS_V01 = 3,
206 CNSS_PCIE_PERST_NO_PULL_V01 = 4,
207 CNSS_AUX_UC_SUPPORT_V01 = 6,
208 CNSS_MAX_FEATURE_V01 = 64,
209 CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
210 };
211
212 struct qmi_wlanfw_host_cap_req_msg_v01 {
213 u8 num_clients_valid;
214 u32 num_clients;
215 u8 wake_msi_valid;
216 u32 wake_msi;
217 u8 gpios_valid;
218 u32 gpios_len;
219 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
220 u8 nm_modem_valid;
221 u8 nm_modem;
222 u8 bdf_support_valid;
223 u8 bdf_support;
224 u8 bdf_cache_support_valid;
225 u8 bdf_cache_support;
226 u8 m3_support_valid;
227 u8 m3_support;
228 u8 m3_cache_support_valid;
229 u8 m3_cache_support;
230 u8 cal_filesys_support_valid;
231 u8 cal_filesys_support;
232 u8 cal_cache_support_valid;
233 u8 cal_cache_support;
234 u8 cal_done_valid;
235 u8 cal_done;
236 u8 mem_bucket_valid;
237 u32 mem_bucket;
238 u8 mem_cfg_mode_valid;
239 u8 mem_cfg_mode;
240 u8 cal_duration_valid;
241 u16 cal_duraiton;
242 u8 platform_name_valid;
243 char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1];
244 u8 ddr_range_valid;
245 struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01];
246 u8 host_build_type_valid;
247 enum qmi_wlanfw_host_build_type host_build_type;
248 u8 mlo_capable_valid;
249 u8 mlo_capable;
250 u8 mlo_chip_id_valid;
251 u16 mlo_chip_id;
252 u8 mlo_group_id_valid;
253 u8 mlo_group_id;
254 u8 max_mlo_peer_valid;
255 u16 max_mlo_peer;
256 u8 mlo_num_chips_valid;
257 u8 mlo_num_chips;
258 u8 mlo_chip_info_valid;
259 struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
260 u8 feature_list_valid;
261 u64 feature_list;
262
263 };
264
265 struct qmi_wlanfw_host_cap_resp_msg_v01 {
266 struct qmi_response_type_v01 resp;
267 };
268
269 #define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0
270 #define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057
271 #define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18
272 #define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057
273
274 struct qmi_wlanfw_phy_cap_req_msg_v01 {
275 };
276
277 struct qmi_wlanfw_phy_cap_resp_msg_v01 {
278 struct qmi_response_type_v01 resp;
279 u8 num_phy_valid;
280 u8 num_phy;
281 u8 board_id_valid;
282 u32 board_id;
283 u8 single_chip_mlo_support_valid;
284 u8 single_chip_mlo_support;
285 };
286
287 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54
288 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020
289 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18
290 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020
291 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c
292
293 struct qmi_wlanfw_ind_register_req_msg_v01 {
294 u8 fw_ready_enable_valid;
295 u8 fw_ready_enable;
296 u8 initiate_cal_download_enable_valid;
297 u8 initiate_cal_download_enable;
298 u8 initiate_cal_update_enable_valid;
299 u8 initiate_cal_update_enable;
300 u8 msa_ready_enable_valid;
301 u8 msa_ready_enable;
302 u8 pin_connect_result_enable_valid;
303 u8 pin_connect_result_enable;
304 u8 client_id_valid;
305 u32 client_id;
306 u8 request_mem_enable_valid;
307 u8 request_mem_enable;
308 u8 fw_mem_ready_enable_valid;
309 u8 fw_mem_ready_enable;
310 u8 fw_init_done_enable_valid;
311 u8 fw_init_done_enable;
312 u8 rejuvenate_enable_valid;
313 u32 rejuvenate_enable;
314 u8 xo_cal_enable_valid;
315 u8 xo_cal_enable;
316 u8 cal_done_enable_valid;
317 u8 cal_done_enable;
318 };
319
320 struct qmi_wlanfw_ind_register_resp_msg_v01 {
321 struct qmi_response_type_v01 resp;
322 u8 fw_status_valid;
323 u64 fw_status;
324 };
325
326 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824
327 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888
328 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7
329 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035
330 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036
331 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036
332 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2
333 #define QMI_WLANFW_MAX_STR_LEN_V01 16
334
335 struct qmi_wlanfw_mem_cfg_s_v01 {
336 u64 offset;
337 u32 size;
338 u8 secure_flag;
339 };
340
341 enum qmi_wlanfw_mem_type_enum_v01 {
342 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
343 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
344 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
345 QMI_WLANFW_MEM_BDF_V01 = 2,
346 QMI_WLANFW_MEM_M3_V01 = 3,
347 QMI_WLANFW_MEM_CAL_V01 = 4,
348 QMI_WLANFW_MEM_DPD_V01 = 5,
349 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
350 };
351
352 struct qmi_wlanfw_mem_seg_s_v01 {
353 u32 size;
354 enum qmi_wlanfw_mem_type_enum_v01 type;
355 u32 mem_cfg_len;
356 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
357 };
358
359 struct qmi_wlanfw_request_mem_ind_msg_v01 {
360 u32 mem_seg_len;
361 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
362 };
363
364 struct qmi_wlanfw_mem_seg_resp_s_v01 {
365 u64 addr;
366 u32 size;
367 enum qmi_wlanfw_mem_type_enum_v01 type;
368 u8 restore;
369 };
370
371 struct qmi_wlanfw_respond_mem_req_msg_v01 {
372 u32 mem_seg_len;
373 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
374 };
375
376 struct qmi_wlanfw_respond_mem_resp_msg_v01 {
377 struct qmi_response_type_v01 resp;
378 };
379
380 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
381 char placeholder;
382 };
383
384 struct qmi_wlanfw_fw_ready_ind_msg_v01 {
385 char placeholder;
386 };
387
388 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0
389 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207
390 #define QMI_WLANFW_CAP_REQ_V01 0x0024
391 #define QMI_WLANFW_CAP_RESP_V01 0x0024
392
393 enum qmi_wlanfw_pipedir_enum_v01 {
394 QMI_WLFW_PIPEDIR_NONE_V01 = 0,
395 QMI_WLFW_PIPEDIR_IN_V01 = 1,
396 QMI_WLFW_PIPEDIR_OUT_V01 = 2,
397 QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
398 };
399
400 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
401 u32 pipe_num;
402 u32 pipe_dir;
403 u32 nentries;
404 u32 nbytes_max;
405 u32 flags;
406 };
407
408 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
409 u32 service_id;
410 u32 pipe_dir;
411 u32 pipe_num;
412 };
413
414 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
415 u16 id;
416 u16 offset;
417 };
418
419 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 {
420 u32 addr;
421 };
422
423 struct qmi_wlanfw_memory_region_info_s_v01 {
424 u64 region_addr;
425 u32 size;
426 u8 secure_flag;
427 };
428
429 struct qmi_wlanfw_rf_chip_info_s_v01 {
430 u32 chip_id;
431 u32 chip_family;
432 };
433
434 struct qmi_wlanfw_rf_board_info_s_v01 {
435 u32 board_id;
436 };
437
438 struct qmi_wlanfw_soc_info_s_v01 {
439 u32 soc_id;
440 };
441
442 struct qmi_wlanfw_fw_version_info_s_v01 {
443 u32 fw_version;
444 char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
445 };
446
447 struct qmi_wlanfw_dev_mem_info_s_v01 {
448 u64 start;
449 u64 size;
450 };
451
452 enum qmi_wlanfw_cal_temp_id_enum_v01 {
453 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
454 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
455 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
456 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
457 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
458 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
459 };
460
461 enum qmi_wlanfw_rd_card_chain_cap_v01 {
462 WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN,
463 WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0,
464 WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1,
465 WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2,
466 WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX,
467 };
468
469 struct qmi_wlanfw_cap_resp_msg_v01 {
470 struct qmi_response_type_v01 resp;
471 u8 chip_info_valid;
472 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
473 u8 board_info_valid;
474 struct qmi_wlanfw_rf_board_info_s_v01 board_info;
475 u8 soc_info_valid;
476 struct qmi_wlanfw_soc_info_s_v01 soc_info;
477 u8 fw_version_info_valid;
478 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
479 u8 fw_build_id_valid;
480 char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
481 u8 num_macs_valid;
482 u8 num_macs;
483 u8 voltage_mv_valid;
484 u32 voltage_mv;
485 u8 time_freq_hz_valid;
486 u32 time_freq_hz;
487 u8 otp_version_valid;
488 u32 otp_version;
489 u8 eeprom_caldata_read_timeout_valid;
490 u32 eeprom_caldata_read_timeout;
491 u8 fw_caps_valid;
492 u64 fw_caps;
493 u8 rd_card_chain_cap_valid;
494 enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap;
495 u8 dev_mem_info_valid;
496 struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
497 };
498
499 struct qmi_wlanfw_cap_req_msg_v01 {
500 char placeholder;
501 };
502
503 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182
504 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7
505 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025
506 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025
507 /* TODO: Need to check with MCL and FW team that data can be pointer and
508 * can be last element in structure
509 */
510 struct qmi_wlanfw_bdf_download_req_msg_v01 {
511 u8 valid;
512 u8 file_id_valid;
513 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
514 u8 total_size_valid;
515 u32 total_size;
516 u8 seg_id_valid;
517 u32 seg_id;
518 u8 data_valid;
519 u32 data_len;
520 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
521 u8 end_valid;
522 u8 end;
523 u8 bdf_type_valid;
524 u8 bdf_type;
525
526 };
527
528 struct qmi_wlanfw_bdf_download_resp_msg_v01 {
529 struct qmi_response_type_v01 resp;
530 };
531
532 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18
533 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7
534 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C
535 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C
536
537 struct qmi_wlanfw_m3_info_req_msg_v01 {
538 u64 addr;
539 u32 size;
540 };
541
542 struct qmi_wlanfw_m3_info_resp_msg_v01 {
543 struct qmi_response_type_v01 resp;
544 };
545
546 #define QMI_WLANFW_AUX_UC_INFO_REQ_MSG_V01_MAX_MSG_LEN 18
547 #define QMI_WLANFW_AUX_UC_INFO_RESP_MSG_V01_MAX_MSG_LEN 7
548 #define QMI_WLANFW_AUX_UC_INFO_REQ_V01 0x005A
549
550 struct qmi_wlanfw_aux_uc_info_req_msg_v01 {
551 u64 addr;
552 u32 size;
553 };
554
555 struct qmi_wlanfw_aux_uc_info_resp_msg_v01 {
556 struct qmi_response_type_v01 resp;
557 };
558
559 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11
560 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7
561 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803
562 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7
563 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022
564 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022
565 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023
566 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023
567 #define QMI_WLANFW_MAX_STR_LEN_V01 16
568 #define QMI_WLANFW_MAX_NUM_CE_V01 12
569 #define QMI_WLANFW_MAX_NUM_SVC_V01 24
570 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24
571 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01 60
572
573 struct qmi_wlanfw_wlan_mode_req_msg_v01 {
574 u32 mode;
575 u8 hw_debug_valid;
576 u8 hw_debug;
577 };
578
579 struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
580 struct qmi_response_type_v01 resp;
581 };
582
583 struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
584 u8 host_version_valid;
585 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
586 u8 tgt_cfg_valid;
587 u32 tgt_cfg_len;
588 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
589 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
590 u8 svc_cfg_valid;
591 u32 svc_cfg_len;
592 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
593 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
594 u8 shadow_reg_valid;
595 u32 shadow_reg_len;
596 struct qmi_wlanfw_shadow_reg_cfg_s_v01
597 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
598 u8 shadow_reg_v3_valid;
599 u32 shadow_reg_v3_len;
600 struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01
601 shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01];
602 };
603
604 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
605 struct qmi_response_type_v01 resp;
606 };
607
608 #define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01 0x002F
609 #define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01 0x002F
610 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN 7
611 #define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN 7
612
613 struct qmi_wlanfw_wlan_ini_req_msg_v01 {
614 /* Must be set to true if enable_fwlog is being passed */
615 u8 enable_fwlog_valid;
616 u8 enable_fwlog;
617 };
618
619 struct qmi_wlanfw_wlan_ini_resp_msg_v01 {
620 struct qmi_response_type_v01 resp;
621 };
622
623 enum ath12k_qmi_mem_mode {
624 ATH12K_QMI_MEMORY_MODE_DEFAULT = 0,
625 ATH12K_QMI_MEMORY_MODE_LOW_512_M,
626 };
627
ath12k_qmi_set_event_block(struct ath12k_qmi * qmi,bool block)628 static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block)
629 {
630 lockdep_assert_held(&qmi->event_lock);
631
632 qmi->block_event = block;
633 }
634
ath12k_qmi_get_event_block(struct ath12k_qmi * qmi)635 static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi)
636 {
637 lockdep_assert_held(&qmi->event_lock);
638
639 return qmi->block_event;
640 }
641
642 int ath12k_qmi_firmware_start(struct ath12k_base *ab,
643 u32 mode);
644 void ath12k_qmi_firmware_stop(struct ath12k_base *ab);
645 void ath12k_qmi_deinit_service(struct ath12k_base *ab);
646 int ath12k_qmi_init_service(struct ath12k_base *ab);
647 void ath12k_qmi_free_resource(struct ath12k_base *ab);
648 void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab);
649 void ath12k_qmi_reset_mlo_mem(struct ath12k_hw_group *ag);
650
651 #endif
652