1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2011 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include <dt-bindings/clock/imx6qdl-clock.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 /* 14 * The decompressor and also some bootloaders rely on a 15 * pre-existing /chosen node to be available to insert the 16 * command line and merge other ATAGS info. 17 */ 18 chosen {}; 19 20 aliases { 21 ethernet0 = &fec; 22 can0 = &can1; 23 can1 = &can2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 gpio5 = &gpio6; 30 gpio6 = &gpio7; 31 i2c0 = &i2c1; 32 i2c1 = &i2c2; 33 i2c2 = &i2c3; 34 ipu0 = &ipu1; 35 mmc0 = &usdhc1; 36 mmc1 = &usdhc2; 37 mmc2 = &usdhc3; 38 mmc3 = &usdhc4; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 spi0 = &ecspi1; 45 spi1 = &ecspi2; 46 spi2 = &ecspi3; 47 spi3 = &ecspi4; 48 usb0 = &usbotg; 49 usb1 = &usbh1; 50 usb2 = &usbh2; 51 usb3 = &usbh3; 52 usbphy0 = &usbphy1; 53 usbphy1 = &usbphy2; 54 }; 55 56 clocks { 57 ckil { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <32768>; 61 }; 62 63 ckih1 { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 69 osc { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <24000000>; 73 }; 74 }; 75 76 ldb: ldb { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 80 gpr = <&gpr>; 81 status = "disabled"; 82 83 lvds-channel@0 { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 reg = <0>; 87 status = "disabled"; 88 89 port@0 { 90 reg = <0>; 91 92 lvds0_mux_0: endpoint { 93 remote-endpoint = <&ipu1_di0_lvds0>; 94 }; 95 }; 96 97 port@1 { 98 reg = <1>; 99 100 lvds0_mux_1: endpoint { 101 remote-endpoint = <&ipu1_di1_lvds0>; 102 }; 103 }; 104 }; 105 106 lvds-channel@1 { 107 #address-cells = <1>; 108 #size-cells = <0>; 109 reg = <1>; 110 status = "disabled"; 111 112 port@0 { 113 reg = <0>; 114 115 lvds1_mux_0: endpoint { 116 remote-endpoint = <&ipu1_di0_lvds1>; 117 }; 118 }; 119 120 port@1 { 121 reg = <1>; 122 123 lvds1_mux_1: endpoint { 124 remote-endpoint = <&ipu1_di1_lvds1>; 125 }; 126 }; 127 }; 128 }; 129 130 pmu: pmu { 131 compatible = "arm,cortex-a9-pmu"; 132 interrupt-parent = <&gpc>; 133 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 134 }; 135 136 usbphynop1: usbphynop1 { 137 compatible = "usb-nop-xceiv"; 138 #phy-cells = <0>; 139 }; 140 141 usbphynop2: usbphynop2 { 142 compatible = "usb-nop-xceiv"; 143 #phy-cells = <0>; 144 }; 145 146 soc: soc { 147 #address-cells = <1>; 148 #size-cells = <1>; 149 compatible = "simple-bus"; 150 interrupt-parent = <&gpc>; 151 ranges; 152 153 dma_apbh: dma-controller@110000 { 154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 155 reg = <0x00110000 0x2000>; 156 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 157 <0 13 IRQ_TYPE_LEVEL_HIGH>, 158 <0 13 IRQ_TYPE_LEVEL_HIGH>, 159 <0 13 IRQ_TYPE_LEVEL_HIGH>; 160 #dma-cells = <1>; 161 dma-channels = <4>; 162 clocks = <&clks IMX6QDL_CLK_APBH_DMA>; 163 }; 164 165 gpmi: nand-controller@112000 { 166 compatible = "fsl,imx6q-gpmi-nand"; 167 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 168 reg-names = "gpmi-nand", "bch"; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-names = "bch"; 173 clocks = <&clks IMX6QDL_CLK_GPMI_IO>, 174 <&clks IMX6QDL_CLK_GPMI_APB>, 175 <&clks IMX6QDL_CLK_GPMI_BCH>, 176 <&clks IMX6QDL_CLK_GPMI_BCH_APB>, 177 <&clks IMX6QDL_CLK_PER1_BCH>; 178 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 179 "gpmi_bch_apb", "per1_bch"; 180 dmas = <&dma_apbh 0>; 181 dma-names = "rx-tx"; 182 status = "disabled"; 183 }; 184 185 hdmi: hdmi@120000 { 186 reg = <0x00120000 0x9000>; 187 interrupts = <0 115 0x04>; 188 gpr = <&gpr>; 189 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, 190 <&clks IMX6QDL_CLK_HDMI_ISFR>; 191 clock-names = "iahb", "isfr"; 192 status = "disabled"; 193 194 ports { 195 #address-cells = <1>; 196 #size-cells = <0>; 197 198 port@0 { 199 reg = <0>; 200 201 hdmi_mux_0: endpoint { 202 remote-endpoint = <&ipu1_di0_hdmi>; 203 }; 204 }; 205 206 port@1 { 207 reg = <1>; 208 209 hdmi_mux_1: endpoint { 210 remote-endpoint = <&ipu1_di1_hdmi>; 211 }; 212 }; 213 }; 214 }; 215 216 gpu_3d: gpu@130000 { 217 compatible = "vivante,gc"; 218 reg = <0x00130000 0x4000>; 219 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, 221 <&clks IMX6QDL_CLK_GPU3D_CORE>, 222 <&clks IMX6QDL_CLK_GPU3D_SHADER>; 223 clock-names = "bus", "core", "shader"; 224 power-domains = <&pd_pu>; 225 #cooling-cells = <2>; 226 }; 227 228 gpu_2d: gpu@134000 { 229 compatible = "vivante,gc"; 230 reg = <0x00134000 0x4000>; 231 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, 233 <&clks IMX6QDL_CLK_GPU2D_CORE>; 234 clock-names = "bus", "core"; 235 power-domains = <&pd_pu>; 236 #cooling-cells = <2>; 237 }; 238 239 timer@a00600 { 240 compatible = "arm,cortex-a9-twd-timer"; 241 reg = <0x00a00600 0x20>; 242 interrupts = <1 13 0xf01>; 243 interrupt-parent = <&intc>; 244 clocks = <&clks IMX6QDL_CLK_TWD>; 245 }; 246 247 intc: interrupt-controller@a01000 { 248 compatible = "arm,cortex-a9-gic"; 249 #interrupt-cells = <3>; 250 interrupt-controller; 251 reg = <0x00a01000 0x1000>, 252 <0x00a00100 0x100>; 253 interrupt-parent = <&intc>; 254 }; 255 256 L2: cache-controller@a02000 { 257 compatible = "arm,pl310-cache"; 258 reg = <0x00a02000 0x1000>; 259 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 260 cache-unified; 261 cache-level = <2>; 262 arm,tag-latency = <4 2 3>; 263 arm,data-latency = <4 2 3>; 264 arm,shared-override; 265 }; 266 267 pcie: pcie@1ffc000 { 268 compatible = "fsl,imx6q-pcie"; 269 reg = <0x01ffc000 0x04000>, 270 <0x01f00000 0x80000>; 271 reg-names = "dbi", "config"; 272 #address-cells = <3>; 273 #size-cells = <2>; 274 device_type = "pci"; 275 bus-range = <0x00 0xff>; 276 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */ 277 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 278 num-lanes = <1>; 279 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 280 interrupt-names = "msi"; 281 #interrupt-cells = <1>; 282 interrupt-map-mask = <0 0 0 0x7>; 283 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 284 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 285 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 286 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 288 <&clks IMX6QDL_CLK_LVDS1_GATE>, 289 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 290 clock-names = "pcie", "pcie_bus", "pcie_phy"; 291 status = "disabled"; 292 }; 293 294 aips1: bus@2000000 { /* AIPS1 */ 295 compatible = "fsl,aips-bus", "simple-bus"; 296 #address-cells = <1>; 297 #size-cells = <1>; 298 reg = <0x02000000 0x100000>; 299 ranges; 300 301 spba-bus@2000000 { 302 compatible = "fsl,spba-bus", "simple-bus"; 303 #address-cells = <1>; 304 #size-cells = <1>; 305 reg = <0x02000000 0x40000>; 306 ranges; 307 308 spdif: spdif@2004000 { 309 compatible = "fsl,imx35-spdif"; 310 reg = <0x02004000 0x4000>; 311 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 312 dmas = <&sdma 14 18 0>, 313 <&sdma 15 18 0>; 314 dma-names = "rx", "tx"; 315 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, 316 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, 317 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, 318 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, 319 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; 320 clock-names = "core", "rxtx0", 321 "rxtx1", "rxtx2", 322 "rxtx3", "rxtx4", 323 "rxtx5", "rxtx6", 324 "rxtx7", "spba"; 325 status = "disabled"; 326 }; 327 328 ecspi1: spi@2008000 { 329 #address-cells = <1>; 330 #size-cells = <0>; 331 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 332 reg = <0x02008000 0x4000>; 333 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&clks IMX6QDL_CLK_ECSPI1>, 335 <&clks IMX6QDL_CLK_ECSPI1>; 336 clock-names = "ipg", "per"; 337 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 338 dma-names = "rx", "tx"; 339 status = "disabled"; 340 }; 341 342 ecspi2: spi@200c000 { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 346 reg = <0x0200c000 0x4000>; 347 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clks IMX6QDL_CLK_ECSPI2>, 349 <&clks IMX6QDL_CLK_ECSPI2>; 350 clock-names = "ipg", "per"; 351 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 352 dma-names = "rx", "tx"; 353 status = "disabled"; 354 }; 355 356 ecspi3: spi@2010000 { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 360 reg = <0x02010000 0x4000>; 361 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clks IMX6QDL_CLK_ECSPI3>, 363 <&clks IMX6QDL_CLK_ECSPI3>; 364 clock-names = "ipg", "per"; 365 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 366 dma-names = "rx", "tx"; 367 status = "disabled"; 368 }; 369 370 ecspi4: spi@2014000 { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 374 reg = <0x02014000 0x4000>; 375 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clks IMX6QDL_CLK_ECSPI4>, 377 <&clks IMX6QDL_CLK_ECSPI4>; 378 clock-names = "ipg", "per"; 379 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 380 dma-names = "rx", "tx"; 381 status = "disabled"; 382 }; 383 384 uart1: serial@2020000 { 385 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 386 reg = <0x02020000 0x4000>; 387 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 389 <&clks IMX6QDL_CLK_UART_SERIAL>; 390 clock-names = "ipg", "per"; 391 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 392 dma-names = "rx", "tx"; 393 status = "disabled"; 394 }; 395 396 esai: esai@2024000 { 397 #sound-dai-cells = <0>; 398 compatible = "fsl,imx35-esai"; 399 reg = <0x02024000 0x4000>; 400 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, 402 <&clks IMX6QDL_CLK_ESAI_EXTAL>, 403 <&clks IMX6QDL_CLK_ESAI_IPG>, 404 <&clks IMX6QDL_CLK_SPBA>; 405 clock-names = "core", "extal", "fsys", "spba"; 406 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 ssi1: ssi@2028000 { 412 #sound-dai-cells = <0>; 413 compatible = "fsl,imx6q-ssi", 414 "fsl,imx51-ssi"; 415 reg = <0x02028000 0x4000>; 416 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, 418 <&clks IMX6QDL_CLK_SSI1>; 419 clock-names = "ipg", "baud"; 420 dmas = <&sdma 37 1 0>, 421 <&sdma 38 1 0>; 422 dma-names = "rx", "tx"; 423 fsl,fifo-depth = <15>; 424 status = "disabled"; 425 }; 426 427 ssi2: ssi@202c000 { 428 #sound-dai-cells = <0>; 429 compatible = "fsl,imx6q-ssi", 430 "fsl,imx51-ssi"; 431 reg = <0x0202c000 0x4000>; 432 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, 434 <&clks IMX6QDL_CLK_SSI2>; 435 clock-names = "ipg", "baud"; 436 dmas = <&sdma 41 1 0>, 437 <&sdma 42 1 0>; 438 dma-names = "rx", "tx"; 439 fsl,fifo-depth = <15>; 440 status = "disabled"; 441 }; 442 443 ssi3: ssi@2030000 { 444 #sound-dai-cells = <0>; 445 compatible = "fsl,imx6q-ssi", 446 "fsl,imx51-ssi"; 447 reg = <0x02030000 0x4000>; 448 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, 450 <&clks IMX6QDL_CLK_SSI3>; 451 clock-names = "ipg", "baud"; 452 dmas = <&sdma 45 1 0>, 453 <&sdma 46 1 0>; 454 dma-names = "rx", "tx"; 455 fsl,fifo-depth = <15>; 456 status = "disabled"; 457 }; 458 459 asrc: asrc@2034000 { 460 compatible = "fsl,imx53-asrc"; 461 reg = <0x02034000 0x4000>; 462 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, 464 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, 465 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 466 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 467 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 468 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, 469 <&clks IMX6QDL_CLK_SPBA>; 470 clock-names = "mem", "ipg", "asrck_0", 471 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 472 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 473 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 474 "asrck_d", "asrck_e", "asrck_f", "spba"; 475 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 476 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 477 dma-names = "rxa", "rxb", "rxc", 478 "txa", "txb", "txc"; 479 fsl,asrc-rate = <48000>; 480 fsl,asrc-width = <16>; 481 status = "okay"; 482 }; 483 484 spba-bus@203c000 { 485 reg = <0x0203c000 0x4000>; 486 }; 487 }; 488 489 vpu: vpu@2040000 { 490 compatible = "cnm,coda960"; 491 reg = <0x02040000 0x3c000>; 492 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, 493 <0 3 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-names = "bit", "jpeg"; 495 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 496 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; 497 clock-names = "per", "ahb"; 498 power-domains = <&pd_pu>; 499 resets = <&src 1>; 500 iram = <&ocram>; 501 }; 502 503 aipstz@207c000 { /* AIPSTZ1 */ 504 reg = <0x0207c000 0x4000>; 505 }; 506 507 pwm1: pwm@2080000 { 508 #pwm-cells = <3>; 509 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 510 reg = <0x02080000 0x4000>; 511 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clks IMX6QDL_CLK_IPG>, 513 <&clks IMX6QDL_CLK_PWM1>; 514 clock-names = "ipg", "per"; 515 status = "disabled"; 516 }; 517 518 pwm2: pwm@2084000 { 519 #pwm-cells = <3>; 520 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 521 reg = <0x02084000 0x4000>; 522 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&clks IMX6QDL_CLK_IPG>, 524 <&clks IMX6QDL_CLK_PWM2>; 525 clock-names = "ipg", "per"; 526 status = "disabled"; 527 }; 528 529 pwm3: pwm@2088000 { 530 #pwm-cells = <3>; 531 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 532 reg = <0x02088000 0x4000>; 533 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clks IMX6QDL_CLK_IPG>, 535 <&clks IMX6QDL_CLK_PWM3>; 536 clock-names = "ipg", "per"; 537 status = "disabled"; 538 }; 539 540 pwm4: pwm@208c000 { 541 #pwm-cells = <3>; 542 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 543 reg = <0x0208c000 0x4000>; 544 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clks IMX6QDL_CLK_IPG>, 546 <&clks IMX6QDL_CLK_PWM4>; 547 clock-names = "ipg", "per"; 548 status = "disabled"; 549 }; 550 551 can1: can@2090000 { 552 compatible = "fsl,imx6q-flexcan"; 553 reg = <0x02090000 0x4000>; 554 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, 556 <&clks IMX6QDL_CLK_CAN1_SERIAL>; 557 clock-names = "ipg", "per"; 558 fsl,stop-mode = <&gpr 0x34 28>; 559 status = "disabled"; 560 }; 561 562 can2: can@2094000 { 563 compatible = "fsl,imx6q-flexcan"; 564 reg = <0x02094000 0x4000>; 565 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, 567 <&clks IMX6QDL_CLK_CAN2_SERIAL>; 568 clock-names = "ipg", "per"; 569 fsl,stop-mode = <&gpr 0x34 29>; 570 status = "disabled"; 571 }; 572 573 gpt: timer@2098000 { 574 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 575 reg = <0x02098000 0x4000>; 576 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 578 <&clks IMX6QDL_CLK_GPT_IPG_PER>, 579 <&clks IMX6QDL_CLK_GPT_3M>; 580 clock-names = "ipg", "per", "osc_per"; 581 }; 582 583 gpio1: gpio@209c000 { 584 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 585 reg = <0x0209c000 0x4000>; 586 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 587 <0 67 IRQ_TYPE_LEVEL_HIGH>; 588 gpio-controller; 589 #gpio-cells = <2>; 590 interrupt-controller; 591 #interrupt-cells = <2>; 592 }; 593 594 gpio2: gpio@20a0000 { 595 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 596 reg = <0x020a0000 0x4000>; 597 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 598 <0 69 IRQ_TYPE_LEVEL_HIGH>; 599 gpio-controller; 600 #gpio-cells = <2>; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 }; 604 605 gpio3: gpio@20a4000 { 606 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 607 reg = <0x020a4000 0x4000>; 608 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 609 <0 71 IRQ_TYPE_LEVEL_HIGH>; 610 gpio-controller; 611 #gpio-cells = <2>; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 }; 615 616 gpio4: gpio@20a8000 { 617 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 618 reg = <0x020a8000 0x4000>; 619 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 620 <0 73 IRQ_TYPE_LEVEL_HIGH>; 621 gpio-controller; 622 #gpio-cells = <2>; 623 interrupt-controller; 624 #interrupt-cells = <2>; 625 }; 626 627 gpio5: gpio@20ac000 { 628 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 629 reg = <0x020ac000 0x4000>; 630 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 631 <0 75 IRQ_TYPE_LEVEL_HIGH>; 632 gpio-controller; 633 #gpio-cells = <2>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 }; 637 638 gpio6: gpio@20b0000 { 639 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 640 reg = <0x020b0000 0x4000>; 641 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, 642 <0 77 IRQ_TYPE_LEVEL_HIGH>; 643 gpio-controller; 644 #gpio-cells = <2>; 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 }; 648 649 gpio7: gpio@20b4000 { 650 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 651 reg = <0x020b4000 0x4000>; 652 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, 653 <0 79 IRQ_TYPE_LEVEL_HIGH>; 654 gpio-controller; 655 #gpio-cells = <2>; 656 interrupt-controller; 657 #interrupt-cells = <2>; 658 }; 659 660 kpp: keypad@20b8000 { 661 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; 662 reg = <0x020b8000 0x4000>; 663 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&clks IMX6QDL_CLK_IPG>; 665 status = "disabled"; 666 }; 667 668 wdog1: watchdog@20bc000 { 669 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 670 reg = <0x020bc000 0x4000>; 671 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clks IMX6QDL_CLK_IPG>; 673 }; 674 675 wdog2: watchdog@20c0000 { 676 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 677 reg = <0x020c0000 0x4000>; 678 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&clks IMX6QDL_CLK_IPG>; 680 status = "disabled"; 681 }; 682 683 clks: clock-controller@20c4000 { 684 compatible = "fsl,imx6q-ccm"; 685 reg = <0x020c4000 0x4000>; 686 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 687 <0 88 IRQ_TYPE_LEVEL_HIGH>; 688 #clock-cells = <1>; 689 }; 690 691 anatop: anatop@20c8000 { 692 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; 693 reg = <0x020c8000 0x1000>; 694 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 695 <0 54 IRQ_TYPE_LEVEL_HIGH>, 696 <0 127 IRQ_TYPE_LEVEL_HIGH>; 697 698 reg_vdd1p1: regulator-1p1 { 699 compatible = "fsl,anatop-regulator"; 700 regulator-name = "vdd1p1"; 701 regulator-min-microvolt = <1000000>; 702 regulator-max-microvolt = <1200000>; 703 regulator-always-on; 704 anatop-reg-offset = <0x110>; 705 anatop-vol-bit-shift = <8>; 706 anatop-vol-bit-width = <5>; 707 anatop-min-bit-val = <4>; 708 anatop-min-voltage = <800000>; 709 anatop-max-voltage = <1375000>; 710 anatop-enable-bit = <0>; 711 }; 712 713 reg_vdd3p0: regulator-3p0 { 714 compatible = "fsl,anatop-regulator"; 715 regulator-name = "vdd3p0"; 716 regulator-min-microvolt = <2625000>; 717 regulator-max-microvolt = <3400000>; 718 regulator-always-on; 719 anatop-reg-offset = <0x120>; 720 anatop-vol-bit-shift = <8>; 721 anatop-vol-bit-width = <5>; 722 anatop-min-bit-val = <0>; 723 anatop-min-voltage = <2625000>; 724 anatop-max-voltage = <3400000>; 725 anatop-enable-bit = <0>; 726 }; 727 728 reg_vdd2p5: regulator-2p5 { 729 compatible = "fsl,anatop-regulator"; 730 regulator-name = "vdd2p5"; 731 regulator-min-microvolt = <2250000>; 732 regulator-max-microvolt = <2750000>; 733 regulator-always-on; 734 anatop-reg-offset = <0x130>; 735 anatop-vol-bit-shift = <8>; 736 anatop-vol-bit-width = <5>; 737 anatop-min-bit-val = <0>; 738 anatop-min-voltage = <2100000>; 739 anatop-max-voltage = <2875000>; 740 anatop-enable-bit = <0>; 741 }; 742 743 reg_arm: regulator-vddcore { 744 compatible = "fsl,anatop-regulator"; 745 regulator-name = "vddarm"; 746 regulator-min-microvolt = <725000>; 747 regulator-max-microvolt = <1450000>; 748 regulator-always-on; 749 anatop-reg-offset = <0x140>; 750 anatop-vol-bit-shift = <0>; 751 anatop-vol-bit-width = <5>; 752 anatop-delay-reg-offset = <0x170>; 753 anatop-delay-bit-shift = <24>; 754 anatop-delay-bit-width = <2>; 755 anatop-min-bit-val = <1>; 756 anatop-min-voltage = <725000>; 757 anatop-max-voltage = <1450000>; 758 }; 759 760 reg_pu: regulator-vddpu { 761 compatible = "fsl,anatop-regulator"; 762 regulator-name = "vddpu"; 763 regulator-min-microvolt = <725000>; 764 regulator-max-microvolt = <1450000>; 765 regulator-enable-ramp-delay = <380>; 766 anatop-reg-offset = <0x140>; 767 anatop-vol-bit-shift = <9>; 768 anatop-vol-bit-width = <5>; 769 anatop-delay-reg-offset = <0x170>; 770 anatop-delay-bit-shift = <26>; 771 anatop-delay-bit-width = <2>; 772 anatop-min-bit-val = <1>; 773 anatop-min-voltage = <725000>; 774 anatop-max-voltage = <1450000>; 775 }; 776 777 reg_soc: regulator-vddsoc { 778 compatible = "fsl,anatop-regulator"; 779 regulator-name = "vddsoc"; 780 regulator-min-microvolt = <725000>; 781 regulator-max-microvolt = <1450000>; 782 regulator-always-on; 783 anatop-reg-offset = <0x140>; 784 anatop-vol-bit-shift = <18>; 785 anatop-vol-bit-width = <5>; 786 anatop-delay-reg-offset = <0x170>; 787 anatop-delay-bit-shift = <28>; 788 anatop-delay-bit-width = <2>; 789 anatop-min-bit-val = <1>; 790 anatop-min-voltage = <725000>; 791 anatop-max-voltage = <1450000>; 792 }; 793 794 tempmon: tempmon { 795 compatible = "fsl,imx6q-tempmon"; 796 interrupt-parent = <&gpc>; 797 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 798 fsl,tempmon = <&anatop>; 799 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 800 nvmem-cell-names = "calib", "temp_grade"; 801 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 802 #thermal-sensor-cells = <0>; 803 }; 804 }; 805 806 usbphy1: usbphy@20c9000 { 807 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 808 reg = <0x020c9000 0x1000>; 809 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&clks IMX6QDL_CLK_USBPHY1>; 811 phy-3p0-supply = <®_vdd3p0>; 812 fsl,anatop = <&anatop>; 813 }; 814 815 usbphy2: usbphy@20ca000 { 816 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 817 reg = <0x020ca000 0x1000>; 818 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&clks IMX6QDL_CLK_USBPHY2>; 820 phy-3p0-supply = <®_vdd3p0>; 821 fsl,anatop = <&anatop>; 822 }; 823 824 snvs: snvs@20cc000 { 825 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 826 reg = <0x020cc000 0x4000>; 827 828 snvs_rtc: snvs-rtc-lp { 829 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 830 regmap = <&snvs>; 831 offset = <0x34>; 832 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 833 <0 20 IRQ_TYPE_LEVEL_HIGH>; 834 }; 835 836 snvs_poweroff: snvs-poweroff { 837 compatible = "syscon-poweroff"; 838 regmap = <&snvs>; 839 offset = <0x38>; 840 value = <0x60>; 841 mask = <0x60>; 842 status = "disabled"; 843 }; 844 845 snvs_pwrkey: snvs-powerkey { 846 compatible = "fsl,sec-v4.0-pwrkey"; 847 regmap = <&snvs>; 848 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 849 linux,keycode = <KEY_POWER>; 850 wakeup-source; 851 status = "disabled"; 852 }; 853 854 snvs_lpgpr: snvs-lpgpr { 855 compatible = "fsl,imx6q-snvs-lpgpr"; 856 }; 857 }; 858 859 epit1: epit@20d0000 { /* EPIT1 */ 860 reg = <0x020d0000 0x4000>; 861 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 862 }; 863 864 epit2: epit@20d4000 { /* EPIT2 */ 865 reg = <0x020d4000 0x4000>; 866 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 867 }; 868 869 src: reset-controller@20d8000 { 870 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 871 reg = <0x020d8000 0x4000>; 872 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 873 <0 96 IRQ_TYPE_LEVEL_HIGH>; 874 #reset-cells = <1>; 875 }; 876 877 gpc: gpc@20dc000 { 878 compatible = "fsl,imx6q-gpc"; 879 reg = <0x020dc000 0x4000>; 880 #address-cells = <0>; 881 interrupt-controller; 882 #interrupt-cells = <3>; 883 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 884 interrupt-parent = <&intc>; 885 clocks = <&clks IMX6QDL_CLK_IPG>; 886 clock-names = "ipg"; 887 888 pgc { 889 #address-cells = <1>; 890 #size-cells = <0>; 891 892 power-domain@0 { 893 reg = <0>; 894 #power-domain-cells = <0>; 895 }; 896 pd_pu: power-domain@1 { 897 reg = <1>; 898 #power-domain-cells = <0>; 899 power-supply = <®_pu>; 900 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 901 <&clks IMX6QDL_CLK_GPU3D_SHADER>, 902 <&clks IMX6QDL_CLK_GPU2D_CORE>, 903 <&clks IMX6QDL_CLK_GPU2D_AXI>, 904 <&clks IMX6QDL_CLK_OPENVG_AXI>, 905 <&clks IMX6QDL_CLK_VPU_AXI>; 906 }; 907 }; 908 }; 909 910 gpr: iomuxc-gpr@20e0000 { 911 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; 912 reg = <0x20e0000 0x38>; 913 914 mux: mux-controller { 915 compatible = "mmio-mux"; 916 #mux-control-cells = <1>; 917 }; 918 }; 919 920 iomuxc: pinctrl@20e0000 { 921 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 922 reg = <0x20e0000 0x4000>; 923 }; 924 925 dcic1: dcic@20e4000 { 926 reg = <0x020e4000 0x4000>; 927 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 928 }; 929 930 dcic2: dcic@20e8000 { 931 reg = <0x020e8000 0x4000>; 932 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 933 }; 934 935 sdma: dma-controller@20ec000 { 936 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 937 reg = <0x020ec000 0x4000>; 938 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&clks IMX6QDL_CLK_IPG>, 940 <&clks IMX6QDL_CLK_SDMA>; 941 clock-names = "ipg", "ahb"; 942 #dma-cells = <3>; 943 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 944 }; 945 }; 946 947 aips2: bus@2100000 { /* AIPS2 */ 948 compatible = "fsl,aips-bus", "simple-bus"; 949 #address-cells = <1>; 950 #size-cells = <1>; 951 reg = <0x02100000 0x100000>; 952 ranges; 953 954 crypto: crypto@2100000 { 955 compatible = "fsl,sec-v4.0"; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 reg = <0x2100000 0x10000>; 959 ranges = <0 0x2100000 0x10000>; 960 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, 961 <&clks IMX6QDL_CLK_CAAM_ACLK>, 962 <&clks IMX6QDL_CLK_CAAM_IPG>, 963 <&clks IMX6QDL_CLK_EIM_SLOW>; 964 clock-names = "mem", "aclk", "ipg", "emi_slow"; 965 966 sec_jr0: jr@1000 { 967 compatible = "fsl,sec-v4.0-job-ring"; 968 reg = <0x1000 0x1000>; 969 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 970 }; 971 972 sec_jr1: jr@2000 { 973 compatible = "fsl,sec-v4.0-job-ring"; 974 reg = <0x2000 0x1000>; 975 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 976 }; 977 }; 978 979 aipstz@217c000 { /* AIPSTZ2 */ 980 reg = <0x0217c000 0x4000>; 981 }; 982 983 usbotg: usb@2184000 { 984 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 985 reg = <0x02184000 0x200>; 986 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&clks IMX6QDL_CLK_USBOH3>; 988 fsl,usbphy = <&usbphy1>; 989 fsl,usbmisc = <&usbmisc 0>; 990 ahb-burst-config = <0x0>; 991 tx-burst-size-dword = <0x10>; 992 rx-burst-size-dword = <0x10>; 993 status = "disabled"; 994 }; 995 996 usbh1: usb@2184200 { 997 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 998 reg = <0x02184200 0x200>; 999 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1001 fsl,usbphy = <&usbphy2>; 1002 fsl,usbmisc = <&usbmisc 1>; 1003 dr_mode = "host"; 1004 ahb-burst-config = <0x0>; 1005 tx-burst-size-dword = <0x10>; 1006 rx-burst-size-dword = <0x10>; 1007 status = "disabled"; 1008 }; 1009 1010 usbh2: usb@2184400 { 1011 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1012 reg = <0x02184400 0x200>; 1013 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1015 fsl,usbphy = <&usbphynop1>; 1016 phy_type = "hsic"; 1017 fsl,usbmisc = <&usbmisc 2>; 1018 dr_mode = "host"; 1019 ahb-burst-config = <0x0>; 1020 tx-burst-size-dword = <0x10>; 1021 rx-burst-size-dword = <0x10>; 1022 status = "disabled"; 1023 }; 1024 1025 usbh3: usb@2184600 { 1026 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1027 reg = <0x02184600 0x200>; 1028 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1030 fsl,usbphy = <&usbphynop2>; 1031 phy_type = "hsic"; 1032 fsl,usbmisc = <&usbmisc 3>; 1033 dr_mode = "host"; 1034 ahb-burst-config = <0x0>; 1035 tx-burst-size-dword = <0x10>; 1036 rx-burst-size-dword = <0x10>; 1037 status = "disabled"; 1038 }; 1039 1040 usbmisc: usbmisc@2184800 { 1041 #index-cells = <1>; 1042 compatible = "fsl,imx6q-usbmisc"; 1043 reg = <0x02184800 0x200>; 1044 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1045 }; 1046 1047 fec: ethernet@2188000 { 1048 compatible = "fsl,imx6q-fec"; 1049 reg = <0x02188000 0x4000>; 1050 interrupt-names = "int0", "pps"; 1051 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>, 1052 <0 119 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&clks IMX6QDL_CLK_ENET>, 1054 <&clks IMX6QDL_CLK_ENET>, 1055 <&clks IMX6QDL_CLK_ENET_REF>, 1056 <&clks IMX6QDL_CLK_ENET_REF_SEL>; 1057 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; 1058 fsl,stop-mode = <&gpr 0x34 27>; 1059 nvmem-cells = <&fec_mac_addr>; 1060 nvmem-cell-names = "mac-address"; 1061 status = "disabled"; 1062 }; 1063 1064 mlb@218c000 { 1065 reg = <0x0218c000 0x4000>; 1066 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, 1067 <0 117 IRQ_TYPE_LEVEL_HIGH>, 1068 <0 126 IRQ_TYPE_LEVEL_HIGH>; 1069 }; 1070 1071 usdhc1: mmc@2190000 { 1072 compatible = "fsl,imx6q-usdhc"; 1073 reg = <0x02190000 0x4000>; 1074 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&clks IMX6QDL_CLK_USDHC1>, 1076 <&clks IMX6QDL_CLK_USDHC1>, 1077 <&clks IMX6QDL_CLK_USDHC1>; 1078 clock-names = "ipg", "ahb", "per"; 1079 bus-width = <4>; 1080 status = "disabled"; 1081 }; 1082 1083 usdhc2: mmc@2194000 { 1084 compatible = "fsl,imx6q-usdhc"; 1085 reg = <0x02194000 0x4000>; 1086 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&clks IMX6QDL_CLK_USDHC2>, 1088 <&clks IMX6QDL_CLK_USDHC2>, 1089 <&clks IMX6QDL_CLK_USDHC2>; 1090 clock-names = "ipg", "ahb", "per"; 1091 bus-width = <4>; 1092 status = "disabled"; 1093 }; 1094 1095 usdhc3: mmc@2198000 { 1096 compatible = "fsl,imx6q-usdhc"; 1097 reg = <0x02198000 0x4000>; 1098 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&clks IMX6QDL_CLK_USDHC3>, 1100 <&clks IMX6QDL_CLK_USDHC3>, 1101 <&clks IMX6QDL_CLK_USDHC3>; 1102 clock-names = "ipg", "ahb", "per"; 1103 bus-width = <4>; 1104 status = "disabled"; 1105 }; 1106 1107 usdhc4: mmc@219c000 { 1108 compatible = "fsl,imx6q-usdhc"; 1109 reg = <0x0219c000 0x4000>; 1110 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&clks IMX6QDL_CLK_USDHC4>, 1112 <&clks IMX6QDL_CLK_USDHC4>, 1113 <&clks IMX6QDL_CLK_USDHC4>; 1114 clock-names = "ipg", "ahb", "per"; 1115 bus-width = <4>; 1116 status = "disabled"; 1117 }; 1118 1119 i2c1: i2c@21a0000 { 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1123 reg = <0x021a0000 0x4000>; 1124 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&clks IMX6QDL_CLK_I2C1>; 1126 status = "disabled"; 1127 }; 1128 1129 i2c2: i2c@21a4000 { 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1133 reg = <0x021a4000 0x4000>; 1134 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&clks IMX6QDL_CLK_I2C2>; 1136 status = "disabled"; 1137 }; 1138 1139 i2c3: i2c@21a8000 { 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1143 reg = <0x021a8000 0x4000>; 1144 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&clks IMX6QDL_CLK_I2C3>; 1146 status = "disabled"; 1147 }; 1148 1149 romcp@21ac000 { 1150 reg = <0x021ac000 0x4000>; 1151 }; 1152 1153 mmdc0: memory-controller@21b0000 { /* MMDC0 */ 1154 compatible = "fsl,imx6q-mmdc"; 1155 reg = <0x021b0000 0x4000>; 1156 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 1157 }; 1158 1159 mmdc1: memory-controller@21b4000 { /* MMDC1 */ 1160 compatible = "fsl,imx6q-mmdc"; 1161 reg = <0x021b4000 0x4000>; 1162 status = "disabled"; 1163 }; 1164 1165 weim: memory-controller@21b8000 { 1166 #address-cells = <2>; 1167 #size-cells = <1>; 1168 compatible = "fsl,imx6q-weim"; 1169 reg = <0x021b8000 0x4000>; 1170 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; 1172 fsl,weim-cs-gpr = <&gpr>; 1173 status = "disabled"; 1174 }; 1175 1176 ocotp: efuse@21bc000 { 1177 compatible = "fsl,imx6q-ocotp", "syscon"; 1178 reg = <0x021bc000 0x4000>; 1179 clocks = <&clks IMX6QDL_CLK_IIM>; 1180 #address-cells = <1>; 1181 #size-cells = <1>; 1182 1183 cpu_speed_grade: speed-grade@10 { 1184 reg = <0x10 4>; 1185 }; 1186 1187 tempmon_calib: calib@38 { 1188 reg = <0x38 4>; 1189 }; 1190 1191 tempmon_temp_grade: temp-grade@20 { 1192 reg = <0x20 4>; 1193 }; 1194 1195 fec_mac_addr: mac-addr@88 { 1196 reg = <0x88 6>; 1197 }; 1198 }; 1199 1200 tzasc@21d0000 { /* TZASC1 */ 1201 reg = <0x021d0000 0x4000>; 1202 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1203 }; 1204 1205 tzasc@21d4000 { /* TZASC2 */ 1206 reg = <0x021d4000 0x4000>; 1207 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 1208 }; 1209 1210 audmux: audmux@21d8000 { 1211 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 1212 reg = <0x021d8000 0x4000>; 1213 status = "disabled"; 1214 }; 1215 1216 mipi_csi: mipi@21dc000 { 1217 compatible = "fsl,imx6-mipi-csi2"; 1218 reg = <0x021dc000 0x4000>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interrupts = <0 100 0x04>, <0 101 0x04>; 1222 clocks = <&clks IMX6QDL_CLK_HSI_TX>, 1223 <&clks IMX6QDL_CLK_VIDEO_27M>, 1224 <&clks IMX6QDL_CLK_EIM_PODF>; 1225 clock-names = "dphy", "ref", "pix"; 1226 status = "disabled"; 1227 }; 1228 1229 mipi_dsi: mipi@21e0000 { 1230 reg = <0x021e0000 0x4000>; 1231 status = "disabled"; 1232 1233 ports { 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 1237 port@0 { 1238 reg = <0>; 1239 1240 mipi_mux_0: endpoint { 1241 remote-endpoint = <&ipu1_di0_mipi>; 1242 }; 1243 }; 1244 1245 port@1 { 1246 reg = <1>; 1247 1248 mipi_mux_1: endpoint { 1249 remote-endpoint = <&ipu1_di1_mipi>; 1250 }; 1251 }; 1252 }; 1253 }; 1254 1255 vdoa@21e4000 { 1256 compatible = "fsl,imx6q-vdoa"; 1257 reg = <0x021e4000 0x4000>; 1258 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&clks IMX6QDL_CLK_VDOA>; 1260 }; 1261 1262 uart2: serial@21e8000 { 1263 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1264 reg = <0x021e8000 0x4000>; 1265 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1267 <&clks IMX6QDL_CLK_UART_SERIAL>; 1268 clock-names = "ipg", "per"; 1269 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1270 dma-names = "rx", "tx"; 1271 status = "disabled"; 1272 }; 1273 1274 uart3: serial@21ec000 { 1275 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1276 reg = <0x021ec000 0x4000>; 1277 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1279 <&clks IMX6QDL_CLK_UART_SERIAL>; 1280 clock-names = "ipg", "per"; 1281 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1282 dma-names = "rx", "tx"; 1283 status = "disabled"; 1284 }; 1285 1286 uart4: serial@21f0000 { 1287 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1288 reg = <0x021f0000 0x4000>; 1289 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1290 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1291 <&clks IMX6QDL_CLK_UART_SERIAL>; 1292 clock-names = "ipg", "per"; 1293 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1294 dma-names = "rx", "tx"; 1295 status = "disabled"; 1296 }; 1297 1298 uart5: serial@21f4000 { 1299 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1300 reg = <0x021f4000 0x4000>; 1301 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1303 <&clks IMX6QDL_CLK_UART_SERIAL>; 1304 clock-names = "ipg", "per"; 1305 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1306 dma-names = "rx", "tx"; 1307 status = "disabled"; 1308 }; 1309 }; 1310 1311 ipu1: ipu@2400000 { 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 compatible = "fsl,imx6q-ipu"; 1315 reg = <0x02400000 0x400000>; 1316 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1317 <0 5 IRQ_TYPE_LEVEL_HIGH>; 1318 clocks = <&clks IMX6QDL_CLK_IPU1>, 1319 <&clks IMX6QDL_CLK_IPU1_DI0>, 1320 <&clks IMX6QDL_CLK_IPU1_DI1>; 1321 clock-names = "bus", "di0", "di1"; 1322 resets = <&src 2>; 1323 1324 ipu1_csi0: port@0 { 1325 reg = <0>; 1326 1327 ipu1_csi0_from_ipu1_csi0_mux: endpoint { 1328 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; 1329 }; 1330 }; 1331 1332 ipu1_csi1: port@1 { 1333 reg = <1>; 1334 }; 1335 1336 ipu1_di0: port@2 { 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 reg = <2>; 1340 1341 ipu1_di0_disp0: endpoint@0 { 1342 reg = <0>; 1343 }; 1344 1345 ipu1_di0_hdmi: endpoint@1 { 1346 reg = <1>; 1347 remote-endpoint = <&hdmi_mux_0>; 1348 }; 1349 1350 ipu1_di0_mipi: endpoint@2 { 1351 reg = <2>; 1352 remote-endpoint = <&mipi_mux_0>; 1353 }; 1354 1355 ipu1_di0_lvds0: endpoint@3 { 1356 reg = <3>; 1357 remote-endpoint = <&lvds0_mux_0>; 1358 }; 1359 1360 ipu1_di0_lvds1: endpoint@4 { 1361 reg = <4>; 1362 remote-endpoint = <&lvds1_mux_0>; 1363 }; 1364 }; 1365 1366 ipu1_di1: port@3 { 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 reg = <3>; 1370 1371 ipu1_di1_disp1: endpoint@0 { 1372 reg = <0>; 1373 }; 1374 1375 ipu1_di1_hdmi: endpoint@1 { 1376 reg = <1>; 1377 remote-endpoint = <&hdmi_mux_1>; 1378 }; 1379 1380 ipu1_di1_mipi: endpoint@2 { 1381 reg = <2>; 1382 remote-endpoint = <&mipi_mux_1>; 1383 }; 1384 1385 ipu1_di1_lvds0: endpoint@3 { 1386 reg = <3>; 1387 remote-endpoint = <&lvds0_mux_1>; 1388 }; 1389 1390 ipu1_di1_lvds1: endpoint@4 { 1391 reg = <4>; 1392 remote-endpoint = <&lvds1_mux_1>; 1393 }; 1394 }; 1395 }; 1396 }; 1397}; 1398