1&l4_cfg { /* 0x4a000000 */ 2 compatible = "ti,dra7-l4-cfg", "simple-pm-bus"; 3 power-domains = <&prm_coreaon>; 4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; 5 clock-names = "fck"; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 9 reg-names = "ap", "la", "ia0"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ 13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */ 14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */ 15 dma-ranges; 16 17 segment@0 { /* 0x4a000000 */ 18 compatible = "simple-pm-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 22 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 23 <0x00001000 0x00001000 0x001000>, /* ap 2 */ 24 <0x00002000 0x00002000 0x002000>, /* ap 3 */ 25 <0x00004000 0x00004000 0x001000>, /* ap 4 */ 26 <0x00005000 0x00005000 0x001000>, /* ap 5 */ 27 <0x00006000 0x00006000 0x001000>, /* ap 6 */ 28 <0x00008000 0x00008000 0x002000>, /* ap 7 */ 29 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */ 30 <0x00056000 0x00056000 0x001000>, /* ap 9 */ 31 <0x00057000 0x00057000 0x001000>, /* ap 10 */ 32 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */ 33 <0x00060000 0x00060000 0x001000>, /* ap 12 */ 34 <0x00080000 0x00080000 0x008000>, /* ap 13 */ 35 <0x00088000 0x00088000 0x001000>, /* ap 14 */ 36 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */ 37 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */ 38 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */ 39 <0x000da000 0x000da000 0x001000>, /* ap 18 */ 40 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */ 41 <0x000de000 0x000de000 0x001000>, /* ap 20 */ 42 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */ 43 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */ 44 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */ 45 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */ 46 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */ 47 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */ 48 <0x00090000 0x00090000 0x008000>, /* ap 59 */ 49 <0x00098000 0x00098000 0x001000>; /* ap 60 */ 50 51 target-module@2000 { /* 0x4a002000, ap 3 08.0 */ 52 compatible = "ti,sysc-omap4", "ti,sysc"; 53 reg = <0x2000 0x4>; 54 reg-names = "rev"; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 ranges = <0x0 0x2000 0x2000>; 58 59 scm: scm@0 { 60 compatible = "ti,dra7-scm-core", "simple-bus"; 61 reg = <0 0x2000>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 ranges = <0 0 0x2000>; 65 66 scm_conf: scm_conf@0 { 67 compatible = "syscon", "simple-bus"; 68 reg = <0x0 0x1400>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0 0x0 0x1400>; 72 73 pbias_regulator: pbias_regulator@e00 { 74 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 75 reg = <0xe00 0x4>; 76 syscon = <&scm_conf>; 77 pbias_mmc_reg: pbias_mmc_omap5 { 78 regulator-name = "pbias_mmc_omap5"; 79 regulator-min-microvolt = <1800000>; 80 regulator-max-microvolt = <3300000>; 81 }; 82 }; 83 84 phy_gmii_sel: phy-gmii-sel@554 { 85 compatible = "ti,dra7xx-phy-gmii-sel"; 86 reg = <0x554 0x4>; 87 #phy-cells = <1>; 88 }; 89 90 scm_conf_clocks: clocks { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 }; 94 }; 95 96 dra7_pmx_core: pinmux@1400 { 97 compatible = "ti,dra7-padconf", 98 "pinctrl-single"; 99 reg = <0x1400 0x0468>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 #pinctrl-cells = <1>; 103 #interrupt-cells = <1>; 104 interrupt-controller; 105 pinctrl-single,register-width = <32>; 106 pinctrl-single,function-mask = <0x3fffffff>; 107 }; 108 109 scm_conf1: scm_conf@1c04 { 110 compatible = "syscon"; 111 reg = <0x1c04 0x0020>; 112 }; 113 114 scm_conf_pcie: scm_conf@1c24 { 115 compatible = "syscon"; 116 reg = <0x1c24 0x0024>; 117 }; 118 119 sdma_xbar: dma-router@b78 { 120 compatible = "ti,dra7-dma-crossbar"; 121 reg = <0xb78 0xfc>; 122 #dma-cells = <1>; 123 dma-requests = <205>; 124 ti,dma-safe-map = <0>; 125 dma-masters = <&sdma>; 126 }; 127 128 edma_xbar: dma-router@c78 { 129 compatible = "ti,dra7-dma-crossbar"; 130 reg = <0xc78 0x7c>; 131 #dma-cells = <2>; 132 dma-requests = <204>; 133 ti,dma-safe-map = <0>; 134 dma-masters = <&edma>; 135 }; 136 }; 137 }; 138 139 target-module@5000 { /* 0x4a005000, ap 5 10.0 */ 140 compatible = "ti,sysc-omap4", "ti,sysc"; 141 reg = <0x5000 0x4>; 142 reg-names = "rev"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges = <0x0 0x5000 0x1000>; 146 147 cm_core_aon: cm_core_aon@0 { 148 compatible = "ti,dra7-cm-core-aon", 149 "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 reg = <0 0x2000>; 153 ranges = <0 0 0x2000>; 154 155 cm_core_aon_clocks: clocks { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 }; 159 160 cm_core_aon_clockdomains: clockdomains { 161 }; 162 }; 163 }; 164 165 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */ 166 compatible = "ti,sysc-omap4", "ti,sysc"; 167 reg = <0x8000 0x4>; 168 reg-names = "rev"; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges = <0x0 0x8000 0x2000>; 172 173 cm_core: cm_core@0 { 174 compatible = "ti,dra7-cm-core", "simple-bus"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 reg = <0 0x3000>; 178 ranges = <0 0 0x3000>; 179 180 cm_core_clocks: clocks { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 }; 184 185 cm_core_clockdomains: clockdomains { 186 }; 187 }; 188 }; 189 190 target-module@56000 { /* 0x4a056000, ap 9 02.0 */ 191 compatible = "ti,sysc-omap2", "ti,sysc"; 192 reg = <0x56000 0x4>, 193 <0x5602c 0x4>, 194 <0x56028 0x4>; 195 reg-names = "rev", "sysc", "syss"; 196 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 197 SYSC_OMAP2_EMUFREE | 198 SYSC_OMAP2_SOFTRESET | 199 SYSC_OMAP2_AUTOIDLE)>; 200 ti,sysc-midle = <SYSC_IDLE_FORCE>, 201 <SYSC_IDLE_NO>, 202 <SYSC_IDLE_SMART>, 203 <SYSC_IDLE_SMART_WKUP>; 204 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 205 <SYSC_IDLE_NO>, 206 <SYSC_IDLE_SMART>, 207 <SYSC_IDLE_SMART_WKUP>; 208 ti,syss-mask = <1>; 209 /* Domains (P, C): core_pwrdm, dma_clkdm */ 210 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>; 211 clock-names = "fck"; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 ranges = <0x0 0x56000 0x1000>; 215 216 sdma: dma-controller@0 { 217 compatible = "ti,omap4430-sdma", "ti,omap-sdma"; 218 reg = <0x0 0x1000>; 219 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 223 #dma-cells = <1>; 224 dma-channels = <32>; 225 dma-requests = <127>; 226 }; 227 }; 228 229 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */ 230 compatible = "ti,sysc"; 231 status = "disabled"; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges = <0x0 0x5e000 0x2000>; 235 }; 236 237 target-module@80000 { /* 0x4a080000, ap 13 20.0 */ 238 compatible = "ti,sysc-omap2", "ti,sysc"; 239 reg = <0x80000 0x4>, 240 <0x80010 0x4>, 241 <0x80014 0x4>; 242 reg-names = "rev", "sysc", "syss"; 243 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 244 SYSC_OMAP2_AUTOIDLE)>; 245 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 246 <SYSC_IDLE_NO>, 247 <SYSC_IDLE_SMART>; 248 ti,syss-mask = <1>; 249 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 250 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>; 251 clock-names = "fck"; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 ranges = <0x0 0x80000 0x8000>; 255 256 ocp2scp@0 { 257 compatible = "ti,omap-ocp2scp"; 258 #address-cells = <1>; 259 #size-cells = <1>; 260 ranges = <0 0 0x8000>; 261 reg = <0x0 0x20>; 262 263 usb2_phy1: phy@4000 { 264 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 265 reg = <0x4000 0x400>; 266 syscon-phy-power = <&scm_conf 0x300>; 267 clocks = <&usb_phy1_always_on_clk32k>, 268 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; 269 clock-names = "wkupclk", 270 "refclk"; 271 #phy-cells = <0>; 272 }; 273 274 usb2_phy2: phy@5000 { 275 compatible = "ti,dra7x-usb2-phy2", 276 "ti,omap-usb2"; 277 reg = <0x5000 0x400>; 278 syscon-phy-power = <&scm_conf 0xe74>; 279 clocks = <&usb_phy2_always_on_clk32k>, 280 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; 281 clock-names = "wkupclk", 282 "refclk"; 283 #phy-cells = <0>; 284 }; 285 286 usb3_phy1: phy@4400 { 287 compatible = "ti,omap-usb3"; 288 reg = <0x4400 0x80>, 289 <0x4800 0x64>, 290 <0x4c00 0x40>; 291 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 292 syscon-phy-power = <&scm_conf 0x370>; 293 clocks = <&usb_phy3_always_on_clk32k>, 294 <&sys_clkin1>, 295 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; 296 clock-names = "wkupclk", 297 "sysclk", 298 "refclk"; 299 #phy-cells = <0>; 300 }; 301 }; 302 }; 303 304 target-module@90000 { /* 0x4a090000, ap 59 42.0 */ 305 compatible = "ti,sysc-omap2", "ti,sysc"; 306 reg = <0x90000 0x4>, 307 <0x90010 0x4>, 308 <0x90014 0x4>; 309 reg-names = "rev", "sysc", "syss"; 310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 311 SYSC_OMAP2_AUTOIDLE)>; 312 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 313 <SYSC_IDLE_NO>, 314 <SYSC_IDLE_SMART>; 315 ti,syss-mask = <1>; 316 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 317 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>; 318 clock-names = "fck"; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 ranges = <0x0 0x90000 0x8000>; 322 323 ocp2scp@0 { 324 compatible = "ti,omap-ocp2scp"; 325 #address-cells = <1>; 326 #size-cells = <1>; 327 ranges = <0 0 0x8000>; 328 reg = <0x0 0x20>; 329 330 pcie1_phy: pciephy@4000 { 331 compatible = "ti,phy-pipe3-pcie"; 332 reg = <0x4000 0x80>, /* phy_rx */ 333 <0x4400 0x64>; /* phy_tx */ 334 reg-names = "phy_rx", "phy_tx"; 335 syscon-phy-power = <&scm_conf_pcie 0x1c>; 336 syscon-pcs = <&scm_conf_pcie 0x10>; 337 clocks = <&dpll_pcie_ref_ck>, 338 <&dpll_pcie_ref_m2ldo_ck>, 339 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, 340 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, 341 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, 342 <&optfclk_pciephy_div>, 343 <&sys_clkin1>; 344 clock-names = "dpll_ref", "dpll_ref_m2", 345 "wkupclk", "refclk", 346 "div-clk", "phy-div", "sysclk"; 347 #phy-cells = <0>; 348 }; 349 350 pcie2_phy: pciephy@5000 { 351 compatible = "ti,phy-pipe3-pcie"; 352 reg = <0x5000 0x80>, /* phy_rx */ 353 <0x5400 0x64>; /* phy_tx */ 354 reg-names = "phy_rx", "phy_tx"; 355 syscon-phy-power = <&scm_conf_pcie 0x20>; 356 syscon-pcs = <&scm_conf_pcie 0x10>; 357 clocks = <&dpll_pcie_ref_ck>, 358 <&dpll_pcie_ref_m2ldo_ck>, 359 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, 360 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, 361 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, 362 <&optfclk_pciephy_div>, 363 <&sys_clkin1>; 364 clock-names = "dpll_ref", "dpll_ref_m2", 365 "wkupclk", "refclk", 366 "div-clk", "phy-div", "sysclk"; 367 #phy-cells = <0>; 368 status = "disabled"; 369 }; 370 371 sata_phy: phy@6000 { 372 compatible = "ti,phy-pipe3-sata"; 373 reg = <0x6000 0x80>, /* phy_rx */ 374 <0x6400 0x64>, /* phy_tx */ 375 <0x6800 0x40>; /* pll_ctrl */ 376 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 377 syscon-phy-power = <&scm_conf 0x374>; 378 clocks = <&sys_clkin1>, 379 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; 380 clock-names = "sysclk", "refclk"; 381 syscon-pllreset = <&scm_conf 0x3fc>; 382 #phy-cells = <0>; 383 }; 384 }; 385 }; 386 387 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */ 388 compatible = "ti,sysc"; 389 status = "disabled"; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 ranges = <0x0 0xa0000 0x8000>; 393 }; 394 395 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */ 396 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 397 reg = <0xd9038 0x4>; 398 reg-names = "sysc"; 399 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 400 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 401 <SYSC_IDLE_NO>, 402 <SYSC_IDLE_SMART>, 403 <SYSC_IDLE_SMART_WKUP>; 404 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 405 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; 406 clock-names = "fck"; 407 #address-cells = <1>; 408 #size-cells = <1>; 409 ranges = <0x0 0xd9000 0x1000>; 410 411 /* SmartReflex child device marked reserved in TRM */ 412 }; 413 414 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */ 415 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 416 reg = <0xdd038 0x4>; 417 reg-names = "sysc"; 418 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 419 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 420 <SYSC_IDLE_NO>, 421 <SYSC_IDLE_SMART>, 422 <SYSC_IDLE_SMART_WKUP>; 423 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */ 424 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; 425 clock-names = "fck"; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 ranges = <0x0 0xdd000 0x1000>; 429 430 /* SmartReflex child device marked reserved in TRM */ 431 }; 432 433 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */ 434 compatible = "ti,sysc"; 435 status = "disabled"; 436 #address-cells = <1>; 437 #size-cells = <1>; 438 ranges = <0x0 0xe0000 0x1000>; 439 }; 440 441 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */ 442 compatible = "ti,sysc-omap4", "ti,sysc"; 443 reg = <0xf4000 0x4>, 444 <0xf4010 0x4>; 445 reg-names = "rev", "sysc"; 446 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 447 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 448 <SYSC_IDLE_NO>, 449 <SYSC_IDLE_SMART>; 450 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 451 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>; 452 clock-names = "fck"; 453 #address-cells = <1>; 454 #size-cells = <1>; 455 ranges = <0x0 0xf4000 0x1000>; 456 457 mailbox1: mailbox@0 { 458 compatible = "ti,omap4-mailbox"; 459 reg = <0x0 0x200>; 460 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 463 #mbox-cells = <1>; 464 ti,mbox-num-users = <3>; 465 ti,mbox-num-fifos = <8>; 466 status = "disabled"; 467 }; 468 }; 469 470 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */ 471 compatible = "ti,sysc-omap2", "ti,sysc"; 472 reg = <0xf6000 0x4>, 473 <0xf6010 0x4>, 474 <0xf6014 0x4>; 475 reg-names = "rev", "sysc", "syss"; 476 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 477 SYSC_OMAP2_SOFTRESET | 478 SYSC_OMAP2_AUTOIDLE)>; 479 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 480 <SYSC_IDLE_NO>, 481 <SYSC_IDLE_SMART>; 482 ti,syss-mask = <1>; 483 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 484 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>; 485 clock-names = "fck"; 486 #address-cells = <1>; 487 #size-cells = <1>; 488 ranges = <0x0 0xf6000 0x1000>; 489 490 hwspinlock: spinlock@0 { 491 compatible = "ti,omap4-hwspinlock"; 492 reg = <0x0 0x1000>; 493 #hwlock-cells = <1>; 494 }; 495 }; 496 }; 497 498 segment@100000 { /* 0x4a100000 */ 499 compatible = "simple-pm-bus"; 500 #address-cells = <1>; 501 #size-cells = <1>; 502 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */ 503 <0x00003000 0x00103000 0x001000>, /* ap 28 */ 504 <0x00008000 0x00108000 0x001000>, /* ap 29 */ 505 <0x00009000 0x00109000 0x001000>, /* ap 30 */ 506 <0x00040000 0x00140000 0x010000>, /* ap 31 */ 507 <0x00050000 0x00150000 0x001000>, /* ap 32 */ 508 <0x00051000 0x00151000 0x001000>, /* ap 33 */ 509 <0x00052000 0x00152000 0x001000>, /* ap 34 */ 510 <0x00053000 0x00153000 0x001000>, /* ap 35 */ 511 <0x00054000 0x00154000 0x001000>, /* ap 36 */ 512 <0x00055000 0x00155000 0x001000>, /* ap 37 */ 513 <0x00056000 0x00156000 0x001000>, /* ap 38 */ 514 <0x00057000 0x00157000 0x001000>, /* ap 39 */ 515 <0x00058000 0x00158000 0x001000>, /* ap 40 */ 516 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */ 517 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */ 518 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */ 519 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */ 520 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */ 521 <0x00060000 0x00160000 0x001000>, /* ap 48 */ 522 <0x00061000 0x00161000 0x001000>, /* ap 49 */ 523 <0x00062000 0x00162000 0x001000>, /* ap 50 */ 524 <0x00063000 0x00163000 0x001000>, /* ap 51 */ 525 <0x00064000 0x00164000 0x001000>, /* ap 52 */ 526 <0x00065000 0x00165000 0x001000>, /* ap 53 */ 527 <0x00066000 0x00166000 0x001000>, /* ap 54 */ 528 <0x00067000 0x00167000 0x001000>, /* ap 55 */ 529 <0x00068000 0x00168000 0x001000>, /* ap 56 */ 530 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */ 531 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */ 532 <0x00071000 0x00171000 0x001000>, /* ap 61 */ 533 <0x00072000 0x00172000 0x001000>, /* ap 62 */ 534 <0x00073000 0x00173000 0x001000>, /* ap 63 */ 535 <0x00074000 0x00174000 0x001000>, /* ap 64 */ 536 <0x00075000 0x00175000 0x001000>, /* ap 65 */ 537 <0x00076000 0x00176000 0x001000>, /* ap 66 */ 538 <0x00077000 0x00177000 0x001000>, /* ap 67 */ 539 <0x00078000 0x00178000 0x001000>, /* ap 68 */ 540 <0x00081000 0x00181000 0x001000>, /* ap 69 */ 541 <0x00082000 0x00182000 0x001000>, /* ap 70 */ 542 <0x00083000 0x00183000 0x001000>, /* ap 71 */ 543 <0x00084000 0x00184000 0x001000>, /* ap 72 */ 544 <0x00085000 0x00185000 0x001000>, /* ap 73 */ 545 <0x00086000 0x00186000 0x001000>, /* ap 74 */ 546 <0x00087000 0x00187000 0x001000>, /* ap 75 */ 547 <0x00088000 0x00188000 0x001000>, /* ap 76 */ 548 <0x00069000 0x00169000 0x001000>, /* ap 103 */ 549 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */ 550 <0x00079000 0x00179000 0x001000>, /* ap 105 */ 551 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */ 552 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */ 553 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */ 554 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */ 555 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */ 556 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */ 557 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */ 558 <0x00059000 0x00159000 0x001000>, /* ap 125 */ 559 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */ 560 dma-ranges; 561 562 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */ 563 compatible = "ti,sysc"; 564 status = "disabled"; 565 #address-cells = <1>; 566 #size-cells = <1>; 567 ranges = <0x0 0x2000 0x1000>; 568 }; 569 570 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ 571 compatible = "ti,sysc"; 572 status = "disabled"; 573 #address-cells = <1>; 574 #size-cells = <1>; 575 ranges = <0x0 0x8000 0x1000>; 576 }; 577 578 target-module@40000 { /* 0x4a140000, ap 31 06.0 */ 579 compatible = "ti,sysc-omap4", "ti,sysc"; 580 reg = <0x400fc 4>, 581 <0x41100 4>; 582 reg-names = "rev", "sysc"; 583 ti,sysc-midle = <SYSC_IDLE_FORCE>, 584 <SYSC_IDLE_NO>, 585 <SYSC_IDLE_SMART>; 586 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 587 <SYSC_IDLE_NO>, 588 <SYSC_IDLE_SMART>, 589 <SYSC_IDLE_SMART_WKUP>; 590 power-domains = <&prm_l3init>; 591 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>; 592 clock-names = "fck"; 593 #size-cells = <1>; 594 #address-cells = <1>; 595 ranges = <0x0 0x40000 0x10000>; 596 597 sata: sata@0 { 598 compatible = "snps,dwc-ahci"; 599 reg = <0 0x1100>, <0x1100 0x8>; 600 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 601 phys = <&sata_phy>; 602 phy-names = "sata-phy"; 603 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; 604 ports-implemented = <0x1>; 605 }; 606 }; 607 608 target-module@51000 { /* 0x4a151000, ap 33 50.0 */ 609 compatible = "ti,sysc"; 610 status = "disabled"; 611 #address-cells = <1>; 612 #size-cells = <1>; 613 ranges = <0x0 0x51000 0x1000>; 614 }; 615 616 target-module@53000 { /* 0x4a153000, ap 35 54.0 */ 617 compatible = "ti,sysc"; 618 status = "disabled"; 619 #address-cells = <1>; 620 #size-cells = <1>; 621 ranges = <0x0 0x53000 0x1000>; 622 }; 623 624 target-module@55000 { /* 0x4a155000, ap 37 46.0 */ 625 compatible = "ti,sysc"; 626 status = "disabled"; 627 #address-cells = <1>; 628 #size-cells = <1>; 629 ranges = <0x0 0x55000 0x1000>; 630 }; 631 632 target-module@57000 { /* 0x4a157000, ap 39 58.0 */ 633 compatible = "ti,sysc"; 634 status = "disabled"; 635 #address-cells = <1>; 636 #size-cells = <1>; 637 ranges = <0x0 0x57000 0x1000>; 638 }; 639 640 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */ 641 compatible = "ti,sysc"; 642 status = "disabled"; 643 #address-cells = <1>; 644 #size-cells = <1>; 645 ranges = <0x0 0x59000 0x1000>; 646 }; 647 648 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */ 649 compatible = "ti,sysc"; 650 status = "disabled"; 651 #address-cells = <1>; 652 #size-cells = <1>; 653 ranges = <0x0 0x5b000 0x1000>; 654 }; 655 656 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */ 657 compatible = "ti,sysc"; 658 status = "disabled"; 659 #address-cells = <1>; 660 #size-cells = <1>; 661 ranges = <0x0 0x5d000 0x1000>; 662 }; 663 664 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */ 665 compatible = "ti,sysc"; 666 status = "disabled"; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 ranges = <0x0 0x5f000 0x1000>; 670 }; 671 672 target-module@61000 { /* 0x4a161000, ap 49 32.0 */ 673 compatible = "ti,sysc"; 674 status = "disabled"; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges = <0x0 0x61000 0x1000>; 678 }; 679 680 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */ 681 compatible = "ti,sysc"; 682 status = "disabled"; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 ranges = <0x0 0x63000 0x1000>; 686 }; 687 688 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */ 689 compatible = "ti,sysc"; 690 status = "disabled"; 691 #address-cells = <1>; 692 #size-cells = <1>; 693 ranges = <0x0 0x65000 0x1000>; 694 }; 695 696 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */ 697 compatible = "ti,sysc"; 698 status = "disabled"; 699 #address-cells = <1>; 700 #size-cells = <1>; 701 ranges = <0x0 0x67000 0x1000>; 702 }; 703 704 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */ 705 compatible = "ti,sysc"; 706 status = "disabled"; 707 #address-cells = <1>; 708 #size-cells = <1>; 709 ranges = <0x0 0x69000 0x1000>; 710 }; 711 712 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */ 713 compatible = "ti,sysc"; 714 status = "disabled"; 715 #address-cells = <1>; 716 #size-cells = <1>; 717 ranges = <0x0 0x6b000 0x1000>; 718 }; 719 720 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */ 721 compatible = "ti,sysc"; 722 status = "disabled"; 723 #address-cells = <1>; 724 #size-cells = <1>; 725 ranges = <0x0 0x6d000 0x1000>; 726 }; 727 728 target-module@71000 { /* 0x4a171000, ap 61 48.0 */ 729 compatible = "ti,sysc"; 730 status = "disabled"; 731 #address-cells = <1>; 732 #size-cells = <1>; 733 ranges = <0x0 0x71000 0x1000>; 734 }; 735 736 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */ 737 compatible = "ti,sysc"; 738 status = "disabled"; 739 #address-cells = <1>; 740 #size-cells = <1>; 741 ranges = <0x0 0x73000 0x1000>; 742 }; 743 744 target-module@75000 { /* 0x4a175000, ap 65 64.0 */ 745 compatible = "ti,sysc"; 746 status = "disabled"; 747 #address-cells = <1>; 748 #size-cells = <1>; 749 ranges = <0x0 0x75000 0x1000>; 750 }; 751 752 target-module@77000 { /* 0x4a177000, ap 67 66.0 */ 753 compatible = "ti,sysc"; 754 status = "disabled"; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 ranges = <0x0 0x77000 0x1000>; 758 }; 759 760 target-module@79000 { /* 0x4a179000, ap 105 34.0 */ 761 compatible = "ti,sysc"; 762 status = "disabled"; 763 #address-cells = <1>; 764 #size-cells = <1>; 765 ranges = <0x0 0x79000 0x1000>; 766 }; 767 768 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */ 769 compatible = "ti,sysc"; 770 status = "disabled"; 771 #address-cells = <1>; 772 #size-cells = <1>; 773 ranges = <0x0 0x7b000 0x1000>; 774 }; 775 776 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */ 777 compatible = "ti,sysc"; 778 status = "disabled"; 779 #address-cells = <1>; 780 #size-cells = <1>; 781 ranges = <0x0 0x7d000 0x1000>; 782 }; 783 784 target-module@81000 { /* 0x4a181000, ap 69 26.0 */ 785 compatible = "ti,sysc"; 786 status = "disabled"; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 ranges = <0x0 0x81000 0x1000>; 790 }; 791 792 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */ 793 compatible = "ti,sysc"; 794 status = "disabled"; 795 #address-cells = <1>; 796 #size-cells = <1>; 797 ranges = <0x0 0x83000 0x1000>; 798 }; 799 800 target-module@85000 { /* 0x4a185000, ap 73 36.0 */ 801 compatible = "ti,sysc"; 802 status = "disabled"; 803 #address-cells = <1>; 804 #size-cells = <1>; 805 ranges = <0x0 0x85000 0x1000>; 806 }; 807 808 target-module@87000 { /* 0x4a187000, ap 75 74.0 */ 809 compatible = "ti,sysc"; 810 status = "disabled"; 811 #address-cells = <1>; 812 #size-cells = <1>; 813 ranges = <0x0 0x87000 0x1000>; 814 }; 815 }; 816 817 segment@200000 { /* 0x4a200000 */ 818 compatible = "simple-pm-bus"; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */ 822 <0x00019000 0x00219000 0x001000>, /* ap 44 */ 823 <0x00000000 0x00200000 0x001000>, /* ap 77 */ 824 <0x00001000 0x00201000 0x001000>, /* ap 78 */ 825 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */ 826 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */ 827 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */ 828 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */ 829 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */ 830 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */ 831 <0x00010000 0x00210000 0x001000>, /* ap 85 */ 832 <0x00011000 0x00211000 0x001000>, /* ap 86 */ 833 <0x00012000 0x00212000 0x001000>, /* ap 87 */ 834 <0x00013000 0x00213000 0x001000>, /* ap 88 */ 835 <0x00014000 0x00214000 0x001000>, /* ap 89 */ 836 <0x00015000 0x00215000 0x001000>, /* ap 90 */ 837 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */ 838 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */ 839 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */ 840 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */ 841 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */ 842 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */ 843 <0x00020000 0x00220000 0x001000>, /* ap 97 */ 844 <0x00021000 0x00221000 0x001000>, /* ap 98 */ 845 <0x00024000 0x00224000 0x001000>, /* ap 99 */ 846 <0x00025000 0x00225000 0x001000>, /* ap 100 */ 847 <0x00026000 0x00226000 0x001000>, /* ap 101 */ 848 <0x00027000 0x00227000 0x001000>, /* ap 102 */ 849 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */ 850 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */ 851 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */ 852 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */ 853 <0x00030000 0x00230000 0x001000>, /* ap 113 */ 854 <0x00031000 0x00231000 0x001000>, /* ap 114 */ 855 <0x00032000 0x00232000 0x001000>, /* ap 115 */ 856 <0x00033000 0x00233000 0x001000>, /* ap 116 */ 857 <0x00034000 0x00234000 0x001000>, /* ap 117 */ 858 <0x00035000 0x00235000 0x001000>, /* ap 118 */ 859 <0x00036000 0x00236000 0x001000>, /* ap 119 */ 860 <0x00037000 0x00237000 0x001000>, /* ap 120 */ 861 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */ 862 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */ 863 864 target-module@0 { /* 0x4a200000, ap 77 3e.0 */ 865 compatible = "ti,sysc"; 866 status = "disabled"; 867 #address-cells = <1>; 868 #size-cells = <1>; 869 ranges = <0x0 0x0 0x1000>; 870 }; 871 872 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */ 873 compatible = "ti,sysc"; 874 status = "disabled"; 875 #address-cells = <1>; 876 #size-cells = <1>; 877 ranges = <0x0 0xa000 0x1000>; 878 }; 879 880 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */ 881 compatible = "ti,sysc"; 882 status = "disabled"; 883 #address-cells = <1>; 884 #size-cells = <1>; 885 ranges = <0x0 0xc000 0x1000>; 886 }; 887 888 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */ 889 compatible = "ti,sysc"; 890 status = "disabled"; 891 #address-cells = <1>; 892 #size-cells = <1>; 893 ranges = <0x0 0xe000 0x1000>; 894 }; 895 896 target-module@10000 { /* 0x4a210000, ap 85 14.0 */ 897 compatible = "ti,sysc"; 898 status = "disabled"; 899 #address-cells = <1>; 900 #size-cells = <1>; 901 ranges = <0x0 0x10000 0x1000>; 902 }; 903 904 target-module@12000 { /* 0x4a212000, ap 87 16.0 */ 905 compatible = "ti,sysc"; 906 status = "disabled"; 907 #address-cells = <1>; 908 #size-cells = <1>; 909 ranges = <0x0 0x12000 0x1000>; 910 }; 911 912 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */ 913 compatible = "ti,sysc"; 914 status = "disabled"; 915 #address-cells = <1>; 916 #size-cells = <1>; 917 ranges = <0x0 0x14000 0x1000>; 918 }; 919 920 target-module@18000 { /* 0x4a218000, ap 43 12.0 */ 921 compatible = "ti,sysc"; 922 status = "disabled"; 923 #address-cells = <1>; 924 #size-cells = <1>; 925 ranges = <0x0 0x18000 0x1000>; 926 }; 927 928 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */ 929 compatible = "ti,sysc"; 930 status = "disabled"; 931 #address-cells = <1>; 932 #size-cells = <1>; 933 ranges = <0x0 0x1a000 0x1000>; 934 }; 935 936 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */ 937 compatible = "ti,sysc"; 938 status = "disabled"; 939 #address-cells = <1>; 940 #size-cells = <1>; 941 ranges = <0x0 0x1c000 0x1000>; 942 }; 943 944 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */ 945 compatible = "ti,sysc"; 946 status = "disabled"; 947 #address-cells = <1>; 948 #size-cells = <1>; 949 ranges = <0x0 0x1e000 0x1000>; 950 }; 951 952 target-module@20000 { /* 0x4a220000, ap 97 24.0 */ 953 compatible = "ti,sysc"; 954 status = "disabled"; 955 #address-cells = <1>; 956 #size-cells = <1>; 957 ranges = <0x0 0x20000 0x1000>; 958 }; 959 960 target-module@24000 { /* 0x4a224000, ap 99 44.0 */ 961 compatible = "ti,sysc"; 962 status = "disabled"; 963 #address-cells = <1>; 964 #size-cells = <1>; 965 ranges = <0x0 0x24000 0x1000>; 966 }; 967 968 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */ 969 compatible = "ti,sysc"; 970 status = "disabled"; 971 #address-cells = <1>; 972 #size-cells = <1>; 973 ranges = <0x0 0x26000 0x1000>; 974 }; 975 976 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */ 977 compatible = "ti,sysc"; 978 status = "disabled"; 979 #address-cells = <1>; 980 #size-cells = <1>; 981 ranges = <0x0 0x2a000 0x1000>; 982 }; 983 984 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */ 985 compatible = "ti,sysc"; 986 status = "disabled"; 987 #address-cells = <1>; 988 #size-cells = <1>; 989 ranges = <0x0 0x2c000 0x1000>; 990 }; 991 992 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */ 993 compatible = "ti,sysc"; 994 status = "disabled"; 995 #address-cells = <1>; 996 #size-cells = <1>; 997 ranges = <0x0 0x2e000 0x1000>; 998 }; 999 1000 target-module@30000 { /* 0x4a230000, ap 113 70.0 */ 1001 compatible = "ti,sysc"; 1002 status = "disabled"; 1003 #address-cells = <1>; 1004 #size-cells = <1>; 1005 ranges = <0x0 0x30000 0x1000>; 1006 }; 1007 1008 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */ 1009 compatible = "ti,sysc"; 1010 status = "disabled"; 1011 #address-cells = <1>; 1012 #size-cells = <1>; 1013 ranges = <0x0 0x32000 0x1000>; 1014 }; 1015 1016 target-module@34000 { /* 0x4a234000, ap 117 76.1 */ 1017 compatible = "ti,sysc"; 1018 status = "disabled"; 1019 #address-cells = <1>; 1020 #size-cells = <1>; 1021 ranges = <0x0 0x34000 0x1000>; 1022 }; 1023 1024 target-module@36000 { /* 0x4a236000, ap 119 62.0 */ 1025 compatible = "ti,sysc"; 1026 status = "disabled"; 1027 #address-cells = <1>; 1028 #size-cells = <1>; 1029 ranges = <0x0 0x36000 0x1000>; 1030 }; 1031 }; 1032}; 1033 1034&l4_per1 { /* 0x48000000 */ 1035 compatible = "ti,dra7-l4-per1", "simple-pm-bus"; 1036 power-domains = <&prm_l4per>; 1037 clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>; 1038 clock-names = "fck"; 1039 reg = <0x48000000 0x800>, 1040 <0x48000800 0x800>, 1041 <0x48001000 0x400>, 1042 <0x48001400 0x400>, 1043 <0x48001800 0x400>, 1044 <0x48001c00 0x400>; 1045 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; 1046 #address-cells = <1>; 1047 #size-cells = <1>; 1048 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */ 1049 <0x00200000 0x48200000 0x200000>; /* segment 1 */ 1050 1051 segment@0 { /* 0x48000000 */ 1052 compatible = "simple-pm-bus"; 1053 #address-cells = <1>; 1054 #size-cells = <1>; 1055 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 1056 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 1057 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 1058 <0x00020000 0x00020000 0x001000>, /* ap 3 */ 1059 <0x00021000 0x00021000 0x001000>, /* ap 4 */ 1060 <0x00032000 0x00032000 0x001000>, /* ap 5 */ 1061 <0x00033000 0x00033000 0x001000>, /* ap 6 */ 1062 <0x00034000 0x00034000 0x001000>, /* ap 7 */ 1063 <0x00035000 0x00035000 0x001000>, /* ap 8 */ 1064 <0x00036000 0x00036000 0x001000>, /* ap 9 */ 1065 <0x00037000 0x00037000 0x001000>, /* ap 10 */ 1066 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */ 1067 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */ 1068 <0x00055000 0x00055000 0x001000>, /* ap 13 */ 1069 <0x00056000 0x00056000 0x001000>, /* ap 14 */ 1070 <0x00057000 0x00057000 0x001000>, /* ap 15 */ 1071 <0x00058000 0x00058000 0x001000>, /* ap 16 */ 1072 <0x00059000 0x00059000 0x001000>, /* ap 17 */ 1073 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */ 1074 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */ 1075 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */ 1076 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */ 1077 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */ 1078 <0x00060000 0x00060000 0x001000>, /* ap 23 */ 1079 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */ 1080 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */ 1081 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */ 1082 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */ 1083 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */ 1084 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */ 1085 <0x00070000 0x00070000 0x001000>, /* ap 30 */ 1086 <0x00071000 0x00071000 0x001000>, /* ap 31 */ 1087 <0x00072000 0x00072000 0x001000>, /* ap 32 */ 1088 <0x00073000 0x00073000 0x001000>, /* ap 33 */ 1089 <0x00061000 0x00061000 0x001000>, /* ap 34 */ 1090 <0x00053000 0x00053000 0x001000>, /* ap 35 */ 1091 <0x00054000 0x00054000 0x001000>, /* ap 36 */ 1092 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */ 1093 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */ 1094 <0x00078000 0x00078000 0x001000>, /* ap 39 */ 1095 <0x00079000 0x00079000 0x001000>, /* ap 40 */ 1096 <0x00086000 0x00086000 0x001000>, /* ap 41 */ 1097 <0x00087000 0x00087000 0x001000>, /* ap 42 */ 1098 <0x00088000 0x00088000 0x001000>, /* ap 43 */ 1099 <0x00089000 0x00089000 0x001000>, /* ap 44 */ 1100 <0x00051000 0x00051000 0x001000>, /* ap 45 */ 1101 <0x00052000 0x00052000 0x001000>, /* ap 46 */ 1102 <0x00098000 0x00098000 0x001000>, /* ap 47 */ 1103 <0x00099000 0x00099000 0x001000>, /* ap 48 */ 1104 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */ 1105 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */ 1106 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */ 1107 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */ 1108 <0x00068000 0x00068000 0x001000>, /* ap 53 */ 1109 <0x00069000 0x00069000 0x001000>, /* ap 54 */ 1110 <0x00090000 0x00090000 0x002000>, /* ap 55 */ 1111 <0x00092000 0x00092000 0x001000>, /* ap 56 */ 1112 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ 1113 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ 1114 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ 1115 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ 1116 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */ 1117 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */ 1118 <0x00066000 0x00066000 0x001000>, /* ap 63 */ 1119 <0x00067000 0x00067000 0x001000>, /* ap 64 */ 1120 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */ 1121 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */ 1122 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */ 1123 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */ 1124 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */ 1125 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */ 1126 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */ 1127 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */ 1128 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */ 1129 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */ 1130 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */ 1131 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */ 1132 <0x00001400 0x00001400 0x000400>, /* ap 77 */ 1133 <0x00001800 0x00001800 0x000400>, /* ap 78 */ 1134 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */ 1135 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */ 1136 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */ 1137 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */ 1138 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */ 1139 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */ 1140 1141 target-module@20000 { /* 0x48020000, ap 3 04.0 */ 1142 compatible = "ti,sysc-omap2", "ti,sysc"; 1143 reg = <0x20050 0x4>, 1144 <0x20054 0x4>, 1145 <0x20058 0x4>; 1146 reg-names = "rev", "sysc", "syss"; 1147 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1148 SYSC_OMAP2_SOFTRESET | 1149 SYSC_OMAP2_AUTOIDLE)>; 1150 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1151 <SYSC_IDLE_NO>, 1152 <SYSC_IDLE_SMART>, 1153 <SYSC_IDLE_SMART_WKUP>; 1154 ti,syss-mask = <1>; 1155 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1156 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>; 1157 clock-names = "fck"; 1158 #address-cells = <1>; 1159 #size-cells = <1>; 1160 ranges = <0x0 0x20000 0x1000>; 1161 1162 uart3: serial@0 { 1163 compatible = "ti,dra742-uart"; 1164 reg = <0x0 0x100>; 1165 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1166 clock-frequency = <48000000>; 1167 status = "disabled"; 1168 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 1169 dma-names = "tx", "rx"; 1170 }; 1171 }; 1172 1173 target-module@32000 { /* 0x48032000, ap 5 3e.0 */ 1174 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1175 reg = <0x32000 0x4>, 1176 <0x32010 0x4>; 1177 reg-names = "rev", "sysc"; 1178 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1179 SYSC_OMAP4_SOFTRESET)>; 1180 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1181 <SYSC_IDLE_NO>, 1182 <SYSC_IDLE_SMART>, 1183 <SYSC_IDLE_SMART_WKUP>; 1184 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1185 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>; 1186 clock-names = "fck"; 1187 #address-cells = <1>; 1188 #size-cells = <1>; 1189 ranges = <0x0 0x32000 0x1000>; 1190 1191 timer2: timer@0 { 1192 compatible = "ti,omap5430-timer"; 1193 reg = <0x0 0x80>; 1194 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>; 1195 clock-names = "fck", "timer_sys_ck"; 1196 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1197 }; 1198 }; 1199 1200 timer3_target: target-module@34000 { /* 0x48034000, ap 7 46.0 */ 1201 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1202 reg = <0x34000 0x4>, 1203 <0x34010 0x4>; 1204 reg-names = "rev", "sysc"; 1205 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1206 SYSC_OMAP4_SOFTRESET)>; 1207 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1208 <SYSC_IDLE_NO>, 1209 <SYSC_IDLE_SMART>, 1210 <SYSC_IDLE_SMART_WKUP>; 1211 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1212 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>; 1213 clock-names = "fck"; 1214 #address-cells = <1>; 1215 #size-cells = <1>; 1216 ranges = <0x0 0x34000 0x1000>; 1217 1218 timer3: timer@0 { 1219 compatible = "ti,omap5430-timer"; 1220 reg = <0x0 0x80>; 1221 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>; 1222 clock-names = "fck", "timer_sys_ck"; 1223 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1224 }; 1225 }; 1226 1227 timer4_target: target-module@36000 { /* 0x48036000, ap 9 4e.0 */ 1228 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1229 reg = <0x36000 0x4>, 1230 <0x36010 0x4>; 1231 reg-names = "rev", "sysc"; 1232 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1233 SYSC_OMAP4_SOFTRESET)>; 1234 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1235 <SYSC_IDLE_NO>, 1236 <SYSC_IDLE_SMART>, 1237 <SYSC_IDLE_SMART_WKUP>; 1238 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1239 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>; 1240 clock-names = "fck"; 1241 #address-cells = <1>; 1242 #size-cells = <1>; 1243 ranges = <0x0 0x36000 0x1000>; 1244 1245 timer4: timer@0 { 1246 compatible = "ti,omap5430-timer"; 1247 reg = <0x0 0x80>; 1248 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>; 1249 clock-names = "fck", "timer_sys_ck"; 1250 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1251 }; 1252 }; 1253 1254 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */ 1255 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1256 reg = <0x3e000 0x4>, 1257 <0x3e010 0x4>; 1258 reg-names = "rev", "sysc"; 1259 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1260 SYSC_OMAP4_SOFTRESET)>; 1261 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1262 <SYSC_IDLE_NO>, 1263 <SYSC_IDLE_SMART>, 1264 <SYSC_IDLE_SMART_WKUP>; 1265 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1266 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>; 1267 clock-names = "fck"; 1268 #address-cells = <1>; 1269 #size-cells = <1>; 1270 ranges = <0x0 0x3e000 0x1000>; 1271 1272 timer9: timer@0 { 1273 compatible = "ti,omap5430-timer"; 1274 reg = <0x0 0x80>; 1275 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>; 1276 clock-names = "fck", "timer_sys_ck"; 1277 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1278 }; 1279 }; 1280 1281 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */ 1282 compatible = "ti,sysc-omap2", "ti,sysc"; 1283 reg = <0x51000 0x4>, 1284 <0x51010 0x4>, 1285 <0x51114 0x4>; 1286 reg-names = "rev", "sysc", "syss"; 1287 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1288 SYSC_OMAP2_SOFTRESET | 1289 SYSC_OMAP2_AUTOIDLE)>; 1290 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1291 <SYSC_IDLE_NO>, 1292 <SYSC_IDLE_SMART>, 1293 <SYSC_IDLE_SMART_WKUP>; 1294 ti,syss-mask = <1>; 1295 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1296 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>, 1297 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>; 1298 clock-names = "fck", "dbclk"; 1299 #address-cells = <1>; 1300 #size-cells = <1>; 1301 ranges = <0x0 0x51000 0x1000>; 1302 1303 gpio7: gpio@0 { 1304 compatible = "ti,omap4-gpio"; 1305 reg = <0x0 0x200>; 1306 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1307 gpio-controller; 1308 #gpio-cells = <2>; 1309 interrupt-controller; 1310 #interrupt-cells = <2>; 1311 }; 1312 }; 1313 1314 target-module@53000 { /* 0x48053000, ap 35 36.0 */ 1315 compatible = "ti,sysc-omap2", "ti,sysc"; 1316 reg = <0x53000 0x4>, 1317 <0x53010 0x4>, 1318 <0x53114 0x4>; 1319 reg-names = "rev", "sysc", "syss"; 1320 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1321 SYSC_OMAP2_SOFTRESET | 1322 SYSC_OMAP2_AUTOIDLE)>; 1323 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1324 <SYSC_IDLE_NO>, 1325 <SYSC_IDLE_SMART>, 1326 <SYSC_IDLE_SMART_WKUP>; 1327 ti,syss-mask = <1>; 1328 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1329 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>, 1330 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>; 1331 clock-names = "fck", "dbclk"; 1332 #address-cells = <1>; 1333 #size-cells = <1>; 1334 ranges = <0x0 0x53000 0x1000>; 1335 1336 gpio8: gpio@0 { 1337 compatible = "ti,omap4-gpio"; 1338 reg = <0x0 0x200>; 1339 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1340 gpio-controller; 1341 #gpio-cells = <2>; 1342 interrupt-controller; 1343 #interrupt-cells = <2>; 1344 }; 1345 }; 1346 1347 gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */ 1348 compatible = "ti,sysc-omap2", "ti,sysc"; 1349 reg = <0x55000 0x4>, 1350 <0x55010 0x4>, 1351 <0x55114 0x4>; 1352 reg-names = "rev", "sysc", "syss"; 1353 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1354 SYSC_OMAP2_SOFTRESET | 1355 SYSC_OMAP2_AUTOIDLE)>; 1356 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1357 <SYSC_IDLE_NO>, 1358 <SYSC_IDLE_SMART>, 1359 <SYSC_IDLE_SMART_WKUP>; 1360 ti,syss-mask = <1>; 1361 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1362 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>, 1363 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>; 1364 clock-names = "fck", "dbclk"; 1365 #address-cells = <1>; 1366 #size-cells = <1>; 1367 ranges = <0x0 0x55000 0x1000>; 1368 1369 gpio2: gpio@0 { 1370 compatible = "ti,omap4-gpio"; 1371 reg = <0x0 0x200>; 1372 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1373 gpio-controller; 1374 #gpio-cells = <2>; 1375 interrupt-controller; 1376 #interrupt-cells = <2>; 1377 }; 1378 }; 1379 1380 gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */ 1381 compatible = "ti,sysc-omap2", "ti,sysc"; 1382 reg = <0x57000 0x4>, 1383 <0x57010 0x4>, 1384 <0x57114 0x4>; 1385 reg-names = "rev", "sysc", "syss"; 1386 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1387 SYSC_OMAP2_SOFTRESET | 1388 SYSC_OMAP2_AUTOIDLE)>; 1389 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1390 <SYSC_IDLE_NO>, 1391 <SYSC_IDLE_SMART>, 1392 <SYSC_IDLE_SMART_WKUP>; 1393 ti,syss-mask = <1>; 1394 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1395 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>, 1396 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>; 1397 clock-names = "fck", "dbclk"; 1398 #address-cells = <1>; 1399 #size-cells = <1>; 1400 ranges = <0x0 0x57000 0x1000>; 1401 1402 gpio3: gpio@0 { 1403 compatible = "ti,omap4-gpio"; 1404 reg = <0x0 0x200>; 1405 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1406 gpio-controller; 1407 #gpio-cells = <2>; 1408 interrupt-controller; 1409 #interrupt-cells = <2>; 1410 }; 1411 }; 1412 1413 target-module@59000 { /* 0x48059000, ap 17 16.0 */ 1414 compatible = "ti,sysc-omap2", "ti,sysc"; 1415 reg = <0x59000 0x4>, 1416 <0x59010 0x4>, 1417 <0x59114 0x4>; 1418 reg-names = "rev", "sysc", "syss"; 1419 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1420 SYSC_OMAP2_SOFTRESET | 1421 SYSC_OMAP2_AUTOIDLE)>; 1422 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1423 <SYSC_IDLE_NO>, 1424 <SYSC_IDLE_SMART>, 1425 <SYSC_IDLE_SMART_WKUP>; 1426 ti,syss-mask = <1>; 1427 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1428 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>, 1429 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>; 1430 clock-names = "fck", "dbclk"; 1431 #address-cells = <1>; 1432 #size-cells = <1>; 1433 ranges = <0x0 0x59000 0x1000>; 1434 1435 gpio4: gpio@0 { 1436 compatible = "ti,omap4-gpio"; 1437 reg = <0x0 0x200>; 1438 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1439 gpio-controller; 1440 #gpio-cells = <2>; 1441 interrupt-controller; 1442 #interrupt-cells = <2>; 1443 }; 1444 }; 1445 1446 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */ 1447 compatible = "ti,sysc-omap2", "ti,sysc"; 1448 reg = <0x5b000 0x4>, 1449 <0x5b010 0x4>, 1450 <0x5b114 0x4>; 1451 reg-names = "rev", "sysc", "syss"; 1452 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1453 SYSC_OMAP2_SOFTRESET | 1454 SYSC_OMAP2_AUTOIDLE)>; 1455 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1456 <SYSC_IDLE_NO>, 1457 <SYSC_IDLE_SMART>, 1458 <SYSC_IDLE_SMART_WKUP>; 1459 ti,syss-mask = <1>; 1460 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1461 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>, 1462 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>; 1463 clock-names = "fck", "dbclk"; 1464 #address-cells = <1>; 1465 #size-cells = <1>; 1466 ranges = <0x0 0x5b000 0x1000>; 1467 1468 gpio5: gpio@0 { 1469 compatible = "ti,omap4-gpio"; 1470 reg = <0x0 0x200>; 1471 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1472 gpio-controller; 1473 #gpio-cells = <2>; 1474 interrupt-controller; 1475 #interrupt-cells = <2>; 1476 }; 1477 }; 1478 1479 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */ 1480 compatible = "ti,sysc-omap2", "ti,sysc"; 1481 reg = <0x5d000 0x4>, 1482 <0x5d010 0x4>, 1483 <0x5d114 0x4>; 1484 reg-names = "rev", "sysc", "syss"; 1485 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1486 SYSC_OMAP2_SOFTRESET | 1487 SYSC_OMAP2_AUTOIDLE)>; 1488 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1489 <SYSC_IDLE_NO>, 1490 <SYSC_IDLE_SMART>, 1491 <SYSC_IDLE_SMART_WKUP>; 1492 ti,syss-mask = <1>; 1493 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1494 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>, 1495 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>; 1496 clock-names = "fck", "dbclk"; 1497 #address-cells = <1>; 1498 #size-cells = <1>; 1499 ranges = <0x0 0x5d000 0x1000>; 1500 1501 gpio6: gpio@0 { 1502 compatible = "ti,omap4-gpio"; 1503 reg = <0x0 0x200>; 1504 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1505 gpio-controller; 1506 #gpio-cells = <2>; 1507 interrupt-controller; 1508 #interrupt-cells = <2>; 1509 }; 1510 }; 1511 1512 target-module@60000 { /* 0x48060000, ap 23 32.0 */ 1513 compatible = "ti,sysc-omap2", "ti,sysc"; 1514 reg = <0x60000 0x8>, 1515 <0x60010 0x8>, 1516 <0x60090 0x8>; 1517 reg-names = "rev", "sysc", "syss"; 1518 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1519 SYSC_OMAP2_ENAWAKEUP | 1520 SYSC_OMAP2_SOFTRESET | 1521 SYSC_OMAP2_AUTOIDLE)>; 1522 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1523 <SYSC_IDLE_NO>, 1524 <SYSC_IDLE_SMART>, 1525 <SYSC_IDLE_SMART_WKUP>; 1526 ti,syss-mask = <1>; 1527 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1528 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>; 1529 clock-names = "fck"; 1530 #address-cells = <1>; 1531 #size-cells = <1>; 1532 ranges = <0x0 0x60000 0x1000>; 1533 1534 i2c3: i2c@0 { 1535 compatible = "ti,omap4-i2c"; 1536 reg = <0x0 0x100>; 1537 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 status = "disabled"; 1541 }; 1542 }; 1543 1544 target-module@66000 { /* 0x48066000, ap 63 14.0 */ 1545 compatible = "ti,sysc-omap2", "ti,sysc"; 1546 reg = <0x66050 0x4>, 1547 <0x66054 0x4>, 1548 <0x66058 0x4>; 1549 reg-names = "rev", "sysc", "syss"; 1550 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1551 SYSC_OMAP2_SOFTRESET | 1552 SYSC_OMAP2_AUTOIDLE)>; 1553 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1554 <SYSC_IDLE_NO>, 1555 <SYSC_IDLE_SMART>, 1556 <SYSC_IDLE_SMART_WKUP>; 1557 ti,syss-mask = <1>; 1558 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1559 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>; 1560 clock-names = "fck"; 1561 #address-cells = <1>; 1562 #size-cells = <1>; 1563 ranges = <0x0 0x66000 0x1000>; 1564 1565 uart5: serial@0 { 1566 compatible = "ti,dra742-uart"; 1567 reg = <0x0 0x100>; 1568 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1569 clock-frequency = <48000000>; 1570 status = "disabled"; 1571 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 1572 dma-names = "tx", "rx"; 1573 }; 1574 }; 1575 1576 target-module@68000 { /* 0x48068000, ap 53 1c.0 */ 1577 compatible = "ti,sysc-omap2", "ti,sysc"; 1578 reg = <0x68050 0x4>, 1579 <0x68054 0x4>, 1580 <0x68058 0x4>; 1581 reg-names = "rev", "sysc", "syss"; 1582 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1583 SYSC_OMAP2_SOFTRESET | 1584 SYSC_OMAP2_AUTOIDLE)>; 1585 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1586 <SYSC_IDLE_NO>, 1587 <SYSC_IDLE_SMART>, 1588 <SYSC_IDLE_SMART_WKUP>; 1589 ti,syss-mask = <1>; 1590 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 1591 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>; 1592 clock-names = "fck"; 1593 #address-cells = <1>; 1594 #size-cells = <1>; 1595 ranges = <0x0 0x68000 0x1000>; 1596 1597 uart6: serial@0 { 1598 compatible = "ti,dra742-uart"; 1599 reg = <0x0 0x100>; 1600 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1601 clock-frequency = <48000000>; 1602 status = "disabled"; 1603 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 1604 dma-names = "tx", "rx"; 1605 }; 1606 }; 1607 1608 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */ 1609 compatible = "ti,sysc-omap2", "ti,sysc"; 1610 reg = <0x6a050 0x4>, 1611 <0x6a054 0x4>, 1612 <0x6a058 0x4>; 1613 reg-names = "rev", "sysc", "syss"; 1614 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1615 SYSC_OMAP2_SOFTRESET | 1616 SYSC_OMAP2_AUTOIDLE)>; 1617 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1618 <SYSC_IDLE_NO>, 1619 <SYSC_IDLE_SMART>, 1620 <SYSC_IDLE_SMART_WKUP>; 1621 ti,syss-mask = <1>; 1622 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1623 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>; 1624 clock-names = "fck"; 1625 #address-cells = <1>; 1626 #size-cells = <1>; 1627 ranges = <0x0 0x6a000 0x1000>; 1628 1629 uart1: serial@0 { 1630 compatible = "ti,dra742-uart"; 1631 reg = <0x0 0x100>; 1632 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1633 clock-frequency = <48000000>; 1634 status = "disabled"; 1635 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 1636 dma-names = "tx", "rx"; 1637 }; 1638 }; 1639 1640 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */ 1641 compatible = "ti,sysc-omap2", "ti,sysc"; 1642 reg = <0x6c050 0x4>, 1643 <0x6c054 0x4>, 1644 <0x6c058 0x4>; 1645 reg-names = "rev", "sysc", "syss"; 1646 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1647 SYSC_OMAP2_SOFTRESET | 1648 SYSC_OMAP2_AUTOIDLE)>; 1649 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1650 <SYSC_IDLE_NO>, 1651 <SYSC_IDLE_SMART>, 1652 <SYSC_IDLE_SMART_WKUP>; 1653 ti,syss-mask = <1>; 1654 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1655 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>; 1656 clock-names = "fck"; 1657 #address-cells = <1>; 1658 #size-cells = <1>; 1659 ranges = <0x0 0x6c000 0x1000>; 1660 1661 uart2: serial@0 { 1662 compatible = "ti,dra742-uart"; 1663 reg = <0x0 0x100>; 1664 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1665 clock-frequency = <48000000>; 1666 status = "disabled"; 1667 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 1668 dma-names = "tx", "rx"; 1669 }; 1670 }; 1671 1672 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */ 1673 compatible = "ti,sysc-omap2", "ti,sysc"; 1674 reg = <0x6e050 0x4>, 1675 <0x6e054 0x4>, 1676 <0x6e058 0x4>; 1677 reg-names = "rev", "sysc", "syss"; 1678 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 1679 SYSC_OMAP2_SOFTRESET | 1680 SYSC_OMAP2_AUTOIDLE)>; 1681 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1682 <SYSC_IDLE_NO>, 1683 <SYSC_IDLE_SMART>, 1684 <SYSC_IDLE_SMART_WKUP>; 1685 ti,syss-mask = <1>; 1686 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1687 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>; 1688 clock-names = "fck"; 1689 #address-cells = <1>; 1690 #size-cells = <1>; 1691 ranges = <0x0 0x6e000 0x1000>; 1692 1693 uart4: serial@0 { 1694 compatible = "ti,dra742-uart"; 1695 reg = <0x0 0x100>; 1696 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1697 clock-frequency = <48000000>; 1698 status = "disabled"; 1699 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 1700 dma-names = "tx", "rx"; 1701 }; 1702 }; 1703 1704 target-module@70000 { /* 0x48070000, ap 30 22.0 */ 1705 compatible = "ti,sysc-omap2", "ti,sysc"; 1706 reg = <0x70000 0x8>, 1707 <0x70010 0x8>, 1708 <0x70090 0x8>; 1709 reg-names = "rev", "sysc", "syss"; 1710 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1711 SYSC_OMAP2_ENAWAKEUP | 1712 SYSC_OMAP2_SOFTRESET | 1713 SYSC_OMAP2_AUTOIDLE)>; 1714 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1715 <SYSC_IDLE_NO>, 1716 <SYSC_IDLE_SMART>, 1717 <SYSC_IDLE_SMART_WKUP>; 1718 ti,syss-mask = <1>; 1719 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1720 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>; 1721 clock-names = "fck"; 1722 #address-cells = <1>; 1723 #size-cells = <1>; 1724 ranges = <0x0 0x70000 0x1000>; 1725 1726 i2c1: i2c@0 { 1727 compatible = "ti,omap4-i2c"; 1728 reg = <0x0 0x100>; 1729 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 status = "disabled"; 1733 }; 1734 }; 1735 1736 target-module@72000 { /* 0x48072000, ap 32 2a.0 */ 1737 compatible = "ti,sysc-omap2", "ti,sysc"; 1738 reg = <0x72000 0x8>, 1739 <0x72010 0x8>, 1740 <0x72090 0x8>; 1741 reg-names = "rev", "sysc", "syss"; 1742 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1743 SYSC_OMAP2_ENAWAKEUP | 1744 SYSC_OMAP2_SOFTRESET | 1745 SYSC_OMAP2_AUTOIDLE)>; 1746 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1747 <SYSC_IDLE_NO>, 1748 <SYSC_IDLE_SMART>, 1749 <SYSC_IDLE_SMART_WKUP>; 1750 ti,syss-mask = <1>; 1751 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1752 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>; 1753 clock-names = "fck"; 1754 #address-cells = <1>; 1755 #size-cells = <1>; 1756 ranges = <0x0 0x72000 0x1000>; 1757 1758 i2c2: i2c@0 { 1759 compatible = "ti,omap4-i2c"; 1760 reg = <0x0 0x100>; 1761 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 status = "disabled"; 1765 }; 1766 }; 1767 1768 target-module@78000 { /* 0x48078000, ap 39 0a.0 */ 1769 compatible = "ti,sysc-omap2", "ti,sysc"; 1770 reg = <0x78000 0x4>, 1771 <0x78010 0x4>, 1772 <0x78014 0x4>; 1773 reg-names = "rev", "sysc", "syss"; 1774 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1775 SYSC_OMAP2_SOFTRESET | 1776 SYSC_OMAP2_AUTOIDLE)>; 1777 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1778 <SYSC_IDLE_NO>, 1779 <SYSC_IDLE_SMART>, 1780 <SYSC_IDLE_SMART_WKUP>; 1781 ti,syss-mask = <1>; 1782 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1783 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>; 1784 clock-names = "fck"; 1785 #address-cells = <1>; 1786 #size-cells = <1>; 1787 ranges = <0x0 0x78000 0x1000>; 1788 1789 elm: elm@0 { 1790 compatible = "ti,am3352-elm"; 1791 reg = <0x0 0xfc0>; /* device IO registers */ 1792 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1793 status = "disabled"; 1794 }; 1795 }; 1796 1797 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */ 1798 compatible = "ti,sysc-omap2", "ti,sysc"; 1799 reg = <0x7a000 0x8>, 1800 <0x7a010 0x8>, 1801 <0x7a090 0x8>; 1802 reg-names = "rev", "sysc", "syss"; 1803 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1804 SYSC_OMAP2_ENAWAKEUP | 1805 SYSC_OMAP2_SOFTRESET | 1806 SYSC_OMAP2_AUTOIDLE)>; 1807 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1808 <SYSC_IDLE_NO>, 1809 <SYSC_IDLE_SMART>, 1810 <SYSC_IDLE_SMART_WKUP>; 1811 ti,syss-mask = <1>; 1812 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1813 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>; 1814 clock-names = "fck"; 1815 #address-cells = <1>; 1816 #size-cells = <1>; 1817 ranges = <0x0 0x7a000 0x1000>; 1818 1819 i2c4: i2c@0 { 1820 compatible = "ti,omap4-i2c"; 1821 reg = <0x0 0x100>; 1822 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 status = "disabled"; 1826 }; 1827 }; 1828 1829 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */ 1830 compatible = "ti,sysc-omap2", "ti,sysc"; 1831 reg = <0x7c000 0x8>, 1832 <0x7c010 0x8>, 1833 <0x7c090 0x8>; 1834 reg-names = "rev", "sysc", "syss"; 1835 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 1836 SYSC_OMAP2_ENAWAKEUP | 1837 SYSC_OMAP2_SOFTRESET | 1838 SYSC_OMAP2_AUTOIDLE)>; 1839 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1840 <SYSC_IDLE_NO>, 1841 <SYSC_IDLE_SMART>, 1842 <SYSC_IDLE_SMART_WKUP>; 1843 ti,syss-mask = <1>; 1844 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 1845 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>; 1846 clock-names = "fck"; 1847 #address-cells = <1>; 1848 #size-cells = <1>; 1849 ranges = <0x0 0x7c000 0x1000>; 1850 1851 i2c5: i2c@0 { 1852 compatible = "ti,omap4-i2c"; 1853 reg = <0x0 0x100>; 1854 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 status = "disabled"; 1858 }; 1859 }; 1860 1861 target-module@86000 { /* 0x48086000, ap 41 5e.0 */ 1862 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1863 reg = <0x86000 0x4>, 1864 <0x86010 0x4>; 1865 reg-names = "rev", "sysc"; 1866 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1867 SYSC_OMAP4_SOFTRESET)>; 1868 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1869 <SYSC_IDLE_NO>, 1870 <SYSC_IDLE_SMART>, 1871 <SYSC_IDLE_SMART_WKUP>; 1872 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1873 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>; 1874 clock-names = "fck"; 1875 #address-cells = <1>; 1876 #size-cells = <1>; 1877 ranges = <0x0 0x86000 0x1000>; 1878 1879 timer10: timer@0 { 1880 compatible = "ti,omap5430-timer"; 1881 reg = <0x0 0x80>; 1882 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>; 1883 clock-names = "fck", "timer_sys_ck"; 1884 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1885 }; 1886 }; 1887 1888 target-module@88000 { /* 0x48088000, ap 43 66.0 */ 1889 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 1890 reg = <0x88000 0x4>, 1891 <0x88010 0x4>; 1892 reg-names = "rev", "sysc"; 1893 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1894 SYSC_OMAP4_SOFTRESET)>; 1895 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1896 <SYSC_IDLE_NO>, 1897 <SYSC_IDLE_SMART>, 1898 <SYSC_IDLE_SMART_WKUP>; 1899 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1900 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>; 1901 clock-names = "fck"; 1902 #address-cells = <1>; 1903 #size-cells = <1>; 1904 ranges = <0x0 0x88000 0x1000>; 1905 1906 timer11: timer@0 { 1907 compatible = "ti,omap5430-timer"; 1908 reg = <0x0 0x80>; 1909 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>; 1910 clock-names = "fck", "timer_sys_ck"; 1911 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1912 }; 1913 }; 1914 1915 target-module@90000 { /* 0x48090000, ap 55 12.0 */ 1916 compatible = "ti,sysc-omap2", "ti,sysc"; 1917 reg = <0x91fe0 0x4>, 1918 <0x91fe4 0x4>; 1919 reg-names = "rev", "sysc"; 1920 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>; 1921 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1922 <SYSC_IDLE_NO>; 1923 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 1924 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>; 1925 clock-names = "fck"; 1926 #address-cells = <1>; 1927 #size-cells = <1>; 1928 ranges = <0x0 0x90000 0x2000>; 1929 1930 rng: rng@0 { 1931 compatible = "ti,omap4-rng"; 1932 reg = <0x0 0x2000>; 1933 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1934 clocks = <&l3_iclk_div>; 1935 clock-names = "fck"; 1936 }; 1937 }; 1938 1939 target-module@98000 { /* 0x48098000, ap 47 08.0 */ 1940 compatible = "ti,sysc-omap4", "ti,sysc"; 1941 reg = <0x98000 0x4>, 1942 <0x98010 0x4>; 1943 reg-names = "rev", "sysc"; 1944 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1945 SYSC_OMAP4_SOFTRESET)>; 1946 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1947 <SYSC_IDLE_NO>, 1948 <SYSC_IDLE_SMART>, 1949 <SYSC_IDLE_SMART_WKUP>; 1950 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1951 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>; 1952 clock-names = "fck"; 1953 #address-cells = <1>; 1954 #size-cells = <1>; 1955 ranges = <0x0 0x98000 0x1000>; 1956 1957 mcspi1: spi@0 { 1958 compatible = "ti,omap4-mcspi"; 1959 reg = <0x0 0x200>; 1960 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1961 #address-cells = <1>; 1962 #size-cells = <0>; 1963 ti,spi-num-cs = <4>; 1964 dmas = <&sdma_xbar 35>, 1965 <&sdma_xbar 36>, 1966 <&sdma_xbar 37>, 1967 <&sdma_xbar 38>, 1968 <&sdma_xbar 39>, 1969 <&sdma_xbar 40>, 1970 <&sdma_xbar 41>, 1971 <&sdma_xbar 42>; 1972 dma-names = "tx0", "rx0", "tx1", "rx1", 1973 "tx2", "rx2", "tx3", "rx3"; 1974 status = "disabled"; 1975 }; 1976 }; 1977 1978 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */ 1979 compatible = "ti,sysc-omap4", "ti,sysc"; 1980 reg = <0x9a000 0x4>, 1981 <0x9a010 0x4>; 1982 reg-names = "rev", "sysc"; 1983 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 1984 SYSC_OMAP4_SOFTRESET)>; 1985 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1986 <SYSC_IDLE_NO>, 1987 <SYSC_IDLE_SMART>, 1988 <SYSC_IDLE_SMART_WKUP>; 1989 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 1990 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>; 1991 clock-names = "fck"; 1992 #address-cells = <1>; 1993 #size-cells = <1>; 1994 ranges = <0x0 0x9a000 0x1000>; 1995 1996 mcspi2: spi@0 { 1997 compatible = "ti,omap4-mcspi"; 1998 reg = <0x0 0x200>; 1999 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 ti,spi-num-cs = <2>; 2003 dmas = <&sdma_xbar 43>, 2004 <&sdma_xbar 44>, 2005 <&sdma_xbar 45>, 2006 <&sdma_xbar 46>; 2007 dma-names = "tx0", "rx0", "tx1", "rx1"; 2008 status = "disabled"; 2009 }; 2010 }; 2011 2012 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */ 2013 compatible = "ti,sysc-omap4", "ti,sysc"; 2014 reg = <0x9c000 0x4>, 2015 <0x9c010 0x4>; 2016 reg-names = "rev", "sysc"; 2017 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2018 SYSC_OMAP4_SOFTRESET)>; 2019 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2020 <SYSC_IDLE_NO>, 2021 <SYSC_IDLE_SMART>, 2022 <SYSC_IDLE_SMART_WKUP>; 2023 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2024 <SYSC_IDLE_NO>, 2025 <SYSC_IDLE_SMART>, 2026 <SYSC_IDLE_SMART_WKUP>; 2027 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 2028 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>; 2029 clock-names = "fck"; 2030 #address-cells = <1>; 2031 #size-cells = <1>; 2032 ranges = <0x0 0x9c000 0x1000>; 2033 2034 mmc1: mmc@0 { 2035 compatible = "ti,dra7-sdhci"; 2036 reg = <0x0 0x400>; 2037 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2038 status = "disabled"; 2039 pbias-supply = <&pbias_mmc_reg>; 2040 max-frequency = <192000000>; 2041 mmc-ddr-1_8v; 2042 mmc-ddr-3_3v; 2043 }; 2044 }; 2045 2046 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */ 2047 compatible = "ti,sysc"; 2048 status = "disabled"; 2049 #address-cells = <1>; 2050 #size-cells = <1>; 2051 ranges = <0x0 0xa2000 0x1000>; 2052 }; 2053 2054 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */ 2055 compatible = "ti,sysc"; 2056 status = "disabled"; 2057 #address-cells = <1>; 2058 #size-cells = <1>; 2059 ranges = <0x00000000 0x000a4000 0x00001000>, 2060 <0x00001000 0x000a5000 0x00001000>; 2061 }; 2062 2063 des_target: target-module@a5000 { /* 0x480a5000 */ 2064 compatible = "ti,sysc-omap2", "ti,sysc"; 2065 reg = <0xa5030 0x4>, 2066 <0xa5034 0x4>, 2067 <0xa5038 0x4>; 2068 reg-names = "rev", "sysc", "syss"; 2069 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2070 SYSC_OMAP2_AUTOIDLE)>; 2071 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2072 <SYSC_IDLE_NO>, 2073 <SYSC_IDLE_SMART>, 2074 <SYSC_IDLE_SMART_WKUP>; 2075 ti,syss-mask = <1>; 2076 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ 2077 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>; 2078 clock-names = "fck"; 2079 #address-cells = <1>; 2080 #size-cells = <1>; 2081 ranges = <0 0xa5000 0x00001000>; 2082 2083 des: des@0 { 2084 compatible = "ti,omap4-des"; 2085 reg = <0 0xa0>; 2086 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 2087 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; 2088 dma-names = "tx", "rx"; 2089 clocks = <&l3_iclk_div>; 2090 clock-names = "fck"; 2091 }; 2092 }; 2093 2094 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */ 2095 compatible = "ti,sysc"; 2096 status = "disabled"; 2097 #address-cells = <1>; 2098 #size-cells = <1>; 2099 ranges = <0x0 0xa8000 0x4000>; 2100 }; 2101 2102 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */ 2103 compatible = "ti,sysc-omap4", "ti,sysc"; 2104 reg = <0xad000 0x4>, 2105 <0xad010 0x4>; 2106 reg-names = "rev", "sysc"; 2107 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2108 SYSC_OMAP4_SOFTRESET)>; 2109 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2110 <SYSC_IDLE_NO>, 2111 <SYSC_IDLE_SMART>, 2112 <SYSC_IDLE_SMART_WKUP>; 2113 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2114 <SYSC_IDLE_NO>, 2115 <SYSC_IDLE_SMART>, 2116 <SYSC_IDLE_SMART_WKUP>; 2117 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2118 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>; 2119 clock-names = "fck"; 2120 #address-cells = <1>; 2121 #size-cells = <1>; 2122 ranges = <0x0 0xad000 0x1000>; 2123 2124 mmc3: mmc@0 { 2125 compatible = "ti,dra7-sdhci"; 2126 reg = <0x0 0x400>; 2127 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 2128 status = "disabled"; 2129 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ 2130 max-frequency = <64000000>; 2131 /* SDMA is not supported */ 2132 sdhci-caps-mask = <0x0 0x400000>; 2133 }; 2134 }; 2135 2136 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */ 2137 compatible = "ti,sysc-omap2", "ti,sysc"; 2138 reg = <0xb2000 0x4>, 2139 <0xb2014 0x4>, 2140 <0xb2018 0x4>; 2141 reg-names = "rev", "sysc", "syss"; 2142 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 2143 SYSC_OMAP2_AUTOIDLE)>; 2144 ti,syss-mask = <1>; 2145 ti,no-reset-on-init; 2146 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2147 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>; 2148 clock-names = "fck"; 2149 #address-cells = <1>; 2150 #size-cells = <1>; 2151 ranges = <0x0 0xb2000 0x1000>; 2152 2153 hdqw1w: 1w@0 { 2154 compatible = "ti,omap3-1w"; 2155 reg = <0x0 0x1000>; 2156 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2157 }; 2158 }; 2159 2160 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */ 2161 compatible = "ti,sysc-omap4", "ti,sysc"; 2162 reg = <0xb4000 0x4>, 2163 <0xb4010 0x4>; 2164 reg-names = "rev", "sysc"; 2165 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2166 SYSC_OMAP4_SOFTRESET)>; 2167 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2168 <SYSC_IDLE_NO>, 2169 <SYSC_IDLE_SMART>, 2170 <SYSC_IDLE_SMART_WKUP>; 2171 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2172 <SYSC_IDLE_NO>, 2173 <SYSC_IDLE_SMART>, 2174 <SYSC_IDLE_SMART_WKUP>; 2175 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 2176 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>; 2177 clock-names = "fck"; 2178 #address-cells = <1>; 2179 #size-cells = <1>; 2180 ranges = <0x0 0xb4000 0x1000>; 2181 2182 mmc2: mmc@0 { 2183 compatible = "ti,dra7-sdhci"; 2184 reg = <0x0 0x400>; 2185 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2186 status = "disabled"; 2187 max-frequency = <192000000>; 2188 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ 2189 sdhci-caps-mask = <0x7 0x0>; 2190 mmc-hs200-1_8v; 2191 mmc-ddr-1_8v; 2192 mmc-ddr-3_3v; 2193 }; 2194 }; 2195 2196 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */ 2197 compatible = "ti,sysc-omap4", "ti,sysc"; 2198 reg = <0xb8000 0x4>, 2199 <0xb8010 0x4>; 2200 reg-names = "rev", "sysc"; 2201 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2202 SYSC_OMAP4_SOFTRESET)>; 2203 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2204 <SYSC_IDLE_NO>, 2205 <SYSC_IDLE_SMART>, 2206 <SYSC_IDLE_SMART_WKUP>; 2207 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2208 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>; 2209 clock-names = "fck"; 2210 #address-cells = <1>; 2211 #size-cells = <1>; 2212 ranges = <0x0 0xb8000 0x1000>; 2213 2214 mcspi3: spi@0 { 2215 compatible = "ti,omap4-mcspi"; 2216 reg = <0x0 0x200>; 2217 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 ti,spi-num-cs = <2>; 2221 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 2222 dma-names = "tx0", "rx0"; 2223 status = "disabled"; 2224 }; 2225 }; 2226 2227 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */ 2228 compatible = "ti,sysc-omap4", "ti,sysc"; 2229 reg = <0xba000 0x4>, 2230 <0xba010 0x4>; 2231 reg-names = "rev", "sysc"; 2232 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2233 SYSC_OMAP4_SOFTRESET)>; 2234 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2235 <SYSC_IDLE_NO>, 2236 <SYSC_IDLE_SMART>, 2237 <SYSC_IDLE_SMART_WKUP>; 2238 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2239 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>; 2240 clock-names = "fck"; 2241 #address-cells = <1>; 2242 #size-cells = <1>; 2243 ranges = <0x0 0xba000 0x1000>; 2244 2245 mcspi4: spi@0 { 2246 compatible = "ti,omap4-mcspi"; 2247 reg = <0x0 0x200>; 2248 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 2249 #address-cells = <1>; 2250 #size-cells = <0>; 2251 ti,spi-num-cs = <1>; 2252 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 2253 dma-names = "tx0", "rx0"; 2254 status = "disabled"; 2255 }; 2256 }; 2257 2258 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */ 2259 compatible = "ti,sysc-omap4", "ti,sysc"; 2260 reg = <0xd1000 0x4>, 2261 <0xd1010 0x4>; 2262 reg-names = "rev", "sysc"; 2263 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 2264 SYSC_OMAP4_SOFTRESET)>; 2265 ti,sysc-midle = <SYSC_IDLE_FORCE>, 2266 <SYSC_IDLE_NO>, 2267 <SYSC_IDLE_SMART>, 2268 <SYSC_IDLE_SMART_WKUP>; 2269 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2270 <SYSC_IDLE_NO>, 2271 <SYSC_IDLE_SMART>, 2272 <SYSC_IDLE_SMART_WKUP>; 2273 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */ 2274 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>; 2275 clock-names = "fck"; 2276 #address-cells = <1>; 2277 #size-cells = <1>; 2278 ranges = <0x0 0xd1000 0x1000>; 2279 2280 mmc4: mmc@0 { 2281 compatible = "ti,dra7-sdhci"; 2282 reg = <0x0 0x400>; 2283 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2284 status = "disabled"; 2285 max-frequency = <192000000>; 2286 /* SDMA is not supported */ 2287 sdhci-caps-mask = <0x0 0x400000>; 2288 }; 2289 }; 2290 2291 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ 2292 compatible = "ti,sysc"; 2293 status = "disabled"; 2294 #address-cells = <1>; 2295 #size-cells = <1>; 2296 ranges = <0x0 0xd5000 0x1000>; 2297 }; 2298 }; 2299 2300 segment@200000 { /* 0x48200000 */ 2301 compatible = "simple-pm-bus"; 2302 #address-cells = <1>; 2303 #size-cells = <1>; 2304 }; 2305}; 2306 2307&l4_per2 { /* 0x48400000 */ 2308 compatible = "ti,dra7-l4-per2", "simple-pm-bus"; 2309 power-domains = <&prm_l4per>; 2310 clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>; 2311 clock-names = "fck"; 2312 reg = <0x48400000 0x800>, 2313 <0x48400800 0x800>, 2314 <0x48401000 0x400>, 2315 <0x48401400 0x400>, 2316 <0x48401800 0x400>; 2317 reg-names = "ap", "la", "ia0", "ia1", "ia2"; 2318 #address-cells = <1>; 2319 #size-cells = <1>; 2320 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */ 2321 <0x45800000 0x45800000 0x400000>, /* L3 data port */ 2322 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ 2323 <0x46000000 0x46000000 0x400000>, /* L3 data port */ 2324 <0x48436000 0x48436000 0x400000>, /* L3 data port */ 2325 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ 2326 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ 2327 <0x48450000 0x48450000 0x400000>, /* L3 data port */ 2328 <0x48454000 0x48454000 0x400000>; /* L3 data port */ 2329 2330 segment@0 { /* 0x48400000 */ 2331 compatible = "simple-pm-bus"; 2332 #address-cells = <1>; 2333 #size-cells = <1>; 2334 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 2335 <0x00001000 0x00001000 0x000400>, /* ap 1 */ 2336 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 2337 <0x00084000 0x00084000 0x004000>, /* ap 3 */ 2338 <0x00001400 0x00001400 0x000400>, /* ap 4 */ 2339 <0x00001800 0x00001800 0x000400>, /* ap 5 */ 2340 <0x00088000 0x00088000 0x001000>, /* ap 6 */ 2341 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */ 2342 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */ 2343 <0x00060000 0x00060000 0x002000>, /* ap 9 */ 2344 <0x00062000 0x00062000 0x001000>, /* ap 10 */ 2345 <0x00064000 0x00064000 0x002000>, /* ap 11 */ 2346 <0x00066000 0x00066000 0x001000>, /* ap 12 */ 2347 <0x00068000 0x00068000 0x002000>, /* ap 13 */ 2348 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */ 2349 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */ 2350 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */ 2351 <0x00036000 0x00036000 0x001000>, /* ap 17 */ 2352 <0x00037000 0x00037000 0x001000>, /* ap 18 */ 2353 <0x00070000 0x00070000 0x002000>, /* ap 19 */ 2354 <0x00072000 0x00072000 0x001000>, /* ap 20 */ 2355 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */ 2356 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */ 2357 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */ 2358 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */ 2359 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */ 2360 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */ 2361 <0x00040000 0x00040000 0x001000>, /* ap 27 */ 2362 <0x00041000 0x00041000 0x001000>, /* ap 28 */ 2363 <0x00042000 0x00042000 0x001000>, /* ap 29 */ 2364 <0x00043000 0x00043000 0x001000>, /* ap 30 */ 2365 <0x00080000 0x00080000 0x002000>, /* ap 31 */ 2366 <0x00082000 0x00082000 0x001000>, /* ap 32 */ 2367 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */ 2368 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */ 2369 <0x00074000 0x00074000 0x002000>, /* ap 35 */ 2370 <0x00076000 0x00076000 0x001000>, /* ap 36 */ 2371 <0x00050000 0x00050000 0x001000>, /* ap 37 */ 2372 <0x00051000 0x00051000 0x001000>, /* ap 38 */ 2373 <0x00078000 0x00078000 0x002000>, /* ap 39 */ 2374 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */ 2375 <0x00054000 0x00054000 0x001000>, /* ap 41 */ 2376 <0x00055000 0x00055000 0x001000>, /* ap 42 */ 2377 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */ 2378 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */ 2379 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */ 2380 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */ 2381 <0x00020000 0x00020000 0x001000>, /* ap 47 */ 2382 <0x00021000 0x00021000 0x001000>, /* ap 48 */ 2383 <0x00022000 0x00022000 0x001000>, /* ap 49 */ 2384 <0x00023000 0x00023000 0x001000>, /* ap 50 */ 2385 <0x00024000 0x00024000 0x001000>, /* ap 51 */ 2386 <0x00025000 0x00025000 0x001000>, /* ap 52 */ 2387 <0x00046000 0x00046000 0x001000>, /* ap 53 */ 2388 <0x00047000 0x00047000 0x001000>, /* ap 54 */ 2389 <0x00048000 0x00048000 0x001000>, /* ap 55 */ 2390 <0x00049000 0x00049000 0x001000>, /* ap 56 */ 2391 <0x00058000 0x00058000 0x002000>, /* ap 57 */ 2392 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */ 2393 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */ 2394 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */ 2395 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */ 2396 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */ 2397 <0x45800000 0x45800000 0x400000>, /* L3 data port */ 2398 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */ 2399 <0x46000000 0x46000000 0x400000>, /* L3 data port */ 2400 <0x48436000 0x48436000 0x400000>, /* L3 data port */ 2401 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */ 2402 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */ 2403 <0x48450000 0x48450000 0x400000>, /* L3 data port */ 2404 <0x48454000 0x48454000 0x400000>; /* L3 data port */ 2405 2406 target-module@20000 { /* 0x48420000, ap 47 02.0 */ 2407 compatible = "ti,sysc-omap2", "ti,sysc"; 2408 reg = <0x20050 0x4>, 2409 <0x20054 0x4>, 2410 <0x20058 0x4>; 2411 reg-names = "rev", "sysc", "syss"; 2412 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2413 SYSC_OMAP2_SOFTRESET | 2414 SYSC_OMAP2_AUTOIDLE)>; 2415 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2416 <SYSC_IDLE_NO>, 2417 <SYSC_IDLE_SMART>, 2418 <SYSC_IDLE_SMART_WKUP>; 2419 ti,syss-mask = <1>; 2420 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2421 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>; 2422 clock-names = "fck"; 2423 #address-cells = <1>; 2424 #size-cells = <1>; 2425 ranges = <0x0 0x20000 0x1000>; 2426 2427 uart7: serial@0 { 2428 compatible = "ti,dra742-uart"; 2429 reg = <0x0 0x100>; 2430 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 2431 clock-frequency = <48000000>; 2432 status = "disabled"; 2433 }; 2434 }; 2435 2436 target-module@22000 { /* 0x48422000, ap 49 0a.0 */ 2437 compatible = "ti,sysc-omap2", "ti,sysc"; 2438 reg = <0x22050 0x4>, 2439 <0x22054 0x4>, 2440 <0x22058 0x4>; 2441 reg-names = "rev", "sysc", "syss"; 2442 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2443 SYSC_OMAP2_SOFTRESET | 2444 SYSC_OMAP2_AUTOIDLE)>; 2445 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2446 <SYSC_IDLE_NO>, 2447 <SYSC_IDLE_SMART>, 2448 <SYSC_IDLE_SMART_WKUP>; 2449 ti,syss-mask = <1>; 2450 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2451 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>; 2452 clock-names = "fck"; 2453 #address-cells = <1>; 2454 #size-cells = <1>; 2455 ranges = <0x0 0x22000 0x1000>; 2456 2457 uart8: serial@0 { 2458 compatible = "ti,dra742-uart"; 2459 reg = <0x0 0x100>; 2460 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 2461 clock-frequency = <48000000>; 2462 status = "disabled"; 2463 }; 2464 }; 2465 2466 target-module@24000 { /* 0x48424000, ap 51 12.0 */ 2467 compatible = "ti,sysc-omap2", "ti,sysc"; 2468 reg = <0x24050 0x4>, 2469 <0x24054 0x4>, 2470 <0x24058 0x4>; 2471 reg-names = "rev", "sysc", "syss"; 2472 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 2473 SYSC_OMAP2_SOFTRESET | 2474 SYSC_OMAP2_AUTOIDLE)>; 2475 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2476 <SYSC_IDLE_NO>, 2477 <SYSC_IDLE_SMART>, 2478 <SYSC_IDLE_SMART_WKUP>; 2479 ti,syss-mask = <1>; 2480 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2481 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>; 2482 clock-names = "fck"; 2483 #address-cells = <1>; 2484 #size-cells = <1>; 2485 ranges = <0x0 0x24000 0x1000>; 2486 2487 uart9: serial@0 { 2488 compatible = "ti,dra742-uart"; 2489 reg = <0x0 0x100>; 2490 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 2491 clock-frequency = <48000000>; 2492 status = "disabled"; 2493 }; 2494 }; 2495 2496 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */ 2497 compatible = "ti,sysc"; 2498 status = "disabled"; 2499 #address-cells = <1>; 2500 #size-cells = <1>; 2501 ranges = <0x0 0x2c000 0x1000>; 2502 }; 2503 2504 target-module@36000 { /* 0x48436000, ap 17 06.0 */ 2505 compatible = "ti,sysc"; 2506 status = "disabled"; 2507 #address-cells = <1>; 2508 #size-cells = <1>; 2509 ranges = <0x0 0x36000 0x1000>; 2510 }; 2511 2512 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */ 2513 compatible = "ti,sysc"; 2514 status = "disabled"; 2515 #address-cells = <1>; 2516 #size-cells = <1>; 2517 ranges = <0x0 0x3a000 0x1000>; 2518 }; 2519 2520 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */ 2521 compatible = "ti,sysc-omap4", "ti,sysc"; 2522 reg = <0x3c000 0x4>; 2523 reg-names = "rev"; 2524 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>; 2525 clock-names = "fck"; 2526 #address-cells = <1>; 2527 #size-cells = <1>; 2528 ranges = <0x0 0x3c000 0x1000>; 2529 2530 atl: atl@0 { 2531 compatible = "ti,dra7-atl"; 2532 reg = <0x0 0x3ff>; 2533 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 2534 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 2535 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; 2536 clock-names = "fck"; 2537 status = "disabled"; 2538 }; 2539 }; 2540 2541 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */ 2542 compatible = "ti,sysc-omap4", "ti,sysc"; 2543 reg = <0x3e000 0x4>, 2544 <0x3e004 0x4>; 2545 reg-names = "rev", "sysc"; 2546 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2547 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2548 <SYSC_IDLE_NO>, 2549 <SYSC_IDLE_SMART>; 2550 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2551 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>; 2552 clock-names = "fck"; 2553 #address-cells = <1>; 2554 #size-cells = <1>; 2555 ranges = <0x0 0x3e000 0x1000>; 2556 2557 epwmss0: epwmss@0 { 2558 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2559 reg = <0x0 0x30>; 2560 #address-cells = <1>; 2561 #size-cells = <1>; 2562 status = "disabled"; 2563 ranges = <0 0 0x1000>; 2564 2565 ecap0: pwm@100 { 2566 compatible = "ti,dra746-ecap", 2567 "ti,am3352-ecap"; 2568 #pwm-cells = <3>; 2569 reg = <0x100 0x80>; 2570 clocks = <&l4_root_clk_div>; 2571 clock-names = "fck"; 2572 status = "disabled"; 2573 }; 2574 2575 ehrpwm0: pwm@200 { 2576 compatible = "ti,dra746-ehrpwm", 2577 "ti,am3352-ehrpwm"; 2578 #pwm-cells = <3>; 2579 reg = <0x200 0x80>; 2580 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 2581 clock-names = "tbclk", "fck"; 2582 status = "disabled"; 2583 }; 2584 }; 2585 }; 2586 2587 target-module@40000 { /* 0x48440000, ap 27 38.0 */ 2588 compatible = "ti,sysc-omap4", "ti,sysc"; 2589 reg = <0x40000 0x4>, 2590 <0x40004 0x4>; 2591 reg-names = "rev", "sysc"; 2592 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2593 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2594 <SYSC_IDLE_NO>, 2595 <SYSC_IDLE_SMART>; 2596 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2597 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>; 2598 clock-names = "fck"; 2599 #address-cells = <1>; 2600 #size-cells = <1>; 2601 ranges = <0x0 0x40000 0x1000>; 2602 2603 epwmss1: epwmss@0 { 2604 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2605 reg = <0x0 0x30>; 2606 #address-cells = <1>; 2607 #size-cells = <1>; 2608 status = "disabled"; 2609 ranges = <0 0 0x1000>; 2610 2611 ecap1: pwm@100 { 2612 compatible = "ti,dra746-ecap", 2613 "ti,am3352-ecap"; 2614 #pwm-cells = <3>; 2615 reg = <0x100 0x80>; 2616 clocks = <&l4_root_clk_div>; 2617 clock-names = "fck"; 2618 status = "disabled"; 2619 }; 2620 2621 ehrpwm1: pwm@200 { 2622 compatible = "ti,dra746-ehrpwm", 2623 "ti,am3352-ehrpwm"; 2624 #pwm-cells = <3>; 2625 reg = <0x200 0x80>; 2626 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 2627 clock-names = "tbclk", "fck"; 2628 status = "disabled"; 2629 }; 2630 }; 2631 }; 2632 2633 target-module@42000 { /* 0x48442000, ap 29 20.0 */ 2634 compatible = "ti,sysc-omap4", "ti,sysc"; 2635 reg = <0x42000 0x4>, 2636 <0x42004 0x4>; 2637 reg-names = "rev", "sysc"; 2638 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 2639 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2640 <SYSC_IDLE_NO>, 2641 <SYSC_IDLE_SMART>; 2642 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2643 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>; 2644 clock-names = "fck"; 2645 #address-cells = <1>; 2646 #size-cells = <1>; 2647 ranges = <0x0 0x42000 0x1000>; 2648 2649 epwmss2: epwmss@0 { 2650 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2651 reg = <0x0 0x30>; 2652 #address-cells = <1>; 2653 #size-cells = <1>; 2654 status = "disabled"; 2655 ranges = <0 0 0x1000>; 2656 2657 ecap2: pwm@100 { 2658 compatible = "ti,dra746-ecap", 2659 "ti,am3352-ecap"; 2660 #pwm-cells = <3>; 2661 reg = <0x100 0x80>; 2662 clocks = <&l4_root_clk_div>; 2663 clock-names = "fck"; 2664 status = "disabled"; 2665 }; 2666 2667 ehrpwm2: pwm@200 { 2668 compatible = "ti,dra746-ehrpwm", 2669 "ti,am3352-ehrpwm"; 2670 #pwm-cells = <3>; 2671 reg = <0x200 0x80>; 2672 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 2673 clock-names = "tbclk", "fck"; 2674 status = "disabled"; 2675 }; 2676 }; 2677 }; 2678 2679 target-module@46000 { /* 0x48446000, ap 53 40.0 */ 2680 compatible = "ti,sysc"; 2681 status = "disabled"; 2682 #address-cells = <1>; 2683 #size-cells = <1>; 2684 ranges = <0x0 0x46000 0x1000>; 2685 }; 2686 2687 target-module@48000 { /* 0x48448000, ap 55 48.0 */ 2688 compatible = "ti,sysc"; 2689 status = "disabled"; 2690 #address-cells = <1>; 2691 #size-cells = <1>; 2692 ranges = <0x0 0x48000 0x1000>; 2693 }; 2694 2695 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */ 2696 compatible = "ti,sysc"; 2697 status = "disabled"; 2698 #address-cells = <1>; 2699 #size-cells = <1>; 2700 ranges = <0x0 0x4a000 0x1000>; 2701 }; 2702 2703 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */ 2704 compatible = "ti,sysc"; 2705 status = "disabled"; 2706 #address-cells = <1>; 2707 #size-cells = <1>; 2708 ranges = <0x0 0x4c000 0x1000>; 2709 }; 2710 2711 target-module@50000 { /* 0x48450000, ap 37 24.0 */ 2712 compatible = "ti,sysc"; 2713 status = "disabled"; 2714 #address-cells = <1>; 2715 #size-cells = <1>; 2716 ranges = <0x0 0x50000 0x1000>; 2717 }; 2718 2719 target-module@54000 { /* 0x48454000, ap 41 2c.0 */ 2720 compatible = "ti,sysc"; 2721 status = "disabled"; 2722 #address-cells = <1>; 2723 #size-cells = <1>; 2724 ranges = <0x0 0x54000 0x1000>; 2725 }; 2726 2727 target-module@58000 { /* 0x48458000, ap 57 28.0 */ 2728 compatible = "ti,sysc"; 2729 status = "disabled"; 2730 #address-cells = <1>; 2731 #size-cells = <1>; 2732 ranges = <0x0 0x58000 0x2000>; 2733 }; 2734 2735 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ 2736 compatible = "ti,sysc"; 2737 status = "disabled"; 2738 #address-cells = <1>; 2739 #size-cells = <1>; 2740 ranges = <0x0 0x5b000 0x1000>; 2741 }; 2742 2743 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */ 2744 compatible = "ti,sysc"; 2745 status = "disabled"; 2746 #address-cells = <1>; 2747 #size-cells = <1>; 2748 ranges = <0x0 0x5d000 0x1000>; 2749 }; 2750 2751 target-module@60000 { /* 0x48460000, ap 9 0e.0 */ 2752 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2753 reg = <0x60000 0x4>, 2754 <0x60004 0x4>; 2755 reg-names = "rev", "sysc"; 2756 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2757 <SYSC_IDLE_NO>, 2758 <SYSC_IDLE_SMART>; 2759 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 2760 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, 2761 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2762 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2763 clock-names = "fck", "ahclkx", "ahclkr"; 2764 #address-cells = <1>; 2765 #size-cells = <1>; 2766 ranges = <0x0 0x60000 0x2000>, 2767 <0x45800000 0x45800000 0x400000>; 2768 2769 mcasp1: mcasp@0 { 2770 compatible = "ti,dra7-mcasp-audio"; 2771 reg = <0x0 0x2000>, 2772 <0x45800000 0x1000>; /* L3 data port */ 2773 reg-names = "mpu","dat"; 2774 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2775 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2776 interrupt-names = "tx", "rx"; 2777 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 2778 dma-names = "tx", "rx"; 2779 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>, 2780 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2781 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; 2782 clock-names = "fck", "ahclkx", "ahclkr"; 2783 status = "disabled"; 2784 }; 2785 }; 2786 2787 target-module@64000 { /* 0x48464000, ap 11 1e.0 */ 2788 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2789 reg = <0x64000 0x4>, 2790 <0x64004 0x4>; 2791 reg-names = "rev", "sysc"; 2792 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2793 <SYSC_IDLE_NO>, 2794 <SYSC_IDLE_SMART>; 2795 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2796 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, 2797 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, 2798 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2799 clock-names = "fck", "ahclkx", "ahclkr"; 2800 #address-cells = <1>; 2801 #size-cells = <1>; 2802 ranges = <0x0 0x64000 0x2000>, 2803 <0x45c00000 0x45c00000 0x400000>; 2804 2805 mcasp2: mcasp@0 { 2806 compatible = "ti,dra7-mcasp-audio"; 2807 reg = <0x0 0x2000>, 2808 <0x45c00000 0x1000>; /* L3 data port */ 2809 reg-names = "mpu","dat"; 2810 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2812 interrupt-names = "tx", "rx"; 2813 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 2814 dma-names = "tx", "rx"; 2815 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>, 2816 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, 2817 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; 2818 clock-names = "fck", "ahclkx", "ahclkr"; 2819 status = "disabled"; 2820 }; 2821 }; 2822 2823 target-module@68000 { /* 0x48468000, ap 13 26.0 */ 2824 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2825 reg = <0x68000 0x4>, 2826 <0x68004 0x4>; 2827 reg-names = "rev", "sysc"; 2828 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2829 <SYSC_IDLE_NO>, 2830 <SYSC_IDLE_SMART>; 2831 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2832 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2833 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2834 clock-names = "fck", "ahclkx"; 2835 #address-cells = <1>; 2836 #size-cells = <1>; 2837 ranges = <0x0 0x68000 0x2000>, 2838 <0x46000000 0x46000000 0x400000>; 2839 2840 mcasp3: mcasp@0 { 2841 compatible = "ti,dra7-mcasp-audio"; 2842 reg = <0x0 0x2000>, 2843 <0x46000000 0x1000>; /* L3 data port */ 2844 reg-names = "mpu","dat"; 2845 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2847 interrupt-names = "tx", "rx"; 2848 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 2849 dma-names = "tx", "rx"; 2850 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, 2851 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 2852 clock-names = "fck", "ahclkx"; 2853 status = "disabled"; 2854 }; 2855 }; 2856 2857 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ 2858 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2859 reg = <0x6c000 0x4>, 2860 <0x6c004 0x4>; 2861 reg-names = "rev", "sysc"; 2862 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2863 <SYSC_IDLE_NO>, 2864 <SYSC_IDLE_SMART>; 2865 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2866 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2867 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2868 clock-names = "fck", "ahclkx"; 2869 #address-cells = <1>; 2870 #size-cells = <1>; 2871 ranges = <0x0 0x6c000 0x2000>, 2872 <0x48436000 0x48436000 0x400000>; 2873 2874 mcasp4: mcasp@0 { 2875 compatible = "ti,dra7-mcasp-audio"; 2876 reg = <0x0 0x2000>, 2877 <0x48436000 0x1000>; /* L3 data port */ 2878 reg-names = "mpu","dat"; 2879 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2881 interrupt-names = "tx", "rx"; 2882 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 2883 dma-names = "tx", "rx"; 2884 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, 2885 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; 2886 clock-names = "fck", "ahclkx"; 2887 status = "disabled"; 2888 }; 2889 }; 2890 2891 target-module@70000 { /* 0x48470000, ap 19 36.0 */ 2892 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2893 reg = <0x70000 0x4>, 2894 <0x70004 0x4>; 2895 reg-names = "rev", "sysc"; 2896 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2897 <SYSC_IDLE_NO>, 2898 <SYSC_IDLE_SMART>; 2899 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2900 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2901 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2902 clock-names = "fck", "ahclkx"; 2903 #address-cells = <1>; 2904 #size-cells = <1>; 2905 ranges = <0x0 0x70000 0x2000>, 2906 <0x4843a000 0x4843a000 0x400000>; 2907 2908 mcasp5: mcasp@0 { 2909 compatible = "ti,dra7-mcasp-audio"; 2910 reg = <0x0 0x2000>, 2911 <0x4843a000 0x1000>; /* L3 data port */ 2912 reg-names = "mpu","dat"; 2913 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 2914 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 2915 interrupt-names = "tx", "rx"; 2916 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 2917 dma-names = "tx", "rx"; 2918 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, 2919 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; 2920 clock-names = "fck", "ahclkx"; 2921 status = "disabled"; 2922 }; 2923 }; 2924 2925 target-module@74000 { /* 0x48474000, ap 35 14.0 */ 2926 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2927 reg = <0x74000 0x4>, 2928 <0x74004 0x4>; 2929 reg-names = "rev", "sysc"; 2930 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2931 <SYSC_IDLE_NO>, 2932 <SYSC_IDLE_SMART>; 2933 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2934 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2935 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2936 clock-names = "fck", "ahclkx"; 2937 #address-cells = <1>; 2938 #size-cells = <1>; 2939 ranges = <0x0 0x74000 0x2000>, 2940 <0x4844c000 0x4844c000 0x400000>; 2941 2942 mcasp6: mcasp@0 { 2943 compatible = "ti,dra7-mcasp-audio"; 2944 reg = <0x0 0x2000>, 2945 <0x4844c000 0x1000>; /* L3 data port */ 2946 reg-names = "mpu","dat"; 2947 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 2949 interrupt-names = "tx", "rx"; 2950 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 2951 dma-names = "tx", "rx"; 2952 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, 2953 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; 2954 clock-names = "fck", "ahclkx"; 2955 status = "disabled"; 2956 }; 2957 }; 2958 2959 target-module@78000 { /* 0x48478000, ap 39 0c.0 */ 2960 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2961 reg = <0x78000 0x4>, 2962 <0x78004 0x4>; 2963 reg-names = "rev", "sysc"; 2964 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2965 <SYSC_IDLE_NO>, 2966 <SYSC_IDLE_SMART>; 2967 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 2968 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2969 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2970 clock-names = "fck", "ahclkx"; 2971 #address-cells = <1>; 2972 #size-cells = <1>; 2973 ranges = <0x0 0x78000 0x2000>, 2974 <0x48450000 0x48450000 0x400000>; 2975 2976 mcasp7: mcasp@0 { 2977 compatible = "ti,dra7-mcasp-audio"; 2978 reg = <0x0 0x2000>, 2979 <0x48450000 0x1000>; /* L3 data port */ 2980 reg-names = "mpu","dat"; 2981 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2983 interrupt-names = "tx", "rx"; 2984 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 2985 dma-names = "tx", "rx"; 2986 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, 2987 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; 2988 clock-names = "fck", "ahclkx"; 2989 status = "disabled"; 2990 }; 2991 }; 2992 2993 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ 2994 compatible = "ti,sysc-dra7-mcasp", "ti,sysc"; 2995 reg = <0x7c000 0x4>, 2996 <0x7c004 0x4>; 2997 reg-names = "rev", "sysc"; 2998 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 2999 <SYSC_IDLE_NO>, 3000 <SYSC_IDLE_SMART>; 3001 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ 3002 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 3003 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 3004 clock-names = "fck", "ahclkx"; 3005 #address-cells = <1>; 3006 #size-cells = <1>; 3007 ranges = <0x0 0x7c000 0x2000>, 3008 <0x48454000 0x48454000 0x400000>; 3009 3010 mcasp8: mcasp@0 { 3011 compatible = "ti,dra7-mcasp-audio"; 3012 reg = <0x0 0x2000>, 3013 <0x48454000 0x1000>; /* L3 data port */ 3014 reg-names = "mpu","dat"; 3015 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 3016 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 3017 interrupt-names = "tx", "rx"; 3018 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 3019 dma-names = "tx", "rx"; 3020 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, 3021 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; 3022 clock-names = "fck", "ahclkx"; 3023 status = "disabled"; 3024 }; 3025 }; 3026 3027 target-module@80000 { /* 0x48480000, ap 31 16.0 */ 3028 compatible = "ti,sysc-omap4", "ti,sysc"; 3029 reg = <0x80020 0x4>; 3030 reg-names = "rev"; 3031 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>; 3032 clock-names = "fck"; 3033 #address-cells = <1>; 3034 #size-cells = <1>; 3035 ranges = <0x0 0x80000 0x2000>; 3036 3037 dcan2: can@0 { 3038 compatible = "ti,dra7-d_can"; 3039 reg = <0x0 0x2000>; 3040 syscon-raminit = <&scm_conf 0x558 1>; 3041 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 3042 clocks = <&sys_clkin1>; 3043 status = "disabled"; 3044 }; 3045 }; 3046 3047 target-module@84000 { /* 0x48484000, ap 3 10.0 */ 3048 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 3049 reg = <0x85200 0x4>, 3050 <0x85208 0x4>, 3051 <0x85204 0x4>; 3052 reg-names = "rev", "sysc", "syss"; 3053 ti,sysc-mask = <0>; 3054 ti,sysc-midle = <SYSC_IDLE_FORCE>, 3055 <SYSC_IDLE_NO>; 3056 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3057 <SYSC_IDLE_NO>; 3058 ti,syss-mask = <1>; 3059 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>; 3060 clock-names = "fck"; 3061 #address-cells = <1>; 3062 #size-cells = <1>; 3063 ranges = <0x0 0x84000 0x4000>; 3064 /* 3065 * Do not allow gating of cpsw clock as workaround 3066 * for errata i877. Keeping internal clock disabled 3067 * causes the device switching characteristics 3068 * to degrade over time and eventually fail to meet 3069 * the data manual delay time/skew specs. 3070 */ 3071 ti,no-idle; 3072 3073 mac_sw: switch@0 { 3074 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch"; 3075 reg = <0x0 0x4000>; 3076 ranges = <0 0 0x4000>; 3077 clocks = <&gmac_main_clk>; 3078 clock-names = "fck"; 3079 #address-cells = <1>; 3080 #size-cells = <1>; 3081 syscon = <&scm_conf>; 3082 status = "disabled"; 3083 3084 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 3088 interrupt-names = "rx_thresh", "rx", "tx", "misc"; 3089 3090 ethernet-ports { 3091 #address-cells = <1>; 3092 #size-cells = <0>; 3093 3094 cpsw_port1: port@1 { 3095 reg = <1>; 3096 label = "port1"; 3097 mac-address = [ 00 00 00 00 00 00 ]; 3098 phys = <&phy_gmii_sel 1>; 3099 }; 3100 3101 cpsw_port2: port@2 { 3102 reg = <2>; 3103 label = "port2"; 3104 mac-address = [ 00 00 00 00 00 00 ]; 3105 phys = <&phy_gmii_sel 2>; 3106 }; 3107 }; 3108 3109 davinci_mdio_sw: mdio@1000 { 3110 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 3111 clocks = <&gmac_main_clk>; 3112 clock-names = "fck"; 3113 #address-cells = <1>; 3114 #size-cells = <0>; 3115 bus_freq = <1000000>; 3116 reg = <0x1000 0x100>; 3117 }; 3118 3119 cpts { 3120 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; 3121 clock-names = "cpts"; 3122 }; 3123 }; 3124 }; 3125 }; 3126}; 3127 3128&l4_per3 { /* 0x48800000 */ 3129 compatible = "ti,dra7-l4-per3", "simple-pm-bus"; 3130 power-domains = <&prm_l4per>; 3131 clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>; 3132 clock-names = "fck"; 3133 reg = <0x48800000 0x800>, 3134 <0x48800800 0x800>, 3135 <0x48801000 0x400>, 3136 <0x48801400 0x400>, 3137 <0x48801800 0x400>; 3138 reg-names = "ap", "la", "ia0", "ia1", "ia2"; 3139 #address-cells = <1>; 3140 #size-cells = <1>; 3141 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */ 3142 3143 segment@0 { /* 0x48800000 */ 3144 compatible = "simple-pm-bus"; 3145 #address-cells = <1>; 3146 #size-cells = <1>; 3147 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 3148 <0x00000800 0x00000800 0x000800>, /* ap 1 */ 3149 <0x00001000 0x00001000 0x000400>, /* ap 2 */ 3150 <0x00001400 0x00001400 0x000400>, /* ap 3 */ 3151 <0x00001800 0x00001800 0x000400>, /* ap 4 */ 3152 <0x00020000 0x00020000 0x001000>, /* ap 5 */ 3153 <0x00021000 0x00021000 0x001000>, /* ap 6 */ 3154 <0x00022000 0x00022000 0x001000>, /* ap 7 */ 3155 <0x00023000 0x00023000 0x001000>, /* ap 8 */ 3156 <0x00024000 0x00024000 0x001000>, /* ap 9 */ 3157 <0x00025000 0x00025000 0x001000>, /* ap 10 */ 3158 <0x00026000 0x00026000 0x001000>, /* ap 11 */ 3159 <0x00027000 0x00027000 0x001000>, /* ap 12 */ 3160 <0x00028000 0x00028000 0x001000>, /* ap 13 */ 3161 <0x00029000 0x00029000 0x001000>, /* ap 14 */ 3162 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */ 3163 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */ 3164 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */ 3165 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */ 3166 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */ 3167 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */ 3168 <0x00170000 0x00170000 0x010000>, /* ap 21 */ 3169 <0x00180000 0x00180000 0x001000>, /* ap 22 */ 3170 <0x00190000 0x00190000 0x010000>, /* ap 23 */ 3171 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */ 3172 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */ 3173 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */ 3174 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */ 3175 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */ 3176 <0x00038000 0x00038000 0x001000>, /* ap 29 */ 3177 <0x00039000 0x00039000 0x001000>, /* ap 30 */ 3178 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */ 3179 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */ 3180 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */ 3181 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */ 3182 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */ 3183 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */ 3184 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */ 3185 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */ 3186 <0x00040000 0x00040000 0x001000>, /* ap 39 */ 3187 <0x00041000 0x00041000 0x001000>, /* ap 40 */ 3188 <0x00042000 0x00042000 0x001000>, /* ap 41 */ 3189 <0x00043000 0x00043000 0x001000>, /* ap 42 */ 3190 <0x00044000 0x00044000 0x001000>, /* ap 43 */ 3191 <0x00045000 0x00045000 0x001000>, /* ap 44 */ 3192 <0x00046000 0x00046000 0x001000>, /* ap 45 */ 3193 <0x00047000 0x00047000 0x001000>, /* ap 46 */ 3194 <0x00048000 0x00048000 0x001000>, /* ap 47 */ 3195 <0x00049000 0x00049000 0x001000>, /* ap 48 */ 3196 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */ 3197 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */ 3198 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */ 3199 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */ 3200 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */ 3201 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */ 3202 <0x00050000 0x00050000 0x001000>, /* ap 55 */ 3203 <0x00051000 0x00051000 0x001000>, /* ap 56 */ 3204 <0x00052000 0x00052000 0x001000>, /* ap 57 */ 3205 <0x00053000 0x00053000 0x001000>, /* ap 58 */ 3206 <0x00054000 0x00054000 0x001000>, /* ap 59 */ 3207 <0x00055000 0x00055000 0x001000>, /* ap 60 */ 3208 <0x00056000 0x00056000 0x001000>, /* ap 61 */ 3209 <0x00057000 0x00057000 0x001000>, /* ap 62 */ 3210 <0x00058000 0x00058000 0x001000>, /* ap 63 */ 3211 <0x00059000 0x00059000 0x001000>, /* ap 64 */ 3212 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */ 3213 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */ 3214 <0x00064000 0x00064000 0x001000>, /* ap 67 */ 3215 <0x00065000 0x00065000 0x001000>, /* ap 68 */ 3216 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */ 3217 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */ 3218 <0x00060000 0x00060000 0x001000>, /* ap 71 */ 3219 <0x00061000 0x00061000 0x001000>, /* ap 72 */ 3220 <0x00062000 0x00062000 0x001000>, /* ap 73 */ 3221 <0x00063000 0x00063000 0x001000>, /* ap 74 */ 3222 <0x00140000 0x00140000 0x020000>, /* ap 75 */ 3223 <0x00160000 0x00160000 0x001000>, /* ap 76 */ 3224 <0x00016000 0x00016000 0x001000>, /* ap 77 */ 3225 <0x00017000 0x00017000 0x001000>, /* ap 78 */ 3226 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */ 3227 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */ 3228 <0x00004000 0x00004000 0x001000>, /* ap 81 */ 3229 <0x00005000 0x00005000 0x001000>, /* ap 82 */ 3230 <0x00080000 0x00080000 0x020000>, /* ap 83 */ 3231 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */ 3232 <0x00100000 0x00100000 0x020000>, /* ap 85 */ 3233 <0x00120000 0x00120000 0x001000>, /* ap 86 */ 3234 <0x00010000 0x00010000 0x001000>, /* ap 87 */ 3235 <0x00011000 0x00011000 0x001000>, /* ap 88 */ 3236 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */ 3237 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */ 3238 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */ 3239 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */ 3240 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */ 3241 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */ 3242 <0x00002000 0x00002000 0x001000>, /* ap 95 */ 3243 <0x00003000 0x00003000 0x001000>; /* ap 96 */ 3244 3245 target-module@2000 { /* 0x48802000, ap 95 7c.0 */ 3246 compatible = "ti,sysc-omap4", "ti,sysc"; 3247 reg = <0x2000 0x4>, 3248 <0x2010 0x4>; 3249 reg-names = "rev", "sysc"; 3250 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3251 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3252 <SYSC_IDLE_NO>, 3253 <SYSC_IDLE_SMART>; 3254 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3255 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>; 3256 clock-names = "fck"; 3257 #address-cells = <1>; 3258 #size-cells = <1>; 3259 ranges = <0x0 0x2000 0x1000>; 3260 3261 mailbox13: mailbox@0 { 3262 compatible = "ti,omap4-mailbox"; 3263 reg = <0x0 0x200>; 3264 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 3268 #mbox-cells = <1>; 3269 ti,mbox-num-users = <4>; 3270 ti,mbox-num-fifos = <12>; 3271 status = "disabled"; 3272 }; 3273 }; 3274 3275 target-module@4000 { /* 0x48804000, ap 81 20.0 */ 3276 compatible = "ti,sysc"; 3277 status = "disabled"; 3278 #address-cells = <1>; 3279 #size-cells = <1>; 3280 ranges = <0x0 0x4000 0x1000>; 3281 }; 3282 3283 target-module@a000 { /* 0x4880a000, ap 89 18.0 */ 3284 compatible = "ti,sysc"; 3285 status = "disabled"; 3286 #address-cells = <1>; 3287 #size-cells = <1>; 3288 ranges = <0x0 0xa000 0x1000>; 3289 }; 3290 3291 target-module@10000 { /* 0x48810000, ap 87 28.0 */ 3292 compatible = "ti,sysc"; 3293 status = "disabled"; 3294 #address-cells = <1>; 3295 #size-cells = <1>; 3296 ranges = <0x0 0x10000 0x1000>; 3297 }; 3298 3299 target-module@16000 { /* 0x48816000, ap 77 1e.0 */ 3300 compatible = "ti,sysc"; 3301 status = "disabled"; 3302 #address-cells = <1>; 3303 #size-cells = <1>; 3304 ranges = <0x0 0x16000 0x1000>; 3305 }; 3306 3307 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */ 3308 compatible = "ti,sysc"; 3309 status = "disabled"; 3310 #address-cells = <1>; 3311 #size-cells = <1>; 3312 ranges = <0x0 0x1c000 0x1000>; 3313 }; 3314 3315 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */ 3316 compatible = "ti,sysc"; 3317 status = "disabled"; 3318 #address-cells = <1>; 3319 #size-cells = <1>; 3320 ranges = <0x0 0x1e000 0x1000>; 3321 }; 3322 3323 target-module@20000 { /* 0x48820000, ap 5 08.0 */ 3324 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3325 reg = <0x20000 0x4>, 3326 <0x20010 0x4>; 3327 reg-names = "rev", "sysc"; 3328 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3329 SYSC_OMAP4_SOFTRESET)>; 3330 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3331 <SYSC_IDLE_NO>, 3332 <SYSC_IDLE_SMART>, 3333 <SYSC_IDLE_SMART_WKUP>; 3334 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3335 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>; 3336 clock-names = "fck"; 3337 #address-cells = <1>; 3338 #size-cells = <1>; 3339 ranges = <0x0 0x20000 0x1000>; 3340 3341 timer5: timer@0 { 3342 compatible = "ti,omap5430-timer"; 3343 reg = <0x0 0x80>; 3344 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; 3345 clock-names = "fck", "timer_sys_ck"; 3346 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3347 }; 3348 }; 3349 3350 target-module@22000 { /* 0x48822000, ap 7 24.0 */ 3351 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3352 reg = <0x22000 0x4>, 3353 <0x22010 0x4>; 3354 reg-names = "rev", "sysc"; 3355 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3356 SYSC_OMAP4_SOFTRESET)>; 3357 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3358 <SYSC_IDLE_NO>, 3359 <SYSC_IDLE_SMART>, 3360 <SYSC_IDLE_SMART_WKUP>; 3361 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3362 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>; 3363 clock-names = "fck"; 3364 #address-cells = <1>; 3365 #size-cells = <1>; 3366 ranges = <0x0 0x22000 0x1000>; 3367 3368 timer6: timer@0 { 3369 compatible = "ti,omap5430-timer"; 3370 reg = <0x0 0x80>; 3371 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; 3372 clock-names = "fck", "timer_sys_ck"; 3373 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3374 }; 3375 }; 3376 3377 target-module@24000 { /* 0x48824000, ap 9 26.0 */ 3378 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3379 reg = <0x24000 0x4>, 3380 <0x24010 0x4>; 3381 reg-names = "rev", "sysc"; 3382 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3383 SYSC_OMAP4_SOFTRESET)>; 3384 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3385 <SYSC_IDLE_NO>, 3386 <SYSC_IDLE_SMART>, 3387 <SYSC_IDLE_SMART_WKUP>; 3388 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3389 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>; 3390 clock-names = "fck"; 3391 #address-cells = <1>; 3392 #size-cells = <1>; 3393 ranges = <0x0 0x24000 0x1000>; 3394 3395 timer7: timer@0 { 3396 compatible = "ti,omap5430-timer"; 3397 reg = <0x0 0x80>; 3398 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>; 3399 clock-names = "fck", "timer_sys_ck"; 3400 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 3401 }; 3402 }; 3403 3404 target-module@26000 { /* 0x48826000, ap 11 0c.0 */ 3405 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3406 reg = <0x26000 0x4>, 3407 <0x26010 0x4>; 3408 reg-names = "rev", "sysc"; 3409 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3410 SYSC_OMAP4_SOFTRESET)>; 3411 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3412 <SYSC_IDLE_NO>, 3413 <SYSC_IDLE_SMART>, 3414 <SYSC_IDLE_SMART_WKUP>; 3415 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */ 3416 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>; 3417 clock-names = "fck"; 3418 #address-cells = <1>; 3419 #size-cells = <1>; 3420 ranges = <0x0 0x26000 0x1000>; 3421 3422 timer8: timer@0 { 3423 compatible = "ti,omap5430-timer"; 3424 reg = <0x0 0x80>; 3425 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>; 3426 clock-names = "fck", "timer_sys_ck"; 3427 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 3428 }; 3429 }; 3430 3431 target-module@28000 { /* 0x48828000, ap 13 16.0 */ 3432 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3433 reg = <0x28000 0x4>, 3434 <0x28010 0x4>; 3435 reg-names = "rev", "sysc"; 3436 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3437 SYSC_OMAP4_SOFTRESET)>; 3438 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3439 <SYSC_IDLE_NO>, 3440 <SYSC_IDLE_SMART>, 3441 <SYSC_IDLE_SMART_WKUP>; 3442 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3443 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>; 3444 clock-names = "fck"; 3445 #address-cells = <1>; 3446 #size-cells = <1>; 3447 ranges = <0x0 0x28000 0x1000>; 3448 3449 timer13: timer@0 { 3450 compatible = "ti,omap5430-timer"; 3451 reg = <0x0 0x80>; 3452 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>; 3453 clock-names = "fck", "timer_sys_ck"; 3454 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 3455 ti,timer-pwm; 3456 }; 3457 }; 3458 3459 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */ 3460 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3461 reg = <0x2a000 0x4>, 3462 <0x2a010 0x4>; 3463 reg-names = "rev", "sysc"; 3464 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3465 SYSC_OMAP4_SOFTRESET)>; 3466 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3467 <SYSC_IDLE_NO>, 3468 <SYSC_IDLE_SMART>, 3469 <SYSC_IDLE_SMART_WKUP>; 3470 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3471 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>; 3472 clock-names = "fck"; 3473 #address-cells = <1>; 3474 #size-cells = <1>; 3475 ranges = <0x0 0x2a000 0x1000>; 3476 3477 timer14: timer@0 { 3478 compatible = "ti,omap5430-timer"; 3479 reg = <0x0 0x80>; 3480 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; 3481 clock-names = "fck", "timer_sys_ck"; 3482 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 3483 ti,timer-pwm; 3484 }; 3485 }; 3486 timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */ 3487 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3488 reg = <0x2c000 0x4>, 3489 <0x2c010 0x4>; 3490 reg-names = "rev", "sysc"; 3491 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3492 SYSC_OMAP4_SOFTRESET)>; 3493 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3494 <SYSC_IDLE_NO>, 3495 <SYSC_IDLE_SMART>, 3496 <SYSC_IDLE_SMART_WKUP>; 3497 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3498 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>; 3499 clock-names = "fck"; 3500 #address-cells = <1>; 3501 #size-cells = <1>; 3502 ranges = <0x0 0x2c000 0x1000>; 3503 3504 timer15: timer@0 { 3505 compatible = "ti,omap5430-timer"; 3506 reg = <0x0 0x80>; 3507 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; 3508 clock-names = "fck", "timer_sys_ck"; 3509 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 3510 ti,timer-pwm; 3511 }; 3512 }; 3513 3514 timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */ 3515 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 3516 reg = <0x2e000 0x4>, 3517 <0x2e010 0x4>; 3518 reg-names = "rev", "sysc"; 3519 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 3520 SYSC_OMAP4_SOFTRESET)>; 3521 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3522 <SYSC_IDLE_NO>, 3523 <SYSC_IDLE_SMART>, 3524 <SYSC_IDLE_SMART_WKUP>; 3525 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */ 3526 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>; 3527 clock-names = "fck"; 3528 #address-cells = <1>; 3529 #size-cells = <1>; 3530 ranges = <0x0 0x2e000 0x1000>; 3531 3532 timer16: timer@0 { 3533 compatible = "ti,omap5430-timer"; 3534 reg = <0x0 0x80>; 3535 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; 3536 clock-names = "fck", "timer_sys_ck"; 3537 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 3538 ti,timer-pwm; 3539 }; 3540 }; 3541 3542 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */ 3543 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 3544 reg = <0x38074 0x4>, 3545 <0x38078 0x4>; 3546 reg-names = "rev", "sysc"; 3547 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3548 <SYSC_IDLE_NO>, 3549 <SYSC_IDLE_SMART>, 3550 <SYSC_IDLE_SMART_WKUP>; 3551 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */ 3552 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>; 3553 clock-names = "fck"; 3554 #address-cells = <1>; 3555 #size-cells = <1>; 3556 ranges = <0x0 0x38000 0x1000>; 3557 3558 rtc: rtc@0 { 3559 compatible = "ti,am3352-rtc"; 3560 reg = <0x0 0x100>; 3561 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 3563 clocks = <&sys_32k_ck>; 3564 }; 3565 }; 3566 3567 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */ 3568 compatible = "ti,sysc-omap4", "ti,sysc"; 3569 reg = <0x3a000 0x4>, 3570 <0x3a010 0x4>; 3571 reg-names = "rev", "sysc"; 3572 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3573 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3574 <SYSC_IDLE_NO>, 3575 <SYSC_IDLE_SMART>; 3576 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3577 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>; 3578 clock-names = "fck"; 3579 #address-cells = <1>; 3580 #size-cells = <1>; 3581 ranges = <0x0 0x3a000 0x1000>; 3582 3583 mailbox2: mailbox@0 { 3584 compatible = "ti,omap4-mailbox"; 3585 reg = <0x0 0x200>; 3586 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 3590 #mbox-cells = <1>; 3591 ti,mbox-num-users = <4>; 3592 ti,mbox-num-fifos = <12>; 3593 status = "disabled"; 3594 }; 3595 }; 3596 3597 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */ 3598 compatible = "ti,sysc-omap4", "ti,sysc"; 3599 reg = <0x3c000 0x4>, 3600 <0x3c010 0x4>; 3601 reg-names = "rev", "sysc"; 3602 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3603 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3604 <SYSC_IDLE_NO>, 3605 <SYSC_IDLE_SMART>; 3606 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3607 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>; 3608 clock-names = "fck"; 3609 #address-cells = <1>; 3610 #size-cells = <1>; 3611 ranges = <0x0 0x3c000 0x1000>; 3612 3613 mailbox3: mailbox@0 { 3614 compatible = "ti,omap4-mailbox"; 3615 reg = <0x0 0x200>; 3616 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 3620 #mbox-cells = <1>; 3621 ti,mbox-num-users = <4>; 3622 ti,mbox-num-fifos = <12>; 3623 status = "disabled"; 3624 }; 3625 }; 3626 3627 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */ 3628 compatible = "ti,sysc-omap4", "ti,sysc"; 3629 reg = <0x3e000 0x4>, 3630 <0x3e010 0x4>; 3631 reg-names = "rev", "sysc"; 3632 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3633 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3634 <SYSC_IDLE_NO>, 3635 <SYSC_IDLE_SMART>; 3636 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3637 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>; 3638 clock-names = "fck"; 3639 #address-cells = <1>; 3640 #size-cells = <1>; 3641 ranges = <0x0 0x3e000 0x1000>; 3642 3643 mailbox4: mailbox@0 { 3644 compatible = "ti,omap4-mailbox"; 3645 reg = <0x0 0x200>; 3646 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 3650 #mbox-cells = <1>; 3651 ti,mbox-num-users = <4>; 3652 ti,mbox-num-fifos = <12>; 3653 status = "disabled"; 3654 }; 3655 }; 3656 3657 target-module@40000 { /* 0x48840000, ap 39 64.0 */ 3658 compatible = "ti,sysc-omap4", "ti,sysc"; 3659 reg = <0x40000 0x4>, 3660 <0x40010 0x4>; 3661 reg-names = "rev", "sysc"; 3662 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3663 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3664 <SYSC_IDLE_NO>, 3665 <SYSC_IDLE_SMART>; 3666 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3667 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>; 3668 clock-names = "fck"; 3669 #address-cells = <1>; 3670 #size-cells = <1>; 3671 ranges = <0x0 0x40000 0x1000>; 3672 3673 mailbox5: mailbox@0 { 3674 compatible = "ti,omap4-mailbox"; 3675 reg = <0x0 0x200>; 3676 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 3680 #mbox-cells = <1>; 3681 ti,mbox-num-users = <4>; 3682 ti,mbox-num-fifos = <12>; 3683 status = "disabled"; 3684 }; 3685 }; 3686 3687 target-module@42000 { /* 0x48842000, ap 41 4e.0 */ 3688 compatible = "ti,sysc-omap4", "ti,sysc"; 3689 reg = <0x42000 0x4>, 3690 <0x42010 0x4>; 3691 reg-names = "rev", "sysc"; 3692 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3693 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3694 <SYSC_IDLE_NO>, 3695 <SYSC_IDLE_SMART>; 3696 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3697 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>; 3698 clock-names = "fck"; 3699 #address-cells = <1>; 3700 #size-cells = <1>; 3701 ranges = <0x0 0x42000 0x1000>; 3702 3703 mailbox6: mailbox@0 { 3704 compatible = "ti,omap4-mailbox"; 3705 reg = <0x0 0x200>; 3706 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 3710 #mbox-cells = <1>; 3711 ti,mbox-num-users = <4>; 3712 ti,mbox-num-fifos = <12>; 3713 status = "disabled"; 3714 }; 3715 }; 3716 3717 target-module@44000 { /* 0x48844000, ap 43 42.0 */ 3718 compatible = "ti,sysc-omap4", "ti,sysc"; 3719 reg = <0x44000 0x4>, 3720 <0x44010 0x4>; 3721 reg-names = "rev", "sysc"; 3722 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3723 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3724 <SYSC_IDLE_NO>, 3725 <SYSC_IDLE_SMART>; 3726 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3727 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>; 3728 clock-names = "fck"; 3729 #address-cells = <1>; 3730 #size-cells = <1>; 3731 ranges = <0x0 0x44000 0x1000>; 3732 3733 mailbox7: mailbox@0 { 3734 compatible = "ti,omap4-mailbox"; 3735 reg = <0x0 0x200>; 3736 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 3740 #mbox-cells = <1>; 3741 ti,mbox-num-users = <4>; 3742 ti,mbox-num-fifos = <12>; 3743 status = "disabled"; 3744 }; 3745 }; 3746 3747 target-module@46000 { /* 0x48846000, ap 45 48.0 */ 3748 compatible = "ti,sysc-omap4", "ti,sysc"; 3749 reg = <0x46000 0x4>, 3750 <0x46010 0x4>; 3751 reg-names = "rev", "sysc"; 3752 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3753 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3754 <SYSC_IDLE_NO>, 3755 <SYSC_IDLE_SMART>; 3756 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3757 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>; 3758 clock-names = "fck"; 3759 #address-cells = <1>; 3760 #size-cells = <1>; 3761 ranges = <0x0 0x46000 0x1000>; 3762 3763 mailbox8: mailbox@0 { 3764 compatible = "ti,omap4-mailbox"; 3765 reg = <0x0 0x200>; 3766 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 3770 #mbox-cells = <1>; 3771 ti,mbox-num-users = <4>; 3772 ti,mbox-num-fifos = <12>; 3773 status = "disabled"; 3774 }; 3775 }; 3776 3777 target-module@48000 { /* 0x48848000, ap 47 36.0 */ 3778 compatible = "ti,sysc"; 3779 status = "disabled"; 3780 #address-cells = <1>; 3781 #size-cells = <1>; 3782 ranges = <0x0 0x48000 0x1000>; 3783 }; 3784 3785 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */ 3786 compatible = "ti,sysc"; 3787 status = "disabled"; 3788 #address-cells = <1>; 3789 #size-cells = <1>; 3790 ranges = <0x0 0x4a000 0x1000>; 3791 }; 3792 3793 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */ 3794 compatible = "ti,sysc"; 3795 status = "disabled"; 3796 #address-cells = <1>; 3797 #size-cells = <1>; 3798 ranges = <0x0 0x4c000 0x1000>; 3799 }; 3800 3801 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */ 3802 compatible = "ti,sysc"; 3803 status = "disabled"; 3804 #address-cells = <1>; 3805 #size-cells = <1>; 3806 ranges = <0x0 0x4e000 0x1000>; 3807 }; 3808 3809 target-module@50000 { /* 0x48850000, ap 55 40.0 */ 3810 compatible = "ti,sysc"; 3811 status = "disabled"; 3812 #address-cells = <1>; 3813 #size-cells = <1>; 3814 ranges = <0x0 0x50000 0x1000>; 3815 }; 3816 3817 target-module@52000 { /* 0x48852000, ap 57 54.0 */ 3818 compatible = "ti,sysc"; 3819 status = "disabled"; 3820 #address-cells = <1>; 3821 #size-cells = <1>; 3822 ranges = <0x0 0x52000 0x1000>; 3823 }; 3824 3825 target-module@54000 { /* 0x48854000, ap 59 1a.0 */ 3826 compatible = "ti,sysc"; 3827 status = "disabled"; 3828 #address-cells = <1>; 3829 #size-cells = <1>; 3830 ranges = <0x0 0x54000 0x1000>; 3831 }; 3832 3833 target-module@56000 { /* 0x48856000, ap 61 22.0 */ 3834 compatible = "ti,sysc"; 3835 status = "disabled"; 3836 #address-cells = <1>; 3837 #size-cells = <1>; 3838 ranges = <0x0 0x56000 0x1000>; 3839 }; 3840 3841 target-module@58000 { /* 0x48858000, ap 63 2a.0 */ 3842 compatible = "ti,sysc"; 3843 status = "disabled"; 3844 #address-cells = <1>; 3845 #size-cells = <1>; 3846 ranges = <0x0 0x58000 0x1000>; 3847 }; 3848 3849 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */ 3850 compatible = "ti,sysc"; 3851 status = "disabled"; 3852 #address-cells = <1>; 3853 #size-cells = <1>; 3854 ranges = <0x0 0x5a000 0x1000>; 3855 }; 3856 3857 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */ 3858 compatible = "ti,sysc"; 3859 status = "disabled"; 3860 #address-cells = <1>; 3861 #size-cells = <1>; 3862 ranges = <0x0 0x5c000 0x1000>; 3863 }; 3864 3865 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */ 3866 compatible = "ti,sysc-omap4", "ti,sysc"; 3867 reg = <0x5e000 0x4>, 3868 <0x5e010 0x4>; 3869 reg-names = "rev", "sysc"; 3870 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3871 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3872 <SYSC_IDLE_NO>, 3873 <SYSC_IDLE_SMART>; 3874 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3875 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>; 3876 clock-names = "fck"; 3877 #address-cells = <1>; 3878 #size-cells = <1>; 3879 ranges = <0x0 0x5e000 0x1000>; 3880 3881 mailbox9: mailbox@0 { 3882 compatible = "ti,omap4-mailbox"; 3883 reg = <0x0 0x200>; 3884 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 3888 #mbox-cells = <1>; 3889 ti,mbox-num-users = <4>; 3890 ti,mbox-num-fifos = <12>; 3891 status = "disabled"; 3892 }; 3893 }; 3894 3895 target-module@60000 { /* 0x48860000, ap 71 4a.0 */ 3896 compatible = "ti,sysc-omap4", "ti,sysc"; 3897 reg = <0x60000 0x4>, 3898 <0x60010 0x4>; 3899 reg-names = "rev", "sysc"; 3900 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3901 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3902 <SYSC_IDLE_NO>, 3903 <SYSC_IDLE_SMART>; 3904 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3905 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>; 3906 clock-names = "fck"; 3907 #address-cells = <1>; 3908 #size-cells = <1>; 3909 ranges = <0x0 0x60000 0x1000>; 3910 3911 mailbox10: mailbox@0 { 3912 compatible = "ti,omap4-mailbox"; 3913 reg = <0x0 0x200>; 3914 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 3915 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 3916 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3918 #mbox-cells = <1>; 3919 ti,mbox-num-users = <4>; 3920 ti,mbox-num-fifos = <12>; 3921 status = "disabled"; 3922 }; 3923 }; 3924 3925 target-module@62000 { /* 0x48862000, ap 73 74.0 */ 3926 compatible = "ti,sysc-omap4", "ti,sysc"; 3927 reg = <0x62000 0x4>, 3928 <0x62010 0x4>; 3929 reg-names = "rev", "sysc"; 3930 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3931 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3932 <SYSC_IDLE_NO>, 3933 <SYSC_IDLE_SMART>; 3934 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3935 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>; 3936 clock-names = "fck"; 3937 #address-cells = <1>; 3938 #size-cells = <1>; 3939 ranges = <0x0 0x62000 0x1000>; 3940 3941 mailbox11: mailbox@0 { 3942 compatible = "ti,omap4-mailbox"; 3943 reg = <0x0 0x200>; 3944 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 3948 #mbox-cells = <1>; 3949 ti,mbox-num-users = <4>; 3950 ti,mbox-num-fifos = <12>; 3951 status = "disabled"; 3952 }; 3953 }; 3954 3955 target-module@64000 { /* 0x48864000, ap 67 52.0 */ 3956 compatible = "ti,sysc-omap4", "ti,sysc"; 3957 reg = <0x64000 0x4>, 3958 <0x64010 0x4>; 3959 reg-names = "rev", "sysc"; 3960 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 3961 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3962 <SYSC_IDLE_NO>, 3963 <SYSC_IDLE_SMART>; 3964 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */ 3965 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>; 3966 clock-names = "fck"; 3967 #address-cells = <1>; 3968 #size-cells = <1>; 3969 ranges = <0x0 0x64000 0x1000>; 3970 3971 mailbox12: mailbox@0 { 3972 compatible = "ti,omap4-mailbox"; 3973 reg = <0x0 0x200>; 3974 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 3978 #mbox-cells = <1>; 3979 ti,mbox-num-users = <4>; 3980 ti,mbox-num-fifos = <12>; 3981 status = "disabled"; 3982 }; 3983 }; 3984 3985 target-module@80000 { /* 0x48880000, ap 83 0e.1 */ 3986 compatible = "ti,sysc-omap4", "ti,sysc"; 3987 reg = <0x80000 0x4>, 3988 <0x80010 0x4>; 3989 reg-names = "rev", "sysc"; 3990 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 3991 ti,sysc-midle = <SYSC_IDLE_FORCE>, 3992 <SYSC_IDLE_NO>, 3993 <SYSC_IDLE_SMART>, 3994 <SYSC_IDLE_SMART_WKUP>; 3995 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 3996 <SYSC_IDLE_NO>, 3997 <SYSC_IDLE_SMART>, 3998 <SYSC_IDLE_SMART_WKUP>; 3999 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4000 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>; 4001 clock-names = "fck"; 4002 #address-cells = <1>; 4003 #size-cells = <1>; 4004 ranges = <0x0 0x80000 0x20000>; 4005 4006 omap_dwc3_1: omap_dwc3_1@0 { 4007 compatible = "ti,dwc3"; 4008 reg = <0x0 0x10000>; 4009 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4010 #address-cells = <1>; 4011 #size-cells = <1>; 4012 utmi-mode = <2>; 4013 ranges = <0 0 0x20000>; 4014 4015 usb1: usb@10000 { 4016 compatible = "snps,dwc3"; 4017 reg = <0x10000 0x17000>; 4018 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4021 interrupt-names = "peripheral", 4022 "host", 4023 "otg"; 4024 phys = <&usb2_phy1>, <&usb3_phy1>; 4025 phy-names = "usb2-phy", "usb3-phy"; 4026 maximum-speed = "super-speed"; 4027 dr_mode = "otg"; 4028 snps,dis_u3_susphy_quirk; 4029 snps,dis_u2_susphy_quirk; 4030 }; 4031 }; 4032 }; 4033 4034 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */ 4035 compatible = "ti,sysc-omap4", "ti,sysc"; 4036 reg = <0xc0000 0x4>, 4037 <0xc0010 0x4>; 4038 reg-names = "rev", "sysc"; 4039 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4040 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4041 <SYSC_IDLE_NO>, 4042 <SYSC_IDLE_SMART>, 4043 <SYSC_IDLE_SMART_WKUP>; 4044 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4045 <SYSC_IDLE_NO>, 4046 <SYSC_IDLE_SMART>, 4047 <SYSC_IDLE_SMART_WKUP>; 4048 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4049 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>; 4050 clock-names = "fck"; 4051 #address-cells = <1>; 4052 #size-cells = <1>; 4053 ranges = <0x0 0xc0000 0x20000>; 4054 4055 omap_dwc3_2: omap_dwc3_2@0 { 4056 compatible = "ti,dwc3"; 4057 reg = <0x0 0x10000>; 4058 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4059 #address-cells = <1>; 4060 #size-cells = <1>; 4061 utmi-mode = <2>; 4062 ranges = <0 0 0x20000>; 4063 4064 usb2: usb@10000 { 4065 compatible = "snps,dwc3"; 4066 reg = <0x10000 0x17000>; 4067 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 4070 interrupt-names = "peripheral", 4071 "host", 4072 "otg"; 4073 phys = <&usb2_phy2>; 4074 phy-names = "usb2-phy"; 4075 maximum-speed = "high-speed"; 4076 dr_mode = "otg"; 4077 snps,dis_u3_susphy_quirk; 4078 snps,dis_u2_susphy_quirk; 4079 snps,dis_metastability_quirk; 4080 }; 4081 }; 4082 }; 4083 4084 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */ 4085 compatible = "ti,sysc-omap4", "ti,sysc"; 4086 reg = <0x100000 0x4>, 4087 <0x100010 0x4>; 4088 reg-names = "rev", "sysc"; 4089 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>; 4090 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4091 <SYSC_IDLE_NO>, 4092 <SYSC_IDLE_SMART>, 4093 <SYSC_IDLE_SMART_WKUP>; 4094 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4095 <SYSC_IDLE_NO>, 4096 <SYSC_IDLE_SMART>, 4097 <SYSC_IDLE_SMART_WKUP>; 4098 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */ 4099 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>; 4100 clock-names = "fck"; 4101 #address-cells = <1>; 4102 #size-cells = <1>; 4103 ranges = <0x0 0x100000 0x20000>; 4104 4105 omap_dwc3_3: omap_dwc3_3@0 { 4106 compatible = "ti,dwc3"; 4107 reg = <0x0 0x10000>; 4108 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 4109 #address-cells = <1>; 4110 #size-cells = <1>; 4111 utmi-mode = <2>; 4112 ranges = <0 0 0x20000>; 4113 status = "disabled"; 4114 4115 usb3: usb@10000 { 4116 compatible = "snps,dwc3"; 4117 reg = <0x10000 0x17000>; 4118 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 4121 interrupt-names = "peripheral", 4122 "host", 4123 "otg"; 4124 maximum-speed = "high-speed"; 4125 dr_mode = "otg"; 4126 snps,dis_u3_susphy_quirk; 4127 snps,dis_u2_susphy_quirk; 4128 }; 4129 }; 4130 }; 4131 4132 target-module@170000 { /* 0x48970000, ap 21 0a.0 */ 4133 compatible = "ti,sysc-omap4", "ti,sysc"; 4134 reg = <0x170010 0x4>; 4135 reg-names = "sysc"; 4136 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4137 <SYSC_IDLE_NO>, 4138 <SYSC_IDLE_SMART>; 4139 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4140 <SYSC_IDLE_NO>, 4141 <SYSC_IDLE_SMART>; 4142 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>; 4143 clock-names = "fck"; 4144 #address-cells = <1>; 4145 #size-cells = <1>; 4146 ranges = <0x0 0x170000 0x10000>; 4147 status = "disabled"; 4148 }; 4149 4150 target-module@190000 { /* 0x48990000, ap 23 2e.0 */ 4151 compatible = "ti,sysc-omap4", "ti,sysc"; 4152 reg = <0x190010 0x4>; 4153 reg-names = "sysc"; 4154 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4155 <SYSC_IDLE_NO>, 4156 <SYSC_IDLE_SMART>; 4157 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4158 <SYSC_IDLE_NO>, 4159 <SYSC_IDLE_SMART>; 4160 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; 4161 clock-names = "fck"; 4162 #address-cells = <1>; 4163 #size-cells = <1>; 4164 ranges = <0x0 0x190000 0x10000>; 4165 status = "disabled"; 4166 }; 4167 4168 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */ 4169 compatible = "ti,sysc-omap4", "ti,sysc"; 4170 reg = <0x1b0000 0x4>, 4171 <0x1b0010 0x4>; 4172 reg-names = "rev", "sysc"; 4173 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4174 <SYSC_IDLE_NO>, 4175 <SYSC_IDLE_SMART>; 4176 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4177 <SYSC_IDLE_NO>, 4178 <SYSC_IDLE_SMART>; 4179 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>; 4180 clock-names = "fck"; 4181 #address-cells = <1>; 4182 #size-cells = <1>; 4183 ranges = <0x0 0x1b0000 0x10000>; 4184 status = "disabled"; 4185 }; 4186 4187 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */ 4188 compatible = "ti,sysc-omap4", "ti,sysc"; 4189 reg = <0x1d0010 0x4>; 4190 reg-names = "sysc"; 4191 ti,sysc-midle = <SYSC_IDLE_FORCE>, 4192 <SYSC_IDLE_NO>; 4193 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4194 <SYSC_IDLE_NO>, 4195 <SYSC_IDLE_SMART>; 4196 power-domains = <&prm_vpe>; 4197 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>; 4198 clock-names = "fck"; 4199 #address-cells = <1>; 4200 #size-cells = <1>; 4201 ranges = <0x0 0x1d0000 0x10000>; 4202 4203 vpe: vpe@0 { 4204 compatible = "ti,dra7-vpe"; 4205 reg = <0x0000 0x120>, 4206 <0x0700 0x80>, 4207 <0x5700 0x18>, 4208 <0xd000 0x400>; 4209 reg-names = "vpe_top", 4210 "sc", 4211 "csc", 4212 "vpdma"; 4213 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 4214 }; 4215 }; 4216 }; 4217}; 4218 4219&l4_wkup { /* 0x4ae00000 */ 4220 compatible = "ti,dra7-l4-wkup", "simple-pm-bus"; 4221 power-domains = <&prm_wkupaon>; 4222 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>; 4223 clock-names = "fck"; 4224 reg = <0x4ae00000 0x800>, 4225 <0x4ae00800 0x800>, 4226 <0x4ae01000 0x1000>; 4227 reg-names = "ap", "la", "ia0"; 4228 #address-cells = <1>; 4229 #size-cells = <1>; 4230 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */ 4231 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */ 4232 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */ 4233 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */ 4234 4235 segment@0 { /* 0x4ae00000 */ 4236 compatible = "simple-pm-bus"; 4237 #address-cells = <1>; 4238 #size-cells = <1>; 4239 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ 4240 <0x00001000 0x00001000 0x001000>, /* ap 1 */ 4241 <0x00000800 0x00000800 0x000800>, /* ap 2 */ 4242 <0x00006000 0x00006000 0x002000>, /* ap 3 */ 4243 <0x00008000 0x00008000 0x001000>, /* ap 4 */ 4244 <0x00004000 0x00004000 0x001000>, /* ap 15 */ 4245 <0x00005000 0x00005000 0x001000>, /* ap 16 */ 4246 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */ 4247 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */ 4248 4249 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ 4250 compatible = "ti,sysc-omap2", "ti,sysc"; 4251 reg = <0x4000 0x4>, 4252 <0x4010 0x4>; 4253 reg-names = "rev", "sysc"; 4254 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4255 <SYSC_IDLE_NO>, 4256 <SYSC_IDLE_SMART>, 4257 <SYSC_IDLE_SMART_WKUP>; 4258 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4259 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>; 4260 clock-names = "fck"; 4261 #address-cells = <1>; 4262 #size-cells = <1>; 4263 ranges = <0x0 0x4000 0x1000>; 4264 4265 counter32k: counter@0 { 4266 compatible = "ti,omap-counter32k"; 4267 reg = <0x0 0x40>; 4268 }; 4269 }; 4270 4271 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */ 4272 compatible = "ti,sysc-omap4", "ti,sysc"; 4273 reg = <0x6000 0x4>; 4274 reg-names = "rev"; 4275 #address-cells = <1>; 4276 #size-cells = <1>; 4277 ranges = <0x0 0x6000 0x2000>; 4278 4279 prm: prm@0 { 4280 compatible = "ti,dra7-prm", "simple-bus"; 4281 reg = <0 0x3000>; 4282 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4283 #address-cells = <1>; 4284 #size-cells = <1>; 4285 ranges = <0 0 0x3000>; 4286 4287 prm_clocks: clocks { 4288 #address-cells = <1>; 4289 #size-cells = <0>; 4290 }; 4291 4292 prm_clockdomains: clockdomains { 4293 }; 4294 }; 4295 }; 4296 4297 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */ 4298 compatible = "ti,sysc-omap4", "ti,sysc"; 4299 reg = <0xc000 0x4>; 4300 reg-names = "rev"; 4301 #address-cells = <1>; 4302 #size-cells = <1>; 4303 ranges = <0x0 0xc000 0x1000>; 4304 4305 scm_wkup: scm_conf@0 { 4306 compatible = "syscon"; 4307 reg = <0 0x1000>; 4308 }; 4309 }; 4310 }; 4311 4312 segment@10000 { /* 0x4ae10000 */ 4313 compatible = "simple-pm-bus"; 4314 #address-cells = <1>; 4315 #size-cells = <1>; 4316 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */ 4317 <0x00001000 0x00011000 0x001000>, /* ap 6 */ 4318 <0x00004000 0x00014000 0x001000>, /* ap 7 */ 4319 <0x00005000 0x00015000 0x001000>, /* ap 8 */ 4320 <0x00008000 0x00018000 0x001000>, /* ap 9 */ 4321 <0x00009000 0x00019000 0x001000>, /* ap 10 */ 4322 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */ 4323 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */ 4324 4325 target-module@0 { /* 0x4ae10000, ap 5 20.0 */ 4326 compatible = "ti,sysc-omap2", "ti,sysc"; 4327 reg = <0x0 0x4>, 4328 <0x10 0x4>, 4329 <0x114 0x4>; 4330 reg-names = "rev", "sysc", "syss"; 4331 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 4332 SYSC_OMAP2_SOFTRESET | 4333 SYSC_OMAP2_AUTOIDLE)>; 4334 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4335 <SYSC_IDLE_NO>, 4336 <SYSC_IDLE_SMART>, 4337 <SYSC_IDLE_SMART_WKUP>; 4338 ti,syss-mask = <1>; 4339 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4340 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>, 4341 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>; 4342 clock-names = "fck", "dbclk"; 4343 #address-cells = <1>; 4344 #size-cells = <1>; 4345 ranges = <0x0 0x0 0x1000>; 4346 4347 gpio1: gpio@0 { 4348 compatible = "ti,omap4-gpio"; 4349 reg = <0x0 0x200>; 4350 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 4351 gpio-controller; 4352 #gpio-cells = <2>; 4353 interrupt-controller; 4354 #interrupt-cells = <2>; 4355 }; 4356 }; 4357 4358 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */ 4359 compatible = "ti,sysc-omap2", "ti,sysc"; 4360 reg = <0x4000 0x4>, 4361 <0x4010 0x4>, 4362 <0x4014 0x4>; 4363 reg-names = "rev", "sysc", "syss"; 4364 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE | 4365 SYSC_OMAP2_SOFTRESET)>; 4366 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4367 <SYSC_IDLE_NO>, 4368 <SYSC_IDLE_SMART>, 4369 <SYSC_IDLE_SMART_WKUP>; 4370 ti,syss-mask = <1>; 4371 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4372 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>; 4373 clock-names = "fck"; 4374 #address-cells = <1>; 4375 #size-cells = <1>; 4376 ranges = <0x0 0x4000 0x1000>; 4377 4378 wdt2: wdt@0 { 4379 compatible = "ti,omap3-wdt"; 4380 reg = <0x0 0x80>; 4381 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 4382 }; 4383 }; 4384 4385 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ 4386 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 4387 reg = <0x8000 0x4>, 4388 <0x8010 0x4>; 4389 reg-names = "rev", "sysc"; 4390 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 4391 SYSC_OMAP4_SOFTRESET)>; 4392 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4393 <SYSC_IDLE_NO>, 4394 <SYSC_IDLE_SMART>, 4395 <SYSC_IDLE_SMART_WKUP>; 4396 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4397 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>; 4398 clock-names = "fck"; 4399 #address-cells = <1>; 4400 #size-cells = <1>; 4401 ranges = <0x0 0x8000 0x1000>; 4402 4403 timer1: timer@0 { 4404 compatible = "ti,omap5430-timer"; 4405 reg = <0x0 0x80>; 4406 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; 4407 clock-names = "fck"; 4408 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4409 ti,timer-alwon; 4410 }; 4411 }; 4412 4413 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ 4414 compatible = "ti,sysc"; 4415 status = "disabled"; 4416 #address-cells = <1>; 4417 #size-cells = <1>; 4418 ranges = <0x0 0xc000 0x1000>; 4419 }; 4420 }; 4421 4422 segment@20000 { /* 0x4ae20000 */ 4423 compatible = "simple-pm-bus"; 4424 #address-cells = <1>; 4425 #size-cells = <1>; 4426 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */ 4427 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */ 4428 <0x00000000 0x00020000 0x001000>, /* ap 19 */ 4429 <0x00001000 0x00021000 0x001000>, /* ap 20 */ 4430 <0x00002000 0x00022000 0x001000>, /* ap 21 */ 4431 <0x00003000 0x00023000 0x001000>, /* ap 22 */ 4432 <0x00007000 0x00027000 0x000400>, /* ap 23 */ 4433 <0x00008000 0x00028000 0x000800>, /* ap 24 */ 4434 <0x00009000 0x00029000 0x000100>, /* ap 25 */ 4435 <0x00008800 0x00028800 0x000200>, /* ap 26 */ 4436 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */ 4437 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */ 4438 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */ 4439 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */ 4440 4441 target-module@0 { /* 0x4ae20000, ap 19 08.0 */ 4442 compatible = "ti,sysc-omap4-timer", "ti,sysc"; 4443 reg = <0x0 0x4>, 4444 <0x10 0x4>; 4445 reg-names = "rev", "sysc"; 4446 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | 4447 SYSC_OMAP4_SOFTRESET)>; 4448 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4449 <SYSC_IDLE_NO>, 4450 <SYSC_IDLE_SMART>, 4451 <SYSC_IDLE_SMART_WKUP>; 4452 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4453 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>; 4454 clock-names = "fck"; 4455 #address-cells = <1>; 4456 #size-cells = <1>; 4457 ranges = <0x0 0x0 0x1000>; 4458 4459 timer12: timer@0 { 4460 compatible = "ti,omap5430-timer"; 4461 reg = <0x0 0x80>; 4462 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 4463 ti,timer-alwon; 4464 ti,timer-secure; 4465 }; 4466 }; 4467 4468 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */ 4469 compatible = "ti,sysc"; 4470 status = "disabled"; 4471 #address-cells = <1>; 4472 #size-cells = <1>; 4473 ranges = <0x0 0x2000 0x1000>; 4474 }; 4475 4476 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */ 4477 compatible = "ti,sysc"; 4478 status = "disabled"; 4479 #address-cells = <1>; 4480 #size-cells = <1>; 4481 ranges = <0x00000000 0x00006000 0x00001000>, 4482 <0x00001000 0x00007000 0x00000400>, 4483 <0x00002000 0x00008000 0x00000800>, 4484 <0x00002800 0x00008800 0x00000200>, 4485 <0x00002a00 0x00008a00 0x00000100>, 4486 <0x00003000 0x00009000 0x00000100>; 4487 }; 4488 4489 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */ 4490 compatible = "ti,sysc-omap2", "ti,sysc"; 4491 reg = <0xb050 0x4>, 4492 <0xb054 0x4>, 4493 <0xb058 0x4>; 4494 reg-names = "rev", "sysc", "syss"; 4495 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | 4496 SYSC_OMAP2_SOFTRESET | 4497 SYSC_OMAP2_AUTOIDLE)>; 4498 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 4499 <SYSC_IDLE_NO>, 4500 <SYSC_IDLE_SMART>, 4501 <SYSC_IDLE_SMART_WKUP>; 4502 ti,syss-mask = <1>; 4503 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */ 4504 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>; 4505 clock-names = "fck"; 4506 #address-cells = <1>; 4507 #size-cells = <1>; 4508 ranges = <0x0 0xb000 0x1000>; 4509 4510 uart10: serial@0 { 4511 compatible = "ti,dra742-uart"; 4512 reg = <0x0 0x100>; 4513 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 4514 clock-frequency = <48000000>; 4515 status = "disabled"; 4516 }; 4517 }; 4518 4519 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ 4520 compatible = "ti,sysc"; 4521 status = "disabled"; 4522 #address-cells = <1>; 4523 #size-cells = <1>; 4524 ranges = <0x0 0xf000 0x1000>; 4525 }; 4526 }; 4527 4528 segment@30000 { /* 0x4ae30000 */ 4529 compatible = "simple-pm-bus"; 4530 #address-cells = <1>; 4531 #size-cells = <1>; 4532 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */ 4533 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */ 4534 <0x00000000 0x00030000 0x001000>, /* ap 33 */ 4535 <0x00001000 0x00031000 0x001000>, /* ap 34 */ 4536 <0x00002000 0x00032000 0x001000>, /* ap 35 */ 4537 <0x00003000 0x00033000 0x001000>, /* ap 36 */ 4538 <0x00004000 0x00034000 0x001000>, /* ap 37 */ 4539 <0x00005000 0x00035000 0x001000>, /* ap 38 */ 4540 <0x00006000 0x00036000 0x001000>, /* ap 39 */ 4541 <0x00007000 0x00037000 0x001000>, /* ap 40 */ 4542 <0x00008000 0x00038000 0x001000>, /* ap 41 */ 4543 <0x00009000 0x00039000 0x001000>, /* ap 42 */ 4544 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */ 4545 4546 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */ 4547 compatible = "ti,sysc"; 4548 status = "disabled"; 4549 #address-cells = <1>; 4550 #size-cells = <1>; 4551 ranges = <0x0 0x1000 0x1000>; 4552 }; 4553 4554 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */ 4555 compatible = "ti,sysc"; 4556 status = "disabled"; 4557 #address-cells = <1>; 4558 #size-cells = <1>; 4559 ranges = <0x0 0x3000 0x1000>; 4560 }; 4561 4562 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */ 4563 compatible = "ti,sysc"; 4564 status = "disabled"; 4565 #address-cells = <1>; 4566 #size-cells = <1>; 4567 ranges = <0x0 0x5000 0x1000>; 4568 }; 4569 4570 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */ 4571 compatible = "ti,sysc"; 4572 status = "disabled"; 4573 #address-cells = <1>; 4574 #size-cells = <1>; 4575 ranges = <0x0 0x7000 0x1000>; 4576 }; 4577 4578 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */ 4579 compatible = "ti,sysc"; 4580 status = "disabled"; 4581 #address-cells = <1>; 4582 #size-cells = <1>; 4583 ranges = <0x0 0x9000 0x1000>; 4584 }; 4585 4586 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */ 4587 compatible = "ti,sysc-omap4", "ti,sysc"; 4588 reg = <0xc020 0x4>; 4589 reg-names = "rev"; 4590 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>; 4591 clock-names = "fck"; 4592 #address-cells = <1>; 4593 #size-cells = <1>; 4594 ranges = <0x0 0xc000 0x2000>; 4595 4596 dcan1: can@0 { 4597 compatible = "ti,dra7-d_can"; 4598 reg = <0x0 0x2000>; 4599 syscon-raminit = <&scm_conf 0x558 0>; 4600 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 4601 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; 4602 status = "disabled"; 4603 }; 4604 }; 4605 }; 4606}; 4607 4608