1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/clk.h>
4 #include <linux/delay.h>
5 #include <linux/gpio/consumer.h>
6 #include <linux/i2c.h>
7 #include <linux/kernel.h>
8 #include <linux/media.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/types.h>
14 #include <linux/videodev2.h>
15 #include <linux/units.h>
16
17 #include <media/media-entity.h>
18 #include <media/v4l2-async.h>
19 #include <media/v4l2-cci.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
24 #include <media/v4l2-mediabus.h>
25
26 /* product information registers */
27 #define IMX111_PRODUCT_ID CCI_REG16(0x0000)
28 #define IMX111_CHIP_ID 0x111
29 #define IMX111_REVISION CCI_REG8(0x0002)
30 #define IMX111_MANUFACTURER_ID CCI_REG8(0x0003)
31 #define IMX111_FRAME_COUNTER CCI_REG8(0x0005)
32 #define IMX111_PIXEL_ORDER CCI_REG8(0x0006)
33
34 /* general configuration registers */
35 #define IMX111_STREAMING_MODE CCI_REG8(0x0100)
36 #define IMX111_MODE_STANDBY 0
37 #define IMX111_MODE_STREAMING 1
38 #define IMX111_IMAGE_ORIENTATION CCI_REG8(0x0101)
39 #define IMX111_IMAGE_HFLIP BIT(0)
40 #define IMX111_IMAGE_VFLIP BIT(1)
41 #define IMX111_SOFTWARE_RESET CCI_REG8(0x0103)
42 #define IMX111_RESET_ON 1
43 #define IMX111_GROUP_WRITE CCI_REG8(0x0104)
44 #define IMX111_GROUP_WRITE_ON 1
45 #define IMX111_FRAME_DROP CCI_REG8(0x0105)
46 #define IMX111_FRAME_DROP_ON 1
47 #define IMX111_CHANNEL_ID CCI_REG8(0x0110)
48 #define IMX111_SIGNALLING_MODE CCI_REG8(0x0111)
49 #define IMX111_DATA_DEPTH CCI_REG16(0x0112)
50 #define IMX111_DATA_DEPTH_RAW8 0x08
51 #define IMX111_DATA_DEPTH_RAW10 0x0a
52
53 /* integration time registers */
54 #define IMX111_INTEGRATION_TIME CCI_REG16(0x0202)
55 #define IMX111_INTEGRATION_TIME_MIN 0x1
56 #define IMX111_INTEGRATION_TIME_MAX 0xffff
57 #define IMX111_INTEGRATION_TIME_STEP 1
58 #define IMX111_INTEGRATION_TIME_OFFSET 5
59
60 /* analog gain control */
61 #define IMX111_REG_ANALOG_GAIN CCI_REG8(0x0205)
62 #define IMX111_ANA_GAIN_MIN 0
63 #define IMX111_ANA_GAIN_MAX 240
64 #define IMX111_ANA_GAIN_STEP 1
65 #define IMX111_ANA_GAIN_DEFAULT 0
66
67 /* digital gain control */
68 #define IMX111_REG_DIG_GAIN_GREENR CCI_REG16(0x020e)
69 #define IMX111_REG_DIG_GAIN_RED CCI_REG16(0x0210)
70 #define IMX111_REG_DIG_GAIN_BLUE CCI_REG16(0x0212)
71 #define IMX111_REG_DIG_GAIN_GREENB CCI_REG16(0x0214)
72 #define IMX111_DGTL_GAIN_MIN 0x0100
73 #define IMX111_DGTL_GAIN_MAX 0x0fff
74 #define IMX111_DGTL_GAIN_DEFAULT 0x0100
75 #define IMX111_DGTL_GAIN_STEP 1
76
77 /* clock configuration registers */
78 #define IMX111_PIXEL_CLK_DIVIDER_PLL1 CCI_REG8(0x0301)
79 #define IMX111_SYSTEM_CLK_DIVIDER_PLL1 CCI_REG8(0x0303)
80 #define IMX111_PRE_PLL_CLK_DIVIDER_PLL1 CCI_REG8(0x0305)
81 #define IMX111_PLL_MULTIPLIER_PLL1 CCI_REG8(0x0307)
82 #define IMX111_PLL_SETTLING_TIME CCI_REG8(0x303c)
83 #define IMX111_PLL_SETTLING_TIME_DEFAULT 200
84 #define IMX111_POST_DIVIDER CCI_REG8(0x30a4)
85 #define IMX111_POST_DIVIDER_DIV1 2
86 #define IMX111_POST_DIVIDER_DIV2 0
87 #define IMX111_POST_DIVIDER_DIV4 1
88
89 /* frame timing registers */
90 #define IMX111_VERTICAL_TOTAL_LENGTH CCI_REG16(0x0340)
91 #define IMX111_VTL_MAX 0x09d8
92 #define IMX111_VBLANK_MIN 16
93 #define IMX111_HORIZONTAL_TOTAL_LENGTH CCI_REG16(0x0342)
94 #define IMX111_HTL_MAX 0x0dd0
95 #define IMX111_HBLANK_MIN 16
96
97 /* image size registers */
98 #define IMX111_HORIZONTAL_START CCI_REG16(0x0344)
99 #define IMX111_VERTICAL_START CCI_REG16(0x0346)
100 #define IMX111_HORIZONTAL_END CCI_REG16(0x0348)
101 #define IMX111_VERTICAL_END CCI_REG16(0x034a)
102 #define IMX111_IMAGE_WIDTH CCI_REG16(0x034c)
103 #define IMX111_IMAGE_HEIGHT CCI_REG16(0x034e)
104 #define IMX111_H_EVEN_INC CCI_REG8(0x0381)
105 #define IMX111_H_ODD_INC CCI_REG8(0x0383)
106 #define IMX111_W_EVEN_INC CCI_REG8(0x0385)
107 #define IMX111_W_ODD_INC CCI_REG8(0x0387)
108
109 /* test pattern registers */
110 #define IMX111_TEST_PATTERN CCI_REG8(0x0601)
111 #define IMX111_TEST_PATTERN_NONE 0
112 #define IMX111_TEST_PATTERN_SOLID 1
113 #define IMX111_TEST_PATTERN_BARS 2
114 #define IMX111_TEST_PATTERN_FADE 3
115 #define IMX111_TEST_PATTERN_PN9 4
116 #define IMX111_SOLID_COLOR_RED CCI_REG16(0x0602)
117 #define IMX111_SOLID_COLOR_GR CCI_REG16(0x0604)
118 #define IMX111_SOLID_COLOR_BLUE CCI_REG16(0x0606)
119 #define IMX111_SOLID_COLOR_GB CCI_REG16(0x0608)
120 #define IMX111_TESTP_COLOUR_MIN 0
121 #define IMX111_TESTP_COLOUR_MAX 0x03ff
122 #define IMX111_TESTP_COLOUR_STEP 1
123
124 #define IMX111_FRAME_RATE_STEP 5
125
126 #define IMX111_PIXEL_ARRAY_WIDTH 3280U
127 #define IMX111_PIXEL_ARRAY_HEIGHT 2464U
128
129 enum {
130 IMX111_MODE_3280x2464,
131 IMX111_MODE_3280x1848,
132 IMX111_MODE_3280x1098,
133 IMX111_MODE_2100x1200,
134 IMX111_MODE_1952x1098,
135 IMX111_MODE_1920x1080,
136 IMX111_MODE_1640x1232,
137 IMX111_MODE_1440x1080,
138 IMX111_MODE_1640x924,
139 IMX111_MODE_1308x736,
140 IMX111_MODE_1280x720,
141 IMX111_MODE_820x614,
142 IMX111_MODE_640x480,
143 };
144
145 static const struct regulator_bulk_data imx111_supplies[] = {
146 { .supply = "iovdd" },
147 { .supply = "dvdd" },
148 { .supply = "avdd" },
149 };
150
151 struct imx111_mode {
152 u32 width;
153 u32 height;
154
155 /* Default vertical and horizontal total length */
156 u32 vtl_def;
157 u32 htl_def;
158
159 struct {
160 const struct cci_reg_sequence *regs;
161 u32 num_of_regs;
162 } reg_list;
163 };
164
165 struct imx111_pll {
166 u64 extclk_rate;
167 u8 pre_div;
168 u8 mult;
169 };
170
171 struct imx111 {
172 struct regmap *regmap;
173
174 struct clk *extclk;
175 struct gpio_desc *reset;
176 struct regulator_bulk_data *supplies;
177
178 struct v4l2_fwnode_endpoint bus_cfg;
179 struct v4l2_subdev sd;
180 struct media_pad pad;
181
182 /* V4L2 Controls */
183 struct v4l2_ctrl_handler hdl;
184 struct v4l2_ctrl *pixel_rate;
185 struct v4l2_ctrl *link_freq;
186 struct v4l2_ctrl *exposure;
187 struct v4l2_ctrl *vblank;
188 struct v4l2_ctrl *hblank;
189 struct v4l2_ctrl *hflip;
190 struct v4l2_ctrl *vflip;
191
192 /* Current mode */
193 const struct imx111_mode *cur_mode;
194 const struct imx111_pll *pll;
195 u32 data_depth;
196
197 u64 pixel_clk_raw;
198 s64 default_link_freq;
199 };
200
201 static const struct imx111_pll imx111_pll[] = {
202 { .extclk_rate = 6000000, .pre_div = 1, .mult = 113, },
203 { .extclk_rate = 12000000, .pre_div = 2, .mult = 113, },
204 { .extclk_rate = 13500000, .pre_div = 1, .mult = 50, },
205 { .extclk_rate = 18000000, .pre_div = 2, .mult = 75, },
206 { .extclk_rate = 24000000, .pre_div = 4, .mult = 113, },
207 { .extclk_rate = 27000000, .pre_div = 2, .mult = 50, },
208 { .extclk_rate = 36000000, .pre_div = 4, .mult = 75, },
209 { .extclk_rate = 54000000, .pre_div = 4, .mult = 50, },
210 };
211
212 /*
213 * This table MUST contain 4 entries per format, to cover the various flip
214 * combinations in the order
215 * - no flip
216 * - h flip
217 * - v flip
218 * - h&v flips
219 */
220 static const u32 imx111_mbus_formats[] = {
221 MEDIA_BUS_FMT_SGBRG10_1X10,
222 MEDIA_BUS_FMT_SBGGR10_1X10,
223 MEDIA_BUS_FMT_SRGGB10_1X10,
224 MEDIA_BUS_FMT_SGRBG10_1X10,
225
226 MEDIA_BUS_FMT_SGBRG8_1X8,
227 MEDIA_BUS_FMT_SBGGR8_1X8,
228 MEDIA_BUS_FMT_SRGGB8_1X8,
229 MEDIA_BUS_FMT_SGRBG8_1X8,
230 };
231
232 static const struct cci_reg_sequence imx111_global_init[] = {
233 { CCI_REG8(0x3080), 0x50 },
234 { CCI_REG8(0x3087), 0x53 },
235 { CCI_REG8(0x309d), 0x94 },
236 { CCI_REG8(0x30b1), 0x03 },
237 { CCI_REG8(0x30c6), 0x00 },
238 { CCI_REG8(0x30c7), 0x00 },
239 { CCI_REG8(0x3115), 0x0b },
240 { CCI_REG8(0x3118), 0x30 },
241 { CCI_REG8(0x311d), 0x25 },
242 { CCI_REG8(0x3121), 0x0a },
243 { CCI_REG8(0x3212), 0xf2 },
244 { CCI_REG8(0x3213), 0x0f },
245 { CCI_REG8(0x3215), 0x0f },
246 { CCI_REG8(0x3217), 0x0b },
247 { CCI_REG8(0x3219), 0x0b },
248 { CCI_REG8(0x321b), 0x0d },
249 { CCI_REG8(0x321d), 0x0d },
250 { CCI_REG8(0x32aa), 0x11 },
251 { CCI_REG8(0x3032), 0x40 },
252 };
253
254 static const struct cci_reg_sequence mode_820x614[] = {
255 { IMX111_GROUP_WRITE, 1 },
256 { IMX111_HORIZONTAL_START, 0x0008 }, { IMX111_VERTICAL_START, 0x0034 },
257 { IMX111_HORIZONTAL_END, 0x0cd7 }, { IMX111_VERTICAL_END, 0x09cb },
258 { IMX111_IMAGE_WIDTH, 0x0334 }, { IMX111_IMAGE_HEIGHT, 0x0266 },
259 { IMX111_GROUP_WRITE, 0 },
260 { IMX111_H_EVEN_INC, 0x05 }, { IMX111_H_ODD_INC, 0x03 },
261 { IMX111_W_EVEN_INC, 0x05 }, { IMX111_W_ODD_INC, 0x03 },
262 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x10 },
263 { CCI_REG8(0x303e), 0x40 }, { CCI_REG8(0x3040), 0x08 },
264 { CCI_REG8(0x3041), 0x97 }, { CCI_REG8(0x3048), 0x01 },
265 { CCI_REG8(0x304c), 0x6f }, { CCI_REG8(0x304d), 0x03 },
266 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0x00 },
267 { CCI_REG8(0x3074), 0x11 }, { CCI_REG8(0x3075), 0x11 },
268 { CCI_REG8(0x3076), 0x11 }, { CCI_REG8(0x3077), 0x11 },
269 { CCI_REG8(0x3079), 0x00 }, { CCI_REG8(0x307a), 0x00 },
270 { CCI_REG8(0x309b), 0x28 }, { CCI_REG8(0x309c), 0x13 },
271 { CCI_REG8(0x309e), 0x00 }, { CCI_REG8(0x30a0), 0x14 },
272 { CCI_REG8(0x30a1), 0x09 }, { CCI_REG8(0x30aa), 0x03 },
273 { CCI_REG8(0x30b2), 0x03 }, { CCI_REG8(0x30d5), 0x09 },
274 { CCI_REG8(0x30d6), 0x00 }, { CCI_REG8(0x30d7), 0x00 },
275 { CCI_REG8(0x30d8), 0x00 }, { CCI_REG8(0x30d9), 0x00 },
276 { CCI_REG8(0x30de), 0x04 }, { CCI_REG8(0x30df), 0x20 },
277 { CCI_REG8(0x3102), 0x08 }, { CCI_REG8(0x3103), 0x22 },
278 { CCI_REG8(0x3104), 0x20 }, { CCI_REG8(0x3105), 0x00 },
279 { CCI_REG8(0x3106), 0x87 }, { CCI_REG8(0x3107), 0x00 },
280 { CCI_REG8(0x3108), 0x03 }, { CCI_REG8(0x3109), 0x02 },
281 { CCI_REG8(0x310a), 0x03 }, { CCI_REG8(0x315c), 0x9c },
282 { CCI_REG8(0x315d), 0x9b }, { CCI_REG8(0x316e), 0x9d },
283 { CCI_REG8(0x316f), 0x9c }, { CCI_REG8(0x3318), 0x7a },
284 { CCI_REG8(0x3348), 0xe0 },
285 };
286
287 static const struct cci_reg_sequence mode_1308x736[] = {
288 { IMX111_GROUP_WRITE, 1 },
289 { IMX111_HORIZONTAL_START, 0x0154 }, { IMX111_VERTICAL_START, 0x0220 },
290 { IMX111_HORIZONTAL_END, 0x0b8b }, { IMX111_VERTICAL_END, 0x07df },
291 { IMX111_IMAGE_WIDTH, 0x051c }, { IMX111_IMAGE_HEIGHT, 0x02e0 },
292 { IMX111_GROUP_WRITE, 0 },
293 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x01 },
294 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x03 },
295 { CCI_REG8(0x3033), 0x84 }, { CCI_REG8(0x303d), 0x10 },
296 { CCI_REG8(0x303e), 0x40 }, { CCI_REG8(0x3040), 0x08 },
297 { CCI_REG8(0x3041), 0x97 }, { CCI_REG8(0x3048), 0x01 },
298 { CCI_REG8(0x304c), 0xd7 }, { CCI_REG8(0x304d), 0x01 },
299 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0x00 },
300 { CCI_REG8(0x3074), 0x11 }, { CCI_REG8(0x3075), 0x11 },
301 { CCI_REG8(0x3076), 0x11 }, { CCI_REG8(0x3077), 0x11 },
302 { CCI_REG8(0x3079), 0x00 }, { CCI_REG8(0x307a), 0x00 },
303 { CCI_REG8(0x309b), 0x48 }, { CCI_REG8(0x309c), 0x12 },
304 { CCI_REG8(0x309e), 0x04 }, { CCI_REG8(0x30a0), 0x14 },
305 { CCI_REG8(0x30a1), 0x0a }, { CCI_REG8(0x30aa), 0x01 },
306 { CCI_REG8(0x30b2), 0x05 }, { CCI_REG8(0x30d5), 0x04 },
307 { CCI_REG8(0x30d6), 0x85 }, { CCI_REG8(0x30d7), 0x2a },
308 { CCI_REG8(0x30d8), 0x64 }, { CCI_REG8(0x30d9), 0x89 },
309 { CCI_REG8(0x30de), 0x00 }, { CCI_REG8(0x30df), 0x20 },
310 { CCI_REG8(0x3102), 0x08 }, { CCI_REG8(0x3103), 0x22 },
311 { CCI_REG8(0x3104), 0x20 }, { CCI_REG8(0x3105), 0x00 },
312 { CCI_REG8(0x3106), 0x87 }, { CCI_REG8(0x3107), 0x00 },
313 { CCI_REG8(0x3108), 0x03 }, { CCI_REG8(0x3109), 0x02 },
314 { CCI_REG8(0x310a), 0x03 }, { CCI_REG8(0x315c), 0x42 },
315 { CCI_REG8(0x315d), 0x41 }, { CCI_REG8(0x316e), 0x43 },
316 { CCI_REG8(0x316f), 0x42 }, { CCI_REG8(0x3318), 0x62 },
317 { CCI_REG8(0x3348), 0xe0 },
318 };
319
320 static const struct cci_reg_sequence mode_1640x924[] = {
321 { IMX111_GROUP_WRITE, 1 },
322 { IMX111_HORIZONTAL_START, 0x0008 }, { IMX111_VERTICAL_START, 0x0164 },
323 { IMX111_HORIZONTAL_END, 0x0cd7 }, { IMX111_VERTICAL_END, 0x089b },
324 { IMX111_IMAGE_WIDTH, 0x0668 }, { IMX111_IMAGE_HEIGHT, 0x039c },
325 { IMX111_GROUP_WRITE, 0 },
326 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x03 },
327 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x03 },
328 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x10 },
329 { CCI_REG8(0x303e), 0x40 }, { CCI_REG8(0x3040), 0x08 },
330 { CCI_REG8(0x3041), 0x97 }, { CCI_REG8(0x3048), 0x01 },
331 { CCI_REG8(0x304c), 0x6f }, { CCI_REG8(0x304d), 0x03 },
332 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0x00 },
333 { CCI_REG8(0x3074), 0x11 }, { CCI_REG8(0x3075), 0x11 },
334 { CCI_REG8(0x3076), 0x11 }, { CCI_REG8(0x3077), 0x11 },
335 { CCI_REG8(0x3079), 0x00 }, { CCI_REG8(0x307a), 0x00 },
336 { CCI_REG8(0x309b), 0x28 }, { CCI_REG8(0x309c), 0x13 },
337 { CCI_REG8(0x309e), 0x00 }, { CCI_REG8(0x30a0), 0x14 },
338 { CCI_REG8(0x30a1), 0x09 }, { CCI_REG8(0x30aa), 0x03 },
339 { CCI_REG8(0x30b2), 0x05 }, { CCI_REG8(0x30d5), 0x09 },
340 { CCI_REG8(0x30d6), 0x01 }, { CCI_REG8(0x30d7), 0x01 },
341 { CCI_REG8(0x30d8), 0x64 }, { CCI_REG8(0x30d9), 0x89 },
342 { CCI_REG8(0x30de), 0x02 }, { CCI_REG8(0x30df), 0x20 },
343 { CCI_REG8(0x3102), 0x08 }, { CCI_REG8(0x3103), 0x22 },
344 { CCI_REG8(0x3104), 0x20 }, { CCI_REG8(0x3105), 0x00 },
345 { CCI_REG8(0x3106), 0x87 }, { CCI_REG8(0x3107), 0x00 },
346 { CCI_REG8(0x3108), 0x03 }, { CCI_REG8(0x3109), 0x02 },
347 { CCI_REG8(0x310a), 0x03 }, { CCI_REG8(0x315c), 0x9c },
348 { CCI_REG8(0x315d), 0x9b }, { CCI_REG8(0x316e), 0x9d },
349 { CCI_REG8(0x316f), 0x9c }, { CCI_REG8(0x3318), 0x72 },
350 { CCI_REG8(0x3348), 0xe0 },
351 };
352
353 static const struct cci_reg_sequence mode_1640x1232[] = {
354 { IMX111_GROUP_WRITE, 1 },
355 { IMX111_HORIZONTAL_START, 0x0008 }, { IMX111_VERTICAL_START, 0x0030 },
356 { IMX111_HORIZONTAL_END, 0x0cd7 }, { IMX111_VERTICAL_END, 0x09cf },
357 { IMX111_IMAGE_WIDTH, 0x0668 }, { IMX111_IMAGE_HEIGHT, 0x04d0 },
358 { IMX111_GROUP_WRITE, 0 },
359 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x03 },
360 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x03 },
361 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x10 },
362 { CCI_REG8(0x303e), 0x40 }, { CCI_REG8(0x3040), 0x08 },
363 { CCI_REG8(0x3041), 0x97 }, { CCI_REG8(0x3048), 0x01 },
364 { CCI_REG8(0x304c), 0x6f }, { CCI_REG8(0x304d), 0x03 },
365 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0x00 },
366 { CCI_REG8(0x3074), 0x11 }, { CCI_REG8(0x3075), 0x11 },
367 { CCI_REG8(0x3076), 0x11 }, { CCI_REG8(0x3077), 0x11 },
368 { CCI_REG8(0x3079), 0x00 }, { CCI_REG8(0x307a), 0x00 },
369 { CCI_REG8(0x309b), 0x28 }, { CCI_REG8(0x309c), 0x13 },
370 { CCI_REG8(0x309e), 0x00 }, { CCI_REG8(0x30a0), 0x14 },
371 { CCI_REG8(0x30a1), 0x09 }, { CCI_REG8(0x30aa), 0x03 },
372 { CCI_REG8(0x30b2), 0x05 }, { CCI_REG8(0x30d5), 0x09 },
373 { CCI_REG8(0x30d6), 0x01 }, { CCI_REG8(0x30d7), 0x01 },
374 { CCI_REG8(0x30d8), 0x64 }, { CCI_REG8(0x30d9), 0x89 },
375 { CCI_REG8(0x30de), 0x02 }, { CCI_REG8(0x30df), 0x20 },
376 { CCI_REG8(0x3102), 0x08 }, { CCI_REG8(0x3103), 0x22 },
377 { CCI_REG8(0x3104), 0x20 }, { CCI_REG8(0x3105), 0x00 },
378 { CCI_REG8(0x3106), 0x87 }, { CCI_REG8(0x3107), 0x00 },
379 { CCI_REG8(0x3108), 0x03 }, { CCI_REG8(0x3109), 0x02 },
380 { CCI_REG8(0x310a), 0x03 }, { CCI_REG8(0x315c), 0x9c },
381 { CCI_REG8(0x315d), 0x9b }, { CCI_REG8(0x316e), 0x9d },
382 { CCI_REG8(0x316f), 0x9c }, { CCI_REG8(0x3318), 0x72 },
383 { CCI_REG8(0x3348), 0xe0 },
384 };
385
386 static const struct cci_reg_sequence mode_1952x1098[] = {
387 { IMX111_GROUP_WRITE, 1 },
388 { IMX111_HORIZONTAL_START, 0x0016 }, { IMX111_VERTICAL_START, 0x016e },
389 { IMX111_HORIZONTAL_END, 0x0ccb }, { IMX111_VERTICAL_END, 0x0893 },
390 { IMX111_IMAGE_WIDTH, 0x07a0 }, { IMX111_IMAGE_HEIGHT, 0x044a },
391 { IMX111_GROUP_WRITE, 0 },
392 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x01 },
393 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x01 },
394 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x10 },
395 { CCI_REG8(0x303e), 0x00 }, { CCI_REG8(0x3040), 0x08 },
396 { CCI_REG8(0x3041), 0x91 }, { CCI_REG8(0x3048), 0x00 },
397 { CCI_REG8(0x304c), 0x67 }, { CCI_REG8(0x304d), 0x03 },
398 { CCI_REG8(0x3064), 0x10 }, { CCI_REG8(0x3073), 0xa0 },
399 { CCI_REG8(0x3074), 0x12 }, { CCI_REG8(0x3075), 0x12 },
400 { CCI_REG8(0x3076), 0x12 }, { CCI_REG8(0x3077), 0x11 },
401 { CCI_REG8(0x3079), 0x0a }, { CCI_REG8(0x307a), 0x0a },
402 { CCI_REG8(0x309b), 0x60 }, { CCI_REG8(0x309e), 0x04 },
403 { CCI_REG8(0x30a0), 0x15 }, { CCI_REG8(0x30a1), 0x08 },
404 { CCI_REG8(0x30aa), 0x03 }, { CCI_REG8(0x30b2), 0x05 },
405 { CCI_REG8(0x30d5), 0x20 }, { CCI_REG8(0x30d6), 0x85 },
406 { CCI_REG8(0x30d7), 0x2a }, { CCI_REG8(0x30d8), 0x64 },
407 { CCI_REG8(0x30d9), 0x89 }, { CCI_REG8(0x30de), 0x00 },
408 { CCI_REG8(0x30df), 0x21 }, { CCI_REG8(0x3102), 0x08 },
409 { CCI_REG8(0x3103), 0x1d }, { CCI_REG8(0x3104), 0x1e },
410 { CCI_REG8(0x3105), 0x00 }, { CCI_REG8(0x3106), 0x74 },
411 { CCI_REG8(0x3107), 0x00 }, { CCI_REG8(0x3108), 0x03 },
412 { CCI_REG8(0x3109), 0x02 }, { CCI_REG8(0x310a), 0x03 },
413 { CCI_REG8(0x315c), 0x37 }, { CCI_REG8(0x315d), 0x36 },
414 { CCI_REG8(0x316e), 0x38 }, { CCI_REG8(0x316f), 0x37 },
415 { CCI_REG8(0x3318), 0x63 }, { CCI_REG8(0x3348), 0xA0 },
416 };
417
418 static const struct cci_reg_sequence mode_2100x1200[] = {
419 { IMX111_GROUP_WRITE, 1 },
420 { IMX111_HORIZONTAL_START, 0x0256 }, { IMX111_VERTICAL_START, 0x02a8 },
421 { IMX111_HORIZONTAL_END, 0x0a89 }, { IMX111_VERTICAL_END, 0x0757 },
422 { IMX111_IMAGE_WIDTH, 0x0834 }, { IMX111_IMAGE_HEIGHT, 0x04b0 },
423 { IMX111_GROUP_WRITE, 0 },
424 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x01 },
425 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x01 },
426 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x10 },
427 { CCI_REG8(0x303e), 0x40 }, { CCI_REG8(0x3040), 0x08 },
428 { CCI_REG8(0x3041), 0x97 }, { CCI_REG8(0x3048), 0x00 },
429 { CCI_REG8(0x304c), 0x6f }, { CCI_REG8(0x304d), 0x03 },
430 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0x00 },
431 { CCI_REG8(0x3074), 0x11 }, { CCI_REG8(0x3075), 0x11 },
432 { CCI_REG8(0x3076), 0x11 }, { CCI_REG8(0x3077), 0x11 },
433 { CCI_REG8(0x3079), 0x00 }, { CCI_REG8(0x307a), 0x00 },
434 { CCI_REG8(0x309b), 0x20 }, { CCI_REG8(0x309c), 0x13 },
435 { CCI_REG8(0x309e), 0x00 }, { CCI_REG8(0x30a0), 0x14 },
436 { CCI_REG8(0x30a1), 0x08 }, { CCI_REG8(0x30aa), 0x03 },
437 { CCI_REG8(0x30b2), 0x07 }, { CCI_REG8(0x30d5), 0x00 },
438 { CCI_REG8(0x30d6), 0x85 }, { CCI_REG8(0x30d7), 0x2a },
439 { CCI_REG8(0x30d8), 0x64 }, { CCI_REG8(0x30d9), 0x89 },
440 { CCI_REG8(0x30de), 0x00 }, { CCI_REG8(0x30df), 0x20 },
441 { CCI_REG8(0x3102), 0x08 }, { CCI_REG8(0x3103), 0x22 },
442 { CCI_REG8(0x3104), 0x20 }, { CCI_REG8(0x3105), 0x00 },
443 { CCI_REG8(0x3106), 0x87 }, { CCI_REG8(0x3107), 0x00 },
444 { CCI_REG8(0x3108), 0x03 }, { CCI_REG8(0x3109), 0x02 },
445 { CCI_REG8(0x310a), 0x03 }, { CCI_REG8(0x315c), 0x9c },
446 { CCI_REG8(0x315d), 0x9b }, { CCI_REG8(0x316e), 0x9d },
447 { CCI_REG8(0x316f), 0x9c }, { CCI_REG8(0x3318), 0x62 },
448 { CCI_REG8(0x3348), 0xe0 },
449 };
450
451 static const struct cci_reg_sequence mode_3280x1098[] = {
452 { IMX111_GROUP_WRITE, 1 },
453 { IMX111_HORIZONTAL_START, 0x0008 }, { IMX111_VERTICAL_START, 0x01f6 },
454 { IMX111_HORIZONTAL_END, 0x0cd7 }, { IMX111_VERTICAL_END, 0x080b },
455 { IMX111_IMAGE_WIDTH, 0x0cd0 }, { IMX111_IMAGE_HEIGHT, 0x044a },
456 { IMX111_GROUP_WRITE, 0 },
457 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x01 },
458 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x01 },
459 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x10 },
460 { CCI_REG8(0x303e), 0x40 }, { CCI_REG8(0x3040), 0x08 },
461 { CCI_REG8(0x3041), 0x93 }, { CCI_REG8(0x3048), 0x00 },
462 { CCI_REG8(0x304c), 0x67 }, { CCI_REG8(0x304d), 0x03 },
463 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0xe0 },
464 { CCI_REG8(0x3074), 0x12 }, { CCI_REG8(0x3075), 0x12 },
465 { CCI_REG8(0x3076), 0x12 }, { CCI_REG8(0x3077), 0x12 },
466 { CCI_REG8(0x3079), 0x2a }, { CCI_REG8(0x307a), 0x0a },
467 { CCI_REG8(0x309b), 0x60 }, { CCI_REG8(0x309e), 0x04 },
468 { CCI_REG8(0x30a0), 0x15 }, { CCI_REG8(0x30a1), 0x08 },
469 { CCI_REG8(0x30aa), 0x03 }, { CCI_REG8(0x30b2), 0x05 },
470 { CCI_REG8(0x30d5), 0x00 }, { CCI_REG8(0x30d6), 0x85 },
471 { CCI_REG8(0x30d7), 0x2a }, { CCI_REG8(0x30d8), 0x64 },
472 { CCI_REG8(0x30d9), 0x89 }, { CCI_REG8(0x30de), 0x00 },
473 { CCI_REG8(0x30df), 0x20 }, { CCI_REG8(0x3102), 0x08 },
474 { CCI_REG8(0x3103), 0x1d }, { CCI_REG8(0x3104), 0x1e },
475 { CCI_REG8(0x3105), 0x00 }, { CCI_REG8(0x3106), 0x74 },
476 { CCI_REG8(0x3107), 0x00 }, { CCI_REG8(0x3108), 0x03 },
477 { CCI_REG8(0x3109), 0x02 }, { CCI_REG8(0x310a), 0x03 },
478 { CCI_REG8(0x315c), 0x37 }, { CCI_REG8(0x315d), 0x36 },
479 { CCI_REG8(0x316e), 0x38 }, { CCI_REG8(0x316f), 0x37 },
480 { CCI_REG8(0x3318), 0x63 }, { CCI_REG8(0x3348), 0xe0 },
481 };
482
483 static const struct cci_reg_sequence mode_3280x1848[] = {
484 { IMX111_GROUP_WRITE, 1 },
485 { IMX111_HORIZONTAL_START, 0x0008 }, { IMX111_VERTICAL_START, 0x0164 },
486 { IMX111_HORIZONTAL_END, 0x0cd7 }, { IMX111_VERTICAL_END, 0x089b },
487 { IMX111_IMAGE_WIDTH, 0x0cd0 }, { IMX111_IMAGE_HEIGHT, 0x0738 },
488 { IMX111_GROUP_WRITE, 0 },
489 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x01 },
490 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x01 },
491 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x00 },
492 { CCI_REG8(0x303e), 0x41 }, { CCI_REG8(0x3040), 0x08 },
493 { CCI_REG8(0x3041), 0x97 }, { CCI_REG8(0x3048), 0x00 },
494 { CCI_REG8(0x304c), 0x6f }, { CCI_REG8(0x304d), 0x03 },
495 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0x00 },
496 { CCI_REG8(0x3074), 0x11 }, { CCI_REG8(0x3075), 0x11 },
497 { CCI_REG8(0x3076), 0x11 }, { CCI_REG8(0x3077), 0x11 },
498 { CCI_REG8(0x3079), 0x00 }, { CCI_REG8(0x307a), 0x00 },
499 { CCI_REG8(0x309b), 0x20 }, { CCI_REG8(0x309c), 0x13 },
500 { CCI_REG8(0x309e), 0x00 }, { CCI_REG8(0x30a0), 0x14 },
501 { CCI_REG8(0x30a1), 0x08 }, { CCI_REG8(0x30aa), 0x03 },
502 { CCI_REG8(0x30b2), 0x07 }, { CCI_REG8(0x30d5), 0x00 },
503 { CCI_REG8(0x30d6), 0x85 }, { CCI_REG8(0x30d7), 0x2a },
504 { CCI_REG8(0x30d8), 0x64 }, { CCI_REG8(0x30d9), 0x89 },
505 { CCI_REG8(0x30de), 0x00 }, { CCI_REG8(0x30df), 0x20 },
506 { CCI_REG8(0x3102), 0x10 }, { CCI_REG8(0x3103), 0x44 },
507 { CCI_REG8(0x3104), 0x40 }, { CCI_REG8(0x3105), 0x00 },
508 { CCI_REG8(0x3106), 0x0d }, { CCI_REG8(0x3107), 0x01 },
509 { CCI_REG8(0x3108), 0x09 }, { CCI_REG8(0x3109), 0x08 },
510 { CCI_REG8(0x310a), 0x0f }, { CCI_REG8(0x315c), 0x5d },
511 { CCI_REG8(0x315d), 0x5c }, { CCI_REG8(0x316e), 0x5e },
512 { CCI_REG8(0x316f), 0x5d }, { CCI_REG8(0x3318), 0x60 },
513 { CCI_REG8(0x3348), 0xe0 },
514 };
515
516 static const struct cci_reg_sequence mode_3280x2464[] = {
517 { IMX111_GROUP_WRITE, 1 },
518 { IMX111_HORIZONTAL_START, 0x0008 }, { IMX111_VERTICAL_START, 0x0030 },
519 { IMX111_HORIZONTAL_END, 0x0cd7 }, { IMX111_VERTICAL_END, 0x09cf },
520 { IMX111_IMAGE_WIDTH, 0x0cd0 }, { IMX111_IMAGE_HEIGHT, 0x09a0 },
521 { IMX111_GROUP_WRITE, 0 },
522 { IMX111_H_EVEN_INC, 0x01 }, { IMX111_H_ODD_INC, 0x01 },
523 { IMX111_W_EVEN_INC, 0x01 }, { IMX111_W_ODD_INC, 0x01 },
524 { CCI_REG8(0x3033), 0x00 }, { CCI_REG8(0x303d), 0x00 },
525 { CCI_REG8(0x303e), 0x41 }, { CCI_REG8(0x3040), 0x08 },
526 { CCI_REG8(0x3041), 0x97 }, { CCI_REG8(0x3048), 0x00 },
527 { CCI_REG8(0x304c), 0x6f }, { CCI_REG8(0x304d), 0x03 },
528 { CCI_REG8(0x3064), 0x12 }, { CCI_REG8(0x3073), 0x00 },
529 { CCI_REG8(0x3074), 0x11 }, { CCI_REG8(0x3075), 0x11 },
530 { CCI_REG8(0x3076), 0x11 }, { CCI_REG8(0x3077), 0x11 },
531 { CCI_REG8(0x3079), 0x00 }, { CCI_REG8(0x307a), 0x00 },
532 { CCI_REG8(0x309b), 0x20 }, { CCI_REG8(0x309c), 0x13 },
533 { CCI_REG8(0x309e), 0x00 }, { CCI_REG8(0x30a0), 0x14 },
534 { CCI_REG8(0x30a1), 0x08 }, { CCI_REG8(0x30aa), 0x03 },
535 { CCI_REG8(0x30b2), 0x07 }, { CCI_REG8(0x30d5), 0x00 },
536 { CCI_REG8(0x30d6), 0x85 }, { CCI_REG8(0x30d7), 0x2a },
537 { CCI_REG8(0x30d8), 0x64 }, { CCI_REG8(0x30d9), 0x89 },
538 { CCI_REG8(0x30de), 0x00 }, { CCI_REG8(0x30df), 0x20 },
539 { CCI_REG8(0x3102), 0x10 }, { CCI_REG8(0x3103), 0x44 },
540 { CCI_REG8(0x3104), 0x40 }, { CCI_REG8(0x3105), 0x00 },
541 { CCI_REG8(0x3106), 0x0d }, { CCI_REG8(0x3107), 0x01 },
542 { CCI_REG8(0x3108), 0x09 }, { CCI_REG8(0x3109), 0x08 },
543 { CCI_REG8(0x310a), 0x0f }, { CCI_REG8(0x315c), 0x5d },
544 { CCI_REG8(0x315d), 0x5c }, { CCI_REG8(0x316e), 0x5e },
545 { CCI_REG8(0x316f), 0x5d }, { CCI_REG8(0x3318), 0x60 },
546 { CCI_REG8(0x3348), 0xe0 },
547 };
548
549 static const struct imx111_mode imx111_modes[] = {
550 [IMX111_MODE_3280x2464] = {
551 .width = 3280,
552 .height = 2464,
553 .vtl_def = 2490,
554 .htl_def = 3536,
555 .reg_list = {
556 .regs = mode_3280x2464,
557 .num_of_regs = ARRAY_SIZE(mode_3280x2464),
558 },
559 },
560 [IMX111_MODE_3280x1848] = {
561 .width = 3280,
562 .height = 1848,
563 .vtl_def = 1874,
564 .htl_def = 3536,
565 .reg_list = {
566 .regs = mode_3280x1848,
567 .num_of_regs = ARRAY_SIZE(mode_3280x1848),
568 },
569 },
570 [IMX111_MODE_3280x1098] = {
571 .width = 3280,
572 .height = 1098,
573 .vtl_def = 1130,
574 .htl_def = 3500,
575 .reg_list = {
576 .regs = mode_3280x1098,
577 .num_of_regs = ARRAY_SIZE(mode_3280x1098),
578 },
579 },
580 [IMX111_MODE_2100x1200] = {
581 .width = 2100,
582 .height = 1200,
583 .vtl_def = 1260,
584 .htl_def = 3536,
585 .reg_list = {
586 .regs = mode_2100x1200,
587 .num_of_regs = ARRAY_SIZE(mode_2100x1200),
588 },
589 },
590 [IMX111_MODE_1952x1098] = {
591 .width = 1952,
592 .height = 1098,
593 .vtl_def = 1884,
594 .htl_def = 3500,
595 .reg_list = {
596 .regs = mode_1952x1098,
597 .num_of_regs = ARRAY_SIZE(mode_1952x1098),
598 },
599 },
600 [IMX111_MODE_1920x1080] = {
601 .width = 1920,
602 .height = 1080,
603 .vtl_def = 1884,
604 .htl_def = 3500,
605 .reg_list = {
606 .regs = mode_1952x1098,
607 .num_of_regs = ARRAY_SIZE(mode_1952x1098),
608 },
609 },
610 [IMX111_MODE_1640x1232] = {
611 .width = 1640,
612 .height = 1232,
613 .vtl_def = 1254,
614 .htl_def = 3536,
615 .reg_list = {
616 .regs = mode_1640x1232,
617 .num_of_regs = ARRAY_SIZE(mode_1640x1232),
618 },
619 },
620 [IMX111_MODE_1440x1080] = {
621 .width = 1440,
622 .height = 1080,
623 .vtl_def = 1254,
624 .htl_def = 3536,
625 .reg_list = {
626 .regs = mode_1640x1232,
627 .num_of_regs = ARRAY_SIZE(mode_1640x1232),
628 },
629 },
630 [IMX111_MODE_1640x924] = {
631 .width = 1640,
632 .height = 924,
633 .vtl_def = 946,
634 .htl_def = 3536,
635 .reg_list = {
636 .regs = mode_1640x924,
637 .num_of_regs = ARRAY_SIZE(mode_1640x924),
638 },
639 },
640 [IMX111_MODE_1308x736] = {
641 .width = 1308,
642 .height = 736,
643 .vtl_def = 2369,
644 .htl_def = 1896,
645 .reg_list = {
646 .regs = mode_1308x736,
647 .num_of_regs = ARRAY_SIZE(mode_1308x736),
648 },
649 },
650 [IMX111_MODE_1280x720] = {
651 .width = 1280,
652 .height = 720,
653 .vtl_def = 2369,
654 .htl_def = 1896,
655 .reg_list = {
656 .regs = mode_1308x736,
657 .num_of_regs = ARRAY_SIZE(mode_1308x736),
658 },
659 },
660 [IMX111_MODE_820x614] = {
661 .width = 820,
662 .height = 614,
663 .vtl_def = 1260,
664 .htl_def = 3536,
665 .reg_list = {
666 .regs = mode_820x614,
667 .num_of_regs = ARRAY_SIZE(mode_820x614),
668 },
669 },
670 [IMX111_MODE_640x480] = {
671 .width = 640,
672 .height = 480,
673 .vtl_def = 1260,
674 .htl_def = 3536,
675 .reg_list = {
676 .regs = mode_820x614,
677 .num_of_regs = ARRAY_SIZE(mode_820x614),
678 },
679 },
680 };
681
sd_to_imx111(struct v4l2_subdev * sd)682 static inline struct imx111 *sd_to_imx111(struct v4l2_subdev *sd)
683 {
684 return container_of_const(sd, struct imx111, sd);
685 }
686
ctrl_to_imx111(struct v4l2_ctrl * ctrl)687 static inline struct imx111 *ctrl_to_imx111(struct v4l2_ctrl *ctrl)
688 {
689 return container_of_const(ctrl->handler, struct imx111, hdl);
690 }
691
to_settle_delay(u64 extclk_rate)692 static u8 to_settle_delay(u64 extclk_rate)
693 {
694 u64 extclk_mhz = div_u64(extclk_rate, MEGA);
695
696 return DIV_ROUND_UP(IMX111_PLL_SETTLING_TIME_DEFAULT * extclk_mhz - 63,
697 64);
698 }
699
imx111_get_format_code(struct imx111 * sensor,u32 code,bool test)700 static u32 imx111_get_format_code(struct imx111 *sensor, u32 code, bool test)
701 {
702 u32 i;
703
704 for (i = 0; i < ARRAY_SIZE(imx111_mbus_formats); i++)
705 if (imx111_mbus_formats[i] == code)
706 break;
707
708 if (i >= ARRAY_SIZE(imx111_mbus_formats))
709 i = 0;
710
711 if (test)
712 return imx111_mbus_formats[i];
713
714 i = (i & ~3) | (sensor->vflip->val ? 2 : 0) |
715 (sensor->hflip->val ? 1 : 0);
716
717 return imx111_mbus_formats[i];
718 }
719
imx111_get_format_bpp(const struct v4l2_mbus_framefmt * format)720 static u32 imx111_get_format_bpp(const struct v4l2_mbus_framefmt *format)
721 {
722 switch (format->code) {
723 case MEDIA_BUS_FMT_SRGGB8_1X8:
724 case MEDIA_BUS_FMT_SGRBG8_1X8:
725 case MEDIA_BUS_FMT_SGBRG8_1X8:
726 case MEDIA_BUS_FMT_SBGGR8_1X8:
727 return 8;
728
729 case MEDIA_BUS_FMT_SRGGB10_1X10:
730 case MEDIA_BUS_FMT_SGRBG10_1X10:
731 case MEDIA_BUS_FMT_SGBRG10_1X10:
732 case MEDIA_BUS_FMT_SBGGR10_1X10:
733 default:
734 return 10;
735 }
736 }
737
imx111_update_digital_gain(struct imx111 * sensor,u32 val)738 static int imx111_update_digital_gain(struct imx111 *sensor, u32 val)
739 {
740 int ret = 0;
741
742 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
743 IMX111_GROUP_WRITE_ON,
744 IMX111_GROUP_WRITE_ON, &ret);
745
746 cci_write(sensor->regmap, IMX111_REG_DIG_GAIN_GREENR, val, &ret);
747 cci_write(sensor->regmap, IMX111_REG_DIG_GAIN_RED, val, &ret);
748 cci_write(sensor->regmap, IMX111_REG_DIG_GAIN_BLUE, val, &ret);
749 cci_write(sensor->regmap, IMX111_REG_DIG_GAIN_GREENB, val, &ret);
750
751 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
752 IMX111_GROUP_WRITE_ON, 0, &ret);
753
754 return ret;
755 }
756
imx111_set_ctrl(struct v4l2_ctrl * ctrl)757 static int imx111_set_ctrl(struct v4l2_ctrl *ctrl)
758 {
759 struct imx111 *sensor = ctrl_to_imx111(ctrl);
760 struct device *dev = regmap_get_device(sensor->regmap);
761 int ret = 0;
762
763 if (ctrl->id == V4L2_CID_VBLANK) {
764 s64 max = sensor->cur_mode->height + ctrl->val -
765 IMX111_INTEGRATION_TIME_OFFSET;
766
767 ret = __v4l2_ctrl_modify_range(sensor->exposure,
768 sensor->exposure->minimum,
769 max, sensor->exposure->step,
770 max);
771 if (ret)
772 return ret;
773 }
774
775 /*
776 * Applying V4L2 control value only happens
777 * when power is up for streaming
778 */
779 if (!pm_runtime_get_if_in_use(dev))
780 return 0;
781
782 switch (ctrl->id) {
783 case V4L2_CID_ANALOGUE_GAIN:
784 cci_write(sensor->regmap, IMX111_REG_ANALOG_GAIN, ctrl->val,
785 &ret);
786 break;
787 case V4L2_CID_DIGITAL_GAIN:
788 ret = imx111_update_digital_gain(sensor, ctrl->val);
789 break;
790 case V4L2_CID_EXPOSURE:
791 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
792 IMX111_GROUP_WRITE_ON,
793 IMX111_GROUP_WRITE_ON, &ret);
794 cci_write(sensor->regmap, IMX111_INTEGRATION_TIME, ctrl->val,
795 &ret);
796 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
797 IMX111_GROUP_WRITE_ON, 0, &ret);
798 break;
799 case V4L2_CID_HBLANK:
800 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
801 IMX111_GROUP_WRITE_ON,
802 IMX111_GROUP_WRITE_ON, &ret);
803 cci_write(sensor->regmap, IMX111_HORIZONTAL_TOTAL_LENGTH,
804 sensor->cur_mode->width + ctrl->val, &ret);
805 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
806 IMX111_GROUP_WRITE_ON, 0, &ret);
807 break;
808 case V4L2_CID_VBLANK:
809 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
810 IMX111_GROUP_WRITE_ON,
811 IMX111_GROUP_WRITE_ON, &ret);
812 cci_write(sensor->regmap, IMX111_VERTICAL_TOTAL_LENGTH,
813 sensor->cur_mode->height + ctrl->val, &ret);
814 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
815 IMX111_GROUP_WRITE_ON, 0, &ret);
816 break;
817 case V4L2_CID_HFLIP:
818 case V4L2_CID_VFLIP:
819 cci_write(sensor->regmap, IMX111_IMAGE_ORIENTATION,
820 sensor->hflip->val | sensor->vflip->val << 1, &ret);
821 break;
822 case V4L2_CID_TEST_PATTERN:
823 cci_write(sensor->regmap, IMX111_TEST_PATTERN, ctrl->val,
824 &ret);
825 break;
826 case V4L2_CID_TEST_PATTERN_RED:
827 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
828 IMX111_GROUP_WRITE_ON,
829 IMX111_GROUP_WRITE_ON, &ret);
830 cci_write(sensor->regmap, IMX111_SOLID_COLOR_RED, ctrl->val,
831 &ret);
832 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
833 IMX111_GROUP_WRITE_ON, 0, &ret);
834 break;
835 case V4L2_CID_TEST_PATTERN_GREENR:
836 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
837 IMX111_GROUP_WRITE_ON,
838 IMX111_GROUP_WRITE_ON, &ret);
839 cci_write(sensor->regmap, IMX111_SOLID_COLOR_GR, ctrl->val,
840 &ret);
841 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
842 IMX111_GROUP_WRITE_ON, 0, &ret);
843 break;
844 case V4L2_CID_TEST_PATTERN_BLUE:
845 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
846 IMX111_GROUP_WRITE_ON,
847 IMX111_GROUP_WRITE_ON, &ret);
848 cci_write(sensor->regmap, IMX111_SOLID_COLOR_BLUE, ctrl->val,
849 &ret);
850 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
851 IMX111_GROUP_WRITE_ON, 0, &ret);
852 break;
853 case V4L2_CID_TEST_PATTERN_GREENB:
854 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
855 IMX111_GROUP_WRITE_ON,
856 IMX111_GROUP_WRITE_ON, &ret);
857 cci_write(sensor->regmap, IMX111_SOLID_COLOR_GB, ctrl->val,
858 &ret);
859 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
860 IMX111_GROUP_WRITE_ON, 0, &ret);
861 break;
862 default:
863 ret = -EINVAL;
864 }
865
866 pm_runtime_put(dev);
867
868 return ret;
869 }
870
871 static const struct v4l2_ctrl_ops imx111_ctrl_ops = {
872 .s_ctrl = imx111_set_ctrl,
873 };
874
875 static const char * const test_pattern_menu[] = {
876 "Disabled",
877 "Solid Color Fill",
878 "Standard Color Bars",
879 "Fade To Grey Color Bars",
880 "Pseudorandom data",
881 };
882
imx111_init_controls(struct imx111 * sensor)883 static int imx111_init_controls(struct imx111 *sensor)
884 {
885 const struct v4l2_ctrl_ops *ops = &imx111_ctrl_ops;
886 struct device *dev = regmap_get_device(sensor->regmap);
887 const struct imx111_mode *mode = sensor->cur_mode;
888 struct v4l2_fwnode_device_properties props;
889 struct v4l2_ctrl_handler *hdl = &sensor->hdl;
890 s64 pixel_rate_min, pixel_rate_max;
891 int i, ret;
892
893 ret = v4l2_fwnode_device_parse(dev, &props);
894 if (ret < 0)
895 return ret;
896
897 v4l2_ctrl_handler_init(hdl, 15);
898
899 pixel_rate_min = div_u64(sensor->pixel_clk_raw,
900 2 * IMX111_DATA_DEPTH_RAW10);
901 pixel_rate_max = div_u64(sensor->pixel_clk_raw,
902 2 * IMX111_DATA_DEPTH_RAW8);
903 sensor->pixel_rate = v4l2_ctrl_new_std(hdl, NULL, V4L2_CID_PIXEL_RATE,
904 pixel_rate_min, pixel_rate_max,
905 1,
906 div_u64(sensor->pixel_clk_raw,
907 2 *
908 sensor->data_depth));
909
910 sensor->link_freq = v4l2_ctrl_new_int_menu(hdl, NULL,
911 V4L2_CID_LINK_FREQ, 0, 0,
912 &sensor->default_link_freq);
913 if (sensor->link_freq)
914 sensor->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
915
916 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
917 IMX111_ANA_GAIN_MIN, IMX111_ANA_GAIN_MAX,
918 IMX111_ANA_GAIN_STEP, IMX111_ANA_GAIN_DEFAULT);
919
920 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DIGITAL_GAIN,
921 IMX111_DGTL_GAIN_MIN, IMX111_DGTL_GAIN_MAX,
922 IMX111_DGTL_GAIN_STEP, IMX111_DGTL_GAIN_DEFAULT);
923
924 sensor->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP, 0, 1, 1,
925 0);
926 if (sensor->hflip)
927 sensor->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
928
929 sensor->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP, 0, 1, 1,
930 0);
931 if (sensor->vflip)
932 sensor->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
933
934 sensor->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
935 IMX111_VBLANK_MIN,
936 IMX111_VTL_MAX - mode->height, 1,
937 mode->vtl_def - mode->height);
938 sensor->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
939 IMX111_HBLANK_MIN,
940 IMX111_HTL_MAX - mode->width, 1,
941 mode->htl_def - mode->width);
942
943 /*
944 * The maximum coarse integration time is the frame length in lines
945 * minus five.
946 */
947 sensor->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
948 IMX111_INTEGRATION_TIME_MIN,
949 IMX111_PIXEL_ARRAY_HEIGHT -
950 IMX111_INTEGRATION_TIME_OFFSET,
951 IMX111_INTEGRATION_TIME_STEP,
952 IMX111_PIXEL_ARRAY_HEIGHT -
953 IMX111_INTEGRATION_TIME_OFFSET);
954
955 v4l2_ctrl_new_fwnode_properties(hdl, ops, &props);
956
957 v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
958 ARRAY_SIZE(test_pattern_menu) - 1, 0, 0,
959 test_pattern_menu);
960 for (i = 0; i < 4; i++) {
961 /*
962 * The assumption is that
963 * TEST_PATTERN_GREENR == TEST_PATTERN_RED + 1
964 * TEST_PATTERN_BLUE == TEST_PATTERN_RED + 2
965 * TEST_PATTERN_GREENB == TEST_PATTERN_RED + 3
966 */
967 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_TEST_PATTERN_RED + i,
968 IMX111_TESTP_COLOUR_MIN,
969 IMX111_TESTP_COLOUR_MAX,
970 IMX111_TESTP_COLOUR_STEP,
971 IMX111_TESTP_COLOUR_MAX);
972 /* The "Solid color" pattern is white by default */
973 }
974
975 if (hdl->error)
976 return hdl->error;
977
978 sensor->sd.ctrl_handler = hdl;
979
980 return 0;
981 };
982
imx111_enable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)983 static int imx111_enable_streams(struct v4l2_subdev *sd,
984 struct v4l2_subdev_state *state, u32 pad,
985 u64 streams_mask)
986 {
987 struct imx111 *sensor = sd_to_imx111(sd);
988 struct device *dev = regmap_get_device(sensor->regmap);
989 const struct imx111_mode *mode = sensor->cur_mode;
990 int ret;
991
992 ret = pm_runtime_resume_and_get(dev);
993 if (ret < 0)
994 return ret;
995
996 /* Apply default values of current mode */
997 ret = cci_multi_reg_write(sensor->regmap, mode->reg_list.regs,
998 mode->reg_list.num_of_regs, NULL);
999 if (ret < 0) {
1000 dev_err(dev, "Failed to initialize the sensor\n");
1001 goto err_rpm_put;
1002 }
1003
1004 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
1005 IMX111_GROUP_WRITE_ON,
1006 IMX111_GROUP_WRITE_ON, &ret);
1007 cci_write(sensor->regmap, IMX111_DATA_DEPTH,
1008 sensor->data_depth | sensor->data_depth << 8, &ret);
1009 cci_update_bits(sensor->regmap, IMX111_GROUP_WRITE,
1010 IMX111_GROUP_WRITE_ON, 0, &ret);
1011
1012 if (ret)
1013 goto err_rpm_put;
1014
1015 ret = __v4l2_ctrl_handler_setup(&sensor->hdl);
1016 if (ret)
1017 goto err_rpm_put;
1018
1019 ret = cci_write(sensor->regmap, IMX111_STREAMING_MODE,
1020 IMX111_MODE_STREAMING, NULL);
1021 if (ret)
1022 dev_err(dev, "failed to start stream");
1023
1024 /* vflip and hflip cannot change during streaming */
1025 __v4l2_ctrl_grab(sensor->vflip, true);
1026 __v4l2_ctrl_grab(sensor->hflip, true);
1027
1028 msleep(30);
1029
1030 return 0;
1031
1032 err_rpm_put:
1033 pm_runtime_put_autosuspend(dev);
1034 return ret;
1035 }
1036
imx111_disable_streams(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,u32 pad,u64 streams_mask)1037 static int imx111_disable_streams(struct v4l2_subdev *sd,
1038 struct v4l2_subdev_state *state, u32 pad,
1039 u64 streams_mask)
1040 {
1041 struct imx111 *sensor = sd_to_imx111(sd);
1042 struct device *dev = regmap_get_device(sensor->regmap);
1043 int ret;
1044
1045 ret = cci_write(sensor->regmap, IMX111_STREAMING_MODE,
1046 IMX111_MODE_STANDBY, NULL);
1047 if (ret)
1048 dev_err(dev, "failed to stop stream\n");
1049
1050 __v4l2_ctrl_grab(sensor->vflip, false);
1051 __v4l2_ctrl_grab(sensor->hflip, false);
1052
1053 pm_runtime_put_autosuspend(dev);
1054
1055 return ret;
1056 }
1057
imx111_initialize(struct imx111 * sensor)1058 static int imx111_initialize(struct imx111 *sensor)
1059 {
1060 struct device *dev = regmap_get_device(sensor->regmap);
1061 int ret = 0;
1062
1063 /* Configure the PLL. */
1064 cci_write(sensor->regmap, IMX111_PRE_PLL_CLK_DIVIDER_PLL1,
1065 sensor->pll->pre_div, &ret);
1066 cci_write(sensor->regmap, IMX111_PLL_MULTIPLIER_PLL1,
1067 sensor->pll->mult, &ret);
1068 cci_write(sensor->regmap, IMX111_POST_DIVIDER,
1069 IMX111_POST_DIVIDER_DIV1, &ret);
1070 cci_write(sensor->regmap, IMX111_PLL_SETTLING_TIME,
1071 to_settle_delay(sensor->pll->extclk_rate), &ret);
1072
1073 cci_multi_reg_write(sensor->regmap, imx111_global_init,
1074 ARRAY_SIZE(imx111_global_init), &ret);
1075 if (ret < 0) {
1076 dev_err(dev, "Failed to initialize the sensor\n");
1077 return ret;
1078 }
1079
1080 return 0;
1081 }
1082
1083 /* ----------------------------------------------------------------------------
1084 * IMX111 Pad Subdev Init and Operations
1085 */
imx111_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1086 static int imx111_enum_mbus_code(struct v4l2_subdev *sd,
1087 struct v4l2_subdev_state *sd_state,
1088 struct v4l2_subdev_mbus_code_enum *code)
1089 {
1090 struct imx111 *sensor = sd_to_imx111(sd);
1091
1092 if (code->index >= ARRAY_SIZE(imx111_mbus_formats) / 4)
1093 return -EINVAL;
1094
1095 code->code = imx111_get_format_code(sensor,
1096 imx111_mbus_formats[code->index *
1097 4], false);
1098
1099 return 0;
1100 }
1101
imx111_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1102 static int imx111_enum_frame_size(struct v4l2_subdev *sd,
1103 struct v4l2_subdev_state *sd_state,
1104 struct v4l2_subdev_frame_size_enum *fse)
1105 {
1106 struct imx111 *sensor = sd_to_imx111(sd);
1107 u32 code;
1108
1109 if (fse->index >= ARRAY_SIZE(imx111_modes))
1110 return -EINVAL;
1111
1112 code = imx111_get_format_code(sensor, fse->code, true);
1113 if (fse->code != code)
1114 return -EINVAL;
1115
1116 fse->min_width = imx111_modes[fse->index].width;
1117 fse->max_width = fse->min_width;
1118 fse->min_height = imx111_modes[fse->index].height;
1119 fse->max_height = fse->min_height;
1120
1121 return 0;
1122 }
1123
imx111_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * format)1124 static int imx111_set_format(struct v4l2_subdev *sd,
1125 struct v4l2_subdev_state *state,
1126 struct v4l2_subdev_format *format)
1127 {
1128 struct imx111 *sensor = sd_to_imx111(sd);
1129 struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
1130 struct v4l2_mbus_framefmt *fmt;
1131 const struct imx111_mode *mode;
1132
1133 mode = v4l2_find_nearest_size(imx111_modes, ARRAY_SIZE(imx111_modes),
1134 width, height,
1135 mbus_fmt->width, mbus_fmt->height);
1136
1137 fmt = v4l2_subdev_state_get_format(state, format->pad);
1138
1139 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
1140 int ret;
1141
1142 sensor->cur_mode = mode;
1143 sensor->data_depth = imx111_get_format_bpp(fmt);
1144
1145 ret = __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate,
1146 div_u64(sensor->pixel_clk_raw,
1147 2 *
1148 sensor->data_depth));
1149 if (ret)
1150 return ret;
1151
1152 ret = __v4l2_ctrl_modify_range(sensor->vblank,
1153 IMX111_VBLANK_MIN,
1154 IMX111_VTL_MAX - mode->height,
1155 1,
1156 mode->vtl_def - mode->height);
1157 if (ret)
1158 return ret;
1159
1160 ret = __v4l2_ctrl_s_ctrl(sensor->vblank, mode->vtl_def -
1161 mode->height);
1162 if (ret)
1163 return ret;
1164
1165 ret = __v4l2_ctrl_modify_range(sensor->hblank,
1166 IMX111_HBLANK_MIN,
1167 IMX111_HTL_MAX - mode->width,
1168 1,
1169 mode->htl_def - mode->width);
1170 if (ret)
1171 return ret;
1172
1173 ret = __v4l2_ctrl_s_ctrl(sensor->hblank, mode->htl_def -
1174 mode->width);
1175 if (ret)
1176 return ret;
1177 }
1178
1179 fmt->code = imx111_get_format_code(sensor, mbus_fmt->code, false);
1180 fmt->width = mode->width;
1181 fmt->height = mode->height;
1182 fmt->colorspace = V4L2_COLORSPACE_RAW;
1183
1184 *mbus_fmt = *fmt;
1185
1186 return 0;
1187 }
1188
imx111_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)1189 static int imx111_init_state(struct v4l2_subdev *sd,
1190 struct v4l2_subdev_state *sd_state)
1191 {
1192 struct imx111 *sensor = sd_to_imx111(sd);
1193 const struct imx111_mode *mode = sensor->cur_mode;
1194 struct v4l2_mbus_framefmt *fmt;
1195
1196 fmt = v4l2_subdev_state_get_format(sd_state, 0);
1197
1198 fmt->code = MEDIA_BUS_FMT_SGBRG10_1X10;
1199 fmt->width = mode->width;
1200 fmt->height = mode->height;
1201 fmt->field = V4L2_FIELD_NONE;
1202 fmt->colorspace = V4L2_COLORSPACE_RAW;
1203 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
1204 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
1205 fmt->xfer_func = V4L2_XFER_FUNC_NONE;
1206
1207 return 0;
1208 }
1209
1210 static const struct v4l2_subdev_video_ops imx111_video_ops = {
1211 .s_stream = v4l2_subdev_s_stream_helper,
1212 };
1213
1214 static const struct v4l2_subdev_pad_ops imx111_pad_ops = {
1215 .enum_mbus_code = imx111_enum_mbus_code,
1216 .enum_frame_size = imx111_enum_frame_size,
1217 .get_fmt = v4l2_subdev_get_fmt,
1218 .set_fmt = imx111_set_format,
1219 .enable_streams = imx111_enable_streams,
1220 .disable_streams = imx111_disable_streams,
1221 };
1222
1223 static const struct v4l2_subdev_ops imx111_subdev_ops = {
1224 .video = &imx111_video_ops,
1225 .pad = &imx111_pad_ops,
1226 };
1227
1228 static const struct media_entity_operations imx111_subdev_entity_ops = {
1229 .link_validate = v4l2_subdev_link_validate,
1230 };
1231
1232 static const struct v4l2_subdev_internal_ops imx111_internal_ops = {
1233 .init_state = imx111_init_state,
1234 };
1235
imx111_init_subdev(struct imx111 * sensor,struct i2c_client * client)1236 static int imx111_init_subdev(struct imx111 *sensor, struct i2c_client *client)
1237 {
1238 struct device *dev = &client->dev;
1239 struct v4l2_subdev *sd = &sensor->sd;
1240 struct media_pad *pad = &sensor->pad;
1241 struct v4l2_ctrl_handler *hdl = &sensor->hdl;
1242 int ret;
1243
1244 /* Initialize the subdev. */
1245 v4l2_i2c_subdev_init(sd, client, &imx111_subdev_ops);
1246
1247 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1248 sd->internal_ops = &imx111_internal_ops;
1249
1250 /* Initialize the media entity. */
1251 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1252 sd->entity.ops = &imx111_subdev_entity_ops;
1253 pad->flags = MEDIA_PAD_FL_SOURCE;
1254
1255 ret = media_entity_pads_init(&sd->entity, 1, pad);
1256 if (ret < 0) {
1257 dev_err(dev, "failed to init entity pads: %d", ret);
1258 return ret;
1259 }
1260
1261 /* Initialize the control handler. */
1262 ret = imx111_init_controls(sensor);
1263 if (ret)
1264 goto error;
1265
1266 return 0;
1267 error:
1268 v4l2_ctrl_handler_free(hdl);
1269 media_entity_cleanup(&sd->entity);
1270 return ret;
1271 };
1272
1273 /* ----------------------------------------------------------------------------
1274 * Power Management
1275 */
1276
imx111_power_on(struct imx111 * sensor)1277 static int imx111_power_on(struct imx111 *sensor)
1278 {
1279 int ret;
1280
1281 if (sensor->reset)
1282 gpiod_set_value(sensor->reset, 1);
1283
1284 ret = regulator_bulk_enable(ARRAY_SIZE(imx111_supplies),
1285 sensor->supplies);
1286 if (ret < 0)
1287 return ret;
1288
1289 usleep_range(500, 600);
1290
1291 if (sensor->reset)
1292 gpiod_set_value(sensor->reset, 0);
1293
1294 usleep_range(200, 250);
1295
1296 ret = clk_prepare_enable(sensor->extclk);
1297 if (ret < 0)
1298 goto error_regulator;
1299
1300 usleep_range(200, 250);
1301
1302 return 0;
1303
1304 error_regulator:
1305 regulator_bulk_disable(ARRAY_SIZE(imx111_supplies), sensor->supplies);
1306 return ret;
1307 }
1308
imx111_power_off(struct imx111 * sensor)1309 static void imx111_power_off(struct imx111 *sensor)
1310 {
1311 if (sensor->reset)
1312 gpiod_set_value(sensor->reset, 1);
1313 usleep_range(1000, 2000);
1314
1315 clk_disable_unprepare(sensor->extclk);
1316 regulator_bulk_disable(ARRAY_SIZE(imx111_supplies), sensor->supplies);
1317 }
1318
imx111_pm_runtime_resume(struct device * dev)1319 static int __maybe_unused imx111_pm_runtime_resume(struct device *dev)
1320 {
1321 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1322 struct imx111 *sensor = sd_to_imx111(sd);
1323 int ret;
1324
1325 ret = imx111_power_on(sensor);
1326 if (ret)
1327 return ret;
1328
1329 ret = imx111_initialize(sensor);
1330 if (ret) {
1331 imx111_power_off(sensor);
1332 return ret;
1333 }
1334
1335 return 0;
1336 }
1337
imx111_pm_runtime_suspend(struct device * dev)1338 static int __maybe_unused imx111_pm_runtime_suspend(struct device *dev)
1339 {
1340 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1341 struct imx111 *sensor = sd_to_imx111(sd);
1342
1343 imx111_power_off(sensor);
1344
1345 return 0;
1346 }
1347
1348 static const struct dev_pm_ops imx111_pm_ops = {
1349 SET_RUNTIME_PM_OPS(imx111_pm_runtime_suspend,
1350 imx111_pm_runtime_resume, NULL)
1351 };
1352
1353 /* ----------------------------------------------------------------------------
1354 * Probe & Remove
1355 */
1356
imx111_identify_module(struct imx111 * sensor)1357 static int imx111_identify_module(struct imx111 *sensor)
1358 {
1359 struct device *dev = regmap_get_device(sensor->regmap);
1360 u64 value, revision, manufacturer;
1361 int ret = 0;
1362
1363 ret = cci_read(sensor->regmap, IMX111_PRODUCT_ID, &value, NULL);
1364 if (ret)
1365 return ret;
1366
1367 if (value != IMX111_CHIP_ID) {
1368 dev_err(dev, "chip id mismatch: %x!=%04llx", IMX111_CHIP_ID,
1369 value);
1370 return -ENXIO;
1371 }
1372
1373 cci_read(sensor->regmap, IMX111_REVISION, &revision, &ret);
1374 cci_read(sensor->regmap, IMX111_MANUFACTURER_ID, &manufacturer, &ret);
1375
1376 dev_dbg(dev, "module IMX%03llx rev. %llu manufacturer %llu\n",
1377 value, revision, manufacturer);
1378
1379 return ret;
1380 }
1381
imx111_clk_init(struct imx111 * sensor)1382 static int imx111_clk_init(struct imx111 *sensor)
1383 {
1384 struct device *dev = regmap_get_device(sensor->regmap);
1385 u32 ndata_lanes = sensor->bus_cfg.bus.mipi_csi2.num_data_lanes;
1386 u64 extclk_rate, system_clk;
1387 unsigned int i;
1388
1389 extclk_rate = clk_get_rate(sensor->extclk);
1390 if (!extclk_rate)
1391 return dev_err_probe(dev, -EINVAL, "EXTCLK rate unknown\n");
1392
1393 for (i = 0; i < ARRAY_SIZE(imx111_pll); i++) {
1394 if (clk_get_rate(sensor->extclk) ==
1395 imx111_pll[i].extclk_rate) {
1396 sensor->pll = &imx111_pll[i];
1397 break;
1398 }
1399 }
1400 if (!sensor->pll)
1401 return dev_err_probe(dev, -EINVAL,
1402 "Unsupported EXTCLK rate %llu\n",
1403 extclk_rate);
1404
1405 system_clk = div_u64(extclk_rate, sensor->pll->pre_div) *
1406 sensor->pll->mult;
1407
1408 /*
1409 * Pixel clock or Logic clock is used for internal image processing is
1410 * generated by dividing into 1/10 or 1/8 frequency according to the
1411 * word length of the CSI2 interface. This clock is designating the
1412 * pixel rate and used as the base of integration time, frame rate etc.
1413 */
1414 sensor->pixel_clk_raw = system_clk * ndata_lanes;
1415
1416 /*
1417 * The CSI-2 bus is clocked for 16-bit per pixel, transmitted in DDR
1418 * over n lanes for RAW10 default format.
1419 */
1420 sensor->default_link_freq = div_u64(sensor->pixel_clk_raw * 8,
1421 2 * IMX111_DATA_DEPTH_RAW10);
1422
1423 if (sensor->bus_cfg.nr_of_link_frequencies != 1 ||
1424 sensor->bus_cfg.link_frequencies[0] != sensor->default_link_freq)
1425 return dev_err_probe(dev, -EINVAL,
1426 "Invalid link-frequency, expected %llu\n",
1427 sensor->default_link_freq);
1428
1429 return 0;
1430 }
1431
imx111_parse_dt(struct imx111 * sensor)1432 static int imx111_parse_dt(struct imx111 *sensor)
1433 {
1434 struct device *dev = regmap_get_device(sensor->regmap);
1435 struct fwnode_handle *fwnode = dev_fwnode(dev);
1436 struct fwnode_handle *ep;
1437 int ret;
1438
1439 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1440 if (!ep) {
1441 dev_err(dev, "No endpoint found\n");
1442 return -EINVAL;
1443 }
1444
1445 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &sensor->bus_cfg);
1446 fwnode_handle_put(ep);
1447 if (ret < 0) {
1448 dev_err(dev, "Failed to parse endpoint\n");
1449 goto error;
1450 }
1451
1452 sensor->bus_cfg.bus_type = V4L2_MBUS_CSI2_DPHY;
1453
1454 /* Check the number of MIPI CSI2 data lanes */
1455 if (sensor->bus_cfg.bus.mipi_csi2.num_data_lanes > 2) {
1456 dev_err(dev, "number of lanes is more than 2\n");
1457 ret = -EINVAL;
1458 goto error;
1459 }
1460
1461 return 0;
1462
1463 error:
1464 v4l2_fwnode_endpoint_free(&sensor->bus_cfg);
1465 return ret;
1466 }
1467
imx111_probe(struct i2c_client * client)1468 static int imx111_probe(struct i2c_client *client)
1469 {
1470 struct device *dev = &client->dev;
1471 struct imx111 *sensor;
1472 int ret;
1473
1474 sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
1475 if (!sensor)
1476 return -ENOMEM;
1477
1478 sensor->regmap = devm_cci_regmap_init_i2c(client, 16);
1479 if (IS_ERR(sensor->regmap))
1480 return dev_err_probe(dev, PTR_ERR(sensor->regmap),
1481 "Failed to allocate register map\n");
1482
1483 sensor->extclk = devm_v4l2_sensor_clk_get(dev, NULL);
1484 if (IS_ERR(sensor->extclk))
1485 return dev_err_probe(dev, PTR_ERR(sensor->extclk),
1486 "Failed to get clock\n");
1487
1488 sensor->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1489 if (IS_ERR(sensor->reset))
1490 return dev_err_probe(dev, PTR_ERR(sensor->reset),
1491 "Failed to get reset GPIO\n");
1492
1493 ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(imx111_supplies),
1494 imx111_supplies,
1495 &sensor->supplies);
1496 if (ret < 0)
1497 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1498
1499 ret = imx111_parse_dt(sensor);
1500 if (ret < 0)
1501 return ret;
1502
1503 ret = imx111_clk_init(sensor);
1504 if (ret < 0)
1505 goto error_ep_free;
1506
1507 ret = imx111_power_on(sensor);
1508 if (ret < 0) {
1509 dev_err_probe(dev, ret, "Could not power on the device\n");
1510 goto error_ep_free;
1511 }
1512
1513 ret = imx111_identify_module(sensor);
1514 if (ret < 0) {
1515 dev_err_probe(dev, ret, "Could not identify module\n");
1516 goto error_power_off;
1517 }
1518
1519 sensor->cur_mode = &imx111_modes[IMX111_MODE_3280x2464];
1520 sensor->data_depth = IMX111_DATA_DEPTH_RAW10;
1521
1522 ret = imx111_initialize(sensor);
1523 if (ret < 0)
1524 goto error_power_off;
1525
1526 ret = imx111_init_subdev(sensor, client);
1527 if (ret < 0) {
1528 dev_err(dev, "failed to init controls: %d", ret);
1529 goto error_v4l2_ctrl_handler_free;
1530 }
1531
1532 ret = v4l2_subdev_init_finalize(&sensor->sd);
1533 if (ret)
1534 goto error_v4l2_ctrl_handler_free;
1535
1536 pm_runtime_set_active(dev);
1537 pm_runtime_enable(dev);
1538
1539 ret = v4l2_async_register_subdev_sensor(&sensor->sd);
1540 if (ret < 0) {
1541 dev_err(dev, "failed to register V4L2 subdev: %d", ret);
1542 goto error_pm;
1543 }
1544
1545 pm_runtime_set_autosuspend_delay(dev, 1000);
1546 pm_runtime_use_autosuspend(dev);
1547 pm_runtime_idle(dev);
1548
1549 return 0;
1550
1551 error_pm:
1552 v4l2_subdev_cleanup(&sensor->sd);
1553 pm_runtime_disable(dev);
1554 pm_runtime_set_suspended(dev);
1555
1556 error_v4l2_ctrl_handler_free:
1557 v4l2_ctrl_handler_free(&sensor->hdl);
1558 media_entity_cleanup(&sensor->sd.entity);
1559
1560 error_power_off:
1561 imx111_power_off(sensor);
1562
1563 error_ep_free:
1564 v4l2_fwnode_endpoint_free(&sensor->bus_cfg);
1565
1566 return ret;
1567 }
1568
imx111_remove(struct i2c_client * client)1569 static void imx111_remove(struct i2c_client *client)
1570 {
1571 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1572 struct imx111 *sensor = sd_to_imx111(sd);
1573
1574 v4l2_async_unregister_subdev(&sensor->sd);
1575 v4l2_subdev_cleanup(sd);
1576 media_entity_cleanup(&sensor->sd.entity);
1577 v4l2_ctrl_handler_free(&sensor->hdl);
1578 v4l2_fwnode_endpoint_free(&sensor->bus_cfg);
1579
1580 /*
1581 * Disable runtime PM. In case runtime PM is disabled in the kernel,
1582 * make sure to turn power off manually.
1583 */
1584 pm_runtime_disable(&client->dev);
1585 if (!pm_runtime_status_suspended(&client->dev)) {
1586 imx111_power_off(sensor);
1587 pm_runtime_set_suspended(&client->dev);
1588 }
1589 }
1590
1591 static const struct of_device_id imx111_of_match[] = {
1592 { .compatible = "sony,imx111" },
1593 { /* sentinel */ }
1594 };
1595 MODULE_DEVICE_TABLE(of, imx111_of_match);
1596
1597 static struct i2c_driver imx111_i2c_driver = {
1598 .driver = {
1599 .name = "imx111",
1600 .of_match_table = imx111_of_match,
1601 .pm = &imx111_pm_ops,
1602 },
1603 .probe = imx111_probe,
1604 .remove = imx111_remove,
1605 };
1606 module_i2c_driver(imx111_i2c_driver);
1607
1608 MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>");
1609 MODULE_DESCRIPTION("Sony IMX111 CMOS Image Sensor driver");
1610 MODULE_LICENSE("GPL");
1611