1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * AD9832 SPI DDS driver
4  *
5  * Copyright 2011 Analog Devices Inc.
6  */
7 
8 #include <asm/div64.h>
9 
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/spi/spi.h>
18 #include <linux/sysfs.h>
19 
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 
23 #include "ad9832.h"
24 
25 #include "dds.h"
26 
27 /* Registers */
28 
29 #define AD9832_FREQ0LL		0x0
30 #define AD9832_FREQ0HL		0x1
31 #define AD9832_FREQ0LM		0x2
32 #define AD9832_FREQ0HM		0x3
33 #define AD9832_FREQ1LL		0x4
34 #define AD9832_FREQ1HL		0x5
35 #define AD9832_FREQ1LM		0x6
36 #define AD9832_FREQ1HM		0x7
37 #define AD9832_PHASE0L		0x8
38 #define AD9832_PHASE0H		0x9
39 #define AD9832_PHASE1L		0xA
40 #define AD9832_PHASE1H		0xB
41 #define AD9832_PHASE2L		0xC
42 #define AD9832_PHASE2H		0xD
43 #define AD9832_PHASE3L		0xE
44 #define AD9832_PHASE3H		0xF
45 
46 #define AD9832_PHASE_SYM	0x10
47 #define AD9832_FREQ_SYM		0x11
48 #define AD9832_PINCTRL_EN	0x12
49 #define AD9832_OUTPUT_EN	0x13
50 
51 /* Command Control Bits */
52 
53 #define AD9832_CMD_PHA8BITSW	0x1
54 #define AD9832_CMD_PHA16BITSW	0x0
55 #define AD9832_CMD_FRE8BITSW	0x3
56 #define AD9832_CMD_FRE16BITSW	0x2
57 #define AD9832_CMD_FPSELECT	0x6
58 #define AD9832_CMD_SYNCSELSRC	0x8
59 #define AD9832_CMD_SLEEPRESCLR	0xC
60 
61 #define AD9832_FREQ		BIT(11)
62 #define AD9832_PHASE(x)		(((x) & 3) << 9)
63 #define AD9832_SYNC		BIT(13)
64 #define AD9832_SELSRC		BIT(12)
65 #define AD9832_SLEEP		BIT(13)
66 #define AD9832_RESET		BIT(12)
67 #define AD9832_CLR		BIT(11)
68 #define CMD_SHIFT		12
69 #define ADD_SHIFT		8
70 #define AD9832_FREQ_BITS	32
71 #define AD9832_PHASE_BITS	12
72 #define RES_MASK(bits)		((1 << (bits)) - 1)
73 
74 /**
75  * struct ad9832_state - driver instance specific data
76  * @spi:		spi_device
77  * @mclk:		external master clock
78  * @ctrl_fp:		cached frequency/phase control word
79  * @ctrl_ss:		cached sync/selsrc control word
80  * @ctrl_src:		cached sleep/reset/clr word
81  * @xfer:		default spi transfer
82  * @msg:		default spi message
83  * @freq_xfer:		tuning word spi transfer
84  * @freq_msg:		tuning word spi message
85  * @phase_xfer:		tuning word spi transfer
86  * @phase_msg:		tuning word spi message
87  * @lock:		protect sensor state
88  * @data:		spi transmit buffer
89  * @phase_data:		tuning word spi transmit buffer
90  * @freq_data:		tuning word spi transmit buffer
91  */
92 
93 struct ad9832_state {
94 	struct spi_device		*spi;
95 	struct clk			*mclk;
96 	unsigned short			ctrl_fp;
97 	unsigned short			ctrl_ss;
98 	unsigned short			ctrl_src;
99 	struct spi_transfer		xfer;
100 	struct spi_message		msg;
101 	struct spi_transfer		freq_xfer[4];
102 	struct spi_message		freq_msg;
103 	struct spi_transfer		phase_xfer[2];
104 	struct spi_message		phase_msg;
105 	struct mutex			lock;	/* protect sensor state */
106 	/*
107 	 * DMA (thus cache coherency maintenance) requires the
108 	 * transfer buffers to live in their own cache lines.
109 	 */
110 	union {
111 		__be16			freq_data[4];
112 		__be16			phase_data[2];
113 		__be16			data;
114 	} __aligned(IIO_DMA_MINALIGN);
115 };
116 
ad9832_calc_freqreg(unsigned long mclk,unsigned long fout)117 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
118 {
119 	unsigned long long freqreg = (u64)fout *
120 				     (u64)((u64)1L << AD9832_FREQ_BITS);
121 	do_div(freqreg, mclk);
122 	return freqreg;
123 }
124 
ad9832_write_frequency(struct ad9832_state * st,unsigned int addr,unsigned long fout)125 static int ad9832_write_frequency(struct ad9832_state *st,
126 				  unsigned int addr, unsigned long fout)
127 {
128 	unsigned long clk_freq;
129 	unsigned long regval;
130 
131 	clk_freq = clk_get_rate(st->mclk);
132 
133 	if (!clk_freq || fout > (clk_freq / 2))
134 		return -EINVAL;
135 
136 	regval = ad9832_calc_freqreg(clk_freq, fout);
137 
138 	st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
139 					(addr << ADD_SHIFT) |
140 					((regval >> 24) & 0xFF));
141 	st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
142 					((addr - 1) << ADD_SHIFT) |
143 					((regval >> 16) & 0xFF));
144 	st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
145 					((addr - 2) << ADD_SHIFT) |
146 					((regval >> 8) & 0xFF));
147 	st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
148 					((addr - 3) << ADD_SHIFT) |
149 					((regval >> 0) & 0xFF));
150 
151 	return spi_sync(st->spi, &st->freq_msg);
152 }
153 
ad9832_write_phase(struct ad9832_state * st,unsigned long addr,unsigned long phase)154 static int ad9832_write_phase(struct ad9832_state *st,
155 			      unsigned long addr, unsigned long phase)
156 {
157 	if (phase >= BIT(AD9832_PHASE_BITS))
158 		return -EINVAL;
159 
160 	st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
161 					(addr << ADD_SHIFT) |
162 					((phase >> 8) & 0xFF));
163 	st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
164 					((addr - 1) << ADD_SHIFT) |
165 					(phase & 0xFF));
166 
167 	return spi_sync(st->spi, &st->phase_msg);
168 }
169 
ad9832_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)170 static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
171 			    const char *buf, size_t len)
172 {
173 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
174 	struct ad9832_state *st = iio_priv(indio_dev);
175 	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
176 	int ret;
177 	unsigned long val;
178 
179 	ret = kstrtoul(buf, 10, &val);
180 	if (ret)
181 		goto error_ret;
182 
183 	mutex_lock(&st->lock);
184 	switch ((u32)this_attr->address) {
185 	case AD9832_FREQ0HM:
186 	case AD9832_FREQ1HM:
187 		ret = ad9832_write_frequency(st, this_attr->address, val);
188 		break;
189 	case AD9832_PHASE0H:
190 	case AD9832_PHASE1H:
191 	case AD9832_PHASE2H:
192 	case AD9832_PHASE3H:
193 		ret = ad9832_write_phase(st, this_attr->address, val);
194 		break;
195 	case AD9832_PINCTRL_EN:
196 		if (val)
197 			st->ctrl_ss &= ~AD9832_SELSRC;
198 		else
199 			st->ctrl_ss |= AD9832_SELSRC;
200 		st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
201 					st->ctrl_ss);
202 		ret = spi_sync(st->spi, &st->msg);
203 		break;
204 	case AD9832_FREQ_SYM:
205 		if (val == 1) {
206 			st->ctrl_fp |= AD9832_FREQ;
207 		} else if (val == 0) {
208 			st->ctrl_fp &= ~AD9832_FREQ;
209 		} else {
210 			ret = -EINVAL;
211 			break;
212 		}
213 		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
214 					st->ctrl_fp);
215 		ret = spi_sync(st->spi, &st->msg);
216 		break;
217 	case AD9832_PHASE_SYM:
218 		if (val > 3) {
219 			ret = -EINVAL;
220 			break;
221 		}
222 
223 		st->ctrl_fp &= ~AD9832_PHASE(3);
224 		st->ctrl_fp |= AD9832_PHASE(val);
225 
226 		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
227 					st->ctrl_fp);
228 		ret = spi_sync(st->spi, &st->msg);
229 		break;
230 	case AD9832_OUTPUT_EN:
231 		if (val)
232 			st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
233 					AD9832_CLR);
234 		else
235 			st->ctrl_src |= AD9832_RESET;
236 
237 		st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
238 					st->ctrl_src);
239 		ret = spi_sync(st->spi, &st->msg);
240 		break;
241 	default:
242 		ret = -ENODEV;
243 	}
244 	mutex_unlock(&st->lock);
245 
246 error_ret:
247 	return ret ? ret : len;
248 }
249 
250 /*
251  * see dds.h for further information
252  */
253 
254 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM);
255 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM);
256 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SYM);
257 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
258 
259 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H);
260 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H);
261 static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H);
262 static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H);
263 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL,
264 				ad9832_write, AD9832_PHASE_SYM);
265 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
266 
267 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
268 				ad9832_write, AD9832_PINCTRL_EN);
269 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL,
270 				ad9832_write, AD9832_OUTPUT_EN);
271 
272 static struct attribute *ad9832_attributes[] = {
273 	&iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
274 	&iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
275 	&iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
276 	&iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
277 	&iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
278 	&iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
279 	&iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
280 	&iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
281 	&iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
282 	&iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
283 	&iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
284 	&iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
285 	NULL,
286 };
287 
288 static const struct attribute_group ad9832_attribute_group = {
289 	.attrs = ad9832_attributes,
290 };
291 
292 static const struct iio_info ad9832_info = {
293 	.attrs = &ad9832_attribute_group,
294 };
295 
ad9832_probe(struct spi_device * spi)296 static int ad9832_probe(struct spi_device *spi)
297 {
298 	struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev);
299 	struct iio_dev *indio_dev;
300 	struct ad9832_state *st;
301 	int ret;
302 
303 	if (!pdata) {
304 		dev_dbg(&spi->dev, "no platform data?\n");
305 		return -ENODEV;
306 	}
307 
308 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
309 	if (!indio_dev)
310 		return -ENOMEM;
311 
312 	st = iio_priv(indio_dev);
313 
314 	ret = devm_regulator_get_enable(&spi->dev, "avdd");
315 	if (ret)
316 		return dev_err_probe(&spi->dev, ret, "failed to enable specified AVDD voltage\n");
317 
318 	ret = devm_regulator_get_enable(&spi->dev, "dvdd");
319 	if (ret)
320 		return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVDD supply\n");
321 
322 	st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
323 	if (IS_ERR(st->mclk))
324 		return PTR_ERR(st->mclk);
325 
326 	st->spi = spi;
327 	mutex_init(&st->lock);
328 
329 	indio_dev->name = spi_get_device_id(spi)->name;
330 	indio_dev->info = &ad9832_info;
331 	indio_dev->modes = INDIO_DIRECT_MODE;
332 
333 	/* Setup default messages */
334 
335 	st->xfer.tx_buf = &st->data;
336 	st->xfer.len = 2;
337 
338 	spi_message_init(&st->msg);
339 	spi_message_add_tail(&st->xfer, &st->msg);
340 
341 	st->freq_xfer[0].tx_buf = &st->freq_data[0];
342 	st->freq_xfer[0].len = 2;
343 	st->freq_xfer[0].cs_change = 1;
344 	st->freq_xfer[1].tx_buf = &st->freq_data[1];
345 	st->freq_xfer[1].len = 2;
346 	st->freq_xfer[1].cs_change = 1;
347 	st->freq_xfer[2].tx_buf = &st->freq_data[2];
348 	st->freq_xfer[2].len = 2;
349 	st->freq_xfer[2].cs_change = 1;
350 	st->freq_xfer[3].tx_buf = &st->freq_data[3];
351 	st->freq_xfer[3].len = 2;
352 
353 	spi_message_init(&st->freq_msg);
354 	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
355 	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
356 	spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
357 	spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
358 
359 	st->phase_xfer[0].tx_buf = &st->phase_data[0];
360 	st->phase_xfer[0].len = 2;
361 	st->phase_xfer[0].cs_change = 1;
362 	st->phase_xfer[1].tx_buf = &st->phase_data[1];
363 	st->phase_xfer[1].len = 2;
364 
365 	spi_message_init(&st->phase_msg);
366 	spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
367 	spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
368 
369 	st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
370 	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
371 					st->ctrl_src);
372 	ret = spi_sync(st->spi, &st->msg);
373 	if (ret) {
374 		dev_err(&spi->dev, "device init failed\n");
375 		return ret;
376 	}
377 
378 	ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
379 	if (ret)
380 		return ret;
381 
382 	ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
383 	if (ret)
384 		return ret;
385 
386 	ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
387 	if (ret)
388 		return ret;
389 
390 	ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
391 	if (ret)
392 		return ret;
393 
394 	ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
395 	if (ret)
396 		return ret;
397 
398 	ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
399 	if (ret)
400 		return ret;
401 
402 	return devm_iio_device_register(&spi->dev, indio_dev);
403 }
404 
405 static const struct spi_device_id ad9832_id[] = {
406 	{"ad9832", 0},
407 	{"ad9835", 0},
408 	{}
409 };
410 MODULE_DEVICE_TABLE(spi, ad9832_id);
411 
412 static struct spi_driver ad9832_driver = {
413 	.driver = {
414 		.name	= "ad9832",
415 	},
416 	.probe		= ad9832_probe,
417 	.id_table	= ad9832_id,
418 };
419 module_spi_driver(ad9832_driver);
420 
421 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
422 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
423 MODULE_LICENSE("GPL v2");
424