1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Aquantia PHY
4 *
5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
6 *
7 * Copyright 2015 Freescale Semiconductor, Inc.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/bitfield.h>
14 #include <linux/of.h>
15 #include <linux/phy.h>
16
17 #include "aquantia.h"
18
19 #define PHY_ID_AQ1202 0x03a1b445
20 #define PHY_ID_AQ2104 0x03a1b460
21 #define PHY_ID_AQR105 0x03a1b4a2
22 #define PHY_ID_AQR106 0x03a1b4d0
23 #define PHY_ID_AQR107 0x03a1b4e0
24 #define PHY_ID_AQCS109 0x03a1b5c2
25 #define PHY_ID_AQR405 0x03a1b4b0
26 #define PHY_ID_AQR111 0x03a1b610
27 #define PHY_ID_AQR111B0 0x03a1b612
28 #define PHY_ID_AQR112 0x03a1b662
29 #define PHY_ID_AQR412 0x03a1b6f2
30 #define PHY_ID_AQR412C 0x03a1b712
31 #define PHY_ID_AQR113 0x31c31c40
32 #define PHY_ID_AQR113C 0x31c31c12
33 #define PHY_ID_AQR114C 0x31c31c22
34 #define PHY_ID_AQR115 0x31c31c63
35 #define PHY_ID_AQR115C 0x31c31c33
36 #define PHY_ID_AQR813 0x31c31cb2
37
38 #define MDIO_PHYXS_VEND_PROV2 0xc441
39 #define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3)
40
41 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
42 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
43 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
44 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
45 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
46 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
47 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
48 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
49 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
50 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF 9
51 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
52
53 #define MDIO_AN_VEND_PROV 0xc400
54 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
55 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
56 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
57 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
58 #define MDIO_AN_VEND_PROV_EXC_PHYID_INFO BIT(6)
59 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
60 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
61 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
62
63 #define MDIO_AN_RESVD_VEND_PROV 0xc410
64 #define MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO 0
65 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDI 1
66 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX 2
67 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MASK GENMASK(1, 0)
68
69 #define MDIO_AN_TX_VEND_STATUS1 0xc800
70 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
71 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0
72 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
73 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
74 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
75 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
76 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
77 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
78
79 #define MDIO_AN_RESVD_VEND_STATUS1 0xc810
80 #define MDIO_AN_RESVD_VEND_STATUS1_MDIX BIT(8)
81
82 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
83 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
84
85 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
86 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
87
88 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401
89 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
90
91 #define PMAPMD_FW_MISC_ID 0xc41d
92 #define PMAPMD_FW_MISC_VER 0xc41e
93
94 #define PMAPMD_RSVD_VEND_PROV 0xe400
95 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF GENMASK(1, 0)
96 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE BIT(0)
97 #define PMAPMD_RSVD_VEND_PROV_MDI_FORCE BIT(1)
98
99 #define MDIO_AN_RX_LP_STAT1 0xe820
100 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
101 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
102 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
103 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
104 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
105
106 #define MDIO_AN_RX_LP_STAT4 0xe823
107 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
108 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
109
110 #define MDIO_AN_RX_VEND_STAT3 0xe832
111 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
112
113 /* Sleep and timeout for checking if the Processor-Intensive
114 * MDIO operation is finished
115 */
116 #define AQR107_OP_IN_PROG_SLEEP 1000
117 #define AQR107_OP_IN_PROG_TIMEOUT 100000
118
aqr107_get_sset_count(struct phy_device * phydev)119 static int aqr107_get_sset_count(struct phy_device *phydev)
120 {
121 return AQR107_SGMII_STAT_SZ;
122 }
123
aqr107_get_strings(struct phy_device * phydev,u8 * data)124 static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
125 {
126 int i;
127
128 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
129 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
130 ETH_GSTRING_LEN);
131 }
132
aqr107_get_stat(struct phy_device * phydev,int index)133 static u64 aqr107_get_stat(struct phy_device *phydev, int index)
134 {
135 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
136 int len_l = min(stat->size, 16);
137 int len_h = stat->size - len_l;
138 u64 ret;
139 int val;
140
141 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
142 if (val < 0)
143 return U64_MAX;
144
145 ret = val & GENMASK(len_l - 1, 0);
146 if (len_h) {
147 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
148 if (val < 0)
149 return U64_MAX;
150
151 ret += (val & GENMASK(len_h - 1, 0)) << 16;
152 }
153
154 return ret;
155 }
156
aqr107_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)157 static void aqr107_get_stats(struct phy_device *phydev,
158 struct ethtool_stats *stats, u64 *data)
159 {
160 struct aqr107_priv *priv = phydev->priv;
161 u64 val;
162 int i;
163
164 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
165 val = aqr107_get_stat(phydev, i);
166 if (val == U64_MAX)
167 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
168 aqr107_hw_stats[i].name);
169 else
170 priv->sgmii_stats[i] += val;
171
172 data[i] = priv->sgmii_stats[i];
173 }
174 }
175
aqr_set_mdix(struct phy_device * phydev,int mdix)176 static int aqr_set_mdix(struct phy_device *phydev, int mdix)
177 {
178 u16 val = 0;
179
180 switch (mdix) {
181 case ETH_TP_MDI:
182 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDI;
183 break;
184 case ETH_TP_MDI_X:
185 val = MDIO_AN_RESVD_VEND_PROV_MDIX_MDIX;
186 break;
187 case ETH_TP_MDI_AUTO:
188 case ETH_TP_MDI_INVALID:
189 default:
190 val = MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO;
191 break;
192 }
193
194 return phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_PROV,
195 MDIO_AN_RESVD_VEND_PROV_MDIX_MASK, val);
196 }
197
aqr_config_aneg(struct phy_device * phydev)198 static int aqr_config_aneg(struct phy_device *phydev)
199 {
200 bool changed = false;
201 u16 reg;
202 int ret;
203
204 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl);
205 if (ret < 0)
206 return ret;
207 if (ret > 0)
208 changed = true;
209
210 if (phydev->autoneg == AUTONEG_DISABLE)
211 return genphy_c45_pma_setup_forced(phydev);
212
213 ret = genphy_c45_an_config_aneg(phydev);
214 if (ret < 0)
215 return ret;
216 if (ret > 0)
217 changed = true;
218
219 /* Clause 45 has no standardized support for 1000BaseT, therefore
220 * use vendor registers for this mode.
221 */
222 reg = 0;
223 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
224 phydev->advertising))
225 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
226
227 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
228 phydev->advertising))
229 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
230
231 /* Handle the case when the 2.5G and 5G speeds are not advertised */
232 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
233 phydev->advertising))
234 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
235
236 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
237 phydev->advertising))
238 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
239
240 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
241 MDIO_AN_VEND_PROV_1000BASET_HALF |
242 MDIO_AN_VEND_PROV_1000BASET_FULL |
243 MDIO_AN_VEND_PROV_2500BASET_FULL |
244 MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
245 if (ret < 0)
246 return ret;
247 if (ret > 0)
248 changed = true;
249
250 return genphy_c45_check_and_restart_aneg(phydev, changed);
251 }
252
aqr_config_intr(struct phy_device * phydev)253 static int aqr_config_intr(struct phy_device *phydev)
254 {
255 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
256 int err;
257
258 if (en) {
259 /* Clear any pending interrupts before enabling them */
260 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
261 if (err < 0)
262 return err;
263 }
264
265 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
266 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
267 if (err < 0)
268 return err;
269
270 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
271 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
272 if (err < 0)
273 return err;
274
275 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
276 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
277 VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
278 if (err < 0)
279 return err;
280
281 if (!en) {
282 /* Clear any pending interrupts after we have disabled them */
283 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
284 if (err < 0)
285 return err;
286 }
287
288 return 0;
289 }
290
aqr_handle_interrupt(struct phy_device * phydev)291 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
292 {
293 int irq_status;
294
295 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
296 MDIO_AN_TX_VEND_INT_STATUS2);
297 if (irq_status < 0) {
298 phy_error(phydev);
299 return IRQ_NONE;
300 }
301
302 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
303 return IRQ_NONE;
304
305 phy_trigger_machine(phydev);
306
307 return IRQ_HANDLED;
308 }
309
aqr_read_status(struct phy_device * phydev)310 static int aqr_read_status(struct phy_device *phydev)
311 {
312 int val;
313
314 if (phydev->autoneg == AUTONEG_ENABLE) {
315 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
316 if (val < 0)
317 return val;
318
319 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
320 phydev->lp_advertising,
321 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
322 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
323 phydev->lp_advertising,
324 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
325 }
326
327 val = genphy_c45_aneg_done(phydev);
328 if (val < 0)
329 return val;
330 if (val) {
331 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RESVD_VEND_STATUS1);
332 if (val < 0)
333 return val;
334 if (val & MDIO_AN_RESVD_VEND_STATUS1_MDIX)
335 phydev->mdix = ETH_TP_MDI_X;
336 else
337 phydev->mdix = ETH_TP_MDI;
338 } else {
339 phydev->mdix = ETH_TP_MDI_INVALID;
340 }
341
342 return genphy_c45_read_status(phydev);
343 }
344
aqr105_get_features(struct phy_device * phydev)345 static int aqr105_get_features(struct phy_device *phydev)
346 {
347 int ret;
348
349 /* Normal feature discovery */
350 ret = genphy_c45_pma_read_abilities(phydev);
351 if (ret)
352 return ret;
353
354 /* The AQR105 PHY misses to indicate the 2.5G and 5G modes, so add them
355 * here
356 */
357 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
358 phydev->supported);
359 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
360 phydev->supported);
361
362 /* The AQR105 PHY suppports both RJ45 and SFP+ interfaces */
363 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
364 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
365
366 return 0;
367 }
368
aqr105_setup_forced(struct phy_device * phydev)369 static int aqr105_setup_forced(struct phy_device *phydev)
370 {
371 int vend = MDIO_AN_VEND_PROV_EXC_PHYID_INFO;
372 int ctrl10 = 0;
373 int adv = ADVERTISE_CSMA;
374 int ret;
375
376 switch (phydev->speed) {
377 case SPEED_100:
378 adv |= ADVERTISE_100FULL;
379 break;
380 case SPEED_1000:
381 adv |= ADVERTISE_NPAGE;
382 if (phydev->duplex == DUPLEX_FULL)
383 vend |= MDIO_AN_VEND_PROV_1000BASET_FULL;
384 else
385 vend |= MDIO_AN_VEND_PROV_1000BASET_HALF;
386 break;
387 case SPEED_2500:
388 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV);
389 vend |= MDIO_AN_VEND_PROV_2500BASET_FULL;
390 break;
391 case SPEED_5000:
392 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV);
393 vend |= MDIO_AN_VEND_PROV_5000BASET_FULL;
394 break;
395 case SPEED_10000:
396 adv |= (ADVERTISE_NPAGE | ADVERTISE_RESV);
397 ctrl10 |= MDIO_AN_10GBT_CTRL_ADV10G;
398 break;
399 default:
400 return -EINVAL;
401 }
402 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, adv);
403 if (ret < 0)
404 return ret;
405 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, vend);
406 if (ret < 0)
407 return ret;
408 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, ctrl10);
409 if (ret < 0)
410 return ret;
411
412 /* set by vendor driver, but should be on by default */
413 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
414 MDIO_AN_CTRL1_XNP);
415 if (ret < 0)
416 return ret;
417
418 return genphy_c45_an_disable_aneg(phydev);
419 }
420
aqr105_config_aneg(struct phy_device * phydev)421 static int aqr105_config_aneg(struct phy_device *phydev)
422 {
423 bool changed = false;
424 u16 reg;
425 int ret;
426
427 ret = aqr_set_mdix(phydev, phydev->mdix_ctrl);
428 if (ret < 0)
429 return ret;
430 if (ret > 0)
431 changed = true;
432
433 if (phydev->autoneg == AUTONEG_DISABLE)
434 return aqr105_setup_forced(phydev);
435
436 ret = genphy_c45_an_config_aneg(phydev);
437 if (ret < 0)
438 return ret;
439 if (ret > 0)
440 changed = true;
441
442 /* Clause 45 has no standardized support for 1000BaseT, therefore
443 * use vendor registers for this mode.
444 */
445 reg = 0;
446 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
447 phydev->advertising))
448 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
449
450 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
451 phydev->advertising))
452 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
453
454 /* Handle the case when the 2.5G and 5G speeds are not advertised */
455 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
456 phydev->advertising))
457 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
458
459 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
460 phydev->advertising))
461 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
462
463 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
464 MDIO_AN_VEND_PROV_1000BASET_HALF |
465 MDIO_AN_VEND_PROV_1000BASET_FULL |
466 MDIO_AN_VEND_PROV_2500BASET_FULL |
467 MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
468 if (ret < 0)
469 return ret;
470 if (ret > 0)
471 changed = true;
472
473 return genphy_c45_check_and_restart_aneg(phydev, changed);
474 }
475
aqr_gen1_read_rate(struct phy_device * phydev)476 static int aqr_gen1_read_rate(struct phy_device *phydev)
477 {
478 int val;
479
480 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
481 if (val < 0)
482 return val;
483
484 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
485 phydev->duplex = DUPLEX_FULL;
486 else
487 phydev->duplex = DUPLEX_HALF;
488
489 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
490 case MDIO_AN_TX_VEND_STATUS1_10BASET:
491 phydev->speed = SPEED_10;
492 break;
493 case MDIO_AN_TX_VEND_STATUS1_100BASETX:
494 phydev->speed = SPEED_100;
495 break;
496 case MDIO_AN_TX_VEND_STATUS1_1000BASET:
497 phydev->speed = SPEED_1000;
498 break;
499 case MDIO_AN_TX_VEND_STATUS1_2500BASET:
500 phydev->speed = SPEED_2500;
501 break;
502 case MDIO_AN_TX_VEND_STATUS1_5000BASET:
503 phydev->speed = SPEED_5000;
504 break;
505 case MDIO_AN_TX_VEND_STATUS1_10GBASET:
506 phydev->speed = SPEED_10000;
507 break;
508 default:
509 phydev->speed = SPEED_UNKNOWN;
510 }
511
512 return 0;
513 }
514
515 /* Quad port PHYs like AQR412(C) have 4 system interfaces, but they can also be
516 * used with a single system interface over which all 4 ports are multiplexed
517 * (10G-QXGMII). To the MDIO registers, this mode is indistinguishable from
518 * USXGMII (which implies a single 10G port).
519 *
520 * To not rely solely on the device tree, we allow the regular system interface
521 * detection to work as usual, but we replace USXGMII with 10G-QXGMII based on
522 * the specific fingerprint of firmware images that are known to be for MUSX.
523 */
aqr_translate_interface(struct phy_device * phydev,phy_interface_t interface)524 static phy_interface_t aqr_translate_interface(struct phy_device *phydev,
525 phy_interface_t interface)
526 {
527 struct aqr107_priv *priv = phydev->priv;
528
529 if (phy_id_compare(phydev->drv->phy_id, PHY_ID_AQR412C, phydev->drv->phy_id_mask) &&
530 priv->fingerprint == AQR_G3_V4_3_C_AQR_NXP_SPF_30841_MUSX_ID40019_VER1198 &&
531 interface == PHY_INTERFACE_MODE_USXGMII)
532 return PHY_INTERFACE_MODE_10G_QXGMII;
533
534 return interface;
535 }
536
aqr_gen1_read_status(struct phy_device * phydev)537 static int aqr_gen1_read_status(struct phy_device *phydev)
538 {
539 phy_interface_t interface;
540 int ret;
541 int val;
542
543 ret = aqr_read_status(phydev);
544 if (ret)
545 return ret;
546
547 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
548 return 0;
549
550 /* The status register is not immediately correct on line side link up.
551 * Poll periodically until it reflects the correct ON state.
552 * Only return fail for read error, timeout defaults to OFF state.
553 */
554 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PHYXS,
555 MDIO_PHYXS_VEND_IF_STATUS, val,
556 (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val) !=
557 MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF),
558 AQR107_OP_IN_PROG_SLEEP,
559 AQR107_OP_IN_PROG_TIMEOUT, false);
560 if (ret && ret != -ETIMEDOUT)
561 return ret;
562
563 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
564 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
565 interface = PHY_INTERFACE_MODE_10GKR;
566 break;
567 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
568 interface = PHY_INTERFACE_MODE_1000BASEKX;
569 break;
570 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
571 interface = PHY_INTERFACE_MODE_10GBASER;
572 break;
573 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
574 interface = PHY_INTERFACE_MODE_USXGMII;
575 break;
576 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
577 interface = PHY_INTERFACE_MODE_XAUI;
578 break;
579 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
580 interface = PHY_INTERFACE_MODE_SGMII;
581 break;
582 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
583 interface = PHY_INTERFACE_MODE_RXAUI;
584 break;
585 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
586 interface = PHY_INTERFACE_MODE_2500BASEX;
587 break;
588 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OFF:
589 default:
590 phydev->link = false;
591 interface = PHY_INTERFACE_MODE_NA;
592 break;
593 }
594
595 phydev->interface = aqr_translate_interface(phydev, interface);
596
597 /* Read rate from vendor register */
598 return aqr_gen1_read_rate(phydev);
599 }
600
aqr_gen2_read_status(struct phy_device * phydev)601 static int aqr_gen2_read_status(struct phy_device *phydev)
602 {
603 struct aqr107_priv *priv = phydev->priv;
604 int i, ret;
605
606 ret = aqr_gen1_read_status(phydev);
607 if (ret)
608 return ret;
609
610 for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {
611 struct aqr_global_syscfg *syscfg = &priv->global_cfg[i];
612
613 if (syscfg->speed != phydev->speed)
614 continue;
615
616 if (syscfg->rate_adapt == AQR_RATE_ADAPT_PAUSE)
617 phydev->rate_matching = RATE_MATCH_PAUSE;
618 else
619 phydev->rate_matching = RATE_MATCH_NONE;
620 break;
621 }
622
623 return 0;
624 }
625
aqr107_get_downshift(struct phy_device * phydev,u8 * data)626 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
627 {
628 int val, cnt, enable;
629
630 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
631 if (val < 0)
632 return val;
633
634 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
635 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
636
637 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
638
639 return 0;
640 }
641
aqr107_set_downshift(struct phy_device * phydev,u8 cnt)642 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
643 {
644 int val = 0;
645
646 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
647 return -E2BIG;
648
649 if (cnt != DOWNSHIFT_DEV_DISABLE) {
650 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
651 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
652 }
653
654 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
655 MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
656 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
657 }
658
aqr107_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)659 static int aqr107_get_tunable(struct phy_device *phydev,
660 struct ethtool_tunable *tuna, void *data)
661 {
662 switch (tuna->id) {
663 case ETHTOOL_PHY_DOWNSHIFT:
664 return aqr107_get_downshift(phydev, data);
665 default:
666 return -EOPNOTSUPP;
667 }
668 }
669
aqr107_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)670 static int aqr107_set_tunable(struct phy_device *phydev,
671 struct ethtool_tunable *tuna, const void *data)
672 {
673 switch (tuna->id) {
674 case ETHTOOL_PHY_DOWNSHIFT:
675 return aqr107_set_downshift(phydev, *(const u8 *)data);
676 default:
677 return -EOPNOTSUPP;
678 }
679 }
680
681 #define AQR_FW_WAIT_SLEEP_US 20000
682 #define AQR_FW_WAIT_TIMEOUT_US 2000000
683
684 /* If we configure settings whilst firmware is still initializing the chip,
685 * then these settings may be overwritten. Therefore make sure chip
686 * initialization has completed. Use presence of the firmware ID as
687 * indicator for initialization having completed.
688 * The chip also provides a "reset completed" bit, but it's cleared after
689 * read. Therefore function would time out if called again.
690 */
aqr_wait_reset_complete(struct phy_device * phydev)691 int aqr_wait_reset_complete(struct phy_device *phydev)
692 {
693 int ret, val;
694
695 ret = read_poll_timeout(phy_read_mmd, val, val != 0,
696 AQR_FW_WAIT_SLEEP_US, AQR_FW_WAIT_TIMEOUT_US,
697 false, phydev, MDIO_MMD_VEND1,
698 VEND1_GLOBAL_FW_ID);
699 if (val < 0) {
700 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n",
701 ERR_PTR(val));
702 return val;
703 }
704
705 return ret;
706 }
707
aqr_build_fingerprint(struct phy_device * phydev)708 static int aqr_build_fingerprint(struct phy_device *phydev)
709 {
710 u8 fw_major, fw_minor, build_id, prov_id;
711 struct aqr107_priv *priv = phydev->priv;
712 u16 misc_id, misc_ver;
713 int val;
714
715 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
716 if (val < 0)
717 return val;
718
719 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
720 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
721
722 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
723 if (val < 0)
724 return val;
725
726 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
727 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
728
729 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_FW_MISC_ID);
730 if (val < 0)
731 return val;
732
733 misc_id = val;
734
735 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_FW_MISC_VER);
736 if (val < 0)
737 return val;
738
739 misc_ver = val;
740
741 priv->fingerprint = AQR_FW_FINGERPRINT(fw_major, fw_minor, build_id,
742 prov_id, misc_id, misc_ver);
743
744 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u, Misc ID %u, Version %u\n",
745 fw_major, fw_minor, build_id, prov_id, misc_id, misc_ver);
746
747 return 0;
748 }
749
aqr107_config_mdi(struct phy_device * phydev)750 static int aqr107_config_mdi(struct phy_device *phydev)
751 {
752 struct device_node *np = phydev->mdio.dev.of_node;
753 u32 mdi_conf;
754 int ret;
755
756 ret = of_property_read_u32(np, "marvell,mdi-cfg-order", &mdi_conf);
757
758 /* Do nothing in case property "marvell,mdi-cfg-order" is not present */
759 if (ret == -EINVAL || ret == -ENOSYS)
760 return 0;
761
762 if (ret)
763 return ret;
764
765 if (mdi_conf & ~PMAPMD_RSVD_VEND_PROV_MDI_REVERSE)
766 return -EINVAL;
767
768 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV,
769 PMAPMD_RSVD_VEND_PROV_MDI_CONF,
770 mdi_conf | PMAPMD_RSVD_VEND_PROV_MDI_FORCE);
771 }
772
aqr_gen1_config_init(struct phy_device * phydev)773 static int aqr_gen1_config_init(struct phy_device *phydev)
774 {
775 struct aqr107_priv *priv = phydev->priv;
776 u32 led_idx;
777 int ret;
778
779 /* Check that the PHY interface type is compatible */
780 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
781 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
782 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
783 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
784 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
785 phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII &&
786 phydev->interface != PHY_INTERFACE_MODE_10GKR &&
787 phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
788 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
789 phydev->interface != PHY_INTERFACE_MODE_RXAUI)
790 return -ENODEV;
791
792 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
793 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
794
795 ret = aqr_wait_reset_complete(phydev);
796 if (!ret) {
797 /* The PHY might work without a firmware image, so only build a
798 * fingerprint if the firmware was initialized.
799 */
800 ret = aqr_build_fingerprint(phydev);
801 if (ret)
802 return ret;
803 }
804
805 ret = aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
806 if (ret)
807 return ret;
808
809 ret = aqr107_config_mdi(phydev);
810 if (ret)
811 return ret;
812
813 /* Restore LED polarity state after reset */
814 for_each_set_bit(led_idx, &priv->leds_active_low, AQR_MAX_LEDS) {
815 ret = aqr_phy_led_active_low_set(phydev, led_idx, true);
816 if (ret)
817 return ret;
818 }
819
820 for_each_set_bit(led_idx, &priv->leds_active_high, AQR_MAX_LEDS) {
821 ret = aqr_phy_led_active_low_set(phydev, led_idx, false);
822 if (ret)
823 return ret;
824 }
825
826 return 0;
827 }
828
829 /* Walk the media-speed configuration registers to determine which
830 * host-side serdes modes may be used by the PHY depending on the
831 * negotiated media speed.
832 */
aqr_gen2_read_global_syscfg(struct phy_device * phydev)833 static int aqr_gen2_read_global_syscfg(struct phy_device *phydev)
834 {
835 struct aqr107_priv *priv = phydev->priv;
836 unsigned int serdes_mode, rate_adapt;
837 phy_interface_t interface;
838 int i, val;
839
840 for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {
841 struct aqr_global_syscfg *syscfg = &priv->global_cfg[i];
842
843 syscfg->speed = aqr_global_cfg_regs[i].speed;
844
845 val = phy_read_mmd(phydev, MDIO_MMD_VEND1,
846 aqr_global_cfg_regs[i].reg);
847 if (val < 0)
848 return val;
849
850 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val);
851 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val);
852
853 switch (serdes_mode) {
854 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI:
855 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX)
856 interface = PHY_INTERFACE_MODE_USXGMII;
857 else
858 interface = PHY_INTERFACE_MODE_10GBASER;
859 break;
860
861 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G:
862 interface = PHY_INTERFACE_MODE_5GBASER;
863 break;
864
865 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII:
866 interface = PHY_INTERFACE_MODE_2500BASEX;
867 break;
868
869 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII:
870 interface = PHY_INTERFACE_MODE_SGMII;
871 break;
872
873 default:
874 phydev_warn(phydev, "unrecognised serdes mode %u\n",
875 serdes_mode);
876 interface = PHY_INTERFACE_MODE_NA;
877 break;
878 }
879
880 syscfg->interface = aqr_translate_interface(phydev, interface);
881
882 switch (rate_adapt) {
883 case VEND1_GLOBAL_CFG_RATE_ADAPT_NONE:
884 syscfg->rate_adapt = AQR_RATE_ADAPT_NONE;
885 break;
886 case VEND1_GLOBAL_CFG_RATE_ADAPT_USX:
887 syscfg->rate_adapt = AQR_RATE_ADAPT_USX;
888 break;
889 case VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE:
890 syscfg->rate_adapt = AQR_RATE_ADAPT_PAUSE;
891 break;
892 default:
893 phydev_warn(phydev, "unrecognized rate adapt mode %u\n",
894 rate_adapt);
895 break;
896 }
897
898 phydev_dbg(phydev,
899 "Media speed %d uses host interface %s with %s\n",
900 syscfg->speed, phy_modes(syscfg->interface),
901 syscfg->rate_adapt == AQR_RATE_ADAPT_NONE ? "no rate adaptation" :
902 syscfg->rate_adapt == AQR_RATE_ADAPT_PAUSE ? "rate adaptation through flow control" :
903 syscfg->rate_adapt == AQR_RATE_ADAPT_USX ? "rate adaptation through symbol replication" :
904 "unrecognized rate adaptation type");
905 }
906
907 return 0;
908 }
909
aqr_gen2_fill_interface_modes(struct phy_device * phydev)910 static int aqr_gen2_fill_interface_modes(struct phy_device *phydev)
911 {
912 unsigned long *possible = phydev->possible_interfaces;
913 struct aqr107_priv *priv = phydev->priv;
914 phy_interface_t interface;
915 int i, val, ret;
916
917 /* It's been observed on some models that - when coming out of suspend
918 * - the FW signals that the PHY is ready but the GLOBAL_CFG registers
919 * continue on returning zeroes for some time. Let's poll the 100M
920 * register until it returns a real value as both 113c and 115c support
921 * this mode.
922 */
923 if (priv->wait_on_global_cfg) {
924 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
925 VEND1_GLOBAL_CFG_100M, val,
926 val != 0, 1000, 100000, false);
927 if (ret)
928 return ret;
929 }
930
931 ret = aqr_gen2_read_global_syscfg(phydev);
932 if (ret)
933 return ret;
934
935 for (i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {
936 interface = priv->global_cfg[i].interface;
937 if (interface != PHY_INTERFACE_MODE_NA)
938 __set_bit(interface, possible);
939 }
940
941 return 0;
942 }
943
aqr_gen2_config_init(struct phy_device * phydev)944 static int aqr_gen2_config_init(struct phy_device *phydev)
945 {
946 int ret;
947
948 ret = aqr_gen1_config_init(phydev);
949 if (ret)
950 return ret;
951
952 return aqr_gen2_fill_interface_modes(phydev);
953 }
954
aqr_gen3_config_init(struct phy_device * phydev)955 static int aqr_gen3_config_init(struct phy_device *phydev)
956 {
957 return aqr_gen2_config_init(phydev);
958 }
959
aqcs109_config_init(struct phy_device * phydev)960 static int aqcs109_config_init(struct phy_device *phydev)
961 {
962 /* Check that the PHY interface type is compatible */
963 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
964 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
965 return -ENODEV;
966
967 return aqr_gen2_config_init(phydev);
968 }
969
aqr107_link_change_notify(struct phy_device * phydev)970 static void aqr107_link_change_notify(struct phy_device *phydev)
971 {
972 u8 fw_major, fw_minor;
973 bool downshift, short_reach, afr;
974 int mode, val;
975
976 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
977 return;
978
979 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
980 /* call failed or link partner is no Aquantia PHY */
981 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
982 return;
983
984 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
985 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
986
987 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
988 if (val < 0)
989 return;
990
991 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
992 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
993
994 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
995 if (val < 0)
996 return;
997
998 afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
999
1000 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
1001 fw_major, fw_minor,
1002 short_reach ? ", short reach mode" : "",
1003 downshift ? ", fast-retrain downshift advertised" : "",
1004 afr ? ", fast reframe advertised" : "");
1005
1006 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
1007 if (val < 0)
1008 return;
1009
1010 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
1011 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
1012 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
1013 }
1014
aqr_gen1_wait_processor_intensive_op(struct phy_device * phydev)1015 static int aqr_gen1_wait_processor_intensive_op(struct phy_device *phydev)
1016 {
1017 int val, err;
1018
1019 /* The datasheet notes to wait at least 1ms after issuing a
1020 * processor intensive operation before checking.
1021 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
1022 * because that just determines the maximum time slept, not the minimum.
1023 */
1024 usleep_range(1000, 5000);
1025
1026 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1027 VEND1_GLOBAL_GEN_STAT2, val,
1028 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
1029 AQR107_OP_IN_PROG_SLEEP,
1030 AQR107_OP_IN_PROG_TIMEOUT, false);
1031 if (err) {
1032 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
1033 return err;
1034 }
1035
1036 return 0;
1037 }
1038
aqr_gen2_get_rate_matching(struct phy_device * phydev,phy_interface_t iface)1039 static int aqr_gen2_get_rate_matching(struct phy_device *phydev,
1040 phy_interface_t iface)
1041 {
1042 if (iface == PHY_INTERFACE_MODE_10GBASER ||
1043 iface == PHY_INTERFACE_MODE_2500BASEX)
1044 return RATE_MATCH_PAUSE;
1045 return RATE_MATCH_NONE;
1046 }
1047
aqr_gen1_suspend(struct phy_device * phydev)1048 static int aqr_gen1_suspend(struct phy_device *phydev)
1049 {
1050 int err;
1051
1052 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1053 MDIO_CTRL1_LPOWER);
1054 if (err)
1055 return err;
1056
1057 return aqr_gen1_wait_processor_intensive_op(phydev);
1058 }
1059
aqr_gen1_resume(struct phy_device * phydev)1060 static int aqr_gen1_resume(struct phy_device *phydev)
1061 {
1062 int err;
1063
1064 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1065 MDIO_CTRL1_LPOWER);
1066 if (err)
1067 return err;
1068
1069 return aqr_gen1_wait_processor_intensive_op(phydev);
1070 }
1071
aqr115c_get_features(struct phy_device * phydev)1072 static int aqr115c_get_features(struct phy_device *phydev)
1073 {
1074 unsigned long *supported = phydev->supported;
1075
1076 /* PHY supports speeds up to 2.5G with autoneg. PMA capabilities
1077 * are not useful.
1078 */
1079 linkmode_or(supported, supported, phy_gbit_features);
1080 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, supported);
1081
1082 return 0;
1083 }
1084
aqr111_get_features(struct phy_device * phydev)1085 static int aqr111_get_features(struct phy_device *phydev)
1086 {
1087 /* PHY supports speeds up to 5G with autoneg. PMA capabilities
1088 * are not useful.
1089 */
1090 aqr115c_get_features(phydev);
1091 linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1092 phydev->supported);
1093
1094 return 0;
1095 }
1096
aqr_gen4_config_init(struct phy_device * phydev)1097 static int aqr_gen4_config_init(struct phy_device *phydev)
1098 {
1099 struct aqr107_priv *priv = phydev->priv;
1100 int ret;
1101
1102 priv->wait_on_global_cfg = true;
1103
1104 ret = aqr_gen3_config_init(phydev);
1105 if (ret < 0)
1106 return ret;
1107
1108 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS,
1109 MDIO_PMD_TXDIS_GLOBAL);
1110 if (ret)
1111 return ret;
1112
1113 return aqr_gen1_wait_processor_intensive_op(phydev);
1114 }
1115
aqr_gen2_inband_caps(struct phy_device * phydev,phy_interface_t interface)1116 static unsigned int aqr_gen2_inband_caps(struct phy_device *phydev,
1117 phy_interface_t interface)
1118 {
1119 if (interface == PHY_INTERFACE_MODE_SGMII ||
1120 interface == PHY_INTERFACE_MODE_USXGMII ||
1121 interface == PHY_INTERFACE_MODE_10G_QXGMII)
1122 return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
1123
1124 return 0;
1125 }
1126
aqr_gen2_config_inband(struct phy_device * phydev,unsigned int modes)1127 static int aqr_gen2_config_inband(struct phy_device *phydev, unsigned int modes)
1128 {
1129 struct aqr107_priv *priv = phydev->priv;
1130
1131 if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
1132 phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) {
1133 u16 set = 0;
1134
1135 if (modes == LINK_INBAND_ENABLE)
1136 set = MDIO_PHYXS_VEND_PROV2_USX_AN;
1137
1138 return phy_modify_mmd(phydev, MDIO_MMD_PHYXS,
1139 MDIO_PHYXS_VEND_PROV2,
1140 MDIO_PHYXS_VEND_PROV2_USX_AN, set);
1141 }
1142
1143 for (int i = 0; i < AQR_NUM_GLOBAL_CFG; i++) {
1144 struct aqr_global_syscfg *syscfg = &priv->global_cfg[i];
1145 u16 set = 0;
1146 int err;
1147
1148 if (syscfg->interface != phydev->interface)
1149 continue;
1150
1151 if (modes == LINK_INBAND_ENABLE)
1152 set = VEND1_GLOBAL_CFG_AUTONEG_ENA;
1153
1154 err = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1155 aqr_global_cfg_regs[i].reg,
1156 VEND1_GLOBAL_CFG_AUTONEG_ENA, set);
1157 if (err)
1158 return err;
1159 }
1160
1161 return 0;
1162 }
1163
aqr107_probe(struct phy_device * phydev)1164 static int aqr107_probe(struct phy_device *phydev)
1165 {
1166 int ret;
1167
1168 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
1169 sizeof(struct aqr107_priv), GFP_KERNEL);
1170 if (!phydev->priv)
1171 return -ENOMEM;
1172
1173 ret = aqr_firmware_load(phydev);
1174 if (ret)
1175 return ret;
1176
1177 return aqr_hwmon_probe(phydev);
1178 }
1179
1180
1181 static struct phy_driver aqr_driver[] = {
1182 {
1183 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
1184 .name = "Aquantia AQ1202",
1185 .config_aneg = aqr_config_aneg,
1186 .config_intr = aqr_config_intr,
1187 .handle_interrupt = aqr_handle_interrupt,
1188 .read_status = aqr_read_status,
1189 },
1190 {
1191 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
1192 .name = "Aquantia AQ2104",
1193 .config_aneg = aqr_config_aneg,
1194 .config_intr = aqr_config_intr,
1195 .handle_interrupt = aqr_handle_interrupt,
1196 .read_status = aqr_read_status,
1197 },
1198 {
1199 PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
1200 .name = "Aquantia AQR105",
1201 .get_features = aqr105_get_features,
1202 .probe = aqr107_probe,
1203 .config_init = aqr_gen1_config_init,
1204 .config_aneg = aqr105_config_aneg,
1205 .config_intr = aqr_config_intr,
1206 .handle_interrupt = aqr_handle_interrupt,
1207 .read_status = aqr_gen1_read_status,
1208 .suspend = aqr_gen1_suspend,
1209 .resume = aqr_gen1_resume,
1210 },
1211 {
1212 PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
1213 .name = "Aquantia AQR106",
1214 .config_aneg = aqr_config_aneg,
1215 .config_intr = aqr_config_intr,
1216 .handle_interrupt = aqr_handle_interrupt,
1217 .read_status = aqr_read_status,
1218 },
1219 {
1220 PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
1221 .name = "Aquantia AQR107",
1222 .probe = aqr107_probe,
1223 .get_rate_matching = aqr_gen2_get_rate_matching,
1224 .config_init = aqr_gen2_config_init,
1225 .config_aneg = aqr_config_aneg,
1226 .config_intr = aqr_config_intr,
1227 .handle_interrupt = aqr_handle_interrupt,
1228 .read_status = aqr_gen2_read_status,
1229 .get_tunable = aqr107_get_tunable,
1230 .set_tunable = aqr107_set_tunable,
1231 .suspend = aqr_gen1_suspend,
1232 .resume = aqr_gen1_resume,
1233 .get_sset_count = aqr107_get_sset_count,
1234 .get_strings = aqr107_get_strings,
1235 .get_stats = aqr107_get_stats,
1236 .link_change_notify = aqr107_link_change_notify,
1237 .led_brightness_set = aqr_phy_led_brightness_set,
1238 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1239 .led_hw_control_set = aqr_phy_led_hw_control_set,
1240 .led_hw_control_get = aqr_phy_led_hw_control_get,
1241 .led_polarity_set = aqr_phy_led_polarity_set,
1242 .inband_caps = aqr_gen2_inband_caps,
1243 .config_inband = aqr_gen2_config_inband,
1244 },
1245 {
1246 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
1247 .name = "Aquantia AQCS109",
1248 .probe = aqr107_probe,
1249 .get_rate_matching = aqr_gen2_get_rate_matching,
1250 .config_init = aqcs109_config_init,
1251 .config_aneg = aqr_config_aneg,
1252 .config_intr = aqr_config_intr,
1253 .handle_interrupt = aqr_handle_interrupt,
1254 .read_status = aqr_gen2_read_status,
1255 .get_tunable = aqr107_get_tunable,
1256 .set_tunable = aqr107_set_tunable,
1257 .suspend = aqr_gen1_suspend,
1258 .resume = aqr_gen1_resume,
1259 .get_sset_count = aqr107_get_sset_count,
1260 .get_strings = aqr107_get_strings,
1261 .get_stats = aqr107_get_stats,
1262 .get_features = aqr115c_get_features,
1263 .link_change_notify = aqr107_link_change_notify,
1264 .led_brightness_set = aqr_phy_led_brightness_set,
1265 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1266 .led_hw_control_set = aqr_phy_led_hw_control_set,
1267 .led_hw_control_get = aqr_phy_led_hw_control_get,
1268 .led_polarity_set = aqr_phy_led_polarity_set,
1269 .inband_caps = aqr_gen2_inband_caps,
1270 .config_inband = aqr_gen2_config_inband,
1271 },
1272 {
1273 PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
1274 .name = "Aquantia AQR111",
1275 .probe = aqr107_probe,
1276 .get_rate_matching = aqr_gen2_get_rate_matching,
1277 .config_init = aqr_gen3_config_init,
1278 .config_aneg = aqr_config_aneg,
1279 .config_intr = aqr_config_intr,
1280 .handle_interrupt = aqr_handle_interrupt,
1281 .read_status = aqr_gen2_read_status,
1282 .get_tunable = aqr107_get_tunable,
1283 .set_tunable = aqr107_set_tunable,
1284 .suspend = aqr_gen1_suspend,
1285 .resume = aqr_gen1_resume,
1286 .get_sset_count = aqr107_get_sset_count,
1287 .get_strings = aqr107_get_strings,
1288 .get_stats = aqr107_get_stats,
1289 .get_features = aqr111_get_features,
1290 .link_change_notify = aqr107_link_change_notify,
1291 .led_brightness_set = aqr_phy_led_brightness_set,
1292 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1293 .led_hw_control_set = aqr_phy_led_hw_control_set,
1294 .led_hw_control_get = aqr_phy_led_hw_control_get,
1295 .led_polarity_set = aqr_phy_led_polarity_set,
1296 .inband_caps = aqr_gen2_inband_caps,
1297 .config_inband = aqr_gen2_config_inband,
1298 },
1299 {
1300 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
1301 .name = "Aquantia AQR111B0",
1302 .probe = aqr107_probe,
1303 .get_rate_matching = aqr_gen2_get_rate_matching,
1304 .config_init = aqr_gen3_config_init,
1305 .config_aneg = aqr_config_aneg,
1306 .config_intr = aqr_config_intr,
1307 .handle_interrupt = aqr_handle_interrupt,
1308 .read_status = aqr_gen2_read_status,
1309 .get_tunable = aqr107_get_tunable,
1310 .set_tunable = aqr107_set_tunable,
1311 .suspend = aqr_gen1_suspend,
1312 .resume = aqr_gen1_resume,
1313 .get_sset_count = aqr107_get_sset_count,
1314 .get_strings = aqr107_get_strings,
1315 .get_stats = aqr107_get_stats,
1316 .get_features = aqr111_get_features,
1317 .link_change_notify = aqr107_link_change_notify,
1318 .led_brightness_set = aqr_phy_led_brightness_set,
1319 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1320 .led_hw_control_set = aqr_phy_led_hw_control_set,
1321 .led_hw_control_get = aqr_phy_led_hw_control_get,
1322 .led_polarity_set = aqr_phy_led_polarity_set,
1323 .inband_caps = aqr_gen2_inband_caps,
1324 .config_inband = aqr_gen2_config_inband,
1325 },
1326 {
1327 PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
1328 .name = "Aquantia AQR405",
1329 .config_aneg = aqr_config_aneg,
1330 .config_intr = aqr_config_intr,
1331 .handle_interrupt = aqr_handle_interrupt,
1332 .read_status = aqr_read_status,
1333 .inband_caps = aqr_gen2_inband_caps,
1334 .config_inband = aqr_gen2_config_inband,
1335 },
1336 {
1337 PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
1338 .name = "Aquantia AQR112",
1339 .probe = aqr107_probe,
1340 .config_init = aqr_gen3_config_init,
1341 .config_aneg = aqr_config_aneg,
1342 .config_intr = aqr_config_intr,
1343 .handle_interrupt = aqr_handle_interrupt,
1344 .get_tunable = aqr107_get_tunable,
1345 .set_tunable = aqr107_set_tunable,
1346 .suspend = aqr_gen1_suspend,
1347 .resume = aqr_gen1_resume,
1348 .read_status = aqr_gen2_read_status,
1349 .get_rate_matching = aqr_gen2_get_rate_matching,
1350 .get_sset_count = aqr107_get_sset_count,
1351 .get_strings = aqr107_get_strings,
1352 .get_stats = aqr107_get_stats,
1353 .link_change_notify = aqr107_link_change_notify,
1354 .led_brightness_set = aqr_phy_led_brightness_set,
1355 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1356 .led_hw_control_set = aqr_phy_led_hw_control_set,
1357 .led_hw_control_get = aqr_phy_led_hw_control_get,
1358 .led_polarity_set = aqr_phy_led_polarity_set,
1359 .inband_caps = aqr_gen2_inband_caps,
1360 .config_inband = aqr_gen2_config_inband,
1361 },
1362 {
1363 PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
1364 .name = "Aquantia AQR412",
1365 .probe = aqr107_probe,
1366 .config_init = aqr_gen3_config_init,
1367 .config_aneg = aqr_config_aneg,
1368 .config_intr = aqr_config_intr,
1369 .handle_interrupt = aqr_handle_interrupt,
1370 .get_tunable = aqr107_get_tunable,
1371 .set_tunable = aqr107_set_tunable,
1372 .suspend = aqr_gen1_suspend,
1373 .resume = aqr_gen1_resume,
1374 .read_status = aqr_gen2_read_status,
1375 .get_rate_matching = aqr_gen2_get_rate_matching,
1376 .get_sset_count = aqr107_get_sset_count,
1377 .get_strings = aqr107_get_strings,
1378 .get_stats = aqr107_get_stats,
1379 .link_change_notify = aqr107_link_change_notify,
1380 .inband_caps = aqr_gen2_inband_caps,
1381 .config_inband = aqr_gen2_config_inband,
1382 },
1383 {
1384 PHY_ID_MATCH_MODEL(PHY_ID_AQR412C),
1385 .name = "Aquantia AQR412C",
1386 .probe = aqr107_probe,
1387 .config_init = aqr_gen3_config_init,
1388 .config_aneg = aqr_config_aneg,
1389 .config_intr = aqr_config_intr,
1390 .handle_interrupt = aqr_handle_interrupt,
1391 .get_tunable = aqr107_get_tunable,
1392 .set_tunable = aqr107_set_tunable,
1393 .suspend = aqr_gen1_suspend,
1394 .resume = aqr_gen1_resume,
1395 .read_status = aqr_gen2_read_status,
1396 .get_rate_matching = aqr_gen2_get_rate_matching,
1397 .get_sset_count = aqr107_get_sset_count,
1398 .get_strings = aqr107_get_strings,
1399 .get_stats = aqr107_get_stats,
1400 .link_change_notify = aqr107_link_change_notify,
1401 .inband_caps = aqr_gen2_inband_caps,
1402 .config_inband = aqr_gen2_config_inband,
1403 },
1404 {
1405 PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
1406 .name = "Aquantia AQR113",
1407 .probe = aqr107_probe,
1408 .get_rate_matching = aqr_gen2_get_rate_matching,
1409 .config_init = aqr_gen4_config_init,
1410 .config_aneg = aqr_config_aneg,
1411 .config_intr = aqr_config_intr,
1412 .handle_interrupt = aqr_handle_interrupt,
1413 .read_status = aqr_gen2_read_status,
1414 .get_tunable = aqr107_get_tunable,
1415 .set_tunable = aqr107_set_tunable,
1416 .suspend = aqr_gen1_suspend,
1417 .resume = aqr_gen1_resume,
1418 .get_sset_count = aqr107_get_sset_count,
1419 .get_strings = aqr107_get_strings,
1420 .get_stats = aqr107_get_stats,
1421 .link_change_notify = aqr107_link_change_notify,
1422 .led_brightness_set = aqr_phy_led_brightness_set,
1423 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1424 .led_hw_control_set = aqr_phy_led_hw_control_set,
1425 .led_hw_control_get = aqr_phy_led_hw_control_get,
1426 .led_polarity_set = aqr_phy_led_polarity_set,
1427 .inband_caps = aqr_gen2_inband_caps,
1428 .config_inband = aqr_gen2_config_inband,
1429 },
1430 {
1431 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
1432 .name = "Aquantia AQR113C",
1433 .probe = aqr107_probe,
1434 .get_rate_matching = aqr_gen2_get_rate_matching,
1435 .config_init = aqr_gen4_config_init,
1436 .config_aneg = aqr_config_aneg,
1437 .config_intr = aqr_config_intr,
1438 .handle_interrupt = aqr_handle_interrupt,
1439 .read_status = aqr_gen2_read_status,
1440 .get_tunable = aqr107_get_tunable,
1441 .set_tunable = aqr107_set_tunable,
1442 .suspend = aqr_gen1_suspend,
1443 .resume = aqr_gen1_resume,
1444 .get_sset_count = aqr107_get_sset_count,
1445 .get_strings = aqr107_get_strings,
1446 .get_stats = aqr107_get_stats,
1447 .link_change_notify = aqr107_link_change_notify,
1448 .led_brightness_set = aqr_phy_led_brightness_set,
1449 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1450 .led_hw_control_set = aqr_phy_led_hw_control_set,
1451 .led_hw_control_get = aqr_phy_led_hw_control_get,
1452 .led_polarity_set = aqr_phy_led_polarity_set,
1453 .inband_caps = aqr_gen2_inband_caps,
1454 .config_inband = aqr_gen2_config_inband,
1455 },
1456 {
1457 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
1458 .name = "Aquantia AQR114C",
1459 .probe = aqr107_probe,
1460 .get_rate_matching = aqr_gen2_get_rate_matching,
1461 .config_init = aqr_gen4_config_init,
1462 .config_aneg = aqr_config_aneg,
1463 .config_intr = aqr_config_intr,
1464 .handle_interrupt = aqr_handle_interrupt,
1465 .read_status = aqr_gen2_read_status,
1466 .get_tunable = aqr107_get_tunable,
1467 .set_tunable = aqr107_set_tunable,
1468 .suspend = aqr_gen1_suspend,
1469 .resume = aqr_gen1_resume,
1470 .get_sset_count = aqr107_get_sset_count,
1471 .get_strings = aqr107_get_strings,
1472 .get_stats = aqr107_get_stats,
1473 .get_features = aqr111_get_features,
1474 .link_change_notify = aqr107_link_change_notify,
1475 .led_brightness_set = aqr_phy_led_brightness_set,
1476 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1477 .led_hw_control_set = aqr_phy_led_hw_control_set,
1478 .led_hw_control_get = aqr_phy_led_hw_control_get,
1479 .led_polarity_set = aqr_phy_led_polarity_set,
1480 .inband_caps = aqr_gen2_inband_caps,
1481 .config_inband = aqr_gen2_config_inband,
1482 },
1483 {
1484 PHY_ID_MATCH_MODEL(PHY_ID_AQR115),
1485 .name = "Aquantia AQR115",
1486 .probe = aqr107_probe,
1487 .get_rate_matching = aqr_gen2_get_rate_matching,
1488 .config_init = aqr_gen4_config_init,
1489 .config_aneg = aqr_config_aneg,
1490 .config_intr = aqr_config_intr,
1491 .handle_interrupt = aqr_handle_interrupt,
1492 .read_status = aqr_gen2_read_status,
1493 .get_tunable = aqr107_get_tunable,
1494 .set_tunable = aqr107_set_tunable,
1495 .suspend = aqr_gen1_suspend,
1496 .resume = aqr_gen1_resume,
1497 .get_sset_count = aqr107_get_sset_count,
1498 .get_strings = aqr107_get_strings,
1499 .get_stats = aqr107_get_stats,
1500 .get_features = aqr115c_get_features,
1501 .link_change_notify = aqr107_link_change_notify,
1502 .led_brightness_set = aqr_phy_led_brightness_set,
1503 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1504 .led_hw_control_set = aqr_phy_led_hw_control_set,
1505 .led_hw_control_get = aqr_phy_led_hw_control_get,
1506 .led_polarity_set = aqr_phy_led_polarity_set,
1507 .inband_caps = aqr_gen2_inband_caps,
1508 .config_inband = aqr_gen2_config_inband,
1509 },
1510 {
1511 PHY_ID_MATCH_MODEL(PHY_ID_AQR115C),
1512 .name = "Aquantia AQR115C",
1513 .probe = aqr107_probe,
1514 .get_rate_matching = aqr_gen2_get_rate_matching,
1515 .config_init = aqr_gen4_config_init,
1516 .config_aneg = aqr_config_aneg,
1517 .config_intr = aqr_config_intr,
1518 .handle_interrupt = aqr_handle_interrupt,
1519 .read_status = aqr_gen2_read_status,
1520 .get_tunable = aqr107_get_tunable,
1521 .set_tunable = aqr107_set_tunable,
1522 .suspend = aqr_gen1_suspend,
1523 .resume = aqr_gen1_resume,
1524 .get_sset_count = aqr107_get_sset_count,
1525 .get_strings = aqr107_get_strings,
1526 .get_stats = aqr107_get_stats,
1527 .get_features = aqr115c_get_features,
1528 .link_change_notify = aqr107_link_change_notify,
1529 .led_brightness_set = aqr_phy_led_brightness_set,
1530 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1531 .led_hw_control_set = aqr_phy_led_hw_control_set,
1532 .led_hw_control_get = aqr_phy_led_hw_control_get,
1533 .led_polarity_set = aqr_phy_led_polarity_set,
1534 .inband_caps = aqr_gen2_inband_caps,
1535 .config_inband = aqr_gen2_config_inband,
1536 },
1537 {
1538 PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
1539 .name = "Aquantia AQR813",
1540 .probe = aqr107_probe,
1541 .get_rate_matching = aqr_gen2_get_rate_matching,
1542 .config_init = aqr_gen4_config_init,
1543 .config_aneg = aqr_config_aneg,
1544 .config_intr = aqr_config_intr,
1545 .handle_interrupt = aqr_handle_interrupt,
1546 .read_status = aqr_gen2_read_status,
1547 .get_tunable = aqr107_get_tunable,
1548 .set_tunable = aqr107_set_tunable,
1549 .suspend = aqr_gen1_suspend,
1550 .resume = aqr_gen1_resume,
1551 .get_sset_count = aqr107_get_sset_count,
1552 .get_strings = aqr107_get_strings,
1553 .get_stats = aqr107_get_stats,
1554 .link_change_notify = aqr107_link_change_notify,
1555 .led_brightness_set = aqr_phy_led_brightness_set,
1556 .led_hw_is_supported = aqr_phy_led_hw_is_supported,
1557 .led_hw_control_set = aqr_phy_led_hw_control_set,
1558 .led_hw_control_get = aqr_phy_led_hw_control_get,
1559 .led_polarity_set = aqr_phy_led_polarity_set,
1560 .inband_caps = aqr_gen2_inband_caps,
1561 .config_inband = aqr_gen2_config_inband,
1562 },
1563 };
1564
1565 module_phy_driver(aqr_driver);
1566
1567 static const struct mdio_device_id __maybe_unused aqr_tbl[] = {
1568 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
1569 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
1570 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
1571 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
1572 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
1573 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
1574 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
1575 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
1576 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
1577 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
1578 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
1579 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412C) },
1580 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
1581 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
1582 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
1583 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115) },
1584 { PHY_ID_MATCH_MODEL(PHY_ID_AQR115C) },
1585 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
1586 { }
1587 };
1588
1589 MODULE_DEVICE_TABLE(mdio, aqr_tbl);
1590
1591 MODULE_DESCRIPTION("Aquantia PHY driver");
1592 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
1593 MODULE_LICENSE("GPL v2");
1594