1 /* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
2 *
3 * Copyright (C) 2008
4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com>
6 *
7 * based on PalmOne's (TM) PDAs support (palm.c)
8 */
9
10 /*
11 * PalmOne's (TM) PDAs.
12 *
13 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28 #include "qemu/osdep.h"
29 #include "qemu/units.h"
30 #include "qapi/error.h"
31 #include "ui/console.h"
32 #include "hw/arm/omap.h"
33 #include "hw/boards.h"
34 #include "hw/arm/boot.h"
35 #include "hw/block/flash.h"
36 #include "system/qtest.h"
37 #include "system/address-spaces.h"
38 #include "qemu/cutils.h"
39 #include "qemu/error-report.h"
40
41
42 /*****************************************************************************/
43 /* Siemens SX1 Cellphone V1 */
44 /* - ARM OMAP310 processor
45 * - SRAM 192 kB
46 * - SDRAM 32 MB at 0x10000000
47 * - Boot flash 16 MB at 0x00000000
48 * - Application flash 8 MB at 0x04000000
49 * - 3 serial ports
50 * - 1 SecureDigital
51 * - 1 LCD display
52 * - 1 RTC
53 */
54
55 /*****************************************************************************/
56 /* Siemens SX1 Cellphone V2 */
57 /* - ARM OMAP310 processor
58 * - SRAM 192 kB
59 * - SDRAM 32 MB at 0x10000000
60 * - Boot flash 32 MB at 0x00000000
61 * - 3 serial ports
62 * - 1 SecureDigital
63 * - 1 LCD display
64 * - 1 RTC
65 */
66
static_read(void * opaque,hwaddr offset,unsigned size)67 static uint64_t static_read(void *opaque, hwaddr offset,
68 unsigned size)
69 {
70 uint32_t *val = opaque;
71 uint32_t mask = (4 / size) - 1;
72
73 return *val >> ((offset & mask) << 3);
74 }
75
static_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)76 static void static_write(void *opaque, hwaddr offset,
77 uint64_t value, unsigned size)
78 {
79 }
80
81 static const MemoryRegionOps static_ops = {
82 .read = static_read,
83 .write = static_write,
84 .endianness = DEVICE_NATIVE_ENDIAN,
85 };
86
87 #define SDRAM_SIZE (32 * MiB)
88 #define SECTOR_SIZE (128 * KiB)
89 #define FLASH0_SIZE (16 * MiB)
90 #define FLASH1_SIZE (8 * MiB)
91 #define FLASH2_SIZE (32 * MiB)
92
93 static struct arm_boot_info sx1_binfo = {
94 .loader_start = OMAP_EMIFF_BASE,
95 .ram_size = SDRAM_SIZE,
96 .board_id = 0x265,
97 };
98
sx1_init(MachineState * machine,const int version)99 static void sx1_init(MachineState *machine, const int version)
100 {
101 struct omap_mpu_state_s *mpu;
102 MachineClass *mc = MACHINE_GET_CLASS(machine);
103 MemoryRegion *address_space = get_system_memory();
104 MemoryRegion *flash = g_new(MemoryRegion, 1);
105 MemoryRegion *cs = g_new(MemoryRegion, 4);
106 static uint32_t cs0val = 0x00213090;
107 static uint32_t cs1val = 0x00215070;
108 static uint32_t cs2val = 0x00001139;
109 static uint32_t cs3val = 0x00001139;
110 DriveInfo *dinfo;
111 int fl_idx;
112 uint32_t flash_size = FLASH0_SIZE;
113
114 if (machine->ram_size != mc->default_ram_size) {
115 char *sz = size_to_str(mc->default_ram_size);
116 error_report("Invalid RAM size, should be %s", sz);
117 g_free(sz);
118 exit(EXIT_FAILURE);
119 }
120
121 if (version == 2) {
122 flash_size = FLASH2_SIZE;
123 }
124
125 memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram);
126
127 mpu = omap310_mpu_init(machine->ram, machine->cpu_type);
128
129 /* External Flash (EMIFS) */
130 memory_region_init_rom(flash, NULL, "omap_sx1.flash0-0", flash_size,
131 &error_fatal);
132 memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
133
134 memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val,
135 "sx1.cs0", OMAP_CS0_SIZE - flash_size);
136 memory_region_add_subregion(address_space,
137 OMAP_CS0_BASE + flash_size, &cs[0]);
138
139
140 memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val,
141 "sx1.cs2", OMAP_CS2_SIZE);
142 memory_region_add_subregion(address_space,
143 OMAP_CS2_BASE, &cs[2]);
144
145 memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val,
146 "sx1.cs3", OMAP_CS3_SIZE);
147 memory_region_add_subregion(address_space,
148 OMAP_CS2_BASE, &cs[3]);
149
150 fl_idx = 0;
151 if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
152 pflash_cfi01_register(OMAP_CS0_BASE,
153 "omap_sx1.flash0-1", flash_size,
154 blk_by_legacy_dinfo(dinfo),
155 SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
156 fl_idx++;
157 }
158
159 if ((version == 1) &&
160 (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
161 MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
162 memory_region_init_rom(flash_1, NULL, "omap_sx1.flash1-0",
163 FLASH1_SIZE, &error_fatal);
164 memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
165
166 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
167 "sx1.cs1", OMAP_CS1_SIZE - FLASH1_SIZE);
168 memory_region_add_subregion(address_space,
169 OMAP_CS1_BASE + FLASH1_SIZE, &cs[1]);
170
171 pflash_cfi01_register(OMAP_CS1_BASE,
172 "omap_sx1.flash1-1", FLASH1_SIZE,
173 blk_by_legacy_dinfo(dinfo),
174 SECTOR_SIZE, 4, 0, 0, 0, 0, 0);
175 fl_idx++;
176 } else {
177 memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val,
178 "sx1.cs1", OMAP_CS1_SIZE);
179 memory_region_add_subregion(address_space,
180 OMAP_CS1_BASE, &cs[1]);
181 }
182
183 if (!machine->kernel_filename && !fl_idx && !qtest_enabled()) {
184 error_report("Kernel or Flash image must be specified");
185 exit(1);
186 }
187
188 /* Load the kernel. */
189 arm_load_kernel(mpu->cpu, machine, &sx1_binfo);
190
191 /* TODO: fix next line */
192 //~ qemu_console_resize(ds, 640, 480);
193 }
194
sx1_init_v1(MachineState * machine)195 static void sx1_init_v1(MachineState *machine)
196 {
197 sx1_init(machine, 1);
198 }
199
sx1_init_v2(MachineState * machine)200 static void sx1_init_v2(MachineState *machine)
201 {
202 sx1_init(machine, 2);
203 }
204
sx1_machine_v2_class_init(ObjectClass * oc,const void * data)205 static void sx1_machine_v2_class_init(ObjectClass *oc, const void *data)
206 {
207 MachineClass *mc = MACHINE_CLASS(oc);
208
209 mc->desc = "Siemens SX1 (OMAP310) V2";
210 mc->init = sx1_init_v2;
211 mc->ignore_memory_transaction_failures = true;
212 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
213 mc->default_ram_size = SDRAM_SIZE;
214 mc->default_ram_id = "omap1.dram";
215 mc->auto_create_sdcard = true;
216 }
217
218 static const TypeInfo sx1_machine_v2_type = {
219 .name = MACHINE_TYPE_NAME("sx1"),
220 .parent = TYPE_MACHINE,
221 .class_init = sx1_machine_v2_class_init,
222 };
223
sx1_machine_v1_class_init(ObjectClass * oc,const void * data)224 static void sx1_machine_v1_class_init(ObjectClass *oc, const void *data)
225 {
226 MachineClass *mc = MACHINE_CLASS(oc);
227
228 mc->desc = "Siemens SX1 (OMAP310) V1";
229 mc->init = sx1_init_v1;
230 mc->ignore_memory_transaction_failures = true;
231 mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
232 mc->default_ram_size = SDRAM_SIZE;
233 mc->default_ram_id = "omap1.dram";
234 mc->auto_create_sdcard = true;
235 }
236
237 static const TypeInfo sx1_machine_v1_type = {
238 .name = MACHINE_TYPE_NAME("sx1-v1"),
239 .parent = TYPE_MACHINE,
240 .class_init = sx1_machine_v1_class_init,
241 };
242
sx1_machine_init(void)243 static void sx1_machine_init(void)
244 {
245 type_register_static(&sx1_machine_v1_type);
246 type_register_static(&sx1_machine_v2_type);
247 }
248
249 type_init(sx1_machine_init)
250