1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/clock/st,stm32mp25-rcc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/regulator/st,stm32mp25-regulator.h> 9#include <dt-bindings/reset/st,stm32mp25-rcc.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 reg = <0>; 22 device_type = "cpu"; 23 enable-method = "psci"; 24 power-domains = <&cpu0_pd>; 25 power-domain-names = "psci"; 26 }; 27 }; 28 29 arm-pmu { 30 compatible = "arm,cortex-a35-pmu"; 31 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-affinity = <&cpu0>; 33 interrupt-parent = <&intc>; 34 }; 35 36 arm_wdt: watchdog { 37 compatible = "arm,smc-wdt"; 38 arm,smc-id = <0xb200005a>; 39 status = "disabled"; 40 }; 41 42 clk_dsi_txbyte: clock-0 { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <0>; 46 }; 47 48 clk_rcbsec: clk-64000000 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <64000000>; 52 }; 53 54 firmware { 55 optee: optee { 56 compatible = "linaro,optee-tz"; 57 method = "smc"; 58 interrupt-parent = <&intc>; 59 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 60 }; 61 62 scmi { 63 compatible = "linaro,scmi-optee"; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 linaro,optee-channel-id = <0>; 67 68 scmi_clk: protocol@14 { 69 reg = <0x14>; 70 #clock-cells = <1>; 71 }; 72 73 scmi_reset: protocol@16 { 74 reg = <0x16>; 75 #reset-cells = <1>; 76 }; 77 78 scmi_voltd: protocol@17 { 79 reg = <0x17>; 80 81 scmi_regu: regulators { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 scmi_vddio1: regulator@0 { 86 reg = <VOLTD_SCMI_VDDIO1>; 87 regulator-name = "vddio1"; 88 }; 89 scmi_vddio2: regulator@1 { 90 reg = <VOLTD_SCMI_VDDIO2>; 91 regulator-name = "vddio2"; 92 }; 93 scmi_vddio3: regulator@2 { 94 reg = <VOLTD_SCMI_VDDIO3>; 95 regulator-name = "vddio3"; 96 }; 97 scmi_vddio4: regulator@3 { 98 reg = <VOLTD_SCMI_VDDIO4>; 99 regulator-name = "vddio4"; 100 }; 101 scmi_vdd33ucpd: regulator@5 { 102 reg = <VOLTD_SCMI_UCPD>; 103 regulator-name = "vdd33ucpd"; 104 }; 105 scmi_vdda18adc: regulator@7 { 106 reg = <VOLTD_SCMI_ADC>; 107 regulator-name = "vdda18adc"; 108 }; 109 }; 110 }; 111 }; 112 }; 113 114 psci { 115 compatible = "arm,psci-1.0"; 116 method = "smc"; 117 118 cpu0_pd: power-domain-cpu0 { 119 #power-domain-cells = <0>; 120 power-domains = <&cluster_pd>; 121 }; 122 123 cluster_pd: power-domain-cluster { 124 #power-domain-cells = <0>; 125 power-domains = <&ret_pd>; 126 }; 127 128 ret_pd: power-domain-retention { 129 #power-domain-cells = <0>; 130 }; 131 }; 132 133 timer { 134 compatible = "arm,armv8-timer"; 135 interrupt-parent = <&intc>; 136 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 137 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 138 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 139 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 140 always-on; 141 }; 142 143 soc@0 { 144 compatible = "simple-bus"; 145 ranges = <0x0 0x0 0x0 0x80000000>; 146 interrupt-parent = <&intc>; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 150 hpdma: dma-controller@40400000 { 151 compatible = "st,stm32mp25-dma3"; 152 reg = <0x40400000 0x1000>; 153 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&scmi_clk CK_SCMI_HPDMA1>; 170 #dma-cells = <3>; 171 }; 172 173 hpdma2: dma-controller@40410000 { 174 compatible = "st,stm32mp25-dma3"; 175 reg = <0x40410000 0x1000>; 176 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&scmi_clk CK_SCMI_HPDMA2>; 193 #dma-cells = <3>; 194 }; 195 196 hpdma3: dma-controller@40420000 { 197 compatible = "st,stm32mp25-dma3"; 198 reg = <0x40420000 0x1000>; 199 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&scmi_clk CK_SCMI_HPDMA3>; 216 #dma-cells = <3>; 217 }; 218 219 rifsc: bus@42080000 { 220 compatible = "st,stm32mp25-rifsc", "simple-bus"; 221 reg = <0x42080000 0x1000>; 222 ranges; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 #access-controller-cells = <1>; 226 227 i2s2: audio-controller@400b0000 { 228 compatible = "st,stm32mp25-i2s"; 229 reg = <0x400b0000 0x400>; 230 #sound-dai-cells = <0>; 231 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; 233 clock-names = "pclk", "i2sclk"; 234 resets = <&rcc SPI2_R>; 235 dmas = <&hpdma 51 0x43 0x12>, 236 <&hpdma 52 0x43 0x21>; 237 dma-names = "rx", "tx"; 238 access-controllers = <&rifsc 23>; 239 status = "disabled"; 240 }; 241 242 spi2: spi@400b0000 { 243 compatible = "st,stm32mp25-spi"; 244 reg = <0x400b0000 0x400>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&rcc CK_KER_SPI2>; 249 resets = <&rcc SPI2_R>; 250 dmas = <&hpdma 51 0x20 0x3012>, 251 <&hpdma 52 0x20 0x3021>; 252 dma-names = "rx", "tx"; 253 access-controllers = <&rifsc 23>; 254 power-domains = <&cluster_pd>; 255 status = "disabled"; 256 }; 257 258 i2s3: audio-controller@400c0000 { 259 compatible = "st,stm32mp25-i2s"; 260 reg = <0x400c0000 0x400>; 261 #sound-dai-cells = <0>; 262 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; 264 clock-names = "pclk", "i2sclk"; 265 resets = <&rcc SPI3_R>; 266 dmas = <&hpdma 53 0x43 0x12>, 267 <&hpdma 54 0x43 0x21>; 268 dma-names = "rx", "tx"; 269 access-controllers = <&rifsc 24>; 270 status = "disabled"; 271 }; 272 273 spi3: spi@400c0000 { 274 compatible = "st,stm32mp25-spi"; 275 reg = <0x400c0000 0x400>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&rcc CK_KER_SPI3>; 280 resets = <&rcc SPI3_R>; 281 dmas = <&hpdma 53 0x20 0x3012>, 282 <&hpdma 54 0x20 0x3021>; 283 dma-names = "rx", "tx"; 284 access-controllers = <&rifsc 24>; 285 power-domains = <&cluster_pd>; 286 status = "disabled"; 287 }; 288 289 spdifrx: audio-controller@400d0000 { 290 compatible = "st,stm32h7-spdifrx"; 291 reg = <0x400d0000 0x400>; 292 #sound-dai-cells = <0>; 293 clocks = <&rcc CK_KER_SPDIFRX>; 294 clock-names = "kclk"; 295 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 296 dmas = <&hpdma 71 0x43 0x212>, 297 <&hpdma 72 0x43 0x212>; 298 dma-names = "rx", "rx-ctrl"; 299 access-controllers = <&rifsc 30>; 300 status = "disabled"; 301 }; 302 303 usart2: serial@400e0000 { 304 compatible = "st,stm32h7-uart"; 305 reg = <0x400e0000 0x400>; 306 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&rcc CK_KER_USART2>; 308 dmas = <&hpdma 11 0x20 0x10012>, 309 <&hpdma 12 0x20 0x3021>; 310 dma-names = "rx", "tx"; 311 access-controllers = <&rifsc 32>; 312 status = "disabled"; 313 }; 314 315 usart3: serial@400f0000 { 316 compatible = "st,stm32h7-uart"; 317 reg = <0x400f0000 0x400>; 318 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&rcc CK_KER_USART3>; 320 dmas = <&hpdma 13 0x20 0x10012>, 321 <&hpdma 14 0x20 0x3021>; 322 dma-names = "rx", "tx"; 323 access-controllers = <&rifsc 33>; 324 status = "disabled"; 325 }; 326 327 uart4: serial@40100000 { 328 compatible = "st,stm32h7-uart"; 329 reg = <0x40100000 0x400>; 330 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&rcc CK_KER_UART4>; 332 dmas = <&hpdma 15 0x20 0x10012>, 333 <&hpdma 16 0x20 0x3021>; 334 dma-names = "rx", "tx"; 335 access-controllers = <&rifsc 34>; 336 status = "disabled"; 337 }; 338 339 uart5: serial@40110000 { 340 compatible = "st,stm32h7-uart"; 341 reg = <0x40110000 0x400>; 342 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&rcc CK_KER_UART5>; 344 dmas = <&hpdma 17 0x20 0x10012>, 345 <&hpdma 18 0x20 0x3021>; 346 dma-names = "rx", "tx"; 347 access-controllers = <&rifsc 35>; 348 status = "disabled"; 349 }; 350 351 i2c1: i2c@40120000 { 352 compatible = "st,stm32mp25-i2c"; 353 reg = <0x40120000 0x400>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 interrupt-names = "event"; 357 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&rcc CK_KER_I2C1>; 359 resets = <&rcc I2C1_R>; 360 dmas = <&hpdma 27 0x20 0x3012>, 361 <&hpdma 28 0x20 0x3021>; 362 dma-names = "rx", "tx"; 363 access-controllers = <&rifsc 41>; 364 power-domains = <&cluster_pd>; 365 i2c-analog-filter; 366 status = "disabled"; 367 }; 368 369 i2c2: i2c@40130000 { 370 compatible = "st,stm32mp25-i2c"; 371 reg = <0x40130000 0x400>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 interrupt-names = "event"; 375 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&rcc CK_KER_I2C2>; 377 resets = <&rcc I2C2_R>; 378 dmas = <&hpdma 30 0x20 0x3012>, 379 <&hpdma 31 0x20 0x3021>; 380 dma-names = "rx", "tx"; 381 access-controllers = <&rifsc 42>; 382 power-domains = <&cluster_pd>; 383 i2c-analog-filter; 384 status = "disabled"; 385 }; 386 387 i2c7: i2c@40180000 { 388 compatible = "st,stm32mp25-i2c"; 389 reg = <0x40180000 0x400>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 interrupt-names = "event"; 393 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&rcc CK_KER_I2C7>; 395 resets = <&rcc I2C7_R>; 396 dmas = <&hpdma 45 0x20 0x3012>, 397 <&hpdma 46 0x20 0x3021>; 398 dma-names = "rx", "tx"; 399 access-controllers = <&rifsc 47>; 400 power-domains = <&cluster_pd>; 401 i2c-analog-filter; 402 status = "disabled"; 403 }; 404 405 usart6: serial@40220000 { 406 compatible = "st,stm32h7-uart"; 407 reg = <0x40220000 0x400>; 408 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&rcc CK_KER_USART6>; 410 dmas = <&hpdma 19 0x20 0x10012>, 411 <&hpdma 20 0x20 0x3021>; 412 dma-names = "rx", "tx"; 413 access-controllers = <&rifsc 36>; 414 status = "disabled"; 415 }; 416 417 i2s1: audio-controller@40230000 { 418 compatible = "st,stm32mp25-i2s"; 419 reg = <0x40230000 0x400>; 420 #sound-dai-cells = <0>; 421 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; 423 clock-names = "pclk", "i2sclk"; 424 resets = <&rcc SPI1_R>; 425 dmas = <&hpdma 49 0x43 0x12>, 426 <&hpdma 50 0x43 0x21>; 427 dma-names = "rx", "tx"; 428 access-controllers = <&rifsc 22>; 429 status = "disabled"; 430 }; 431 432 spi1: spi@40230000 { 433 compatible = "st,stm32mp25-spi"; 434 reg = <0x40230000 0x400>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&rcc CK_KER_SPI1>; 439 resets = <&rcc SPI1_R>; 440 dmas = <&hpdma 49 0x20 0x3012>, 441 <&hpdma 50 0x20 0x3021>; 442 dma-names = "rx", "tx"; 443 access-controllers = <&rifsc 22>; 444 power-domains = <&cluster_pd>; 445 status = "disabled"; 446 }; 447 448 spi4: spi@40240000 { 449 compatible = "st,stm32mp25-spi"; 450 reg = <0x40240000 0x400>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&rcc CK_KER_SPI4>; 455 resets = <&rcc SPI4_R>; 456 dmas = <&hpdma 55 0x20 0x3012>, 457 <&hpdma 56 0x20 0x3021>; 458 dma-names = "rx", "tx"; 459 access-controllers = <&rifsc 25>; 460 power-domains = <&cluster_pd>; 461 status = "disabled"; 462 }; 463 464 spi5: spi@40280000 { 465 compatible = "st,stm32mp25-spi"; 466 reg = <0x40280000 0x400>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&rcc CK_KER_SPI5>; 471 resets = <&rcc SPI5_R>; 472 dmas = <&hpdma 57 0x20 0x3012>, 473 <&hpdma 58 0x20 0x3021>; 474 dma-names = "rx", "tx"; 475 access-controllers = <&rifsc 26>; 476 power-domains = <&cluster_pd>; 477 status = "disabled"; 478 }; 479 480 sai1: sai@40290000 { 481 compatible = "st,stm32mp25-sai"; 482 reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; 483 ranges = <0 0x40290000 0x400>; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 clocks = <&rcc CK_BUS_SAI1>; 487 clock-names = "pclk"; 488 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 489 resets = <&rcc SAI1_R>; 490 access-controllers = <&rifsc 49>; 491 status = "disabled"; 492 493 sai1a: audio-controller@40290004 { 494 compatible = "st,stm32-sai-sub-a"; 495 reg = <0x4 0x20>; 496 #sound-dai-cells = <0>; 497 clocks = <&rcc CK_KER_SAI1>; 498 clock-names = "sai_ck"; 499 dmas = <&hpdma 73 0x43 0x21>; 500 status = "disabled"; 501 }; 502 503 sai1b: audio-controller@40290024 { 504 compatible = "st,stm32-sai-sub-b"; 505 reg = <0x24 0x20>; 506 #sound-dai-cells = <0>; 507 clocks = <&rcc CK_KER_SAI1>; 508 clock-names = "sai_ck"; 509 dmas = <&hpdma 74 0x43 0x12>; 510 status = "disabled"; 511 }; 512 }; 513 514 sai2: sai@402a0000 { 515 compatible = "st,stm32mp25-sai"; 516 reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; 517 ranges = <0 0x402a0000 0x400>; 518 #address-cells = <1>; 519 #size-cells = <1>; 520 clocks = <&rcc CK_BUS_SAI2>; 521 clock-names = "pclk"; 522 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 523 resets = <&rcc SAI2_R>; 524 access-controllers = <&rifsc 50>; 525 status = "disabled"; 526 527 sai2a: audio-controller@402a0004 { 528 compatible = "st,stm32-sai-sub-a"; 529 reg = <0x4 0x20>; 530 #sound-dai-cells = <0>; 531 clocks = <&rcc CK_KER_SAI2>; 532 clock-names = "sai_ck"; 533 dmas = <&hpdma 75 0x43 0x21>; 534 status = "disabled"; 535 }; 536 537 sai2b: audio-controller@402a0024 { 538 compatible = "st,stm32-sai-sub-b"; 539 reg = <0x24 0x20>; 540 #sound-dai-cells = <0>; 541 clocks = <&rcc CK_KER_SAI2>; 542 clock-names = "sai_ck"; 543 dmas = <&hpdma 76 0x43 0x12>; 544 status = "disabled"; 545 }; 546 }; 547 548 sai3: sai@402b0000 { 549 compatible = "st,stm32mp25-sai"; 550 reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; 551 ranges = <0 0x402b0000 0x400>; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 clocks = <&rcc CK_BUS_SAI3>; 555 clock-names = "pclk"; 556 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 557 resets = <&rcc SAI3_R>; 558 access-controllers = <&rifsc 51>; 559 status = "disabled"; 560 561 sai3a: audio-controller@402b0004 { 562 compatible = "st,stm32-sai-sub-a"; 563 reg = <0x4 0x20>; 564 #sound-dai-cells = <0>; 565 clocks = <&rcc CK_KER_SAI3>; 566 clock-names = "sai_ck"; 567 dmas = <&hpdma 77 0x43 0x21>; 568 status = "disabled"; 569 }; 570 571 sai3b: audio-controller@502b0024 { 572 compatible = "st,stm32-sai-sub-b"; 573 reg = <0x24 0x20>; 574 #sound-dai-cells = <0>; 575 clocks = <&rcc CK_KER_SAI3>; 576 clock-names = "sai_ck"; 577 dmas = <&hpdma 78 0x43 0x12>; 578 status = "disabled"; 579 }; 580 }; 581 582 usart1: serial@40330000 { 583 compatible = "st,stm32h7-uart"; 584 reg = <0x40330000 0x400>; 585 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&rcc CK_KER_USART1>; 587 dmas = <&hpdma 9 0x20 0x10012>, 588 <&hpdma 10 0x20 0x3021>; 589 dma-names = "rx", "tx"; 590 access-controllers = <&rifsc 31>; 591 status = "disabled"; 592 }; 593 594 sai4: sai@40340000 { 595 compatible = "st,stm32mp25-sai"; 596 reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; 597 ranges = <0 0x40340000 0x400>; 598 #address-cells = <1>; 599 #size-cells = <1>; 600 clocks = <&rcc CK_BUS_SAI4>; 601 clock-names = "pclk"; 602 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 603 resets = <&rcc SAI4_R>; 604 access-controllers = <&rifsc 52>; 605 status = "disabled"; 606 607 sai4a: audio-controller@40340004 { 608 compatible = "st,stm32-sai-sub-a"; 609 reg = <0x4 0x20>; 610 #sound-dai-cells = <0>; 611 clocks = <&rcc CK_KER_SAI4>; 612 clock-names = "sai_ck"; 613 dmas = <&hpdma 79 0x63 0x21>; 614 status = "disabled"; 615 }; 616 617 sai4b: audio-controller@40340024 { 618 compatible = "st,stm32-sai-sub-b"; 619 reg = <0x24 0x20>; 620 #sound-dai-cells = <0>; 621 clocks = <&rcc CK_KER_SAI4>; 622 clock-names = "sai_ck"; 623 dmas = <&hpdma 80 0x43 0x12>; 624 status = "disabled"; 625 }; 626 }; 627 628 uart7: serial@40370000 { 629 compatible = "st,stm32h7-uart"; 630 reg = <0x40370000 0x400>; 631 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&rcc CK_KER_UART7>; 633 dmas = <&hpdma 21 0x20 0x10012>, 634 <&hpdma 22 0x20 0x3021>; 635 dma-names = "rx", "tx"; 636 access-controllers = <&rifsc 37>; 637 status = "disabled"; 638 }; 639 640 rng: rng@42020000 { 641 compatible = "st,stm32mp25-rng"; 642 reg = <0x42020000 0x400>; 643 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 644 clock-names = "core", "bus"; 645 resets = <&rcc RNG_R>; 646 access-controllers = <&rifsc 92>; 647 status = "disabled"; 648 }; 649 650 spi8: spi@46020000 { 651 compatible = "st,stm32mp25-spi"; 652 reg = <0x46020000 0x400>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&rcc CK_KER_SPI8>; 657 resets = <&rcc SPI8_R>; 658 dmas = <&hpdma 171 0x20 0x3012>, 659 <&hpdma 172 0x20 0x3021>; 660 dma-names = "rx", "tx"; 661 access-controllers = <&rifsc 29>; 662 status = "disabled"; 663 }; 664 665 i2c8: i2c@46040000 { 666 compatible = "st,stm32mp25-i2c"; 667 reg = <0x46040000 0x400>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 interrupt-names = "event"; 671 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&rcc CK_KER_I2C8>; 673 resets = <&rcc I2C8_R>; 674 dmas = <&hpdma 168 0x20 0x3012>, 675 <&hpdma 169 0x20 0x3021>; 676 dma-names = "rx", "tx"; 677 access-controllers = <&rifsc 48>; 678 power-domains = <&cluster_pd>; 679 i2c-analog-filter; 680 status = "disabled"; 681 }; 682 683 csi: csi@48020000 { 684 compatible = "st,stm32mp25-csi"; 685 reg = <0x48020000 0x2000>; 686 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 687 resets = <&rcc CSI_R>; 688 clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, 689 <&rcc CK_KER_CSIPHY>; 690 clock-names = "pclk", "txesc", "csi2phy"; 691 access-controllers = <&rifsc 86>; 692 power-domains = <&cluster_pd>; 693 status = "disabled"; 694 }; 695 696 dcmipp: dcmipp@48030000 { 697 compatible = "st,stm32mp25-dcmipp"; 698 reg = <0x48030000 0x1000>; 699 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 700 resets = <&rcc DCMIPP_R>; 701 clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; 702 clock-names = "kclk", "mclk"; 703 access-controllers = <&rifsc 87>; 704 power-domains = <&cluster_pd>; 705 status = "disabled"; 706 }; 707 708 sdmmc1: mmc@48220000 { 709 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 710 reg = <0x48220000 0x400>, <0x44230400 0x8>; 711 arm,primecell-periphid = <0x00353180>; 712 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&rcc CK_KER_SDMMC1 >; 714 clock-names = "apb_pclk"; 715 resets = <&rcc SDMMC1_R>; 716 cap-sd-highspeed; 717 cap-mmc-highspeed; 718 max-frequency = <120000000>; 719 access-controllers = <&rifsc 76>; 720 status = "disabled"; 721 }; 722 723 ethernet1: ethernet@482c0000 { 724 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; 725 reg = <0x482c0000 0x4000>; 726 reg-names = "stmmaceth"; 727 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 728 interrupt-names = "macirq"; 729 clock-names = "stmmaceth", 730 "mac-clk-tx", 731 "mac-clk-rx", 732 "ptp_ref", 733 "ethstp", 734 "eth-ck"; 735 clocks = <&rcc CK_ETH1_MAC>, 736 <&rcc CK_ETH1_TX>, 737 <&rcc CK_ETH1_RX>, 738 <&rcc CK_KER_ETH1PTP>, 739 <&rcc CK_ETH1_STP>, 740 <&rcc CK_KER_ETH1>; 741 snps,axi-config = <&stmmac_axi_config_1>; 742 snps,mixed-burst; 743 snps,mtl-rx-config = <&mtl_rx_setup_1>; 744 snps,mtl-tx-config = <&mtl_tx_setup_1>; 745 snps,pbl = <2>; 746 snps,tso; 747 st,syscon = <&syscfg 0x3000>; 748 access-controllers = <&rifsc 60>; 749 status = "disabled"; 750 751 mtl_rx_setup_1: rx-queues-config { 752 snps,rx-queues-to-use = <2>; 753 queue0 {}; 754 queue1 {}; 755 }; 756 757 mtl_tx_setup_1: tx-queues-config { 758 snps,tx-queues-to-use = <4>; 759 queue0 {}; 760 queue1 {}; 761 queue2 {}; 762 queue3 {}; 763 }; 764 765 stmmac_axi_config_1: stmmac-axi-config { 766 snps,blen = <0 0 0 0 16 8 4>; 767 snps,rd_osr_lmt = <0x7>; 768 snps,wr_osr_lmt = <0x7>; 769 }; 770 }; 771 }; 772 773 bsec: efuse@44000000 { 774 compatible = "st,stm32mp25-bsec"; 775 reg = <0x44000000 0x1000>; 776 #address-cells = <1>; 777 #size-cells = <1>; 778 779 part-number-otp@24 { 780 reg = <0x24 0x4>; 781 }; 782 783 package-otp@1e8 { 784 reg = <0x1e8 0x1>; 785 bits = <0 3>; 786 }; 787 }; 788 789 rcc: clock-controller@44200000 { 790 compatible = "st,stm32mp25-rcc"; 791 reg = <0x44200000 0x10000>; 792 #clock-cells = <1>; 793 #reset-cells = <1>; 794 clocks = <&scmi_clk CK_SCMI_HSE>, 795 <&scmi_clk CK_SCMI_HSI>, 796 <&scmi_clk CK_SCMI_MSI>, 797 <&scmi_clk CK_SCMI_LSE>, 798 <&scmi_clk CK_SCMI_LSI>, 799 <&scmi_clk CK_SCMI_HSE_DIV2>, 800 <&scmi_clk CK_SCMI_ICN_HS_MCU>, 801 <&scmi_clk CK_SCMI_ICN_LS_MCU>, 802 <&scmi_clk CK_SCMI_ICN_SDMMC>, 803 <&scmi_clk CK_SCMI_ICN_DDR>, 804 <&scmi_clk CK_SCMI_ICN_DISPLAY>, 805 <&scmi_clk CK_SCMI_ICN_HSL>, 806 <&scmi_clk CK_SCMI_ICN_NIC>, 807 <&scmi_clk CK_SCMI_ICN_VID>, 808 <&scmi_clk CK_SCMI_FLEXGEN_07>, 809 <&scmi_clk CK_SCMI_FLEXGEN_08>, 810 <&scmi_clk CK_SCMI_FLEXGEN_09>, 811 <&scmi_clk CK_SCMI_FLEXGEN_10>, 812 <&scmi_clk CK_SCMI_FLEXGEN_11>, 813 <&scmi_clk CK_SCMI_FLEXGEN_12>, 814 <&scmi_clk CK_SCMI_FLEXGEN_13>, 815 <&scmi_clk CK_SCMI_FLEXGEN_14>, 816 <&scmi_clk CK_SCMI_FLEXGEN_15>, 817 <&scmi_clk CK_SCMI_FLEXGEN_16>, 818 <&scmi_clk CK_SCMI_FLEXGEN_17>, 819 <&scmi_clk CK_SCMI_FLEXGEN_18>, 820 <&scmi_clk CK_SCMI_FLEXGEN_19>, 821 <&scmi_clk CK_SCMI_FLEXGEN_20>, 822 <&scmi_clk CK_SCMI_FLEXGEN_21>, 823 <&scmi_clk CK_SCMI_FLEXGEN_22>, 824 <&scmi_clk CK_SCMI_FLEXGEN_23>, 825 <&scmi_clk CK_SCMI_FLEXGEN_24>, 826 <&scmi_clk CK_SCMI_FLEXGEN_25>, 827 <&scmi_clk CK_SCMI_FLEXGEN_26>, 828 <&scmi_clk CK_SCMI_FLEXGEN_27>, 829 <&scmi_clk CK_SCMI_FLEXGEN_28>, 830 <&scmi_clk CK_SCMI_FLEXGEN_29>, 831 <&scmi_clk CK_SCMI_FLEXGEN_30>, 832 <&scmi_clk CK_SCMI_FLEXGEN_31>, 833 <&scmi_clk CK_SCMI_FLEXGEN_32>, 834 <&scmi_clk CK_SCMI_FLEXGEN_33>, 835 <&scmi_clk CK_SCMI_FLEXGEN_34>, 836 <&scmi_clk CK_SCMI_FLEXGEN_35>, 837 <&scmi_clk CK_SCMI_FLEXGEN_36>, 838 <&scmi_clk CK_SCMI_FLEXGEN_37>, 839 <&scmi_clk CK_SCMI_FLEXGEN_38>, 840 <&scmi_clk CK_SCMI_FLEXGEN_39>, 841 <&scmi_clk CK_SCMI_FLEXGEN_40>, 842 <&scmi_clk CK_SCMI_FLEXGEN_41>, 843 <&scmi_clk CK_SCMI_FLEXGEN_42>, 844 <&scmi_clk CK_SCMI_FLEXGEN_43>, 845 <&scmi_clk CK_SCMI_FLEXGEN_44>, 846 <&scmi_clk CK_SCMI_FLEXGEN_45>, 847 <&scmi_clk CK_SCMI_FLEXGEN_46>, 848 <&scmi_clk CK_SCMI_FLEXGEN_47>, 849 <&scmi_clk CK_SCMI_FLEXGEN_48>, 850 <&scmi_clk CK_SCMI_FLEXGEN_49>, 851 <&scmi_clk CK_SCMI_FLEXGEN_50>, 852 <&scmi_clk CK_SCMI_FLEXGEN_51>, 853 <&scmi_clk CK_SCMI_FLEXGEN_52>, 854 <&scmi_clk CK_SCMI_FLEXGEN_53>, 855 <&scmi_clk CK_SCMI_FLEXGEN_54>, 856 <&scmi_clk CK_SCMI_FLEXGEN_55>, 857 <&scmi_clk CK_SCMI_FLEXGEN_56>, 858 <&scmi_clk CK_SCMI_FLEXGEN_57>, 859 <&scmi_clk CK_SCMI_FLEXGEN_58>, 860 <&scmi_clk CK_SCMI_FLEXGEN_59>, 861 <&scmi_clk CK_SCMI_FLEXGEN_60>, 862 <&scmi_clk CK_SCMI_FLEXGEN_61>, 863 <&scmi_clk CK_SCMI_FLEXGEN_62>, 864 <&scmi_clk CK_SCMI_FLEXGEN_63>, 865 <&scmi_clk CK_SCMI_ICN_APB1>, 866 <&scmi_clk CK_SCMI_ICN_APB2>, 867 <&scmi_clk CK_SCMI_ICN_APB3>, 868 <&scmi_clk CK_SCMI_ICN_APB4>, 869 <&scmi_clk CK_SCMI_ICN_APBDBG>, 870 <&scmi_clk CK_SCMI_TIMG1>, 871 <&scmi_clk CK_SCMI_TIMG2>, 872 <&scmi_clk CK_SCMI_PLL3>, 873 <&clk_dsi_txbyte>; 874 access-controllers = <&rifsc 156>; 875 }; 876 877 exti1: interrupt-controller@44220000 { 878 compatible = "st,stm32mp1-exti", "syscon"; 879 reg = <0x44220000 0x400>; 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 interrupts-extended = 883 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 884 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 885 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 886 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 887 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 888 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 889 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 890 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 891 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 892 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 893 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 894 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 895 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 896 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 897 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 898 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 899 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 900 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 901 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 902 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 903 <0>, /* EXTI_20 */ 904 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 905 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 906 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 907 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 908 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 909 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 910 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 911 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 912 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 913 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 914 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 915 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 916 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 917 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 918 <0>, 919 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 920 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 921 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 922 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 923 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 924 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 925 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 926 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 927 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 928 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 929 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 930 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 931 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 932 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 933 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 934 <0>, 935 <0>, 936 <0>, 937 <0>, 938 <0>, 939 <0>, 940 <0>, 941 <0>, 942 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 943 <0>, /* EXTI_60 */ 944 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 945 <0>, 946 <0>, 947 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 948 <0>, 949 <0>, 950 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 951 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 952 <0>, 953 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 954 <0>, 955 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 956 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 957 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 958 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 959 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 960 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 961 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 962 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 963 <0>, /* EXTI_80 */ 964 <0>, 965 <0>, 966 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 967 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 968 }; 969 970 syscfg: syscon@44230000 { 971 compatible = "st,stm32mp23-syscfg", "syscon"; 972 reg = <0x44230000 0x10000>; 973 }; 974 975 pinctrl: pinctrl@44240000 { 976 compatible = "st,stm32mp257-pinctrl"; 977 ranges = <0 0x44240000 0xa0400>; 978 #address-cells = <1>; 979 #size-cells = <1>; 980 interrupt-parent = <&exti1>; 981 st,syscfg = <&exti1 0x60 0xff>; 982 pins-are-numbered; 983 984 gpioa: gpio@44240000 { 985 reg = <0x0 0x400>; 986 gpio-controller; 987 #gpio-cells = <2>; 988 interrupt-controller; 989 #interrupt-cells = <2>; 990 clocks = <&scmi_clk CK_SCMI_GPIOA>; 991 st,bank-name = "GPIOA"; 992 status = "disabled"; 993 }; 994 995 gpiob: gpio@44250000 { 996 reg = <0x10000 0x400>; 997 gpio-controller; 998 #gpio-cells = <2>; 999 interrupt-controller; 1000 #interrupt-cells = <2>; 1001 clocks = <&scmi_clk CK_SCMI_GPIOB>; 1002 st,bank-name = "GPIOB"; 1003 status = "disabled"; 1004 }; 1005 1006 gpioc: gpio@44260000 { 1007 reg = <0x20000 0x400>; 1008 gpio-controller; 1009 #gpio-cells = <2>; 1010 interrupt-controller; 1011 #interrupt-cells = <2>; 1012 clocks = <&scmi_clk CK_SCMI_GPIOC>; 1013 st,bank-name = "GPIOC"; 1014 status = "disabled"; 1015 }; 1016 1017 gpiod: gpio@44270000 { 1018 reg = <0x30000 0x400>; 1019 gpio-controller; 1020 #gpio-cells = <2>; 1021 interrupt-controller; 1022 #interrupt-cells = <2>; 1023 clocks = <&scmi_clk CK_SCMI_GPIOD>; 1024 st,bank-name = "GPIOD"; 1025 status = "disabled"; 1026 }; 1027 1028 gpioe: gpio@44280000 { 1029 reg = <0x40000 0x400>; 1030 gpio-controller; 1031 #gpio-cells = <2>; 1032 interrupt-controller; 1033 #interrupt-cells = <2>; 1034 clocks = <&scmi_clk CK_SCMI_GPIOE>; 1035 st,bank-name = "GPIOE"; 1036 status = "disabled"; 1037 }; 1038 1039 gpiof: gpio@44290000 { 1040 reg = <0x50000 0x400>; 1041 gpio-controller; 1042 #gpio-cells = <2>; 1043 interrupt-controller; 1044 #interrupt-cells = <2>; 1045 clocks = <&scmi_clk CK_SCMI_GPIOF>; 1046 st,bank-name = "GPIOF"; 1047 status = "disabled"; 1048 }; 1049 1050 gpiog: gpio@442a0000 { 1051 reg = <0x60000 0x400>; 1052 gpio-controller; 1053 #gpio-cells = <2>; 1054 interrupt-controller; 1055 #interrupt-cells = <2>; 1056 clocks = <&scmi_clk CK_SCMI_GPIOG>; 1057 st,bank-name = "GPIOG"; 1058 status = "disabled"; 1059 }; 1060 1061 gpioh: gpio@442b0000 { 1062 reg = <0x70000 0x400>; 1063 gpio-controller; 1064 #gpio-cells = <2>; 1065 interrupt-controller; 1066 #interrupt-cells = <2>; 1067 clocks = <&scmi_clk CK_SCMI_GPIOH>; 1068 st,bank-name = "GPIOH"; 1069 status = "disabled"; 1070 }; 1071 1072 gpioi: gpio@442c0000 { 1073 reg = <0x80000 0x400>; 1074 gpio-controller; 1075 #gpio-cells = <2>; 1076 interrupt-controller; 1077 #interrupt-cells = <2>; 1078 clocks = <&scmi_clk CK_SCMI_GPIOI>; 1079 st,bank-name = "GPIOI"; 1080 status = "disabled"; 1081 }; 1082 }; 1083 1084 rtc: rtc@46000000 { 1085 compatible = "st,stm32mp25-rtc"; 1086 reg = <0x46000000 0x400>; 1087 clocks = <&scmi_clk CK_SCMI_RTC>, 1088 <&scmi_clk CK_SCMI_RTCCK>; 1089 clock-names = "pclk", "rtc_ck"; 1090 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; 1091 status = "disabled"; 1092 }; 1093 1094 pinctrl_z: pinctrl@46200000 { 1095 compatible = "st,stm32mp257-z-pinctrl"; 1096 ranges = <0 0x46200000 0x400>; 1097 #address-cells = <1>; 1098 #size-cells = <1>; 1099 interrupt-parent = <&exti1>; 1100 st,syscfg = <&exti1 0x60 0xff>; 1101 pins-are-numbered; 1102 1103 gpioz: gpio@46200000 { 1104 reg = <0 0x400>; 1105 gpio-controller; 1106 #gpio-cells = <2>; 1107 interrupt-controller; 1108 #interrupt-cells = <2>; 1109 clocks = <&scmi_clk CK_SCMI_GPIOZ>; 1110 st,bank-name = "GPIOZ"; 1111 st,bank-ioport = <11>; 1112 status = "disabled"; 1113 }; 1114 1115 }; 1116 1117 exti2: interrupt-controller@46230000 { 1118 compatible = "st,stm32mp1-exti", "syscon"; 1119 reg = <0x46230000 0x400>; 1120 interrupt-controller; 1121 #interrupt-cells = <2>; 1122 interrupts-extended = 1123 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 1124 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1125 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1126 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1127 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1128 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1129 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 1130 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1131 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1132 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1133 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 1134 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1135 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1136 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1137 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1138 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1139 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1140 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1141 <0>, 1142 <0>, 1143 <0>, /* EXTI_20 */ 1144 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1145 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1146 <0>, 1147 <0>, 1148 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1149 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1150 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1151 <0>, 1152 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1153 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 1154 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1155 <0>, 1156 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1157 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1158 <0>, 1159 <0>, 1160 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1161 <0>, 1162 <0>, 1163 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 1164 <0>, 1165 <0>, 1166 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1167 <0>, 1168 <0>, 1169 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1170 <0>, 1171 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1172 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1173 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 1174 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1175 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1176 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1177 <0>, 1178 <0>, 1179 <0>, 1180 <0>, 1181 <0>, 1182 <0>, 1183 <0>, /* EXTI_60 */ 1184 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1185 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1186 <0>, 1187 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1188 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1189 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1190 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1191 <0>, 1192 <0>, 1193 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 1194 }; 1195 1196 intc: interrupt-controller@4ac10000 { 1197 compatible = "arm,gic-400"; 1198 reg = <0x4ac10000 0x1000>, 1199 <0x4ac20000 0x20000>, 1200 <0x4ac40000 0x20000>, 1201 <0x4ac60000 0x20000>; 1202 #interrupt-cells = <3>; 1203 interrupt-controller; 1204 }; 1205 }; 1206}; 1207