1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // cs35l36.c -- CS35L36 ALSA SoC audio driver
4 //
5 // Copyright 2018 Cirrus Logic, Inc.
6 //
7 // Author: James Schulman <james.schulman@cirrus.com>
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/i2c.h>
15 #include <linux/slab.h>
16 #include <linux/workqueue.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/irq.h>
21 #include <linux/of.h>
22 #include <linux/regmap.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/cs35l36.h>
31 #include <linux/completion.h>
32
33 #include "cs35l36.h"
34
35 /*
36 * Some fields take zero as a valid value so use a high bit flag that won't
37 * get written to the device to mark those.
38 */
39 #define CS35L36_VALID_PDATA 0x80000000
40
41 static const char * const cs35l36_supplies[] = {
42 "VA",
43 "VP",
44 };
45
46 struct cs35l36_private {
47 struct device *dev;
48 struct cs35l36_platform_data pdata;
49 struct regmap *regmap;
50 struct regulator_bulk_data supplies[2];
51 int num_supplies;
52 int clksrc;
53 int chip_version;
54 int rev_id;
55 int ldm_mode_sel;
56 struct gpio_desc *reset_gpio;
57 };
58
59 struct cs35l36_pll_config {
60 int freq;
61 int clk_cfg;
62 int fll_igain;
63 };
64
65 static const struct cs35l36_pll_config cs35l36_pll_sysclk[] = {
66 {32768, 0x00, 0x05},
67 {8000, 0x01, 0x03},
68 {11025, 0x02, 0x03},
69 {12000, 0x03, 0x03},
70 {16000, 0x04, 0x04},
71 {22050, 0x05, 0x04},
72 {24000, 0x06, 0x04},
73 {32000, 0x07, 0x05},
74 {44100, 0x08, 0x05},
75 {48000, 0x09, 0x05},
76 {88200, 0x0A, 0x06},
77 {96000, 0x0B, 0x06},
78 {128000, 0x0C, 0x07},
79 {176400, 0x0D, 0x07},
80 {192000, 0x0E, 0x07},
81 {256000, 0x0F, 0x08},
82 {352800, 0x10, 0x08},
83 {384000, 0x11, 0x08},
84 {512000, 0x12, 0x09},
85 {705600, 0x13, 0x09},
86 {750000, 0x14, 0x09},
87 {768000, 0x15, 0x09},
88 {1000000, 0x16, 0x0A},
89 {1024000, 0x17, 0x0A},
90 {1200000, 0x18, 0x0A},
91 {1411200, 0x19, 0x0A},
92 {1500000, 0x1A, 0x0A},
93 {1536000, 0x1B, 0x0A},
94 {2000000, 0x1C, 0x0A},
95 {2048000, 0x1D, 0x0A},
96 {2400000, 0x1E, 0x0A},
97 {2822400, 0x1F, 0x0A},
98 {3000000, 0x20, 0x0A},
99 {3072000, 0x21, 0x0A},
100 {3200000, 0x22, 0x0A},
101 {4000000, 0x23, 0x0A},
102 {4096000, 0x24, 0x0A},
103 {4800000, 0x25, 0x0A},
104 {5644800, 0x26, 0x0A},
105 {6000000, 0x27, 0x0A},
106 {6144000, 0x28, 0x0A},
107 {6250000, 0x29, 0x08},
108 {6400000, 0x2A, 0x0A},
109 {6500000, 0x2B, 0x08},
110 {6750000, 0x2C, 0x09},
111 {7526400, 0x2D, 0x0A},
112 {8000000, 0x2E, 0x0A},
113 {8192000, 0x2F, 0x0A},
114 {9600000, 0x30, 0x0A},
115 {11289600, 0x31, 0x0A},
116 {12000000, 0x32, 0x0A},
117 {12288000, 0x33, 0x0A},
118 {12500000, 0x34, 0x08},
119 {12800000, 0x35, 0x0A},
120 {13000000, 0x36, 0x0A},
121 {13500000, 0x37, 0x0A},
122 {19200000, 0x38, 0x0A},
123 {22579200, 0x39, 0x0A},
124 {24000000, 0x3A, 0x0A},
125 {24576000, 0x3B, 0x0A},
126 {25000000, 0x3C, 0x0A},
127 {25600000, 0x3D, 0x0A},
128 {26000000, 0x3E, 0x0A},
129 {27000000, 0x3F, 0x0A},
130 };
131
132 static const struct reg_default cs35l36_reg[] = {
133 {CS35L36_TESTKEY_CTRL, 0x00000000},
134 {CS35L36_USERKEY_CTL, 0x00000000},
135 {CS35L36_OTP_CTRL1, 0x00002460},
136 {CS35L36_OTP_CTRL2, 0x00000000},
137 {CS35L36_OTP_CTRL3, 0x00000000},
138 {CS35L36_OTP_CTRL4, 0x00000000},
139 {CS35L36_OTP_CTRL5, 0x00000000},
140 {CS35L36_PAC_CTL1, 0x00000004},
141 {CS35L36_PAC_CTL2, 0x00000000},
142 {CS35L36_PAC_CTL3, 0x00000000},
143 {CS35L36_PWR_CTRL1, 0x00000000},
144 {CS35L36_PWR_CTRL2, 0x00003321},
145 {CS35L36_PWR_CTRL3, 0x01000010},
146 {CS35L36_CTRL_OVRRIDE, 0x00000002},
147 {CS35L36_AMP_OUT_MUTE, 0x00000000},
148 {CS35L36_OTP_TRIM_STATUS, 0x00000000},
149 {CS35L36_DISCH_FILT, 0x00000000},
150 {CS35L36_PROTECT_REL_ERR, 0x00000000},
151 {CS35L36_PAD_INTERFACE, 0x00000038},
152 {CS35L36_PLL_CLK_CTRL, 0x00000010},
153 {CS35L36_GLOBAL_CLK_CTRL, 0x00000003},
154 {CS35L36_ADC_CLK_CTRL, 0x00000000},
155 {CS35L36_SWIRE_CLK_CTRL, 0x00000000},
156 {CS35L36_SP_SCLK_CLK_CTRL, 0x00000000},
157 {CS35L36_MDSYNC_EN, 0x00000000},
158 {CS35L36_MDSYNC_TX_ID, 0x00000000},
159 {CS35L36_MDSYNC_PWR_CTRL, 0x00000000},
160 {CS35L36_MDSYNC_DATA_TX, 0x00000000},
161 {CS35L36_MDSYNC_TX_STATUS, 0x00000002},
162 {CS35L36_MDSYNC_RX_STATUS, 0x00000000},
163 {CS35L36_MDSYNC_ERR_STATUS, 0x00000000},
164 {CS35L36_BSTCVRT_VCTRL1, 0x00000000},
165 {CS35L36_BSTCVRT_VCTRL2, 0x00000001},
166 {CS35L36_BSTCVRT_PEAK_CUR, 0x0000004A},
167 {CS35L36_BSTCVRT_SFT_RAMP, 0x00000003},
168 {CS35L36_BSTCVRT_COEFF, 0x00002424},
169 {CS35L36_BSTCVRT_SLOPE_LBST, 0x00005800},
170 {CS35L36_BSTCVRT_SW_FREQ, 0x00010000},
171 {CS35L36_BSTCVRT_DCM_CTRL, 0x00002001},
172 {CS35L36_BSTCVRT_DCM_MODE_FORCE, 0x00000000},
173 {CS35L36_BSTCVRT_OVERVOLT_CTRL, 0x00000130},
174 {CS35L36_VPI_LIMIT_MODE, 0x00000000},
175 {CS35L36_VPI_LIMIT_MINMAX, 0x00003000},
176 {CS35L36_VPI_VP_THLD, 0x00101010},
177 {CS35L36_VPI_TRACK_CTRL, 0x00000000},
178 {CS35L36_VPI_TRIG_MODE_CTRL, 0x00000000},
179 {CS35L36_VPI_TRIG_STEPS, 0x00000000},
180 {CS35L36_VI_SPKMON_FILT, 0x00000003},
181 {CS35L36_VI_SPKMON_GAIN, 0x00000909},
182 {CS35L36_VI_SPKMON_IP_SEL, 0x00000000},
183 {CS35L36_DTEMP_WARN_THLD, 0x00000002},
184 {CS35L36_DTEMP_STATUS, 0x00000000},
185 {CS35L36_VPVBST_FS_SEL, 0x00000001},
186 {CS35L36_VPVBST_VP_CTRL, 0x000001C0},
187 {CS35L36_VPVBST_VBST_CTRL, 0x000001C0},
188 {CS35L36_ASP_TX_PIN_CTRL, 0x00000028},
189 {CS35L36_ASP_RATE_CTRL, 0x00090000},
190 {CS35L36_ASP_FORMAT, 0x00000002},
191 {CS35L36_ASP_FRAME_CTRL, 0x00180018},
192 {CS35L36_ASP_TX1_TX2_SLOT, 0x00010000},
193 {CS35L36_ASP_TX3_TX4_SLOT, 0x00030002},
194 {CS35L36_ASP_TX5_TX6_SLOT, 0x00050004},
195 {CS35L36_ASP_TX7_TX8_SLOT, 0x00070006},
196 {CS35L36_ASP_RX1_SLOT, 0x00000000},
197 {CS35L36_ASP_RX_TX_EN, 0x00000000},
198 {CS35L36_ASP_RX1_SEL, 0x00000008},
199 {CS35L36_ASP_TX1_SEL, 0x00000018},
200 {CS35L36_ASP_TX2_SEL, 0x00000019},
201 {CS35L36_ASP_TX3_SEL, 0x00000028},
202 {CS35L36_ASP_TX4_SEL, 0x00000029},
203 {CS35L36_ASP_TX5_SEL, 0x00000020},
204 {CS35L36_ASP_TX6_SEL, 0x00000000},
205 {CS35L36_SWIRE_P1_TX1_SEL, 0x00000018},
206 {CS35L36_SWIRE_P1_TX2_SEL, 0x00000019},
207 {CS35L36_SWIRE_P2_TX1_SEL, 0x00000028},
208 {CS35L36_SWIRE_P2_TX2_SEL, 0x00000029},
209 {CS35L36_SWIRE_P2_TX3_SEL, 0x00000020},
210 {CS35L36_SWIRE_DP1_FIFO_CFG, 0x0000001B},
211 {CS35L36_SWIRE_DP2_FIFO_CFG, 0x0000001B},
212 {CS35L36_SWIRE_DP3_FIFO_CFG, 0x0000001B},
213 {CS35L36_SWIRE_PCM_RX_DATA, 0x00000000},
214 {CS35L36_SWIRE_FS_SEL, 0x00000001},
215 {CS35L36_AMP_DIG_VOL_CTRL, 0x00008000},
216 {CS35L36_VPBR_CFG, 0x02AA1905},
217 {CS35L36_VBBR_CFG, 0x02AA1905},
218 {CS35L36_VPBR_STATUS, 0x00000000},
219 {CS35L36_VBBR_STATUS, 0x00000000},
220 {CS35L36_OVERTEMP_CFG, 0x00000001},
221 {CS35L36_AMP_ERR_VOL, 0x00000000},
222 {CS35L36_CLASSH_CFG, 0x000B0405},
223 {CS35L36_CLASSH_FET_DRV_CFG, 0x00000111},
224 {CS35L36_NG_CFG, 0x00000033},
225 {CS35L36_AMP_GAIN_CTRL, 0x00000273},
226 {CS35L36_PWM_MOD_IO_CTRL, 0x00000000},
227 {CS35L36_PWM_MOD_STATUS, 0x00000000},
228 {CS35L36_DAC_MSM_CFG, 0x00000000},
229 {CS35L36_AMP_SLOPE_CTRL, 0x00000B00},
230 {CS35L36_AMP_PDM_VOLUME, 0x00000000},
231 {CS35L36_AMP_PDM_RATE_CTRL, 0x00000000},
232 {CS35L36_PDM_CH_SEL, 0x00000000},
233 {CS35L36_AMP_NG_CTRL, 0x0000212F},
234 {CS35L36_PDM_HIGHFILT_CTRL, 0x00000000},
235 {CS35L36_PAC_INT0_CTRL, 0x00000001},
236 {CS35L36_PAC_INT1_CTRL, 0x00000001},
237 {CS35L36_PAC_INT2_CTRL, 0x00000001},
238 {CS35L36_PAC_INT3_CTRL, 0x00000001},
239 {CS35L36_PAC_INT4_CTRL, 0x00000001},
240 {CS35L36_PAC_INT5_CTRL, 0x00000001},
241 {CS35L36_PAC_INT6_CTRL, 0x00000001},
242 {CS35L36_PAC_INT7_CTRL, 0x00000001},
243 };
244
cs35l36_readable_reg(struct device * dev,unsigned int reg)245 static bool cs35l36_readable_reg(struct device *dev, unsigned int reg)
246 {
247 switch (reg) {
248 case CS35L36_SW_RESET:
249 case CS35L36_SW_REV:
250 case CS35L36_HW_REV:
251 case CS35L36_TESTKEY_CTRL:
252 case CS35L36_USERKEY_CTL:
253 case CS35L36_OTP_MEM30:
254 case CS35L36_OTP_CTRL1:
255 case CS35L36_OTP_CTRL2:
256 case CS35L36_OTP_CTRL3:
257 case CS35L36_OTP_CTRL4:
258 case CS35L36_OTP_CTRL5:
259 case CS35L36_PAC_CTL1:
260 case CS35L36_PAC_CTL2:
261 case CS35L36_PAC_CTL3:
262 case CS35L36_DEVICE_ID:
263 case CS35L36_FAB_ID:
264 case CS35L36_REV_ID:
265 case CS35L36_PWR_CTRL1:
266 case CS35L36_PWR_CTRL2:
267 case CS35L36_PWR_CTRL3:
268 case CS35L36_CTRL_OVRRIDE:
269 case CS35L36_AMP_OUT_MUTE:
270 case CS35L36_OTP_TRIM_STATUS:
271 case CS35L36_DISCH_FILT:
272 case CS35L36_PROTECT_REL_ERR:
273 case CS35L36_PAD_INTERFACE:
274 case CS35L36_PLL_CLK_CTRL:
275 case CS35L36_GLOBAL_CLK_CTRL:
276 case CS35L36_ADC_CLK_CTRL:
277 case CS35L36_SWIRE_CLK_CTRL:
278 case CS35L36_SP_SCLK_CLK_CTRL:
279 case CS35L36_TST_FS_MON0:
280 case CS35L36_MDSYNC_EN:
281 case CS35L36_MDSYNC_TX_ID:
282 case CS35L36_MDSYNC_PWR_CTRL:
283 case CS35L36_MDSYNC_DATA_TX:
284 case CS35L36_MDSYNC_TX_STATUS:
285 case CS35L36_MDSYNC_RX_STATUS:
286 case CS35L36_MDSYNC_ERR_STATUS:
287 case CS35L36_BSTCVRT_VCTRL1:
288 case CS35L36_BSTCVRT_VCTRL2:
289 case CS35L36_BSTCVRT_PEAK_CUR:
290 case CS35L36_BSTCVRT_SFT_RAMP:
291 case CS35L36_BSTCVRT_COEFF:
292 case CS35L36_BSTCVRT_SLOPE_LBST:
293 case CS35L36_BSTCVRT_SW_FREQ:
294 case CS35L36_BSTCVRT_DCM_CTRL:
295 case CS35L36_BSTCVRT_DCM_MODE_FORCE:
296 case CS35L36_BSTCVRT_OVERVOLT_CTRL:
297 case CS35L36_BST_TST_MANUAL:
298 case CS35L36_BST_ANA2_TEST:
299 case CS35L36_VPI_LIMIT_MODE:
300 case CS35L36_VPI_LIMIT_MINMAX:
301 case CS35L36_VPI_VP_THLD:
302 case CS35L36_VPI_TRACK_CTRL:
303 case CS35L36_VPI_TRIG_MODE_CTRL:
304 case CS35L36_VPI_TRIG_STEPS:
305 case CS35L36_VI_SPKMON_FILT:
306 case CS35L36_VI_SPKMON_GAIN:
307 case CS35L36_VI_SPKMON_IP_SEL:
308 case CS35L36_DTEMP_WARN_THLD:
309 case CS35L36_DTEMP_STATUS:
310 case CS35L36_VPVBST_FS_SEL:
311 case CS35L36_VPVBST_VP_CTRL:
312 case CS35L36_VPVBST_VBST_CTRL:
313 case CS35L36_ASP_TX_PIN_CTRL:
314 case CS35L36_ASP_RATE_CTRL:
315 case CS35L36_ASP_FORMAT:
316 case CS35L36_ASP_FRAME_CTRL:
317 case CS35L36_ASP_TX1_TX2_SLOT:
318 case CS35L36_ASP_TX3_TX4_SLOT:
319 case CS35L36_ASP_TX5_TX6_SLOT:
320 case CS35L36_ASP_TX7_TX8_SLOT:
321 case CS35L36_ASP_RX1_SLOT:
322 case CS35L36_ASP_RX_TX_EN:
323 case CS35L36_ASP_RX1_SEL:
324 case CS35L36_ASP_TX1_SEL:
325 case CS35L36_ASP_TX2_SEL:
326 case CS35L36_ASP_TX3_SEL:
327 case CS35L36_ASP_TX4_SEL:
328 case CS35L36_ASP_TX5_SEL:
329 case CS35L36_ASP_TX6_SEL:
330 case CS35L36_SWIRE_P1_TX1_SEL:
331 case CS35L36_SWIRE_P1_TX2_SEL:
332 case CS35L36_SWIRE_P2_TX1_SEL:
333 case CS35L36_SWIRE_P2_TX2_SEL:
334 case CS35L36_SWIRE_P2_TX3_SEL:
335 case CS35L36_SWIRE_DP1_FIFO_CFG:
336 case CS35L36_SWIRE_DP2_FIFO_CFG:
337 case CS35L36_SWIRE_DP3_FIFO_CFG:
338 case CS35L36_SWIRE_PCM_RX_DATA:
339 case CS35L36_SWIRE_FS_SEL:
340 case CS35L36_AMP_DIG_VOL_CTRL:
341 case CS35L36_VPBR_CFG:
342 case CS35L36_VBBR_CFG:
343 case CS35L36_VPBR_STATUS:
344 case CS35L36_VBBR_STATUS:
345 case CS35L36_OVERTEMP_CFG:
346 case CS35L36_AMP_ERR_VOL:
347 case CS35L36_CLASSH_CFG:
348 case CS35L36_CLASSH_FET_DRV_CFG:
349 case CS35L36_NG_CFG:
350 case CS35L36_AMP_GAIN_CTRL:
351 case CS35L36_PWM_MOD_IO_CTRL:
352 case CS35L36_PWM_MOD_STATUS:
353 case CS35L36_DAC_MSM_CFG:
354 case CS35L36_AMP_SLOPE_CTRL:
355 case CS35L36_AMP_PDM_VOLUME:
356 case CS35L36_AMP_PDM_RATE_CTRL:
357 case CS35L36_PDM_CH_SEL:
358 case CS35L36_AMP_NG_CTRL:
359 case CS35L36_PDM_HIGHFILT_CTRL:
360 case CS35L36_INT1_STATUS:
361 case CS35L36_INT2_STATUS:
362 case CS35L36_INT3_STATUS:
363 case CS35L36_INT4_STATUS:
364 case CS35L36_INT1_RAW_STATUS:
365 case CS35L36_INT2_RAW_STATUS:
366 case CS35L36_INT3_RAW_STATUS:
367 case CS35L36_INT4_RAW_STATUS:
368 case CS35L36_INT1_MASK:
369 case CS35L36_INT2_MASK:
370 case CS35L36_INT3_MASK:
371 case CS35L36_INT4_MASK:
372 case CS35L36_INT1_EDGE_LVL_CTRL:
373 case CS35L36_INT3_EDGE_LVL_CTRL:
374 case CS35L36_PAC_INT_STATUS:
375 case CS35L36_PAC_INT_RAW_STATUS:
376 case CS35L36_PAC_INT_FLUSH_CTRL:
377 case CS35L36_PAC_INT0_CTRL:
378 case CS35L36_PAC_INT1_CTRL:
379 case CS35L36_PAC_INT2_CTRL:
380 case CS35L36_PAC_INT3_CTRL:
381 case CS35L36_PAC_INT4_CTRL:
382 case CS35L36_PAC_INT5_CTRL:
383 case CS35L36_PAC_INT6_CTRL:
384 case CS35L36_PAC_INT7_CTRL:
385 return true;
386 default:
387 if (reg >= CS35L36_PAC_PMEM_WORD0 &&
388 reg <= CS35L36_PAC_PMEM_WORD1023)
389 return true;
390 else
391 return false;
392 }
393 }
394
cs35l36_precious_reg(struct device * dev,unsigned int reg)395 static bool cs35l36_precious_reg(struct device *dev, unsigned int reg)
396 {
397 switch (reg) {
398 case CS35L36_TESTKEY_CTRL:
399 case CS35L36_USERKEY_CTL:
400 case CS35L36_TST_FS_MON0:
401 return true;
402 default:
403 return false;
404 }
405 }
406
cs35l36_volatile_reg(struct device * dev,unsigned int reg)407 static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg)
408 {
409 switch (reg) {
410 case CS35L36_SW_RESET:
411 case CS35L36_SW_REV:
412 case CS35L36_HW_REV:
413 case CS35L36_TESTKEY_CTRL:
414 case CS35L36_USERKEY_CTL:
415 case CS35L36_DEVICE_ID:
416 case CS35L36_FAB_ID:
417 case CS35L36_REV_ID:
418 case CS35L36_INT1_STATUS:
419 case CS35L36_INT2_STATUS:
420 case CS35L36_INT3_STATUS:
421 case CS35L36_INT4_STATUS:
422 case CS35L36_INT1_RAW_STATUS:
423 case CS35L36_INT2_RAW_STATUS:
424 case CS35L36_INT3_RAW_STATUS:
425 case CS35L36_INT4_RAW_STATUS:
426 case CS35L36_INT1_MASK:
427 case CS35L36_INT2_MASK:
428 case CS35L36_INT3_MASK:
429 case CS35L36_INT4_MASK:
430 case CS35L36_INT1_EDGE_LVL_CTRL:
431 case CS35L36_INT3_EDGE_LVL_CTRL:
432 case CS35L36_PAC_INT_STATUS:
433 case CS35L36_PAC_INT_RAW_STATUS:
434 case CS35L36_PAC_INT_FLUSH_CTRL:
435 return true;
436 default:
437 if (reg >= CS35L36_PAC_PMEM_WORD0 &&
438 reg <= CS35L36_PAC_PMEM_WORD1023)
439 return true;
440 else
441 return false;
442 }
443 }
444
445 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 0, 912,
446 TLV_DB_MINMAX_ITEM(-10200, 1200));
447 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
448
449 static const char * const cs35l36_pcm_sftramp_text[] = {
450 "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
451
452 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L36_AMP_DIG_VOL_CTRL, 0,
453 cs35l36_pcm_sftramp_text);
454
cs35l36_ldm_sel_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)455 static int cs35l36_ldm_sel_get(struct snd_kcontrol *kcontrol,
456 struct snd_ctl_elem_value *ucontrol)
457 {
458 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
459 struct cs35l36_private *cs35l36 =
460 snd_soc_component_get_drvdata(component);
461
462 ucontrol->value.integer.value[0] = cs35l36->ldm_mode_sel;
463
464 return 0;
465 }
466
cs35l36_ldm_sel_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)467 static int cs35l36_ldm_sel_put(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469 {
470 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
471 struct cs35l36_private *cs35l36 =
472 snd_soc_component_get_drvdata(component);
473 int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK :
474 0;
475
476 cs35l36->ldm_mode_sel = val;
477
478 regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
479 CS35L36_NG_AMP_EN_MASK, val);
480
481 return 0;
482 }
483
484 static const struct snd_kcontrol_new cs35l36_aud_controls[] = {
485 SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L36_AMP_DIG_VOL_CTRL,
486 3, 0x4D0, 0x390, dig_vol_tlv),
487 SOC_SINGLE_TLV("Analog PCM Volume", CS35L36_AMP_GAIN_CTRL, 5, 0x13, 0,
488 amp_gain_tlv),
489 SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
490 SOC_SINGLE("Amp Gain Zero-Cross Switch", CS35L36_AMP_GAIN_CTRL,
491 CS35L36_AMP_ZC_SHIFT, 1, 0),
492 SOC_SINGLE("PDM LDM Enter Ramp Switch", CS35L36_DAC_MSM_CFG,
493 CS35L36_PDM_LDM_ENTER_SHIFT, 1, 0),
494 SOC_SINGLE("PDM LDM Exit Ramp Switch", CS35L36_DAC_MSM_CFG,
495 CS35L36_PDM_LDM_EXIT_SHIFT, 1, 0),
496 SOC_SINGLE_BOOL_EXT("LDM Select Switch", 0, cs35l36_ldm_sel_get,
497 cs35l36_ldm_sel_put),
498 };
499
cs35l36_main_amp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)500 static int cs35l36_main_amp_event(struct snd_soc_dapm_widget *w,
501 struct snd_kcontrol *kcontrol, int event)
502 {
503 struct snd_soc_component *component =
504 snd_soc_dapm_to_component(w->dapm);
505 struct cs35l36_private *cs35l36 =
506 snd_soc_component_get_drvdata(component);
507 u32 reg;
508
509 switch (event) {
510 case SND_SOC_DAPM_POST_PMU:
511 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
512 CS35L36_GLOBAL_EN_MASK,
513 1 << CS35L36_GLOBAL_EN_SHIFT);
514
515 usleep_range(2000, 2100);
516
517 regmap_read(cs35l36->regmap, CS35L36_INT4_RAW_STATUS, ®);
518
519 if (WARN_ON_ONCE(reg & CS35L36_PLL_UNLOCK_MASK))
520 dev_crit(cs35l36->dev, "PLL Unlocked\n");
521
522 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
523 CS35L36_PCM_RX_SEL_MASK,
524 CS35L36_PCM_RX_SEL_PCM);
525 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
526 CS35L36_AMP_MUTE_MASK,
527 0 << CS35L36_AMP_MUTE_SHIFT);
528 break;
529 case SND_SOC_DAPM_PRE_PMD:
530 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
531 CS35L36_PCM_RX_SEL_MASK,
532 CS35L36_PCM_RX_SEL_ZERO);
533 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
534 CS35L36_AMP_MUTE_MASK,
535 1 << CS35L36_AMP_MUTE_SHIFT);
536 break;
537 case SND_SOC_DAPM_POST_PMD:
538 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
539 CS35L36_GLOBAL_EN_MASK,
540 0 << CS35L36_GLOBAL_EN_SHIFT);
541
542 usleep_range(2000, 2100);
543 break;
544 default:
545 dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
546 return -EINVAL;
547 }
548
549 return 0;
550 }
551
cs35l36_boost_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)552 static int cs35l36_boost_event(struct snd_soc_dapm_widget *w,
553 struct snd_kcontrol *kcontrol, int event)
554 {
555 struct snd_soc_component *component =
556 snd_soc_dapm_to_component(w->dapm);
557 struct cs35l36_private *cs35l36 =
558 snd_soc_component_get_drvdata(component);
559
560 switch (event) {
561 case SND_SOC_DAPM_POST_PMU:
562 if (!cs35l36->pdata.extern_boost)
563 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
564 CS35L36_BST_EN_MASK,
565 CS35L36_BST_EN <<
566 CS35L36_BST_EN_SHIFT);
567 break;
568 case SND_SOC_DAPM_POST_PMD:
569 if (!cs35l36->pdata.extern_boost)
570 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
571 CS35L36_BST_EN_MASK,
572 CS35L36_BST_DIS_VP <<
573 CS35L36_BST_EN_SHIFT);
574 break;
575 default:
576 dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
577 return -EINVAL;
578 }
579
580 return 0;
581 }
582
583 static const char * const cs35l36_chan_text[] = {
584 "RX1",
585 "RX2",
586 };
587
588 static SOC_ENUM_SINGLE_DECL(chansel_enum, CS35L36_ASP_RX1_SLOT, 0,
589 cs35l36_chan_text);
590
591 static const struct snd_kcontrol_new cs35l36_chan_mux =
592 SOC_DAPM_ENUM("Input Mux", chansel_enum);
593
594 static const struct snd_kcontrol_new amp_enable_ctrl =
595 SOC_DAPM_SINGLE_AUTODISABLE("Switch", CS35L36_AMP_OUT_MUTE,
596 CS35L36_AMP_MUTE_SHIFT, 1, 1);
597
598 static const struct snd_kcontrol_new boost_ctrl =
599 SOC_DAPM_SINGLE_VIRT("Switch", 1);
600
601 static const char * const asp_tx_src_text[] = {
602 "Zero Fill", "ASPRX1", "VMON", "IMON", "ERRVOL", "VPMON", "VBSTMON"
603 };
604
605 static const unsigned int asp_tx_src_values[] = {
606 0x00, 0x08, 0x18, 0x19, 0x20, 0x28, 0x29
607 };
608
609 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx1_src_enum, CS35L36_ASP_TX1_SEL, 0,
610 CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
611 asp_tx_src_values);
612
613 static const struct snd_kcontrol_new asp_tx1_src =
614 SOC_DAPM_ENUM("ASPTX1SRC", asp_tx1_src_enum);
615
616 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx2_src_enum, CS35L36_ASP_TX2_SEL, 0,
617 CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
618 asp_tx_src_values);
619
620 static const struct snd_kcontrol_new asp_tx2_src =
621 SOC_DAPM_ENUM("ASPTX2SRC", asp_tx2_src_enum);
622
623 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx3_src_enum, CS35L36_ASP_TX3_SEL, 0,
624 CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
625 asp_tx_src_values);
626
627 static const struct snd_kcontrol_new asp_tx3_src =
628 SOC_DAPM_ENUM("ASPTX3SRC", asp_tx3_src_enum);
629
630 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx4_src_enum, CS35L36_ASP_TX4_SEL, 0,
631 CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
632 asp_tx_src_values);
633
634 static const struct snd_kcontrol_new asp_tx4_src =
635 SOC_DAPM_ENUM("ASPTX4SRC", asp_tx4_src_enum);
636
637 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx5_src_enum, CS35L36_ASP_TX5_SEL, 0,
638 CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
639 asp_tx_src_values);
640
641 static const struct snd_kcontrol_new asp_tx5_src =
642 SOC_DAPM_ENUM("ASPTX5SRC", asp_tx5_src_enum);
643
644 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx6_src_enum, CS35L36_ASP_TX6_SEL, 0,
645 CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
646 asp_tx_src_values);
647
648 static const struct snd_kcontrol_new asp_tx6_src =
649 SOC_DAPM_ENUM("ASPTX6SRC", asp_tx6_src_enum);
650
651 static const struct snd_soc_dapm_widget cs35l36_dapm_widgets[] = {
652 SND_SOC_DAPM_MUX("Channel Mux", SND_SOC_NOPM, 0, 0, &cs35l36_chan_mux),
653 SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS35L36_ASP_RX_TX_EN, 16, 0),
654
655 SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L36_PWR_CTRL2, 0, 0, NULL, 0,
656 cs35l36_main_amp_event, SND_SOC_DAPM_POST_PMD |
657 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
658
659 SND_SOC_DAPM_OUTPUT("SPK"),
660 SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, &_enable_ctrl),
661 SND_SOC_DAPM_MIXER("CLASS H", CS35L36_PWR_CTRL3, 4, 0, NULL, 0),
662 SND_SOC_DAPM_SWITCH_E("BOOST Enable", SND_SOC_NOPM, 0, 0, &boost_ctrl,
663 cs35l36_boost_event, SND_SOC_DAPM_POST_PMD |
664 SND_SOC_DAPM_POST_PMU),
665
666 SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L36_ASP_RX_TX_EN, 0, 0),
667 SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, CS35L36_ASP_RX_TX_EN, 1, 0),
668 SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, CS35L36_ASP_RX_TX_EN, 2, 0),
669 SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, CS35L36_ASP_RX_TX_EN, 3, 0),
670 SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, CS35L36_ASP_RX_TX_EN, 4, 0),
671 SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, CS35L36_ASP_RX_TX_EN, 5, 0),
672
673 SND_SOC_DAPM_MUX("ASPTX1SRC", SND_SOC_NOPM, 0, 0, &asp_tx1_src),
674 SND_SOC_DAPM_MUX("ASPTX2SRC", SND_SOC_NOPM, 0, 0, &asp_tx2_src),
675 SND_SOC_DAPM_MUX("ASPTX3SRC", SND_SOC_NOPM, 0, 0, &asp_tx3_src),
676 SND_SOC_DAPM_MUX("ASPTX4SRC", SND_SOC_NOPM, 0, 0, &asp_tx4_src),
677 SND_SOC_DAPM_MUX("ASPTX5SRC", SND_SOC_NOPM, 0, 0, &asp_tx5_src),
678 SND_SOC_DAPM_MUX("ASPTX6SRC", SND_SOC_NOPM, 0, 0, &asp_tx6_src),
679
680 SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L36_PWR_CTRL2, 12, 0),
681 SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L36_PWR_CTRL2, 13, 0),
682 SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L36_PWR_CTRL2, 8, 0),
683 SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L36_PWR_CTRL2, 9, 0),
684
685 SND_SOC_DAPM_INPUT("VP"),
686 SND_SOC_DAPM_INPUT("VBST"),
687 SND_SOC_DAPM_INPUT("VSENSE"),
688 };
689
690 static const struct snd_soc_dapm_route cs35l36_audio_map[] = {
691 {"VPMON ADC", NULL, "VP"},
692 {"VBSTMON ADC", NULL, "VBST"},
693 {"IMON ADC", NULL, "VSENSE"},
694 {"VMON ADC", NULL, "VSENSE"},
695
696 {"ASPTX1SRC", "IMON", "IMON ADC"},
697 {"ASPTX1SRC", "VMON", "VMON ADC"},
698 {"ASPTX1SRC", "VBSTMON", "VBSTMON ADC"},
699 {"ASPTX1SRC", "VPMON", "VPMON ADC"},
700
701 {"ASPTX2SRC", "IMON", "IMON ADC"},
702 {"ASPTX2SRC", "VMON", "VMON ADC"},
703 {"ASPTX2SRC", "VBSTMON", "VBSTMON ADC"},
704 {"ASPTX2SRC", "VPMON", "VPMON ADC"},
705
706 {"ASPTX3SRC", "IMON", "IMON ADC"},
707 {"ASPTX3SRC", "VMON", "VMON ADC"},
708 {"ASPTX3SRC", "VBSTMON", "VBSTMON ADC"},
709 {"ASPTX3SRC", "VPMON", "VPMON ADC"},
710
711 {"ASPTX4SRC", "IMON", "IMON ADC"},
712 {"ASPTX4SRC", "VMON", "VMON ADC"},
713 {"ASPTX4SRC", "VBSTMON", "VBSTMON ADC"},
714 {"ASPTX4SRC", "VPMON", "VPMON ADC"},
715
716 {"ASPTX5SRC", "IMON", "IMON ADC"},
717 {"ASPTX5SRC", "VMON", "VMON ADC"},
718 {"ASPTX5SRC", "VBSTMON", "VBSTMON ADC"},
719 {"ASPTX5SRC", "VPMON", "VPMON ADC"},
720
721 {"ASPTX6SRC", "IMON", "IMON ADC"},
722 {"ASPTX6SRC", "VMON", "VMON ADC"},
723 {"ASPTX6SRC", "VBSTMON", "VBSTMON ADC"},
724 {"ASPTX6SRC", "VPMON", "VPMON ADC"},
725
726 {"ASPTX1", NULL, "ASPTX1SRC"},
727 {"ASPTX2", NULL, "ASPTX2SRC"},
728 {"ASPTX3", NULL, "ASPTX3SRC"},
729 {"ASPTX4", NULL, "ASPTX4SRC"},
730 {"ASPTX5", NULL, "ASPTX5SRC"},
731 {"ASPTX6", NULL, "ASPTX6SRC"},
732
733 {"AMP Capture", NULL, "ASPTX1"},
734 {"AMP Capture", NULL, "ASPTX2"},
735 {"AMP Capture", NULL, "ASPTX3"},
736 {"AMP Capture", NULL, "ASPTX4"},
737 {"AMP Capture", NULL, "ASPTX5"},
738 {"AMP Capture", NULL, "ASPTX6"},
739
740 {"AMP Enable", "Switch", "AMP Playback"},
741 {"SDIN", NULL, "AMP Enable"},
742 {"Channel Mux", "RX1", "SDIN"},
743 {"Channel Mux", "RX2", "SDIN"},
744 {"BOOST Enable", "Switch", "Channel Mux"},
745 {"CLASS H", NULL, "BOOST Enable"},
746 {"Main AMP", NULL, "Channel Mux"},
747 {"Main AMP", NULL, "CLASS H"},
748 {"SPK", NULL, "Main AMP"},
749 };
750
cs35l36_set_dai_fmt(struct snd_soc_dai * component_dai,unsigned int fmt)751 static int cs35l36_set_dai_fmt(struct snd_soc_dai *component_dai,
752 unsigned int fmt)
753 {
754 struct cs35l36_private *cs35l36 =
755 snd_soc_component_get_drvdata(component_dai->component);
756 unsigned int asp_fmt, lrclk_fmt, sclk_fmt, clock_provider, clk_frc;
757
758 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
759 case SND_SOC_DAIFMT_CBP_CFP:
760 clock_provider = 1;
761 break;
762 case SND_SOC_DAIFMT_CBC_CFC:
763 clock_provider = 0;
764 break;
765 default:
766 return -EINVAL;
767 }
768
769 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
770 CS35L36_SCLK_MSTR_MASK,
771 clock_provider << CS35L36_SCLK_MSTR_SHIFT);
772 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
773 CS35L36_LRCLK_MSTR_MASK,
774 clock_provider << CS35L36_LRCLK_MSTR_SHIFT);
775
776 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
777 case SND_SOC_DAIFMT_CONT:
778 clk_frc = 1;
779 break;
780 case SND_SOC_DAIFMT_GATED:
781 clk_frc = 0;
782 break;
783 default:
784 return -EINVAL;
785 }
786
787 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
788 CS35L36_SCLK_FRC_MASK, clk_frc <<
789 CS35L36_SCLK_FRC_SHIFT);
790 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
791 CS35L36_LRCLK_FRC_MASK, clk_frc <<
792 CS35L36_LRCLK_FRC_SHIFT);
793
794 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
795 case SND_SOC_DAIFMT_DSP_A:
796 asp_fmt = 0;
797 break;
798 case SND_SOC_DAIFMT_I2S:
799 asp_fmt = 2;
800 break;
801 default:
802 return -EINVAL;
803 }
804
805 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
806 case SND_SOC_DAIFMT_NB_IF:
807 lrclk_fmt = 1;
808 sclk_fmt = 0;
809 break;
810 case SND_SOC_DAIFMT_IB_NF:
811 lrclk_fmt = 0;
812 sclk_fmt = 1;
813 break;
814 case SND_SOC_DAIFMT_IB_IF:
815 lrclk_fmt = 1;
816 sclk_fmt = 1;
817 break;
818 case SND_SOC_DAIFMT_NB_NF:
819 lrclk_fmt = 0;
820 sclk_fmt = 0;
821 break;
822 default:
823 return -EINVAL;
824 }
825
826 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
827 CS35L36_LRCLK_INV_MASK,
828 lrclk_fmt << CS35L36_LRCLK_INV_SHIFT);
829 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
830 CS35L36_SCLK_INV_MASK,
831 sclk_fmt << CS35L36_SCLK_INV_SHIFT);
832 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FORMAT,
833 CS35L36_ASP_FMT_MASK, asp_fmt);
834
835 return 0;
836 }
837
838 struct cs35l36_global_fs_config {
839 int rate;
840 int fs_cfg;
841 };
842
843 static const struct cs35l36_global_fs_config cs35l36_fs_rates[] = {
844 {12000, 0x01},
845 {24000, 0x02},
846 {48000, 0x03},
847 {96000, 0x04},
848 {192000, 0x05},
849 {384000, 0x06},
850 {11025, 0x09},
851 {22050, 0x0A},
852 {44100, 0x0B},
853 {88200, 0x0C},
854 {176400, 0x0D},
855 {8000, 0x11},
856 {16000, 0x12},
857 {32000, 0x13},
858 };
859
cs35l36_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)860 static int cs35l36_pcm_hw_params(struct snd_pcm_substream *substream,
861 struct snd_pcm_hw_params *params,
862 struct snd_soc_dai *dai)
863 {
864 struct cs35l36_private *cs35l36 =
865 snd_soc_component_get_drvdata(dai->component);
866 unsigned int asp_width, global_fs = params_rate(params);
867 int i;
868
869 for (i = 0; i < ARRAY_SIZE(cs35l36_fs_rates); i++) {
870 if (global_fs == cs35l36_fs_rates[i].rate)
871 regmap_update_bits(cs35l36->regmap,
872 CS35L36_GLOBAL_CLK_CTRL,
873 CS35L36_GLOBAL_FS_MASK,
874 cs35l36_fs_rates[i].fs_cfg <<
875 CS35L36_GLOBAL_FS_SHIFT);
876 }
877
878 switch (params_width(params)) {
879 case 16:
880 asp_width = CS35L36_ASP_WIDTH_16;
881 break;
882 case 24:
883 asp_width = CS35L36_ASP_WIDTH_24;
884 break;
885 case 32:
886 asp_width = CS35L36_ASP_WIDTH_32;
887 break;
888 default:
889 return -EINVAL;
890 }
891
892 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
893 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
894 CS35L36_ASP_RX_WIDTH_MASK,
895 asp_width << CS35L36_ASP_RX_WIDTH_SHIFT);
896 } else {
897 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
898 CS35L36_ASP_TX_WIDTH_MASK,
899 asp_width << CS35L36_ASP_TX_WIDTH_SHIFT);
900 }
901
902 return 0;
903 }
904
cs35l36_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)905 static int cs35l36_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
906 unsigned int freq, int dir)
907 {
908 struct snd_soc_component *component = dai->component;
909 struct cs35l36_private *cs35l36 =
910 snd_soc_component_get_drvdata(component);
911 int fs1, fs2;
912
913 if (freq > CS35L36_FS_NOM_6MHZ) {
914 fs1 = CS35L36_FS1_DEFAULT_VAL;
915 fs2 = CS35L36_FS2_DEFAULT_VAL;
916 } else {
917 fs1 = 3 * DIV_ROUND_UP(CS35L36_FS_NOM_6MHZ * 4, freq) + 4;
918 fs2 = 5 * DIV_ROUND_UP(CS35L36_FS_NOM_6MHZ * 4, freq) + 4;
919 }
920
921 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
922 CS35L36_TEST_UNLOCK1);
923 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
924 CS35L36_TEST_UNLOCK2);
925
926 regmap_update_bits(cs35l36->regmap, CS35L36_TST_FS_MON0,
927 CS35L36_FS1_WINDOW_MASK | CS35L36_FS2_WINDOW_MASK,
928 fs1 | (fs2 << CS35L36_FS2_WINDOW_SHIFT));
929
930 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
931 CS35L36_TEST_LOCK1);
932 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
933 CS35L36_TEST_LOCK2);
934 return 0;
935 }
936
cs35l36_get_clk_config(struct cs35l36_private * cs35l36,int freq)937 static const struct cs35l36_pll_config *cs35l36_get_clk_config(
938 struct cs35l36_private *cs35l36, int freq)
939 {
940 int i;
941
942 for (i = 0; i < ARRAY_SIZE(cs35l36_pll_sysclk); i++) {
943 if (cs35l36_pll_sysclk[i].freq == freq)
944 return &cs35l36_pll_sysclk[i];
945 }
946
947 return NULL;
948 }
949
950 static const struct snd_soc_dai_ops cs35l36_ops = {
951 .set_fmt = cs35l36_set_dai_fmt,
952 .hw_params = cs35l36_pcm_hw_params,
953 .set_sysclk = cs35l36_dai_set_sysclk,
954 };
955
956 #define CS35L36_RATES ( \
957 SNDRV_PCM_RATE_8000_48000 | \
958 SNDRV_PCM_RATE_12000 | \
959 SNDRV_PCM_RATE_24000 | \
960 SNDRV_PCM_RATE_88200 | \
961 SNDRV_PCM_RATE_96000 | \
962 SNDRV_PCM_RATE_176400 | \
963 SNDRV_PCM_RATE_192000 | \
964 SNDRV_PCM_RATE_384000)
965
966 static struct snd_soc_dai_driver cs35l36_dai[] = {
967 {
968 .name = "cs35l36-pcm",
969 .id = 0,
970 .playback = {
971 .stream_name = "AMP Playback",
972 .channels_min = 1,
973 .channels_max = 8,
974 .rates = CS35L36_RATES,
975 .formats = CS35L36_RX_FORMATS,
976 },
977 .capture = {
978 .stream_name = "AMP Capture",
979 .channels_min = 1,
980 .channels_max = 8,
981 .rates = CS35L36_RATES,
982 .formats = CS35L36_TX_FORMATS,
983 },
984 .ops = &cs35l36_ops,
985 .symmetric_rate = 1,
986 },
987 };
988
cs35l36_component_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)989 static int cs35l36_component_set_sysclk(struct snd_soc_component *component,
990 int clk_id, int source, unsigned int freq,
991 int dir)
992 {
993 struct cs35l36_private *cs35l36 =
994 snd_soc_component_get_drvdata(component);
995 const struct cs35l36_pll_config *clk_cfg;
996 int prev_clksrc;
997 bool pdm_switch;
998
999 prev_clksrc = cs35l36->clksrc;
1000
1001 switch (clk_id) {
1002 case 0:
1003 cs35l36->clksrc = CS35L36_PLLSRC_SCLK;
1004 break;
1005 case 1:
1006 cs35l36->clksrc = CS35L36_PLLSRC_LRCLK;
1007 break;
1008 case 2:
1009 cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK;
1010 break;
1011 case 3:
1012 cs35l36->clksrc = CS35L36_PLLSRC_SELF;
1013 break;
1014 case 4:
1015 cs35l36->clksrc = CS35L36_PLLSRC_MCLK;
1016 break;
1017 default:
1018 return -EINVAL;
1019 }
1020
1021 clk_cfg = cs35l36_get_clk_config(cs35l36, freq);
1022 if (clk_cfg == NULL) {
1023 dev_err(component->dev, "Invalid CLK Config Freq: %d\n", freq);
1024 return -EINVAL;
1025 }
1026
1027 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1028 CS35L36_PLL_OPENLOOP_MASK,
1029 1 << CS35L36_PLL_OPENLOOP_SHIFT);
1030 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1031 CS35L36_REFCLK_FREQ_MASK,
1032 clk_cfg->clk_cfg << CS35L36_REFCLK_FREQ_SHIFT);
1033 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1034 CS35L36_PLL_REFCLK_EN_MASK,
1035 0 << CS35L36_PLL_REFCLK_EN_SHIFT);
1036 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1037 CS35L36_PLL_CLK_SEL_MASK,
1038 cs35l36->clksrc);
1039 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1040 CS35L36_PLL_OPENLOOP_MASK,
1041 0 << CS35L36_PLL_OPENLOOP_SHIFT);
1042 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1043 CS35L36_PLL_REFCLK_EN_MASK,
1044 1 << CS35L36_PLL_REFCLK_EN_SHIFT);
1045
1046 if (cs35l36->rev_id == CS35L36_REV_A0) {
1047 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1048 CS35L36_TEST_UNLOCK1);
1049 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1050 CS35L36_TEST_UNLOCK2);
1051
1052 regmap_write(cs35l36->regmap, CS35L36_DCO_CTRL, 0x00036DA8);
1053 regmap_write(cs35l36->regmap, CS35L36_MISC_CTRL, 0x0100EE0E);
1054
1055 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1056 CS35L36_PLL_IGAIN_MASK,
1057 CS35L36_PLL_IGAIN <<
1058 CS35L36_PLL_IGAIN_SHIFT);
1059 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1060 CS35L36_PLL_FFL_IGAIN_MASK,
1061 clk_cfg->fll_igain);
1062
1063 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1064 CS35L36_TEST_LOCK1);
1065 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1066 CS35L36_TEST_LOCK2);
1067 }
1068
1069 if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) {
1070 pdm_switch = cs35l36->ldm_mode_sel &&
1071 (prev_clksrc != CS35L36_PLLSRC_PDMCLK);
1072
1073 if (pdm_switch)
1074 regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1075 CS35L36_NG_DELAY_MASK,
1076 0 << CS35L36_NG_DELAY_SHIFT);
1077
1078 regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1079 CS35L36_PDM_MODE_MASK,
1080 1 << CS35L36_PDM_MODE_SHIFT);
1081
1082 if (pdm_switch)
1083 regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1084 CS35L36_NG_DELAY_MASK,
1085 3 << CS35L36_NG_DELAY_SHIFT);
1086 } else {
1087 pdm_switch = cs35l36->ldm_mode_sel &&
1088 (prev_clksrc == CS35L36_PLLSRC_PDMCLK);
1089
1090 if (pdm_switch)
1091 regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1092 CS35L36_NG_DELAY_MASK,
1093 0 << CS35L36_NG_DELAY_SHIFT);
1094
1095 regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1096 CS35L36_PDM_MODE_MASK,
1097 0 << CS35L36_PDM_MODE_SHIFT);
1098
1099 if (pdm_switch)
1100 regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1101 CS35L36_NG_DELAY_MASK,
1102 3 << CS35L36_NG_DELAY_SHIFT);
1103 }
1104
1105 return 0;
1106 }
1107
cs35l36_boost_inductor(struct cs35l36_private * cs35l36,int inductor)1108 static int cs35l36_boost_inductor(struct cs35l36_private *cs35l36, int inductor)
1109 {
1110 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1111 CS35L36_BSTCVRT_K1_MASK, 0x3C);
1112 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1113 CS35L36_BSTCVRT_K2_MASK,
1114 0x3C << CS35L36_BSTCVRT_K2_SHIFT);
1115 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SW_FREQ,
1116 CS35L36_BSTCVRT_CCMFREQ_MASK, 0x00);
1117
1118 switch (inductor) {
1119 case 1000: /* 1 uH */
1120 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1121 CS35L36_BSTCVRT_SLOPE_MASK,
1122 0x75 << CS35L36_BSTCVRT_SLOPE_SHIFT);
1123 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1124 CS35L36_BSTCVRT_LBSTVAL_MASK, 0x00);
1125 break;
1126 case 1200: /* 1.2 uH */
1127 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1128 CS35L36_BSTCVRT_SLOPE_MASK,
1129 0x6B << CS35L36_BSTCVRT_SLOPE_SHIFT);
1130 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1131 CS35L36_BSTCVRT_LBSTVAL_MASK, 0x01);
1132 break;
1133 default:
1134 dev_err(cs35l36->dev, "%s Invalid Inductor Value %d uH\n",
1135 __func__, inductor);
1136 return -EINVAL;
1137 }
1138
1139 return 0;
1140 }
1141
cs35l36_component_probe(struct snd_soc_component * component)1142 static int cs35l36_component_probe(struct snd_soc_component *component)
1143 {
1144 struct cs35l36_private *cs35l36 =
1145 snd_soc_component_get_drvdata(component);
1146 int ret;
1147
1148 if ((cs35l36->rev_id == CS35L36_REV_A0) && cs35l36->pdata.dcm_mode) {
1149 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_DCM_CTRL,
1150 CS35L36_DCM_AUTO_MASK,
1151 CS35L36_DCM_AUTO_MASK);
1152
1153 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1154 CS35L36_TEST_UNLOCK1);
1155 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1156 CS35L36_TEST_UNLOCK2);
1157
1158 regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1159 CS35L36_BST_MAN_IPKCOMP_MASK,
1160 0 << CS35L36_BST_MAN_IPKCOMP_SHIFT);
1161 regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1162 CS35L36_BST_MAN_IPKCOMP_EN_MASK,
1163 CS35L36_BST_MAN_IPKCOMP_EN_MASK);
1164
1165 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1166 CS35L36_TEST_LOCK1);
1167 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1168 CS35L36_TEST_LOCK2);
1169 }
1170
1171 if (cs35l36->pdata.amp_pcm_inv)
1172 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_DIG_VOL_CTRL,
1173 CS35L36_AMP_PCM_INV_MASK,
1174 CS35L36_AMP_PCM_INV_MASK);
1175
1176 if (cs35l36->pdata.multi_amp_mode)
1177 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
1178 CS35L36_ASP_TX_HIZ_MASK,
1179 CS35L36_ASP_TX_HIZ_MASK);
1180
1181 if (cs35l36->pdata.imon_pol_inv)
1182 regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1183 CS35L36_IMON_POL_MASK, 0);
1184
1185 if (cs35l36->pdata.vmon_pol_inv)
1186 regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1187 CS35L36_VMON_POL_MASK, 0);
1188
1189 if (cs35l36->pdata.bst_vctl)
1190 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1191 CS35L35_BSTCVRT_CTL_MASK,
1192 cs35l36->pdata.bst_vctl);
1193
1194 if (cs35l36->pdata.bst_vctl_sel)
1195 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1196 CS35L35_BSTCVRT_CTL_SEL_MASK,
1197 cs35l36->pdata.bst_vctl_sel);
1198
1199 if (cs35l36->pdata.bst_ipk)
1200 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_PEAK_CUR,
1201 CS35L36_BST_IPK_MASK,
1202 cs35l36->pdata.bst_ipk);
1203
1204 if (cs35l36->pdata.boost_ind) {
1205 ret = cs35l36_boost_inductor(cs35l36, cs35l36->pdata.boost_ind);
1206 if (ret < 0) {
1207 dev_err(cs35l36->dev,
1208 "Boost inductor config failed(%d)\n", ret);
1209 return ret;
1210 }
1211 }
1212
1213 if (cs35l36->pdata.temp_warn_thld)
1214 regmap_update_bits(cs35l36->regmap, CS35L36_DTEMP_WARN_THLD,
1215 CS35L36_TEMP_THLD_MASK,
1216 cs35l36->pdata.temp_warn_thld);
1217
1218 if (cs35l36->pdata.irq_drv_sel)
1219 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1220 CS35L36_INT_DRV_SEL_MASK,
1221 cs35l36->pdata.irq_drv_sel <<
1222 CS35L36_INT_DRV_SEL_SHIFT);
1223
1224 if (cs35l36->pdata.irq_gpio_sel)
1225 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1226 CS35L36_INT_GPIO_SEL_MASK,
1227 cs35l36->pdata.irq_gpio_sel <<
1228 CS35L36_INT_GPIO_SEL_SHIFT);
1229
1230 /*
1231 * Rev B0 has 2 versions
1232 * L36 is 10V
1233 * L37 is 12V
1234 * If L36 we need to clamp some values for safety
1235 * after probe has setup dt values. We want to make
1236 * sure we dont miss any values set in probe
1237 */
1238 if (cs35l36->chip_version == CS35L36_10V_L36) {
1239 regmap_update_bits(cs35l36->regmap,
1240 CS35L36_BSTCVRT_OVERVOLT_CTRL,
1241 CS35L36_BST_OVP_THLD_MASK,
1242 CS35L36_BST_OVP_THLD_11V);
1243
1244 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1245 CS35L36_TEST_UNLOCK1);
1246 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1247 CS35L36_TEST_UNLOCK2);
1248
1249 regmap_update_bits(cs35l36->regmap, CS35L36_BST_ANA2_TEST,
1250 CS35L36_BST_OVP_TRIM_MASK,
1251 CS35L36_BST_OVP_TRIM_11V <<
1252 CS35L36_BST_OVP_TRIM_SHIFT);
1253 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1254 CS35L36_BST_CTRL_LIM_MASK,
1255 1 << CS35L36_BST_CTRL_LIM_SHIFT);
1256 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1257 CS35L35_BSTCVRT_CTL_MASK,
1258 CS35L36_BST_CTRL_10V_CLAMP);
1259 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1260 CS35L36_TEST_LOCK1);
1261 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1262 CS35L36_TEST_LOCK2);
1263 }
1264
1265 /*
1266 * RevA and B require the disabling of
1267 * SYNC_GLOBAL_OVR when GLOBAL_EN = 0.
1268 * Just turn it off from default
1269 */
1270 regmap_update_bits(cs35l36->regmap, CS35L36_CTRL_OVRRIDE,
1271 CS35L36_SYNC_GLOBAL_OVR_MASK,
1272 0 << CS35L36_SYNC_GLOBAL_OVR_SHIFT);
1273
1274 return 0;
1275 }
1276
1277 static const struct snd_soc_component_driver soc_component_dev_cs35l36 = {
1278 .probe = &cs35l36_component_probe,
1279 .set_sysclk = cs35l36_component_set_sysclk,
1280 .dapm_widgets = cs35l36_dapm_widgets,
1281 .num_dapm_widgets = ARRAY_SIZE(cs35l36_dapm_widgets),
1282 .dapm_routes = cs35l36_audio_map,
1283 .num_dapm_routes = ARRAY_SIZE(cs35l36_audio_map),
1284 .controls = cs35l36_aud_controls,
1285 .num_controls = ARRAY_SIZE(cs35l36_aud_controls),
1286 .idle_bias_on = 1,
1287 .use_pmdown_time = 1,
1288 .endianness = 1,
1289 };
1290
1291 static const struct regmap_config cs35l36_regmap = {
1292 .reg_bits = 32,
1293 .val_bits = 32,
1294 .reg_stride = 4,
1295 .max_register = CS35L36_PAC_PMEM_WORD1023,
1296 .reg_defaults = cs35l36_reg,
1297 .num_reg_defaults = ARRAY_SIZE(cs35l36_reg),
1298 .precious_reg = cs35l36_precious_reg,
1299 .volatile_reg = cs35l36_volatile_reg,
1300 .readable_reg = cs35l36_readable_reg,
1301 .cache_type = REGCACHE_MAPLE,
1302 };
1303
cs35l36_irq(int irq,void * data)1304 static irqreturn_t cs35l36_irq(int irq, void *data)
1305 {
1306 struct cs35l36_private *cs35l36 = data;
1307 unsigned int status[4];
1308 unsigned int masks[4];
1309 int ret = IRQ_NONE;
1310
1311 /* ack the irq by reading all status registers */
1312 regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_STATUS, status,
1313 ARRAY_SIZE(status));
1314
1315 regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_MASK, masks,
1316 ARRAY_SIZE(masks));
1317
1318 /* Check to see if unmasked bits are active */
1319 if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
1320 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) {
1321 return IRQ_NONE;
1322 }
1323
1324 /*
1325 * The following interrupts require a
1326 * protection release cycle to get the
1327 * speaker out of Safe-Mode.
1328 */
1329 if (status[2] & CS35L36_AMP_SHORT_ERR) {
1330 dev_crit(cs35l36->dev, "Amp short error\n");
1331 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1332 CS35L36_AMP_SHORT_ERR_RLS, 0);
1333 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1334 CS35L36_AMP_SHORT_ERR_RLS,
1335 CS35L36_AMP_SHORT_ERR_RLS);
1336 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1337 CS35L36_AMP_SHORT_ERR_RLS, 0);
1338 regmap_update_bits(cs35l36->regmap, CS35L36_INT3_STATUS,
1339 CS35L36_AMP_SHORT_ERR,
1340 CS35L36_AMP_SHORT_ERR);
1341 ret = IRQ_HANDLED;
1342 }
1343
1344 if (status[0] & CS35L36_TEMP_WARN) {
1345 dev_crit(cs35l36->dev, "Over temperature warning\n");
1346 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1347 CS35L36_TEMP_WARN_ERR_RLS, 0);
1348 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1349 CS35L36_TEMP_WARN_ERR_RLS,
1350 CS35L36_TEMP_WARN_ERR_RLS);
1351 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1352 CS35L36_TEMP_WARN_ERR_RLS, 0);
1353 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1354 CS35L36_TEMP_WARN, CS35L36_TEMP_WARN);
1355 ret = IRQ_HANDLED;
1356 }
1357
1358 if (status[0] & CS35L36_TEMP_ERR) {
1359 dev_crit(cs35l36->dev, "Over temperature error\n");
1360 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1361 CS35L36_TEMP_ERR_RLS, 0);
1362 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1363 CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1364 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1365 CS35L36_TEMP_ERR_RLS, 0);
1366 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1367 CS35L36_TEMP_ERR, CS35L36_TEMP_ERR);
1368 ret = IRQ_HANDLED;
1369 }
1370
1371 if (status[0] & CS35L36_BST_OVP_ERR) {
1372 dev_crit(cs35l36->dev, "VBST Over Voltage error\n");
1373 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1374 CS35L36_TEMP_ERR_RLS, 0);
1375 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1376 CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1377 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1378 CS35L36_TEMP_ERR_RLS, 0);
1379 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1380 CS35L36_BST_OVP_ERR, CS35L36_BST_OVP_ERR);
1381 ret = IRQ_HANDLED;
1382 }
1383
1384 if (status[0] & CS35L36_BST_DCM_UVP_ERR) {
1385 dev_crit(cs35l36->dev, "DCM VBST Under Voltage Error\n");
1386 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1387 CS35L36_BST_UVP_ERR_RLS, 0);
1388 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1389 CS35L36_BST_UVP_ERR_RLS,
1390 CS35L36_BST_UVP_ERR_RLS);
1391 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1392 CS35L36_BST_UVP_ERR_RLS, 0);
1393 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1394 CS35L36_BST_DCM_UVP_ERR,
1395 CS35L36_BST_DCM_UVP_ERR);
1396 ret = IRQ_HANDLED;
1397 }
1398
1399 if (status[0] & CS35L36_BST_SHORT_ERR) {
1400 dev_crit(cs35l36->dev, "LBST SHORT error!\n");
1401 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1402 CS35L36_BST_SHORT_ERR_RLS, 0);
1403 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1404 CS35L36_BST_SHORT_ERR_RLS,
1405 CS35L36_BST_SHORT_ERR_RLS);
1406 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1407 CS35L36_BST_SHORT_ERR_RLS, 0);
1408 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1409 CS35L36_BST_SHORT_ERR,
1410 CS35L36_BST_SHORT_ERR);
1411 ret = IRQ_HANDLED;
1412 }
1413
1414 return ret;
1415 }
1416
cs35l36_handle_of_data(struct i2c_client * i2c_client,struct cs35l36_platform_data * pdata)1417 static int cs35l36_handle_of_data(struct i2c_client *i2c_client,
1418 struct cs35l36_platform_data *pdata)
1419 {
1420 struct device_node *np = i2c_client->dev.of_node;
1421 struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1422 struct device_node *vpbr_node;
1423 unsigned int val;
1424 int ret;
1425
1426 if (!np)
1427 return 0;
1428
1429 ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val);
1430 if (!ret) {
1431 if (val < 2550 || val > 12000) {
1432 dev_err(&i2c_client->dev,
1433 "Invalid Boost Voltage %d mV\n", val);
1434 return -EINVAL;
1435 }
1436 pdata->bst_vctl = (((val - 2550) / 100) + 1) << 1;
1437 } else {
1438 dev_err(&i2c_client->dev,
1439 "Unable to find required parameter 'cirrus,boost-ctl-millivolt'");
1440 return -EINVAL;
1441 }
1442
1443 ret = of_property_read_u32(np, "cirrus,boost-ctl-select", &val);
1444 if (!ret)
1445 pdata->bst_vctl_sel = val | CS35L36_VALID_PDATA;
1446
1447 ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val);
1448 if (!ret) {
1449 if (val < 1600 || val > 4500) {
1450 dev_err(&i2c_client->dev,
1451 "Invalid Boost Peak Current %u mA\n", val);
1452 return -EINVAL;
1453 }
1454
1455 pdata->bst_ipk = (val - 1600) / 50;
1456 } else {
1457 dev_err(&i2c_client->dev,
1458 "Unable to find required parameter 'cirrus,boost-peak-milliamp'");
1459 return -EINVAL;
1460 }
1461
1462 pdata->multi_amp_mode = of_property_read_bool(np,
1463 "cirrus,multi-amp-mode");
1464
1465 pdata->dcm_mode = of_property_read_bool(np,
1466 "cirrus,dcm-mode-enable");
1467
1468 pdata->amp_pcm_inv = of_property_read_bool(np,
1469 "cirrus,amp-pcm-inv");
1470
1471 pdata->imon_pol_inv = of_property_read_bool(np,
1472 "cirrus,imon-pol-inv");
1473
1474 pdata->vmon_pol_inv = of_property_read_bool(np,
1475 "cirrus,vmon-pol-inv");
1476
1477 if (of_property_read_u32(np, "cirrus,temp-warn-threshold", &val) >= 0)
1478 pdata->temp_warn_thld = val | CS35L36_VALID_PDATA;
1479
1480 if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
1481 pdata->boost_ind = val;
1482 } else {
1483 dev_err(&i2c_client->dev, "Inductor not specified.\n");
1484 return -EINVAL;
1485 }
1486
1487 if (of_property_read_u32(np, "cirrus,irq-drive-select", &val) >= 0)
1488 pdata->irq_drv_sel = val | CS35L36_VALID_PDATA;
1489
1490 if (of_property_read_u32(np, "cirrus,irq-gpio-select", &val) >= 0)
1491 pdata->irq_gpio_sel = val | CS35L36_VALID_PDATA;
1492
1493 /* VPBR Config */
1494 vpbr_node = of_get_child_by_name(np, "cirrus,vpbr-config");
1495 vpbr_config->is_present = vpbr_node ? true : false;
1496 if (vpbr_config->is_present) {
1497 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-en",
1498 &val) >= 0)
1499 vpbr_config->vpbr_en = val;
1500 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-thld",
1501 &val) >= 0)
1502 vpbr_config->vpbr_thld = val;
1503 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-rate",
1504 &val) >= 0)
1505 vpbr_config->vpbr_atk_rate = val;
1506 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-vol",
1507 &val) >= 0)
1508 vpbr_config->vpbr_atk_vol = val;
1509 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-max-attn",
1510 &val) >= 0)
1511 vpbr_config->vpbr_max_attn = val;
1512 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-wait",
1513 &val) >= 0)
1514 vpbr_config->vpbr_wait = val;
1515 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-rel-rate",
1516 &val) >= 0)
1517 vpbr_config->vpbr_rel_rate = val;
1518 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-mute-en",
1519 &val) >= 0)
1520 vpbr_config->vpbr_mute_en = val;
1521 }
1522 of_node_put(vpbr_node);
1523
1524 return 0;
1525 }
1526
cs35l36_pac(struct cs35l36_private * cs35l36)1527 static int cs35l36_pac(struct cs35l36_private *cs35l36)
1528 {
1529 int ret, count;
1530 unsigned int val;
1531
1532 if (cs35l36->rev_id != CS35L36_REV_B0)
1533 return 0;
1534
1535 /*
1536 * Magic code for internal PAC
1537 */
1538 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1539 CS35L36_TEST_UNLOCK1);
1540 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1541 CS35L36_TEST_UNLOCK2);
1542
1543 usleep_range(9500, 10500);
1544
1545 regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1546 CS35L36_PAC_RESET);
1547 regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1548 CS35L36_PAC_MEM_ACCESS);
1549 regmap_write(cs35l36->regmap, CS35L36_PAC_PMEM_WORD0,
1550 CS35L36_B0_PAC_PATCH);
1551
1552 regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1553 CS35L36_PAC_MEM_ACCESS_CLR);
1554 regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1555 CS35L36_PAC_ENABLE_MASK);
1556
1557 usleep_range(9500, 10500);
1558
1559 ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS, &val);
1560 if (ret < 0) {
1561 dev_err(cs35l36->dev, "Failed to read int4_status %d\n", ret);
1562 return ret;
1563 }
1564
1565 count = 0;
1566 while (!(val & CS35L36_MCU_CONFIG_CLR)) {
1567 usleep_range(100, 200);
1568 count++;
1569
1570 ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS,
1571 &val);
1572 if (ret < 0) {
1573 dev_err(cs35l36->dev, "Failed to read int4_status %d\n",
1574 ret);
1575 return ret;
1576 }
1577
1578 if (count >= 100)
1579 return -EINVAL;
1580 }
1581
1582 regmap_write(cs35l36->regmap, CS35L36_INT4_STATUS,
1583 CS35L36_MCU_CONFIG_CLR);
1584 regmap_update_bits(cs35l36->regmap, CS35L36_PAC_CTL1,
1585 CS35L36_PAC_ENABLE_MASK, 0);
1586
1587 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1588 CS35L36_TEST_LOCK1);
1589 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1590 CS35L36_TEST_LOCK2);
1591
1592 return 0;
1593 }
1594
cs35l36_apply_vpbr_config(struct cs35l36_private * cs35l36)1595 static void cs35l36_apply_vpbr_config(struct cs35l36_private *cs35l36)
1596 {
1597 struct cs35l36_platform_data *pdata = &cs35l36->pdata;
1598 struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1599
1600 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL3,
1601 CS35L36_VPBR_EN_MASK,
1602 vpbr_config->vpbr_en <<
1603 CS35L36_VPBR_EN_SHIFT);
1604 regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1605 CS35L36_VPBR_THLD_MASK,
1606 vpbr_config->vpbr_thld <<
1607 CS35L36_VPBR_THLD_SHIFT);
1608 regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1609 CS35L36_VPBR_MAX_ATTN_MASK,
1610 vpbr_config->vpbr_max_attn <<
1611 CS35L36_VPBR_MAX_ATTN_SHIFT);
1612 regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1613 CS35L36_VPBR_ATK_VOL_MASK,
1614 vpbr_config->vpbr_atk_vol <<
1615 CS35L36_VPBR_ATK_VOL_SHIFT);
1616 regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1617 CS35L36_VPBR_ATK_RATE_MASK,
1618 vpbr_config->vpbr_atk_rate <<
1619 CS35L36_VPBR_ATK_RATE_SHIFT);
1620 regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1621 CS35L36_VPBR_WAIT_MASK,
1622 vpbr_config->vpbr_wait <<
1623 CS35L36_VPBR_WAIT_SHIFT);
1624 regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1625 CS35L36_VPBR_REL_RATE_MASK,
1626 vpbr_config->vpbr_rel_rate <<
1627 CS35L36_VPBR_REL_RATE_SHIFT);
1628 regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1629 CS35L36_VPBR_MUTE_EN_MASK,
1630 vpbr_config->vpbr_mute_en <<
1631 CS35L36_VPBR_MUTE_EN_SHIFT);
1632 }
1633
1634 static const struct reg_sequence cs35l36_reva0_errata_patch[] = {
1635 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
1636 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
1637 /* Errata Writes */
1638 { CS35L36_OTP_CTRL1, 0x00002060 },
1639 { CS35L36_OTP_CTRL2, 0x00000001 },
1640 { CS35L36_OTP_CTRL1, 0x00002460 },
1641 { CS35L36_OTP_CTRL2, 0x00000001 },
1642 { 0x00002088, 0x012A1838 },
1643 { 0x00003014, 0x0100EE0E },
1644 { 0x00003008, 0x0008184A },
1645 { 0x00007418, 0x509001C8 },
1646 { 0x00007064, 0x0929A800 },
1647 { 0x00002D10, 0x0002C01C },
1648 { 0x0000410C, 0x00000A11 },
1649 { 0x00006E08, 0x8B19140C },
1650 { 0x00006454, 0x0300000A },
1651 { CS35L36_AMP_NG_CTRL, 0x000020EF },
1652 { 0x00007E34, 0x0000000E },
1653 { 0x0000410C, 0x00000A11 },
1654 { 0x00007410, 0x20514B00 },
1655 /* PAC Config */
1656 { CS35L36_CTRL_OVRRIDE, 0x00000000 },
1657 { CS35L36_PAC_INT0_CTRL, 0x00860001 },
1658 { CS35L36_PAC_INT1_CTRL, 0x00860001 },
1659 { CS35L36_PAC_INT2_CTRL, 0x00860001 },
1660 { CS35L36_PAC_INT3_CTRL, 0x00860001 },
1661 { CS35L36_PAC_INT4_CTRL, 0x00860001 },
1662 { CS35L36_PAC_INT5_CTRL, 0x00860001 },
1663 { CS35L36_PAC_INT6_CTRL, 0x00860001 },
1664 { CS35L36_PAC_INT7_CTRL, 0x00860001 },
1665 { CS35L36_PAC_INT_FLUSH_CTRL, 0x000000FF },
1666 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
1667 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
1668 };
1669
1670 static const struct reg_sequence cs35l36_revb0_errata_patch[] = {
1671 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
1672 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
1673 { 0x00007064, 0x0929A800 },
1674 { 0x00007850, 0x00002FA9 },
1675 { 0x00007854, 0x0003F1D5 },
1676 { 0x00007858, 0x0003F5E3 },
1677 { 0x0000785C, 0x00001137 },
1678 { 0x00007860, 0x0001A7A5 },
1679 { 0x00007864, 0x0002F16A },
1680 { 0x00007868, 0x00003E21 },
1681 { 0x00007848, 0x00000001 },
1682 { 0x00003854, 0x05180240 },
1683 { 0x00007418, 0x509001C8 },
1684 { 0x0000394C, 0x028764BD },
1685 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
1686 { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
1687 };
1688
cs35l36_i2c_probe(struct i2c_client * i2c_client)1689 static int cs35l36_i2c_probe(struct i2c_client *i2c_client)
1690 {
1691 struct cs35l36_private *cs35l36;
1692 struct device *dev = &i2c_client->dev;
1693 struct cs35l36_platform_data *pdata = dev_get_platdata(dev);
1694 struct irq_data *irq_d;
1695 int ret, irq_pol, chip_irq_pol, i;
1696 u32 reg_id, reg_revid, l37_id_reg;
1697
1698 cs35l36 = devm_kzalloc(dev, sizeof(struct cs35l36_private), GFP_KERNEL);
1699 if (!cs35l36)
1700 return -ENOMEM;
1701
1702 cs35l36->dev = dev;
1703
1704 i2c_set_clientdata(i2c_client, cs35l36);
1705 cs35l36->regmap = devm_regmap_init_i2c(i2c_client, &cs35l36_regmap);
1706 if (IS_ERR(cs35l36->regmap)) {
1707 ret = PTR_ERR(cs35l36->regmap);
1708 dev_err(dev, "regmap_init() failed: %d\n", ret);
1709 return ret;
1710 }
1711
1712 cs35l36->num_supplies = ARRAY_SIZE(cs35l36_supplies);
1713 for (i = 0; i < ARRAY_SIZE(cs35l36_supplies); i++)
1714 cs35l36->supplies[i].supply = cs35l36_supplies[i];
1715
1716 ret = devm_regulator_bulk_get(dev, cs35l36->num_supplies,
1717 cs35l36->supplies);
1718 if (ret != 0) {
1719 dev_err(dev, "Failed to request core supplies: %d\n", ret);
1720 return ret;
1721 }
1722
1723 if (pdata) {
1724 cs35l36->pdata = *pdata;
1725 } else {
1726 pdata = devm_kzalloc(dev, sizeof(struct cs35l36_platform_data),
1727 GFP_KERNEL);
1728 if (!pdata)
1729 return -ENOMEM;
1730
1731 if (i2c_client->dev.of_node) {
1732 ret = cs35l36_handle_of_data(i2c_client, pdata);
1733 if (ret != 0)
1734 return ret;
1735
1736 }
1737
1738 cs35l36->pdata = *pdata;
1739 }
1740
1741 ret = regulator_bulk_enable(cs35l36->num_supplies, cs35l36->supplies);
1742 if (ret != 0) {
1743 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
1744 return ret;
1745 }
1746
1747 /* returning NULL can be an option if in stereo mode */
1748 cs35l36->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1749 GPIOD_OUT_LOW);
1750 if (IS_ERR(cs35l36->reset_gpio)) {
1751 ret = PTR_ERR(cs35l36->reset_gpio);
1752 cs35l36->reset_gpio = NULL;
1753 if (ret == -EBUSY) {
1754 dev_info(dev, "Reset line busy, assuming shared reset\n");
1755 } else {
1756 dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
1757 goto err_disable_regs;
1758 }
1759 }
1760
1761 if (cs35l36->reset_gpio)
1762 gpiod_set_value_cansleep(cs35l36->reset_gpio, 1);
1763
1764 usleep_range(2000, 2100);
1765
1766 /* initialize amplifier */
1767 ret = regmap_read(cs35l36->regmap, CS35L36_SW_RESET, ®_id);
1768 if (ret < 0) {
1769 dev_err(dev, "Get Device ID failed %d\n", ret);
1770 goto err;
1771 }
1772
1773 if (reg_id != CS35L36_CHIP_ID) {
1774 dev_err(dev, "Device ID (%X). Expected ID %X\n", reg_id,
1775 CS35L36_CHIP_ID);
1776 ret = -ENODEV;
1777 goto err;
1778 }
1779
1780 ret = regmap_read(cs35l36->regmap, CS35L36_REV_ID, ®_revid);
1781 if (ret < 0) {
1782 dev_err(&i2c_client->dev, "Get Revision ID failed %d\n", ret);
1783 goto err;
1784 }
1785
1786 cs35l36->rev_id = reg_revid >> 8;
1787
1788 ret = regmap_read(cs35l36->regmap, CS35L36_OTP_MEM30, &l37_id_reg);
1789 if (ret < 0) {
1790 dev_err(&i2c_client->dev, "Failed to read otp_id Register %d\n",
1791 ret);
1792 goto err;
1793 }
1794
1795 if ((l37_id_reg & CS35L36_OTP_REV_MASK) == CS35L36_OTP_REV_L37)
1796 cs35l36->chip_version = CS35L36_12V_L37;
1797 else
1798 cs35l36->chip_version = CS35L36_10V_L36;
1799
1800 switch (cs35l36->rev_id) {
1801 case CS35L36_REV_A0:
1802 ret = regmap_register_patch(cs35l36->regmap,
1803 cs35l36_reva0_errata_patch,
1804 ARRAY_SIZE(cs35l36_reva0_errata_patch));
1805 if (ret < 0) {
1806 dev_err(dev, "Failed to apply A0 errata patch %d\n",
1807 ret);
1808 goto err;
1809 }
1810 break;
1811 case CS35L36_REV_B0:
1812 ret = cs35l36_pac(cs35l36);
1813 if (ret < 0) {
1814 dev_err(dev, "Failed to Trim OTP %d\n", ret);
1815 goto err;
1816 }
1817
1818 ret = regmap_register_patch(cs35l36->regmap,
1819 cs35l36_revb0_errata_patch,
1820 ARRAY_SIZE(cs35l36_revb0_errata_patch));
1821 if (ret < 0) {
1822 dev_err(dev, "Failed to apply B0 errata patch %d\n",
1823 ret);
1824 goto err;
1825 }
1826 break;
1827 }
1828
1829 if (pdata->vpbr_config.is_present)
1830 cs35l36_apply_vpbr_config(cs35l36);
1831
1832 irq_d = irq_get_irq_data(i2c_client->irq);
1833 if (!irq_d) {
1834 dev_err(&i2c_client->dev, "Invalid IRQ: %d\n", i2c_client->irq);
1835 ret = -ENODEV;
1836 goto err;
1837 }
1838
1839 irq_pol = irqd_get_trigger_type(irq_d);
1840
1841 switch (irq_pol) {
1842 case IRQF_TRIGGER_FALLING:
1843 case IRQF_TRIGGER_LOW:
1844 chip_irq_pol = 0;
1845 break;
1846 case IRQF_TRIGGER_RISING:
1847 case IRQF_TRIGGER_HIGH:
1848 chip_irq_pol = 1;
1849 break;
1850 default:
1851 dev_err(cs35l36->dev, "Invalid IRQ polarity: %d\n", irq_pol);
1852 ret = -EINVAL;
1853 goto err;
1854 }
1855
1856 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1857 CS35L36_INT_POL_SEL_MASK,
1858 chip_irq_pol << CS35L36_INT_POL_SEL_SHIFT);
1859
1860 ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l36_irq,
1861 IRQF_ONESHOT | irq_pol, "cs35l36",
1862 cs35l36);
1863 if (ret != 0) {
1864 dev_err(dev, "Failed to request IRQ: %d\n", ret);
1865 goto err;
1866 }
1867
1868 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1869 CS35L36_INT_OUTPUT_EN_MASK, 1);
1870
1871 /* Set interrupt masks for critical errors */
1872 regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1873 CS35L36_INT1_MASK_DEFAULT);
1874 regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1875 CS35L36_INT3_MASK_DEFAULT);
1876
1877 dev_info(&i2c_client->dev, "Cirrus Logic CS35L%d, Revision: %02X\n",
1878 cs35l36->chip_version, reg_revid >> 8);
1879
1880 ret = devm_snd_soc_register_component(dev, &soc_component_dev_cs35l36,
1881 cs35l36_dai,
1882 ARRAY_SIZE(cs35l36_dai));
1883 if (ret < 0) {
1884 dev_err(dev, "%s: Register component failed %d\n", __func__,
1885 ret);
1886 goto err;
1887 }
1888
1889 return 0;
1890
1891 err:
1892 gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1893
1894 err_disable_regs:
1895 regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1896 return ret;
1897 }
1898
cs35l36_i2c_remove(struct i2c_client * client)1899 static void cs35l36_i2c_remove(struct i2c_client *client)
1900 {
1901 struct cs35l36_private *cs35l36 = i2c_get_clientdata(client);
1902
1903 /* Reset interrupt masks for device removal */
1904 regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1905 CS35L36_INT1_MASK_RESET);
1906 regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1907 CS35L36_INT3_MASK_RESET);
1908
1909 if (cs35l36->reset_gpio)
1910 gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1911
1912 regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1913 }
1914 static const struct of_device_id cs35l36_of_match[] = {
1915 {.compatible = "cirrus,cs35l36"},
1916 {},
1917 };
1918 MODULE_DEVICE_TABLE(of, cs35l36_of_match);
1919
1920 static const struct i2c_device_id cs35l36_id[] = {
1921 {"cs35l36"},
1922 {}
1923 };
1924
1925 MODULE_DEVICE_TABLE(i2c, cs35l36_id);
1926
1927 static struct i2c_driver cs35l36_i2c_driver = {
1928 .driver = {
1929 .name = "cs35l36",
1930 .of_match_table = cs35l36_of_match,
1931 },
1932 .id_table = cs35l36_id,
1933 .probe = cs35l36_i2c_probe,
1934 .remove = cs35l36_i2c_remove,
1935 };
1936 module_i2c_driver(cs35l36_i2c_driver);
1937
1938 MODULE_DESCRIPTION("ASoC CS35L36 driver");
1939 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1940 MODULE_LICENSE("GPL");
1941