1 /* 2 * Copyright (c) 2024, Broadcom. All rights reserved. The term 3 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef __BNXT_RE_ABI_H__ 30 #define __BNXT_RE_ABI_H__ 31 32 #include <sys/types.h> 33 #include <sys/mman.h> 34 #include <sys/stat.h> 35 36 #include <infiniband/kern-abi.h> 37 38 #include <errno.h> 39 #include <fcntl.h> 40 #include <limits.h> 41 #include <pthread.h> 42 #include <stdio.h> 43 #include <stdlib.h> 44 #include <string.h> 45 #include <unistd.h> 46 47 #define __aligned_u64 __attribute__((aligned(8))) u64 48 49 #define BNXT_RE_ABI_VERSION 7 50 #define BNXT_RE_MAX_INLINE_SIZE 0x60 51 #define BNXT_RE_MAX_INLINE_SIZE_VAR_WQE 0x1E0 52 #define BNXT_RE_MAX_PUSH_SIZE_VAR_WQE 0xD0 53 #define BNXT_RE_FULL_FLAG_DELTA 0x00 54 55 enum bnxt_re_wr_opcode { 56 BNXT_RE_WR_OPCD_SEND = 0x00, 57 BNXT_RE_WR_OPCD_SEND_IMM = 0x01, 58 BNXT_RE_WR_OPCD_SEND_INVAL = 0x02, 59 BNXT_RE_WR_OPCD_RDMA_WRITE = 0x04, 60 BNXT_RE_WR_OPCD_RDMA_WRITE_IMM = 0x05, 61 BNXT_RE_WR_OPCD_RDMA_READ = 0x06, 62 BNXT_RE_WR_OPCD_ATOMIC_CS = 0x08, 63 BNXT_RE_WR_OPCD_ATOMIC_FA = 0x0B, 64 BNXT_RE_WR_OPCD_LOC_INVAL = 0x0C, 65 BNXT_RE_WR_OPCD_BIND = 0x0E, 66 BNXT_RE_WR_OPCD_RECV = 0x80, 67 BNXT_RE_WR_OPCD_INVAL = 0xFF 68 }; 69 70 enum bnxt_re_wr_flags { 71 BNXT_RE_WR_FLAGS_INLINE = 0x10, 72 BNXT_RE_WR_FLAGS_SE = 0x08, 73 BNXT_RE_WR_FLAGS_UC_FENCE = 0x04, 74 BNXT_RE_WR_FLAGS_RD_FENCE = 0x02, 75 BNXT_RE_WR_FLAGS_SIGNALED = 0x01 76 }; 77 78 #define BNXT_RE_MEMW_TYPE_2 0x02 79 #define BNXT_RE_MEMW_TYPE_1 0x00 80 enum bnxt_re_wr_bind_acc { 81 BNXT_RE_WR_BIND_ACC_LWR = 0x01, 82 BNXT_RE_WR_BIND_ACC_RRD = 0x02, 83 BNXT_RE_WR_BIND_ACC_RWR = 0x04, 84 BNXT_RE_WR_BIND_ACC_RAT = 0x08, 85 BNXT_RE_WR_BIND_ACC_MWB = 0x10, 86 BNXT_RE_WR_BIND_ACC_ZBVA = 0x01, 87 BNXT_RE_WR_BIND_ACC_SHIFT = 0x10 88 }; 89 90 enum bnxt_re_wc_type { 91 BNXT_RE_WC_TYPE_SEND = 0x00, 92 BNXT_RE_WC_TYPE_RECV_RC = 0x01, 93 BNXT_RE_WC_TYPE_RECV_UD = 0x02, 94 BNXT_RE_WC_TYPE_RECV_RAW = 0x03, 95 BNXT_RE_WC_TYPE_TERM = 0x0E, 96 BNXT_RE_WC_TYPE_COFF = 0x0F 97 }; 98 99 #define BNXT_RE_WC_OPCD_RECV 0x80 100 enum bnxt_re_req_wc_status { 101 BNXT_RE_REQ_ST_OK = 0x00, 102 BNXT_RE_REQ_ST_BAD_RESP = 0x01, 103 BNXT_RE_REQ_ST_LOC_LEN = 0x02, 104 BNXT_RE_REQ_ST_LOC_QP_OP = 0x03, 105 BNXT_RE_REQ_ST_PROT = 0x04, 106 BNXT_RE_REQ_ST_MEM_OP = 0x05, 107 BNXT_RE_REQ_ST_REM_INVAL = 0x06, 108 BNXT_RE_REQ_ST_REM_ACC = 0x07, 109 BNXT_RE_REQ_ST_REM_OP = 0x08, 110 BNXT_RE_REQ_ST_RNR_NAK_XCED = 0x09, 111 BNXT_RE_REQ_ST_TRNSP_XCED = 0x0A, 112 BNXT_RE_REQ_ST_WR_FLUSH = 0x0B 113 }; 114 115 enum bnxt_re_rsp_wc_status { 116 BNXT_RE_RSP_ST_OK = 0x00, 117 BNXT_RE_RSP_ST_LOC_ACC = 0x01, 118 BNXT_RE_RSP_ST_LOC_LEN = 0x02, 119 BNXT_RE_RSP_ST_LOC_PROT = 0x03, 120 BNXT_RE_RSP_ST_LOC_QP_OP = 0x04, 121 BNXT_RE_RSP_ST_MEM_OP = 0x05, 122 BNXT_RE_RSP_ST_REM_INVAL = 0x06, 123 BNXT_RE_RSP_ST_WR_FLUSH = 0x07, 124 BNXT_RE_RSP_ST_HW_FLUSH = 0x08 125 }; 126 127 enum bnxt_re_hdr_offset { 128 BNXT_RE_HDR_WT_MASK = 0xFF, 129 BNXT_RE_HDR_FLAGS_MASK = 0xFF, 130 BNXT_RE_HDR_FLAGS_SHIFT = 0x08, 131 BNXT_RE_HDR_WS_MASK = 0xFF, 132 BNXT_RE_HDR_WS_SHIFT = 0x10 133 }; 134 135 enum bnxt_re_db_que_type { 136 BNXT_RE_QUE_TYPE_SQ = 0x00, 137 BNXT_RE_QUE_TYPE_RQ = 0x01, 138 BNXT_RE_QUE_TYPE_SRQ = 0x02, 139 BNXT_RE_QUE_TYPE_SRQ_ARM = 0x03, 140 BNXT_RE_QUE_TYPE_CQ = 0x04, 141 BNXT_RE_QUE_TYPE_CQ_ARMSE = 0x05, 142 BNXT_RE_QUE_TYPE_CQ_ARMALL = 0x06, 143 BNXT_RE_QUE_TYPE_CQ_ARMENA = 0x07, 144 BNXT_RE_QUE_TYPE_SRQ_ARMENA = 0x08, 145 BNXT_RE_QUE_TYPE_CQ_CUT_ACK = 0x09, 146 BNXT_RE_PUSH_TYPE_START = 0x0C, 147 BNXT_RE_PUSH_TYPE_END = 0x0D, 148 BNXT_RE_QUE_TYPE_NULL = 0x0F 149 }; 150 151 enum bnxt_re_db_mask { 152 BNXT_RE_DB_INDX_MASK = 0xFFFFFFUL, 153 BNXT_RE_DB_PILO_MASK = 0x0FFUL, 154 BNXT_RE_DB_PILO_SHIFT = 0x18, 155 BNXT_RE_DB_QID_MASK = 0xFFFFFUL, 156 BNXT_RE_DB_PIHI_MASK = 0xF00UL, 157 BNXT_RE_DB_PIHI_SHIFT = 0x0C, /* Because mask is 0xF00 */ 158 BNXT_RE_DB_TYP_MASK = 0x0FUL, 159 BNXT_RE_DB_TYP_SHIFT = 0x1C, 160 BNXT_RE_DB_VALID_SHIFT = 0x1A, 161 BNXT_RE_DB_EPOCH_SHIFT = 0x18, 162 BNXT_RE_DB_TOGGLE_SHIFT = 0x19, 163 164 }; 165 166 enum bnxt_re_psns_mask { 167 BNXT_RE_PSNS_SPSN_MASK = 0xFFFFFF, 168 BNXT_RE_PSNS_OPCD_MASK = 0xFF, 169 BNXT_RE_PSNS_OPCD_SHIFT = 0x18, 170 BNXT_RE_PSNS_NPSN_MASK = 0xFFFFFF, 171 BNXT_RE_PSNS_FLAGS_MASK = 0xFF, 172 BNXT_RE_PSNS_FLAGS_SHIFT = 0x18 173 }; 174 175 enum bnxt_re_msns_mask { 176 BNXT_RE_SQ_MSN_SEARCH_START_PSN_MASK = 0xFFFFFFUL, 177 BNXT_RE_SQ_MSN_SEARCH_START_PSN_SHIFT = 0, 178 BNXT_RE_SQ_MSN_SEARCH_NEXT_PSN_MASK = 0xFFFFFF000000ULL, 179 BNXT_RE_SQ_MSN_SEARCH_NEXT_PSN_SHIFT = 0x18, 180 BNXT_RE_SQ_MSN_SEARCH_START_IDX_MASK = 0xFFFF000000000000ULL, 181 BNXT_RE_SQ_MSN_SEARCH_START_IDX_SHIFT = 0x30 182 }; 183 184 enum bnxt_re_bcqe_mask { 185 BNXT_RE_BCQE_PH_MASK = 0x01, 186 BNXT_RE_BCQE_TYPE_MASK = 0x0F, 187 BNXT_RE_BCQE_TYPE_SHIFT = 0x01, 188 BNXT_RE_BCQE_STATUS_MASK = 0xFF, 189 BNXT_RE_BCQE_STATUS_SHIFT = 0x08, 190 BNXT_RE_BCQE_FLAGS_MASK = 0xFFFFU, 191 BNXT_RE_BCQE_FLAGS_SHIFT = 0x10, 192 BNXT_RE_BCQE_RWRID_MASK = 0xFFFFFU, 193 BNXT_RE_BCQE_SRCQP_MASK = 0xFF, 194 BNXT_RE_BCQE_SRCQP_SHIFT = 0x18 195 }; 196 197 enum bnxt_re_rc_flags_mask { 198 BNXT_RE_RC_FLAGS_SRQ_RQ_MASK = 0x01, 199 BNXT_RE_RC_FLAGS_IMM_MASK = 0x02, 200 BNXT_RE_RC_FLAGS_IMM_SHIFT = 0x01, 201 BNXT_RE_RC_FLAGS_INV_MASK = 0x04, 202 BNXT_RE_RC_FLAGS_INV_SHIFT = 0x02, 203 BNXT_RE_RC_FLAGS_RDMA_MASK = 0x08, 204 BNXT_RE_RC_FLAGS_RDMA_SHIFT = 0x03 205 }; 206 207 enum bnxt_re_ud_flags_mask { 208 BNXT_RE_UD_FLAGS_SRQ_RQ_MASK = 0x01, 209 BNXT_RE_UD_FLAGS_SRQ_RQ_SFT = 0x00, 210 BNXT_RE_UD_FLAGS_IMM_MASK = 0x02, 211 BNXT_RE_UD_FLAGS_IMM_SFT = 0x01, 212 BNXT_RE_UD_FLAGS_IP_VER_MASK = 0x30, 213 BNXT_RE_UD_FLAGS_IP_VER_SFT = 0x4, 214 BNXT_RE_UD_FLAGS_META_MASK = 0x3C0, 215 BNXT_RE_UD_FLAGS_META_SFT = 0x6, 216 BNXT_RE_UD_FLAGS_EXT_META_MASK = 0xC00, 217 BNXT_RE_UD_FLAGS_EXT_META_SFT = 0x10, 218 }; 219 220 enum bnxt_re_ud_cqe_mask { 221 BNXT_RE_UD_CQE_MAC_MASK = 0xFFFFFFFFFFFFULL, 222 BNXT_RE_UD_CQE_SRCQPLO_MASK = 0xFFFF, 223 BNXT_RE_UD_CQE_SRCQPLO_SHIFT = 0x30, 224 BNXT_RE_UD_CQE_LEN_MASK = 0x3FFFU 225 }; 226 227 enum bnxt_re_shpg_offt { 228 BNXT_RE_SHPG_BEG_RESV_OFFT = 0x00, 229 BNXT_RE_SHPG_AVID_OFFT = 0x10, 230 BNXT_RE_SHPG_AVID_SIZE = 0x04, 231 BNXT_RE_SHPG_END_RESV_OFFT = 0xFF0 232 }; 233 234 enum bnxt_re_que_flags_mask { 235 BNXT_RE_FLAG_EPOCH_TAIL_SHIFT = 0x0UL, 236 BNXT_RE_FLAG_EPOCH_HEAD_SHIFT = 0x1UL, 237 BNXT_RE_FLAG_EPOCH_TAIL_MASK = 0x1UL, 238 BNXT_RE_FLAG_EPOCH_HEAD_MASK = 0x2UL, 239 }; 240 241 enum bnxt_re_db_epoch_flag_shift { 242 BNXT_RE_DB_EPOCH_TAIL_SHIFT = BNXT_RE_DB_EPOCH_SHIFT, 243 BNXT_RE_DB_EPOCH_HEAD_SHIFT = (BNXT_RE_DB_EPOCH_SHIFT - 1) 244 }; 245 246 enum bnxt_re_ppp_st_en_mask { 247 BNXT_RE_PPP_ENABLED_MASK = 0x1UL, 248 BNXT_RE_PPP_STATE_MASK = 0x2UL, 249 }; 250 251 enum bnxt_re_ppp_st_shift { 252 BNXT_RE_PPP_ST_SHIFT = 0x1UL 253 }; 254 255 struct bnxt_re_db_hdr { 256 __u64 typ_qid_indx; /* typ: 4, qid:20, indx:24 */ 257 }; 258 259 #define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00 260 #define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10 261 #define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18 262 263 enum { 264 BNXT_RE_COMP_MASK_UCNTX_WC_DPI_ENABLED = 0x01, 265 BNXT_RE_COMP_MASK_UCNTX_POW2_DISABLED = 0x02, 266 BNXT_RE_COMP_MASK_UCNTX_RSVD_WQE_DISABLED = 0x04, 267 BNXT_RE_COMP_MASK_UCNTX_MQP_EX_SUPPORTED = 0x8, 268 BNXT_RE_COMP_MASK_UCNTX_DBR_PACING_ENABLED = 0x10, 269 BNXT_RE_COMP_MASK_UCNTX_DBR_RECOVERY_ENABLED = 0x20, 270 BNXT_RE_COMP_MASK_UCNTX_HW_RETX_ENABLED = 0x40, 271 BNXT_RE_COMP_MASK_UCNTX_CMASK_HAVE_MODE = 0x80 272 }; 273 274 enum bnxt_re_req_to_drv { 275 BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT = 0x01, 276 BNXT_RE_COMP_MASK_REQ_UCNTX_RSVD_WQE = 0x02, 277 BNXT_RE_COMP_MASK_REQ_UCNTX_VAR_WQE_SUPPORT = 0x03 278 }; 279 280 #define BNXT_RE_WQE_MODES_WQE_MODE_MASK 0x01 281 /* bit wise modes can be extended here. */ 282 enum bnxt_re_modes { 283 BNXT_RE_WQE_MODE_STATIC = 0x00, 284 BNXT_RE_WQE_MODE_VARIABLE = 0x01 285 /* Other modes can be here */ 286 }; 287 288 struct bnxt_re_cntx_req { 289 struct ibv_get_context cmd; 290 __aligned_u64 comp_mask; 291 }; 292 293 struct bnxt_re_cntx_resp { 294 struct ibv_get_context_resp resp; 295 __u32 dev_id; 296 __u32 max_qp; /* To allocate qp-table */ 297 __u32 pg_size; 298 __u32 cqe_size; 299 __u32 max_cqd; 300 __u32 chip_id0; 301 __u32 chip_id1; 302 __u32 modes; 303 __aligned_u64 comp_mask; 304 } __attribute__((packed)); 305 306 enum { 307 BNXT_RE_COMP_MASK_PD_HAS_WC_DPI = 0x01, 308 BNXT_RE_COMP_MASK_PD_HAS_DBR_BAR_ADDR = 0x02, 309 }; 310 311 struct bnxt_re_pd_resp { 312 struct ibv_alloc_pd_resp resp; 313 __u32 pdid; 314 __u32 dpi; 315 __u64 dbr; 316 __u64 comp_mask; 317 __u32 wcdpi; 318 __u64 dbr_bar_map; 319 } __attribute__((packed)); 320 321 struct bnxt_re_mr_resp { 322 struct ibv_reg_mr_resp resp; 323 } __attribute__((packed)); 324 325 /* CQ */ 326 enum { 327 BNXT_RE_COMP_MASK_CQ_HAS_DB_INFO = 0x01, 328 BNXT_RE_COMP_MASK_CQ_HAS_WC_DPI = 0x02, 329 BNXT_RE_COMP_MASK_CQ_HAS_CQ_PAGE = 0x04 330 }; 331 332 enum { 333 BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK = 0x1 334 }; 335 336 enum { 337 BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_RECOVERY = 0x1 338 }; 339 340 struct bnxt_re_cq_req { 341 struct ibv_create_cq cmd; 342 __u64 cq_va; 343 __u64 cq_handle; 344 __aligned_u64 comp_mask; 345 __u16 cq_capab; 346 } __attribute__((packed)); 347 348 struct bnxt_re_cq_resp { 349 struct ibv_create_cq_resp resp; 350 __u32 cqid; 351 __u32 tail; 352 __u32 phase; 353 __u32 rsvd; 354 __aligned_u64 comp_mask; 355 __u32 dpi; 356 __u64 dbr; 357 __u32 wcdpi; 358 __u64 cq_page; 359 } __attribute__((packed)); 360 361 struct bnxt_re_resize_cq_req { 362 struct ibv_resize_cq cmd; 363 __u64 cq_va; 364 } __attribute__((packed)); 365 366 struct bnxt_re_bcqe { 367 __u32 flg_st_typ_ph; 368 __u32 qphi_rwrid; 369 } __attribute__((packed)); 370 371 struct bnxt_re_req_cqe { 372 __u64 qp_handle; 373 __u32 con_indx; /* 16 bits valid. */ 374 __u32 rsvd1; 375 __u64 rsvd2; 376 } __attribute__((packed)); 377 378 struct bnxt_re_rc_cqe { 379 __u32 length; 380 __u32 imm_key; 381 __u64 qp_handle; 382 __u64 mr_handle; 383 } __attribute__((packed)); 384 385 struct bnxt_re_ud_cqe { 386 __u32 length; /* 14 bits */ 387 __u32 immd; 388 __u64 qp_handle; 389 __u64 qplo_mac; /* 16:48*/ 390 } __attribute__((packed)); 391 392 struct bnxt_re_term_cqe { 393 __u64 qp_handle; 394 __u32 rq_sq_cidx; 395 __u32 rsvd; 396 __u64 rsvd1; 397 } __attribute__((packed)); 398 399 struct bnxt_re_cutoff_cqe { 400 __u64 rsvd1; 401 __u64 rsvd2; 402 __u64 rsvd3; 403 __u8 cqe_type_toggle; 404 __u8 status; 405 __u16 rsvd4; 406 __u32 rsvd5; 407 } __attribute__((packed)); 408 409 /* QP */ 410 struct bnxt_re_qp_req { 411 struct ibv_create_qp cmd; 412 __u64 qpsva; 413 __u64 qprva; 414 __u64 qp_handle; 415 __u64 comp_mask; 416 __u32 sq_slots; 417 } __attribute__((packed)); 418 419 struct bnxt_re_qp_resp { 420 struct ibv_create_qp_resp resp; 421 __u32 qpid; 422 } __attribute__((packed)); 423 424 enum bnxt_re_modify_ex_mask { 425 BNXT_RE_MQP_PPP_REQ_EN_MASK = 0x1UL, 426 BNXT_RE_MQP_PPP_REQ_EN = 0x1UL, 427 BNXT_RE_MQP_PATH_MTU_MASK = 0x2UL, 428 BNXT_RE_MQP_PPP_IDX_MASK = 0x7UL, 429 BNXT_RE_MQP_PPP_STATE = 0x10UL 430 }; 431 432 /* Modify QP */ 433 struct bnxt_re_modify_ex_req { 434 struct ibv_modify_qp_ex cmd; 435 __aligned_u64 comp_mask; 436 __u32 dpi; 437 __u32 rsvd; 438 }; 439 440 struct bnxt_re_modify_ex_resp { 441 struct ibv_modify_qp_resp_ex resp; 442 __aligned_u64 comp_mask; 443 __u32 ppp_st_idx; 444 __u32 path_mtu; 445 }; 446 447 union lower_shdr { 448 __u64 qkey_len; 449 __u64 lkey_plkey; 450 __u64 rva; 451 }; 452 453 struct bnxt_re_bsqe { 454 __u32 rsv_ws_fl_wt; 455 __u32 key_immd; 456 union lower_shdr lhdr; 457 } __attribute__((packed)); 458 459 struct bnxt_re_psns_ext { 460 __u32 opc_spsn; 461 __u32 flg_npsn; 462 __u16 st_slot_idx; 463 __u16 rsvd0; 464 __u32 rsvd1; 465 } __attribute__((packed)); 466 467 /* sq_msn_search (size:64b/8B) */ 468 struct bnxt_re_msns { 469 __u64 start_idx_next_psn_start_psn; 470 } __attribute__((packed)); 471 472 struct bnxt_re_psns { 473 __u32 opc_spsn; 474 __u32 flg_npsn; 475 } __attribute__((packed)); 476 477 struct bnxt_re_sge { 478 __u64 pa; 479 __u32 lkey; 480 __u32 length; 481 } __attribute__((packed)); 482 483 struct bnxt_re_send { 484 __u32 dst_qp; 485 __u32 avid; 486 __u64 rsvd; 487 } __attribute__((packed)); 488 489 struct bnxt_re_raw { 490 __u32 cfa_meta; 491 __u32 rsvd2; 492 __u64 rsvd3; 493 } __attribute__((packed)); 494 495 struct bnxt_re_rdma { 496 __u64 rva; 497 __u32 rkey; 498 __u32 rsvd2; 499 } __attribute__((packed)); 500 501 struct bnxt_re_atomic { 502 __u64 swp_dt; 503 __u64 cmp_dt; 504 } __attribute__((packed)); 505 506 struct bnxt_re_inval { 507 __u64 rsvd[2]; 508 } __attribute__((packed)); 509 510 struct bnxt_re_bind { 511 __u64 va; 512 __u64 len; /* only 40 bits are valid */ 513 } __attribute__((packed)); 514 515 struct bnxt_re_brqe { 516 __u32 rsv_ws_fl_wt; 517 __u32 rsvd; 518 __u32 wrid; 519 __u32 rsvd1; 520 } __attribute__((packed)); 521 522 struct bnxt_re_rqe { 523 __u64 rsvd[2]; 524 } __attribute__((packed)); 525 526 /* SRQ */ 527 struct bnxt_re_srq_req { 528 struct ibv_create_srq cmd; 529 __u64 srqva; 530 __u64 srq_handle; 531 } __attribute__((packed)); 532 533 struct bnxt_re_srq_resp { 534 struct ibv_create_srq_resp resp; 535 __u32 srqid; 536 __u64 srq_page; 537 } __attribute__((packed)); 538 539 struct bnxt_re_srqe { 540 __u64 rsvd[2]; 541 } __attribute__((packed)); 542 543 struct bnxt_re_push_wqe { 544 __u64 addr[32]; 545 } __attribute__((packed));; 546 547 #endif 548