1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 */
6
7 #ifndef ATH11K_CORE_H
8 #define ATH11K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include <linux/dmi.h>
15 #include <linux/ctype.h>
16 #include <linux/rhashtable.h>
17 #include <linux/average.h>
18 #include <linux/firmware.h>
19 #include <linux/suspend.h>
20 #include <linux/of.h>
21
22 #include "qmi.h"
23 #include "htc.h"
24 #include "wmi.h"
25 #include "hal.h"
26 #include "dp.h"
27 #include "ce.h"
28 #include "mac.h"
29 #include "hw.h"
30 #include "hal_rx.h"
31 #include "reg.h"
32 #include "thermal.h"
33 #include "dbring.h"
34 #include "spectral.h"
35 #include "wow.h"
36 #include "fw.h"
37 #include "coredump.h"
38 #include "cfr.h"
39
40 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
41
42 #define ATH11K_TX_MGMT_NUM_PENDING_MAX 512
43
44 #define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
45
46 /* Pending management packets threshold for dropping probe responses */
47 #define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
48
49 #define ATH11K_INVALID_HW_MAC_ID 0xFF
50 #define ATH11K_CONNECTION_LOSS_HZ (3 * HZ)
51
52 /* SMBIOS type containing Board Data File Name Extension */
53 #define ATH11K_SMBIOS_BDF_EXT_TYPE 0xF8
54
55 /* SMBIOS type structure length (excluding strings-set) */
56 #define ATH11K_SMBIOS_BDF_EXT_LENGTH 0x9
57
58 /* The magic used by QCA spec */
59 #define ATH11K_SMBIOS_BDF_EXT_MAGIC "BDF_"
60
61 extern unsigned int ath11k_frame_mode;
62 extern bool ath11k_ftm_mode;
63
64 #define ATH11K_SCAN_TIMEOUT_HZ (20 * HZ)
65
66 #define ATH11K_MON_TIMER_INTERVAL 10
67 #define ATH11K_RESET_TIMEOUT_HZ (20 * HZ)
68 #define ATH11K_RESET_MAX_FAIL_COUNT_FIRST 3
69 #define ATH11K_RESET_MAX_FAIL_COUNT_FINAL 5
70 #define ATH11K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
71 #define ATH11K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
72 #define ATH11K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
73
74 enum ath11k_supported_bw {
75 ATH11K_BW_20 = 0,
76 ATH11K_BW_40 = 1,
77 ATH11K_BW_80 = 2,
78 ATH11K_BW_160 = 3,
79 };
80
81 enum ath11k_bdf_search {
82 ATH11K_BDF_SEARCH_DEFAULT,
83 ATH11K_BDF_SEARCH_BUS_AND_BOARD,
84 };
85
86 enum wme_ac {
87 WME_AC_BE,
88 WME_AC_BK,
89 WME_AC_VI,
90 WME_AC_VO,
91 WME_NUM_AC
92 };
93
94 #define ATH11K_HT_MCS_MAX 7
95 #define ATH11K_VHT_MCS_MAX 9
96 #define ATH11K_HE_MCS_MAX 11
97
98 enum ath11k_crypt_mode {
99 /* Only use hardware crypto engine */
100 ATH11K_CRYPT_MODE_HW,
101 /* Only use software crypto */
102 ATH11K_CRYPT_MODE_SW,
103 };
104
ath11k_tid_to_ac(u32 tid)105 static inline enum wme_ac ath11k_tid_to_ac(u32 tid)
106 {
107 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
108 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
109 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
110 WME_AC_VO);
111 }
112
113 enum ath11k_skb_flags {
114 ATH11K_SKB_HW_80211_ENCAP = BIT(0),
115 ATH11K_SKB_CIPHER_SET = BIT(1),
116 };
117
118 struct ath11k_skb_cb {
119 dma_addr_t paddr;
120 u8 eid;
121 u8 flags;
122 u32 cipher;
123 struct ath11k *ar;
124 struct ieee80211_vif *vif;
125 } __packed;
126
127 struct ath11k_skb_rxcb {
128 dma_addr_t paddr;
129 bool is_first_msdu;
130 bool is_last_msdu;
131 bool is_continuation;
132 bool is_mcbc;
133 bool is_eapol;
134 struct hal_rx_desc *rx_desc;
135 u8 err_rel_src;
136 u8 err_code;
137 u8 mac_id;
138 u8 unmapped;
139 u8 is_frag;
140 u8 tid;
141 u16 peer_id;
142 u16 seq_no;
143 };
144
145 enum ath11k_hw_rev {
146 ATH11K_HW_IPQ8074,
147 ATH11K_HW_QCA6390_HW20,
148 ATH11K_HW_IPQ6018_HW10,
149 ATH11K_HW_QCN9074_HW10,
150 ATH11K_HW_WCN6855_HW20,
151 ATH11K_HW_WCN6855_HW21,
152 ATH11K_HW_WCN6750_HW10,
153 ATH11K_HW_IPQ5018_HW10,
154 ATH11K_HW_QCA2066_HW21,
155 ATH11K_HW_QCA6698AQ_HW21,
156 };
157
158 enum ath11k_firmware_mode {
159 /* the default mode, standard 802.11 functionality */
160 ATH11K_FIRMWARE_MODE_NORMAL,
161
162 /* factory tests etc */
163 ATH11K_FIRMWARE_MODE_FTM,
164
165 /* Cold boot calibration */
166 ATH11K_FIRMWARE_MODE_COLD_BOOT = 7,
167 };
168
169 extern bool ath11k_cold_boot_cal;
170
171 #define ATH11K_IRQ_NUM_MAX 52
172 #define ATH11K_EXT_IRQ_NUM_MAX 16
173
174 struct ath11k_ext_irq_grp {
175 struct ath11k_base *ab;
176 u32 irqs[ATH11K_EXT_IRQ_NUM_MAX];
177 u32 num_irq;
178 u32 grp_id;
179 u64 timestamp;
180 bool napi_enabled;
181 struct napi_struct napi;
182 struct net_device *napi_ndev;
183 };
184
185 enum ath11k_smbios_cc_type {
186 /* disable country code setting from SMBIOS */
187 ATH11K_SMBIOS_CC_DISABLE = 0,
188
189 /* set country code by ANSI country name, based on ISO3166-1 alpha2 */
190 ATH11K_SMBIOS_CC_ISO = 1,
191
192 /* worldwide regdomain */
193 ATH11K_SMBIOS_CC_WW = 2,
194 };
195
196 struct ath11k_smbios_bdf {
197 struct dmi_header hdr;
198
199 u8 features_disabled;
200
201 /* enum ath11k_smbios_cc_type */
202 u8 country_code_flag;
203
204 /* To set specific country, you need to set country code
205 * flag=ATH11K_SMBIOS_CC_ISO first, then if country is United
206 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
207 * 0x53). To set country to INDONESIA, then country code value =
208 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
209 * ATH11K_SMBIOS_CC_WW, then you can use worldwide regulatory
210 * setting.
211 */
212 u16 cc_code;
213
214 u8 bdf_enabled;
215 u8 bdf_ext[];
216 } __packed;
217
218 #define HEHANDLE_CAP_PHYINFO_SIZE 3
219 #define HECAP_PHYINFO_SIZE 9
220 #define HECAP_MACINFO_SIZE 5
221 #define HECAP_TXRX_MCS_NSS_SIZE 2
222 #define HECAP_PPET16_PPET8_MAX_SIZE 25
223
224 #define HE_PPET16_PPET8_SIZE 8
225
226 /* 802.11ax PPE (PPDU packet Extension) threshold */
227 struct he_ppe_threshold {
228 u32 numss_m1;
229 u32 ru_mask;
230 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
231 };
232
233 struct ath11k_he {
234 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
235 u32 hecap_rxmcsnssmap;
236 u32 hecap_txmcsnssmap;
237 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
238 struct he_ppe_threshold hecap_ppet;
239 u32 heop_param;
240 };
241
242 #define MAX_RADIOS 3
243
244 /* ipq5018 hw param macros */
245 #define MAX_RADIOS_5018 1
246 #define CE_CNT_5018 6
247 #define TARGET_CE_CNT_5018 9
248 #define SVC_CE_MAP_LEN_5018 17
249 #define RXDMA_PER_PDEV_5018 1
250
251 enum {
252 WMI_HOST_TP_SCALE_MAX = 0,
253 WMI_HOST_TP_SCALE_50 = 1,
254 WMI_HOST_TP_SCALE_25 = 2,
255 WMI_HOST_TP_SCALE_12 = 3,
256 WMI_HOST_TP_SCALE_MIN = 4,
257 WMI_HOST_TP_SCALE_SIZE = 5,
258 };
259
260 enum ath11k_scan_state {
261 ATH11K_SCAN_IDLE,
262 ATH11K_SCAN_STARTING,
263 ATH11K_SCAN_RUNNING,
264 ATH11K_SCAN_ABORTING,
265 };
266
267 enum ath11k_11d_state {
268 ATH11K_11D_IDLE,
269 ATH11K_11D_PREPARING,
270 ATH11K_11D_RUNNING,
271 };
272
273 enum ath11k_dev_flags {
274 ATH11K_CAC_RUNNING,
275 ATH11K_FLAG_CORE_REGISTERED,
276 ATH11K_FLAG_CRASH_FLUSH,
277 ATH11K_FLAG_RAW_MODE,
278 ATH11K_FLAG_HW_CRYPTO_DISABLED,
279 ATH11K_FLAG_BTCOEX,
280 ATH11K_FLAG_RECOVERY,
281 ATH11K_FLAG_UNREGISTERING,
282 ATH11K_FLAG_REGISTERED,
283 ATH11K_FLAG_QMI_FAIL,
284 ATH11K_FLAG_HTC_SUSPEND_COMPLETE,
285 ATH11K_FLAG_CE_IRQ_ENABLED,
286 ATH11K_FLAG_EXT_IRQ_ENABLED,
287 ATH11K_FLAG_FIXED_MEM_RGN,
288 ATH11K_FLAG_DEVICE_INIT_DONE,
289 ATH11K_FLAG_MULTI_MSI_VECTORS,
290 ATH11K_FLAG_FTM_SEGMENTED,
291 };
292
293 enum ath11k_monitor_flags {
294 ATH11K_FLAG_MONITOR_CONF_ENABLED,
295 ATH11K_FLAG_MONITOR_STARTED,
296 ATH11K_FLAG_MONITOR_VDEV_CREATED,
297 };
298
299 #define ATH11K_IPV6_UC_TYPE 0
300 #define ATH11K_IPV6_AC_TYPE 1
301
302 #define ATH11K_IPV6_MAX_COUNT 16
303 #define ATH11K_IPV4_MAX_COUNT 2
304
305 struct ath11k_arp_ns_offload {
306 u8 ipv4_addr[ATH11K_IPV4_MAX_COUNT][4];
307 u32 ipv4_count;
308 u32 ipv6_count;
309 u8 ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
310 u8 self_ipv6_addr[ATH11K_IPV6_MAX_COUNT][16];
311 u8 ipv6_type[ATH11K_IPV6_MAX_COUNT];
312 bool ipv6_valid[ATH11K_IPV6_MAX_COUNT];
313 u8 mac_addr[ETH_ALEN];
314 };
315
316 struct ath11k_rekey_data {
317 u8 kck[NL80211_KCK_LEN];
318 u8 kek[NL80211_KCK_LEN];
319 u64 replay_ctr;
320 bool enable_offload;
321 };
322
323 /**
324 * struct ath11k_chan_power_info - TPE containing power info per channel chunk
325 * @chan_cfreq: channel center freq (MHz)
326 * e.g.
327 * channel 37/20 MHz, it is 6135
328 * channel 37/40 MHz, it is 6125
329 * channel 37/80 MHz, it is 6145
330 * channel 37/160 MHz, it is 6185
331 * @tx_power: transmit power (dBm)
332 */
333 struct ath11k_chan_power_info {
334 u16 chan_cfreq;
335 s8 tx_power;
336 };
337
338 /* ath11k only deals with 160 MHz, so 8 subchannels */
339 #define ATH11K_NUM_PWR_LEVELS 8
340
341 /**
342 * struct ath11k_reg_tpc_power_info - regulatory TPC power info
343 * @is_psd_power: is PSD power or not
344 * @eirp_power: Maximum EIRP power (dBm), valid only if power is PSD
345 * @ap_power_type: type of power (SP/LPI/VLP)
346 * @num_pwr_levels: number of power levels
347 * @reg_max: Array of maximum TX power (dBm) per PSD value
348 * @tpe: TPE values processed from TPE IE
349 * @chan_power_info: power info to send to firmware
350 */
351 struct ath11k_reg_tpc_power_info {
352 bool is_psd_power;
353 u8 eirp_power;
354 enum wmi_reg_6ghz_ap_type ap_power_type;
355 u8 num_pwr_levels;
356 u8 reg_max[ATH11K_NUM_PWR_LEVELS];
357 s8 tpe[ATH11K_NUM_PWR_LEVELS];
358 struct ath11k_chan_power_info chan_power_info[ATH11K_NUM_PWR_LEVELS];
359 };
360
361 struct ath11k_vif {
362 u32 vdev_id;
363 enum wmi_vdev_type vdev_type;
364 enum wmi_vdev_subtype vdev_subtype;
365 u32 beacon_interval;
366 u32 dtim_period;
367 u16 ast_hash;
368 u16 ast_idx;
369 u16 tcl_metadata;
370 u8 hal_addr_search_flags;
371 u8 search_type;
372
373 struct ath11k *ar;
374 struct ieee80211_vif *vif;
375
376 struct wmi_wmm_params_all_arg wmm_params;
377 struct wmi_wmm_params_all_arg muedca_params;
378 struct list_head list;
379 union {
380 struct {
381 u32 uapsd;
382 } sta;
383 struct {
384 /* 127 stations; wmi limit */
385 u8 tim_bitmap[16];
386 u8 tim_len;
387 u32 ssid_len;
388 u8 ssid[IEEE80211_MAX_SSID_LEN];
389 bool hidden_ssid;
390 /* P2P_IE with NoA attribute for P2P_GO case */
391 u32 noa_len;
392 u8 *noa_data;
393 } ap;
394 } u;
395
396 bool is_started;
397 bool is_up;
398 bool ftm_responder;
399 bool spectral_enabled;
400 bool ps;
401 u32 aid;
402 u8 bssid[ETH_ALEN];
403 struct cfg80211_bitrate_mask bitrate_mask;
404 struct delayed_work connection_loss_work;
405 struct work_struct bcn_tx_work;
406 int num_legacy_stations;
407 int rtscts_prot_mode;
408 int txpower;
409 bool rsnie_present;
410 bool wpaie_present;
411 bool bcca_zero_sent;
412 bool do_not_send_tmpl;
413 struct ath11k_arp_ns_offload arp_ns_offload;
414 struct ath11k_rekey_data rekey_data;
415 u32 num_stations;
416 bool reinstall_group_keys;
417
418 struct ath11k_reg_tpc_power_info reg_tpc_info;
419
420 /* Must be last - ends in a flexible-array member.
421 *
422 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
423 * especially because it has a flexible array. Find a better way.
424 */
425 struct ieee80211_chanctx_conf chanctx;
426 };
427
428 struct ath11k_vif_iter {
429 u32 vdev_id;
430 struct ath11k_vif *arvif;
431 };
432
433 struct ath11k_rx_peer_stats {
434 u64 num_msdu;
435 u64 num_mpdu_fcs_ok;
436 u64 num_mpdu_fcs_err;
437 u64 tcp_msdu_count;
438 u64 udp_msdu_count;
439 u64 other_msdu_count;
440 u64 ampdu_msdu_count;
441 u64 non_ampdu_msdu_count;
442 u64 stbc_count;
443 u64 beamformed_count;
444 u64 mcs_count[HAL_RX_MAX_MCS + 1];
445 u64 nss_count[HAL_RX_MAX_NSS];
446 u64 bw_count[HAL_RX_BW_MAX];
447 u64 gi_count[HAL_RX_GI_MAX];
448 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
449 u64 tid_count[IEEE80211_NUM_TIDS + 1];
450 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
451 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
452 u64 rx_duration;
453 u64 dcm_count;
454 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
455 };
456
457 #define ATH11K_HE_MCS_NUM 12
458 #define ATH11K_VHT_MCS_NUM 10
459 #define ATH11K_BW_NUM 4
460 #define ATH11K_NSS_NUM 4
461 #define ATH11K_LEGACY_NUM 12
462 #define ATH11K_GI_NUM 4
463 #define ATH11K_HT_MCS_NUM 32
464
465 enum ath11k_pkt_rx_err {
466 ATH11K_PKT_RX_ERR_FCS,
467 ATH11K_PKT_RX_ERR_TKIP,
468 ATH11K_PKT_RX_ERR_CRYPT,
469 ATH11K_PKT_RX_ERR_PEER_IDX_INVAL,
470 ATH11K_PKT_RX_ERR_MAX,
471 };
472
473 enum ath11k_ampdu_subfrm_num {
474 ATH11K_AMPDU_SUBFRM_NUM_10,
475 ATH11K_AMPDU_SUBFRM_NUM_20,
476 ATH11K_AMPDU_SUBFRM_NUM_30,
477 ATH11K_AMPDU_SUBFRM_NUM_40,
478 ATH11K_AMPDU_SUBFRM_NUM_50,
479 ATH11K_AMPDU_SUBFRM_NUM_60,
480 ATH11K_AMPDU_SUBFRM_NUM_MORE,
481 ATH11K_AMPDU_SUBFRM_NUM_MAX,
482 };
483
484 enum ath11k_amsdu_subfrm_num {
485 ATH11K_AMSDU_SUBFRM_NUM_1,
486 ATH11K_AMSDU_SUBFRM_NUM_2,
487 ATH11K_AMSDU_SUBFRM_NUM_3,
488 ATH11K_AMSDU_SUBFRM_NUM_4,
489 ATH11K_AMSDU_SUBFRM_NUM_MORE,
490 ATH11K_AMSDU_SUBFRM_NUM_MAX,
491 };
492
493 enum ath11k_counter_type {
494 ATH11K_COUNTER_TYPE_BYTES,
495 ATH11K_COUNTER_TYPE_PKTS,
496 ATH11K_COUNTER_TYPE_MAX,
497 };
498
499 enum ath11k_stats_type {
500 ATH11K_STATS_TYPE_SUCC,
501 ATH11K_STATS_TYPE_FAIL,
502 ATH11K_STATS_TYPE_RETRY,
503 ATH11K_STATS_TYPE_AMPDU,
504 ATH11K_STATS_TYPE_MAX,
505 };
506
507 struct ath11k_htt_data_stats {
508 u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM];
509 u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM];
510 u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM];
511 u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM];
512 u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM];
513 u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM];
514 u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM];
515 };
516
517 struct ath11k_htt_tx_stats {
518 struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX];
519 u64 tx_duration;
520 u64 ba_fails;
521 u64 ack_fails;
522 };
523
524 struct ath11k_per_ppdu_tx_stats {
525 u16 succ_pkts;
526 u16 failed_pkts;
527 u16 retry_pkts;
528 u32 succ_bytes;
529 u32 failed_bytes;
530 u32 retry_bytes;
531 };
532
533 DECLARE_EWMA(avg_rssi, 10, 8)
534
535 struct ath11k_per_peer_cfr_capture {
536 enum ath11k_cfr_capture_method cfr_method;
537 enum ath11k_cfr_capture_bw cfr_bw;
538 u32 cfr_enable;
539 u32 cfr_period;
540 };
541
542 struct ath11k_sta {
543 struct ath11k_vif *arvif;
544
545 /* the following are protected by ar->data_lock */
546 u32 changed; /* IEEE80211_RC_* */
547 u32 bw;
548 u32 nss;
549 u32 smps;
550 enum hal_pn_type pn_type;
551
552 struct work_struct update_wk;
553 struct work_struct set_4addr_wk;
554 struct rate_info txrate;
555 u32 peer_nss;
556 struct rate_info last_txrate;
557 u64 rx_duration;
558 u64 tx_duration;
559 u8 rssi_comb;
560 struct ewma_avg_rssi avg_rssi;
561 s8 rssi_beacon;
562 s8 chain_signal[IEEE80211_MAX_CHAINS];
563 struct ath11k_htt_tx_stats *tx_stats;
564 struct ath11k_rx_peer_stats *rx_stats;
565
566 #ifdef CONFIG_MAC80211_DEBUGFS
567 /* protected by conf_mutex */
568 bool aggr_mode;
569 #endif
570
571 bool use_4addr_set;
572 u16 tcl_metadata;
573
574 /* Protected with ar->data_lock */
575 enum ath11k_wmi_peer_ps_state peer_ps_state;
576 u64 ps_start_time;
577 u64 ps_start_jiffies;
578 u64 ps_total_duration;
579 bool peer_current_ps_valid;
580
581 u32 bw_prev;
582
583 #ifdef CONFIG_ATH11K_CFR
584 struct ath11k_per_peer_cfr_capture cfr_capture;
585 #endif
586 };
587
588 #define ATH11K_MIN_5G_FREQ 4150
589 #define ATH11K_MIN_6G_FREQ 5925
590 #define ATH11K_MAX_6G_FREQ 7115
591 #define ATH11K_NUM_CHANS 102
592 #define ATH11K_MAX_5G_CHAN 177
593
594 enum ath11k_state {
595 ATH11K_STATE_OFF,
596 ATH11K_STATE_ON,
597 ATH11K_STATE_RESTARTING,
598 ATH11K_STATE_RESTARTED,
599 ATH11K_STATE_WEDGED,
600 ATH11K_STATE_FTM,
601 /* Add other states as required */
602 };
603
604 /* Antenna noise floor */
605 #define ATH11K_DEFAULT_NOISE_FLOOR -95
606
607 #define ATH11K_INVALID_RSSI_FULL -1
608
609 #define ATH11K_INVALID_RSSI_EMPTY -128
610
611 struct ath11k_fw_stats {
612 struct dentry *debugfs_fwstats;
613 u32 pdev_id;
614 u32 stats_id;
615 struct list_head pdevs;
616 struct list_head vdevs;
617 struct list_head bcn;
618 u32 num_vdev_recvd;
619 u32 num_bcn_recvd;
620 };
621
622 struct ath11k_dbg_htt_stats {
623 u8 type;
624 u8 reset;
625 struct debug_htt_stats_req *stats_req;
626 /* protects shared stats req buffer */
627 spinlock_t lock;
628 };
629
630 #define MAX_MODULE_ID_BITMAP_WORDS 16
631
632 struct ath11k_debug {
633 struct dentry *debugfs_pdev;
634 struct ath11k_dbg_htt_stats htt_stats;
635 u32 extd_tx_stats;
636 u32 extd_rx_stats;
637 u32 pktlog_filter;
638 u32 pktlog_mode;
639 u32 pktlog_peer_valid;
640 u8 pktlog_peer_addr[ETH_ALEN];
641 u32 rx_filter;
642 u32 mem_offset;
643 u32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS];
644 struct ath11k_debug_dbr *dbr_debug[WMI_DIRECT_BUF_MAX];
645 };
646
647 struct ath11k_per_peer_tx_stats {
648 u32 succ_bytes;
649 u32 retry_bytes;
650 u32 failed_bytes;
651 u16 succ_pkts;
652 u16 retry_pkts;
653 u16 failed_pkts;
654 u32 duration;
655 u8 ba_fails;
656 bool is_ampdu;
657 };
658
659 #define ATH11K_FLUSH_TIMEOUT (5 * HZ)
660 #define ATH11K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
661
662 struct ath11k {
663 struct ath11k_base *ab;
664 struct ath11k_pdev *pdev;
665 struct ieee80211_hw *hw;
666 struct ath11k_pdev_wmi *wmi;
667 struct ath11k_pdev_dp dp;
668 u8 mac_addr[ETH_ALEN];
669 struct ath11k_he ar_he;
670 enum ath11k_state state;
671 bool supports_6ghz;
672 struct {
673 struct completion started;
674 struct completion completed;
675 struct completion on_channel;
676 struct delayed_work timeout;
677 enum ath11k_scan_state state;
678 bool is_roc;
679 int vdev_id;
680 int roc_freq;
681 bool roc_notify;
682 } scan;
683
684 struct {
685 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
686 struct ieee80211_sband_iftype_data
687 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
688 } mac;
689
690 unsigned long dev_flags;
691 unsigned int filter_flags;
692 unsigned long monitor_flags;
693 u32 min_tx_power;
694 u32 max_tx_power;
695 u32 txpower_limit_2g;
696 u32 txpower_limit_5g;
697 u32 txpower_scale;
698 u32 power_scale;
699 u32 chan_tx_pwr;
700 u32 num_stations;
701 u32 max_num_stations;
702 /* To synchronize concurrent synchronous mac80211 callback operations,
703 * concurrent debugfs configuration and concurrent FW statistics events.
704 */
705 struct mutex conf_mutex;
706 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
707 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info,
708 * channel context data, survey info, test mode data, channel_update_queue.
709 */
710 spinlock_t data_lock;
711
712 struct list_head arvifs;
713 /* should never be NULL; needed for regular htt rx */
714 struct ieee80211_channel *rx_channel;
715
716 /* valid during scan; needed for mgmt rx during scan */
717 struct ieee80211_channel *scan_channel;
718
719 u8 cfg_tx_chainmask;
720 u8 cfg_rx_chainmask;
721 u8 num_rx_chains;
722 u8 num_tx_chains;
723 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
724 u8 pdev_idx;
725 u8 lmac_id;
726
727 struct completion peer_assoc_done;
728 struct completion peer_delete_done;
729
730 int install_key_status;
731 struct completion install_key_done;
732
733 int last_wmi_vdev_start_status;
734 struct completion vdev_setup_done;
735 struct completion vdev_delete_done;
736
737 int num_peers;
738 int max_num_peers;
739 u32 num_started_vdevs;
740 u32 num_created_vdevs;
741 unsigned long long allocated_vdev_map;
742
743 struct idr txmgmt_idr;
744 /* protects txmgmt_idr data */
745 spinlock_t txmgmt_idr_lock;
746 atomic_t num_pending_mgmt_tx;
747 wait_queue_head_t txmgmt_empty_waitq;
748
749 /* cycle count is reported twice for each visited channel during scan.
750 * access protected by data_lock
751 */
752 u32 survey_last_rx_clear_count;
753 u32 survey_last_cycle_count;
754
755 /* Channel info events are expected to come in pairs without and with
756 * COMPLETE flag set respectively for each channel visit during scan.
757 *
758 * However there are deviations from this rule. This flag is used to
759 * avoid reporting garbage data.
760 */
761 bool ch_info_can_report_survey;
762 struct survey_info survey[ATH11K_NUM_CHANS];
763 struct completion bss_survey_done;
764
765 struct work_struct regd_update_work;
766 struct work_struct channel_update_work;
767 /* protected with data_lock */
768 struct list_head channel_update_queue;
769
770 struct work_struct wmi_mgmt_tx_work;
771 struct sk_buff_head wmi_mgmt_tx_queue;
772
773 struct ath11k_wow wow;
774 struct completion target_suspend;
775 bool target_suspend_ack;
776 struct ath11k_per_peer_tx_stats peer_tx_stats;
777 struct list_head ppdu_stats_info;
778 u32 ppdu_stat_list_depth;
779
780 struct ath11k_per_peer_tx_stats cached_stats;
781 u32 last_ppdu_id;
782 u32 cached_ppdu_id;
783 int monitor_vdev_id;
784 struct completion fw_mode_reset;
785 u8 ftm_msgref;
786 #ifdef CONFIG_ATH11K_DEBUGFS
787 struct ath11k_debug debug;
788 #endif
789 #ifdef CONFIG_ATH11K_SPECTRAL
790 struct ath11k_spectral spectral;
791 #endif
792 bool dfs_block_radar_events;
793 struct ath11k_thermal thermal;
794 u32 vdev_id_11d_scan;
795 struct completion completed_11d_scan;
796 enum ath11k_11d_state state_11d;
797 bool regdom_set_by_user;
798 int hw_rate_code;
799 u8 twt_enabled;
800 bool nlo_enabled;
801 u8 alpha2[REG_ALPHA2_LEN + 1];
802 struct ath11k_fw_stats fw_stats;
803 struct completion fw_stats_complete;
804 struct completion fw_stats_done;
805
806 /* protected by conf_mutex */
807 bool ps_state_enable;
808 bool ps_timekeeper_enable;
809 s8 max_allowed_tx_power;
810
811 #ifdef CONFIG_ATH11K_CFR
812 struct ath11k_cfr cfr;
813 #endif
814 bool cfr_enabled;
815 };
816
817 struct ath11k_band_cap {
818 u32 phy_id;
819 u32 max_bw_supported;
820 u32 ht_cap_info;
821 u32 he_cap_info[2];
822 u32 he_mcs;
823 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
824 struct ath11k_ppe_threshold he_ppet;
825 u16 he_6ghz_capa;
826 };
827
828 struct ath11k_pdev_cap {
829 u32 supported_bands;
830 u32 ampdu_density;
831 u32 vht_cap;
832 u32 vht_mcs;
833 u32 he_mcs;
834 u32 tx_chain_mask;
835 u32 rx_chain_mask;
836 u32 tx_chain_mask_shift;
837 u32 rx_chain_mask_shift;
838 struct ath11k_band_cap band[NUM_NL80211_BANDS];
839 bool nss_ratio_enabled;
840 u8 nss_ratio_info;
841 };
842
843 struct ath11k_pdev {
844 struct ath11k *ar;
845 u32 pdev_id;
846 struct ath11k_pdev_cap cap;
847 u8 mac_addr[ETH_ALEN];
848 };
849
850 struct ath11k_board_data {
851 const struct firmware *fw;
852 const void *data;
853 size_t len;
854 };
855
856 struct ath11k_pci_ops {
857 int (*wakeup)(struct ath11k_base *ab);
858 void (*release)(struct ath11k_base *ab);
859 int (*get_msi_irq)(struct ath11k_base *ab, unsigned int vector);
860 void (*window_write32)(struct ath11k_base *ab, u32 offset, u32 value);
861 u32 (*window_read32)(struct ath11k_base *ab, u32 offset);
862 };
863
864 /* IPQ8074 HW channel counters frequency value in hertz */
865 #define IPQ8074_CC_FREQ_HERTZ 320000
866
867 struct ath11k_bp_stats {
868 /* Head Pointer reported by the last HTT Backpressure event for the ring */
869 u16 hp;
870
871 /* Tail Pointer reported by the last HTT Backpressure event for the ring */
872 u16 tp;
873
874 /* Number of Backpressure events received for the ring */
875 u32 count;
876
877 /* Last recorded event timestamp */
878 unsigned long jiffies;
879 };
880
881 struct ath11k_dp_ring_bp_stats {
882 struct ath11k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX];
883 struct ath11k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS];
884 };
885
886 struct ath11k_soc_dp_tx_err_stats {
887 /* TCL Ring Descriptor unavailable */
888 u32 desc_na[DP_TCL_NUM_RING_MAX];
889 /* Other failures during dp_tx due to mem allocation failure
890 * idr unavailable etc.
891 */
892 atomic_t misc_fail;
893 };
894
895 struct ath11k_soc_dp_stats {
896 u32 err_ring_pkts;
897 u32 invalid_rbm;
898 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
899 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
900 u32 hal_reo_error[DP_REO_DST_RING_MAX];
901 struct ath11k_soc_dp_tx_err_stats tx_err;
902 struct ath11k_dp_ring_bp_stats bp_stats;
903 };
904
905 struct ath11k_msi_user {
906 char *name;
907 int num_vectors;
908 u32 base_vector;
909 };
910
911 struct ath11k_msi_config {
912 int total_vectors;
913 int total_users;
914 struct ath11k_msi_user *users;
915 u16 hw_rev;
916 };
917
918 enum ath11k_pm_policy {
919 ATH11K_PM_DEFAULT,
920 ATH11K_PM_WOW,
921 };
922
923 /* Master structure to hold the hw data which may be used in core module */
924 struct ath11k_base {
925 enum ath11k_hw_rev hw_rev;
926 enum ath11k_firmware_mode fw_mode;
927 struct platform_device *pdev;
928 struct device *dev;
929 struct ath11k_qmi qmi;
930 struct ath11k_wmi_base wmi_ab;
931 struct completion fw_ready;
932 int num_radios;
933 /* HW channel counters frequency value in hertz common to all MACs */
934 u32 cc_freq_hz;
935
936 struct ath11k_dump_file_data *dump_data;
937 size_t ath11k_coredump_len;
938 struct work_struct dump_work;
939
940 struct ath11k_htc htc;
941
942 struct ath11k_dp dp;
943
944 void __iomem *mem;
945 void __iomem *mem_ce;
946 unsigned long mem_len;
947
948 struct {
949 enum ath11k_bus bus;
950 const struct ath11k_hif_ops *ops;
951 } hif;
952
953 struct {
954 struct completion wakeup_completed;
955 } wow;
956
957 struct ath11k_ce ce;
958 struct timer_list rx_replenish_retry;
959 struct ath11k_hal hal;
960 /* To synchronize core_start/core_stop */
961 struct mutex core_lock;
962 /* Protects data like peers */
963 spinlock_t base_lock;
964 struct ath11k_pdev pdevs[MAX_RADIOS];
965 struct {
966 enum WMI_HOST_WLAN_BAND supported_bands;
967 u32 pdev_id;
968 } target_pdev_ids[MAX_RADIOS];
969 u8 target_pdev_count;
970 struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
971 struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
972 unsigned long long free_vdev_map;
973
974 /* To synchronize rhash tbl write operation */
975 struct mutex tbl_mtx_lock;
976
977 /* The rhashtable containing struct ath11k_peer keyed by mac addr */
978 struct rhashtable *rhead_peer_addr;
979 struct rhashtable_params rhash_peer_addr_param;
980
981 /* The rhashtable containing struct ath11k_peer keyed by id */
982 struct rhashtable *rhead_peer_id;
983 struct rhashtable_params rhash_peer_id_param;
984
985 struct list_head peers;
986 wait_queue_head_t peer_mapping_wq;
987 u8 mac_addr[ETH_ALEN];
988 int irq_num[ATH11K_IRQ_NUM_MAX];
989 struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
990 struct ath11k_targ_cap target_caps;
991 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
992 bool pdevs_macaddr_valid;
993
994 struct ath11k_hw_params hw_params;
995
996 const struct firmware *cal_file;
997
998 /* Below regd's are protected by ab->data_lock */
999 /* This is the regd set for every radio
1000 * by the firmware during initialization
1001 */
1002 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
1003 /* This regd is set during dynamic country setting
1004 * This may or may not be used during the runtime
1005 */
1006 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
1007 struct cur_regulatory_info *reg_info_store;
1008
1009 /* Current DFS Regulatory */
1010 enum ath11k_dfs_region dfs_region;
1011 #ifdef CONFIG_ATH11K_DEBUGFS
1012 struct dentry *debugfs_soc;
1013 #endif
1014 struct ath11k_soc_dp_stats soc_stats;
1015
1016 unsigned long dev_flags;
1017 struct completion driver_recovery;
1018 struct workqueue_struct *workqueue;
1019 struct work_struct restart_work;
1020 struct work_struct update_11d_work;
1021 u8 new_alpha2[3];
1022 struct workqueue_struct *workqueue_aux;
1023 struct work_struct reset_work;
1024 atomic_t reset_count;
1025 atomic_t recovery_count;
1026 atomic_t recovery_start_count;
1027 bool is_reset;
1028 struct completion reset_complete;
1029 struct completion reconfigure_complete;
1030 struct completion recovery_start;
1031 /* continuous recovery fail count */
1032 atomic_t fail_cont_count;
1033 unsigned long reset_fail_timeout;
1034 struct {
1035 /* protected by data_lock */
1036 u32 fw_crash_counter;
1037 } stats;
1038 u32 pktlog_defs_checksum;
1039
1040 struct ath11k_dbring_cap *db_caps;
1041 u32 num_db_cap;
1042
1043 /* To synchronize 11d scan vdev id */
1044 struct mutex vdev_id_11d_lock;
1045 struct timer_list mon_reap_timer;
1046
1047 struct completion htc_suspend;
1048
1049 struct {
1050 enum ath11k_bdf_search bdf_search;
1051 u32 vendor;
1052 u32 device;
1053 u32 subsystem_vendor;
1054 u32 subsystem_device;
1055 } id;
1056
1057 struct {
1058 struct {
1059 const struct ath11k_msi_config *config;
1060 u32 ep_base_data;
1061 u32 irqs[32];
1062 u32 addr_lo;
1063 u32 addr_hi;
1064 } msi;
1065
1066 const struct ath11k_pci_ops *ops;
1067 } pci;
1068
1069 struct {
1070 u32 api_version;
1071
1072 const struct firmware *fw;
1073 const u8 *amss_data;
1074 size_t amss_len;
1075 const u8 *m3_data;
1076 size_t m3_len;
1077
1078 DECLARE_BITMAP(fw_features, ATH11K_FW_FEATURE_COUNT);
1079 } fw;
1080
1081 struct completion restart_completed;
1082
1083 #ifdef CONFIG_NL80211_TESTMODE
1084 struct {
1085 u32 data_pos;
1086 u32 expected_seq;
1087 u8 *eventdata;
1088 } testmode;
1089 #endif
1090
1091 enum ath11k_pm_policy pm_policy;
1092 enum ath11k_pm_policy actual_pm_policy;
1093 struct notifier_block pm_nb;
1094
1095 /* must be last */
1096 u8 drv_priv[] __aligned(sizeof(void *));
1097 };
1098
1099 struct ath11k_fw_stats_pdev {
1100 struct list_head list;
1101
1102 /* PDEV stats */
1103 s32 ch_noise_floor;
1104 /* Cycles spent transmitting frames */
1105 u32 tx_frame_count;
1106 /* Cycles spent receiving frames */
1107 u32 rx_frame_count;
1108 /* Total channel busy time, evidently */
1109 u32 rx_clear_count;
1110 /* Total on-channel time */
1111 u32 cycle_count;
1112 u32 phy_err_count;
1113 u32 chan_tx_power;
1114 u32 ack_rx_bad;
1115 u32 rts_bad;
1116 u32 rts_good;
1117 u32 fcs_bad;
1118 u32 no_beacons;
1119 u32 mib_int_count;
1120
1121 /* PDEV TX stats */
1122 /* Num HTT cookies queued to dispatch list */
1123 s32 comp_queued;
1124 /* Num HTT cookies dispatched */
1125 s32 comp_delivered;
1126 /* Num MSDU queued to WAL */
1127 s32 msdu_enqued;
1128 /* Num MPDU queue to WAL */
1129 s32 mpdu_enqued;
1130 /* Num MSDUs dropped by WMM limit */
1131 s32 wmm_drop;
1132 /* Num Local frames queued */
1133 s32 local_enqued;
1134 /* Num Local frames done */
1135 s32 local_freed;
1136 /* Num queued to HW */
1137 s32 hw_queued;
1138 /* Num PPDU reaped from HW */
1139 s32 hw_reaped;
1140 /* Num underruns */
1141 s32 underrun;
1142 /* Num hw paused */
1143 u32 hw_paused;
1144 /* Num PPDUs cleaned up in TX abort */
1145 s32 tx_abort;
1146 /* Num MPDUs requeued by SW */
1147 s32 mpdus_requeued;
1148 /* excessive retries */
1149 u32 tx_ko;
1150 u32 tx_xretry;
1151 /* data hw rate code */
1152 u32 data_rc;
1153 /* Scheduler self triggers */
1154 u32 self_triggers;
1155 /* frames dropped due to excessive sw retries */
1156 u32 sw_retry_failure;
1157 /* illegal rate phy errors */
1158 u32 illgl_rate_phy_err;
1159 /* wal pdev continuous xretry */
1160 u32 pdev_cont_xretry;
1161 /* wal pdev tx timeouts */
1162 u32 pdev_tx_timeout;
1163 /* wal pdev resets */
1164 u32 pdev_resets;
1165 /* frames dropped due to non-availability of stateless TIDs */
1166 u32 stateless_tid_alloc_failure;
1167 /* PhY/BB underrun */
1168 u32 phy_underrun;
1169 /* MPDU is more than txop limit */
1170 u32 txop_ovf;
1171 /* Num sequences posted */
1172 u32 seq_posted;
1173 /* Num sequences failed in queueing */
1174 u32 seq_failed_queueing;
1175 /* Num sequences completed */
1176 u32 seq_completed;
1177 /* Num sequences restarted */
1178 u32 seq_restarted;
1179 /* Num of MU sequences posted */
1180 u32 mu_seq_posted;
1181 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
1182 * (Reset,channel change)
1183 */
1184 s32 mpdus_sw_flush;
1185 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */
1186 s32 mpdus_hw_filter;
1187 /* Num MPDUs truncated by PDG (TXOP, TBTT,
1188 * PPDU_duration based on rate, dyn_bw)
1189 */
1190 s32 mpdus_truncated;
1191 /* Num MPDUs that was tried but didn't receive ACK or BA */
1192 s32 mpdus_ack_failed;
1193 /* Num MPDUs that was dropped du to expiry. */
1194 s32 mpdus_expired;
1195
1196 /* PDEV RX stats */
1197 /* Cnts any change in ring routing mid-ppdu */
1198 s32 mid_ppdu_route_change;
1199 /* Total number of statuses processed */
1200 s32 status_rcvd;
1201 /* Extra frags on rings 0-3 */
1202 s32 r0_frags;
1203 s32 r1_frags;
1204 s32 r2_frags;
1205 s32 r3_frags;
1206 /* MSDUs / MPDUs delivered to HTT */
1207 s32 htt_msdus;
1208 s32 htt_mpdus;
1209 /* MSDUs / MPDUs delivered to local stack */
1210 s32 loc_msdus;
1211 s32 loc_mpdus;
1212 /* AMSDUs that have more MSDUs than the status ring size */
1213 s32 oversize_amsdu;
1214 /* Number of PHY errors */
1215 s32 phy_errs;
1216 /* Number of PHY errors drops */
1217 s32 phy_err_drop;
1218 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1219 s32 mpdu_errs;
1220 /* Num overflow errors */
1221 s32 rx_ovfl_errs;
1222 };
1223
1224 struct ath11k_fw_stats_vdev {
1225 struct list_head list;
1226
1227 u32 vdev_id;
1228 u32 beacon_snr;
1229 u32 data_snr;
1230 u32 num_tx_frames[WLAN_MAX_AC];
1231 u32 num_rx_frames;
1232 u32 num_tx_frames_retries[WLAN_MAX_AC];
1233 u32 num_tx_frames_failures[WLAN_MAX_AC];
1234 u32 num_rts_fail;
1235 u32 num_rts_success;
1236 u32 num_rx_err;
1237 u32 num_rx_discard;
1238 u32 num_tx_not_acked;
1239 u32 tx_rate_history[MAX_TX_RATE_VALUES];
1240 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1241 };
1242
1243 struct ath11k_fw_stats_bcn {
1244 struct list_head list;
1245
1246 u32 vdev_id;
1247 u32 tx_bcn_succ_cnt;
1248 u32 tx_bcn_outage_cnt;
1249 };
1250
1251 void ath11k_fw_stats_init(struct ath11k *ar);
1252 void ath11k_fw_stats_pdevs_free(struct list_head *head);
1253 void ath11k_fw_stats_vdevs_free(struct list_head *head);
1254 void ath11k_fw_stats_bcn_free(struct list_head *head);
1255 void ath11k_fw_stats_free(struct ath11k_fw_stats *stats);
1256
1257 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[];
1258 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[];
1259 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[];
1260
1261 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[];
1262 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[];
1263
1264 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[];
1265 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[];
1266
1267 extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[];
1268 extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[];
1269 int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab);
1270 int ath11k_core_pre_init(struct ath11k_base *ab);
1271 int ath11k_core_init(struct ath11k_base *ath11k);
1272 void ath11k_core_deinit(struct ath11k_base *ath11k);
1273 struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
1274 enum ath11k_bus bus);
1275 void ath11k_core_free(struct ath11k_base *ath11k);
1276 int ath11k_core_fetch_bdf(struct ath11k_base *ath11k,
1277 struct ath11k_board_data *bd);
1278 int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd);
1279 int ath11k_core_fetch_board_data_api_1(struct ath11k_base *ab,
1280 struct ath11k_board_data *bd,
1281 const char *name);
1282 void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd);
1283 int ath11k_core_check_dt(struct ath11k_base *ath11k);
1284 int ath11k_core_check_smbios(struct ath11k_base *ab);
1285 void ath11k_core_halt(struct ath11k *ar);
1286 int ath11k_core_resume_early(struct ath11k_base *ab);
1287 int ath11k_core_resume(struct ath11k_base *ab);
1288 int ath11k_core_suspend(struct ath11k_base *ab);
1289 int ath11k_core_suspend_late(struct ath11k_base *ab);
1290 void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab);
1291 bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab);
1292
1293 const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
1294 const char *filename);
1295 const char *ath11k_core_get_usecase_firmware(struct ath11k_base *ab);
1296
ath11k_scan_state_str(enum ath11k_scan_state state)1297 static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state)
1298 {
1299 switch (state) {
1300 case ATH11K_SCAN_IDLE:
1301 return "idle";
1302 case ATH11K_SCAN_STARTING:
1303 return "starting";
1304 case ATH11K_SCAN_RUNNING:
1305 return "running";
1306 case ATH11K_SCAN_ABORTING:
1307 return "aborting";
1308 }
1309
1310 return "unknown";
1311 }
1312
ATH11K_SKB_CB(struct sk_buff * skb)1313 static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb)
1314 {
1315 BUILD_BUG_ON(sizeof(struct ath11k_skb_cb) >
1316 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1317 return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1318 }
1319
ATH11K_SKB_RXCB(struct sk_buff * skb)1320 static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb)
1321 {
1322 BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb));
1323 return (struct ath11k_skb_rxcb *)skb->cb;
1324 }
1325
ath11k_vif_to_arvif(struct ieee80211_vif * vif)1326 static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif)
1327 {
1328 return (struct ath11k_vif *)vif->drv_priv;
1329 }
1330
ath11k_sta_to_arsta(struct ieee80211_sta * sta)1331 static inline struct ath11k_sta *ath11k_sta_to_arsta(struct ieee80211_sta *sta)
1332 {
1333 return (struct ath11k_sta *)sta->drv_priv;
1334 }
1335
ath11k_ab_to_ar(struct ath11k_base * ab,int mac_id)1336 static inline struct ath11k *ath11k_ab_to_ar(struct ath11k_base *ab,
1337 int mac_id)
1338 {
1339 return ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
1340 }
1341
ath11k_core_create_firmware_path(struct ath11k_base * ab,const char * filename,void * buf,size_t buf_len)1342 static inline void ath11k_core_create_firmware_path(struct ath11k_base *ab,
1343 const char *filename,
1344 void *buf, size_t buf_len)
1345 {
1346 const char *fw_name = NULL;
1347
1348 of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name);
1349
1350 if (!fw_name)
1351 fw_name = ath11k_core_get_usecase_firmware(ab);
1352
1353 if (fw_name && strncmp(filename, "board", 5))
1354 snprintf(buf, buf_len, "%s/%s/%s/%s", ATH11K_FW_DIR,
1355 ab->hw_params.fw.dir, fw_name, filename);
1356 else
1357 snprintf(buf, buf_len, "%s/%s/%s", ATH11K_FW_DIR,
1358 ab->hw_params.fw.dir, filename);
1359 }
1360
ath11k_bus_str(enum ath11k_bus bus)1361 static inline const char *ath11k_bus_str(enum ath11k_bus bus)
1362 {
1363 switch (bus) {
1364 case ATH11K_BUS_PCI:
1365 return "pci";
1366 case ATH11K_BUS_AHB:
1367 return "ahb";
1368 }
1369
1370 return "unknown";
1371 }
1372
1373 void ath11k_core_pm_notifier_unregister(struct ath11k_base *ab);
1374
1375 #endif /* _CORE_H_ */
1376